GB2380604A - Bi-directional semiconductor switch - Google Patents

Bi-directional semiconductor switch Download PDF

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Publication number
GB2380604A
GB2380604A GB0113336A GB0113336A GB2380604A GB 2380604 A GB2380604 A GB 2380604A GB 0113336 A GB0113336 A GB 0113336A GB 0113336 A GB0113336 A GB 0113336A GB 2380604 A GB2380604 A GB 2380604A
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region
terminal
drift
conduction type
gate
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GB0113336A
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GB2380604B (en
GB0113336D0 (en
Inventor
Gehan Anil Joseph Amaratunga
Kuang Sheng
Florin Udrea
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A bi-directional semiconductor switch 10 that can selectively conduct current and block voltage in both directions has a first terminal region 12 of a first conduction type and a second terminal region 12' of the first conduction type. Each of the first and second terminal regions 12,12' has at least one highly doped region 14,14' of a second conduction type formed therein. The switch 10 includes a drift region 20 that has at least three adjacent voltage-floating drift sub-regions 21,22 that alternate in conduction type transversely of the first and second terminal regions 12,12'. The switch 10 has a first gate, Gate 1, to which a voltage can be applied to modulate charge in the first drift sub-region 21 in the vicinity of the first terminal region 12. The switch 10 further has a second gate, Gate 2, to which a voltage can be applied to modulate charge in the first drift sub-region 21 in the vicinity of the second terminal region 12'.

Description

<Desc/Clms Page number 1>
SEMICONDUCTOR SWITCH The present invention relates to a semiconductor switch.
In its preferred embodiment, the present invention provides a symmetrical, double MOS-gate controlled, bi-directional semiconductor switch with floating N and P drift regions to realise high breakdown voltage, low on-state voltage drop and fast switching speed.
Semiconductor switches that can conduct current and block voltage in both directions have a wide range of applications.
These include single-phase AC-AC power conversion, multisource power electronic circuits and matrix converters. A matrix converter is a universal converter which allows bi-directional power flow and any desired number of input and output phases. A matrix converter can be a pure solid-state (silicon) converter since it theoretically does not require any energy storage devices, which dramatically reduces the size of the whole system. A bi-directional switch is an essential component of a matrix converter.
Limited by the availability of such devices, most applications combine two uni-directional switches and two diodes as an AC switch. However this decreases system reliability and increases system cost and size significantly.
Although triacs are readily available, they are normally expensive, unable to turn-off and difficult to use. Other bi-directional switch concepts have been proposed but these
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devices are either technologically impractical or require extra auxiliary components/circuitry.
According to the present invention, there is provided a bi-directional semiconductor switch that can selectively conduct current and block voltage in both directions, the switch comprising: a first terminal region of a first conduction type, the first terminal region having at least one highly doped region of a second conduction type formed therein; a second terminal region of the first conduction type, the second terminal region having at least one highly doped region of a second conduction type formed therein; a drift region comprising at least three adjacent voltagefloating drift sub-regions that alternate in conduction type transversely of the first and second terminal regions, the at least three drift sub-regions comprising a first drift subregion of the second conduction type extending between the first and second terminal regions and second and third drift sub-regions each of the first conduction type and respectively located either side of the first drift sub-region; a first gate to which a voltage can be applied to modulate charge in the first drift sub-region in the vicinity of the first terminal region; and, a second gate to which a voltage can be applied to modulate charge in the first drift sub-region in the vicinity of the second terminal region.
When the switch is operated to block voltage, because of the charge balance that can be achieved between the floating drift sub-regions, a uniform electric field distribution is obtained in the drift region. This in turn provides a high
<Desc/Clms Page number 3>
breakdown voltage for a short drift region length. In operation, the potentials of the floating drift sub-regions are referenced to the correct terminal automatically. In a practical embodiment, the length of the drift region is short and the floating drift sub-regions have relatively high doping, each of which tends to give a low on-state voltage drop for the switch.
Preferably, at least one of the gates is provided by a trench having a dielectric-coated wall adjacent the portion of the drift sub-region in which the charge is modulated by applying a voltage to said gate. More preferably, each gate is provided by a trench having a dielectric-coated wall adjacent the portion of the drift sub-region in which the charge is modulated by applying a voltage to said gate. In these preferred arrangements, the typical reach-through problem of known AC switches at off-state is avoided by fieldstopping deep trenches which act in use to inhibit or limit expansion of the depletion region in the drift region.
The device may be a vertical device with first and second terminals positioned on opposed end walls, the first terminal being in electrical contact with the first terminal region of the first conduction type and the highly doped region of the second conduction type provided therein, and the second terminal being in electrical contact with the second terminal region of the first conduction type and the highly doped region of the second conduction type provided therein.
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Alternatively, the device may be a lateral device with the first terminal region of the first conduction type, the second terminal region of the first conduction type and the drift region all being provided at one surface of a substrate.
Preferably, at least one of the gates is provided by a trench having a dielectric-coated wall adjacent the portion of the drift sub-region in which the charge is modulated by applying a voltage to said gate, the at least one trench extending into the substrate. More preferably, each gate is provided by a trench having a dielectric-coated wall adjacent the portion of the drift sub-region in which the charge is modulated by applying a voltage to said gate, each trench extending into the substrate. This particular arrangement has the advantage that a higher breakdown voltage can be obtained for the same drift region length or a shorter drift region can be used for the same breakdown voltage.
Thus, in its most preferred embodiment, the present invention provides a bi-directional (AC) switch which realises high breakdown voltage, low on-state voltage drop and fast switching speed by utilising floating drift sub-regions of alternating conductivity type. Fast turn-off of the switch can be achieved in the preferred embodiment by biasing both MOS gates to extract both electrons and holes rapidly. The switches can be operated in several different modes, depending on the voltage applied on both gates. The switch can be symmetrical and can be either a vertical or a lateral power devices with a voltage rating ranging from 50V to several thousand volts and a current rating ranging from milliamperes
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to several thousand amperes. The switch is a normally-off device.
An embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which: Figures l (a) and l (b) respectively show schematically examples of a vertical and a lateral bi-directional switch structure in accordance with an embodiment of the present invention ; Figures 2 (a) and 2 (b) respectively show graphically the potential and electric field distribution in the drift region of the vertical device of Figure l (a) ; Figure 3 (a) shows graphically the potential distribution of an example of a lateral structure without trenches into the substrate in accordance with an embodiment of the present invention; Figure 3 (b) shows graphically the potential distribution of an example of a lateral structure with trenches into the substrate in accordance with an embodiment of the present invention ; Figure 4 (a) shows graphically the on-state characteristics of the vertical device of Figure l (a) ;
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Figure 4 (b) shows graphically the on-state characteristics of the lateral devices with and without trenches into the substrate ; Figure 5 shows graphically the turn-off transient of the vertical device of Figure 1 (a) with I1Oad=100A/cm2 and Vdc=600Vi and, Figures 6 (a) and (b) show graphically the turn-off waveforms of the lateral devices without and with trenches into the substrate respectively.
Referring to the drawings, examples of switches in accordance with a preferred embodiment of the present invention are shown schematically in Figures l (a) and l (b) for vertical and lateral structures respectively. The vertical and lateral devices shown in Figures l (a) and (b) have the same basic structure. The lateral structure can also be realised on a lateral junction isolation substrate or a silicon-on-insulator substrate.
Referring now specifically to Figure l (a), the switch 10 has first and second opposed P wells 12, 12' between which is provided a drift region 20 which will be discussed in more detail below. Discrete N+ regions 14, 14' are formed in the P wells 12, 12' at a surface of the P wells 12, 12' remote from the drift region 20.
Plural gates are provided at each end of the drift region 20 in order to allow the conductivity of the drift region 20
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to be selectively modified, as will be discussed further below. The gates are designated "Gate 1" and "Gate 2" in the drawings and the specific description. In the preferred embodiment shown, each Gate 1,2 is formed by etching into the silicon in selected portions of the drift region 20 adjacent the P wells 12, 12' and into the P wells 12, 12' themselves. A dielectric oxide layer 15 is then grown onto the internal walls of the etched portions. The etched portions are then re-filled with polycrystalline silicon 16 which is then doped to have a high conductivity. A further dielectric oxide layer
17, 17' is then formed over the exposed (outer) portions of the polycrystalline silicon 16. A metal layer 18, 18' is then formed at each end over the P wells 12, 12', N+ regions 14, 14' and polycrystalline silicon 16/dielectric layers 17,17'. A first terminal, designated Terminal 1, is thus effectively provided by the contact of the metal layer 18 to the top P well 12 and its N+ regions 14. A second terminal, designated Terminal 2, is similarly effectively provided by the contact of the metal layer 18'to the lower P well 12'and its N+ regions 14'. Electrical connections are also made to the polycrystalline silicon 16 to provide gate terminals designated Terminal 3 and Terminal 4 for the gates Gate 1 and Gate 2 respectively, as shown schematically in the drawings.
The drift region 20 is provided by alternating strips or
stripes of N-and P-drift sub-regions 21, 22. As shown in the drawings, the width of the N-and P-drift sub-regions 21, 22 and the width of the Gates 1, 2 are such that the P-drift sub- regions 22 extend longitudinally only between the Gates 1,2 (and not for example up to the P wells 12, 12') and such that
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the N-drift sub-regions 21 at their ends adjacent the P wells 12, 12' are fully contained between the respective trenches that provide the Gates 1, 2. Doping of each of the N-and Pdrift sub-regions 21, 22 is designed according to the following expression in order to give a charge balance when the switch 10 is blocking voltage :
Ndoping * W"-Pdoping P
where WN, p are the widths of the N-and P-drift subregions 21, 22 and Ndoplng and Pdoping are the respective dopant concentrations.
For the vertical switch 10, the trenches are normally deep (e. g. 6 to 10um) in a direction parallel to the vertical extent of the device 10 and their spacing is small (e. g.
< 4m).
Referring now briefly to Figure l (b), a corresponding lateral switch 10 is shown. The same reference numerals have been used for corresponding elements of the switch 10 and these will not be further described as such. The semiconductor elements are formed on a substrate 19 which, in the example shown, is sapphire or another material which is completely insulating with physical properties equivalent to those of sapphire, such as for example a silicon dioxide layer on silicon.
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It will be understood that the basic structures in Figures l (a) and l (b) can be repeated ad infinitum to produce parallel rows of such switches.
OFF-STATE Vertical Structure In the off-state, Terminal 1 is shorted to Terminal 3 or driven with the same voltage, and correspondingly Terminal 2 is shorted to Terminal 4 or driven with the same voltage.
When Terminal 1 of the vertical switch 10 shown in Figure l (a) is biased with a small positive voltage with respect to Terminal 2 (the Gates 1, 2 having the same potential as their respective Terminals 1, 2 because of the same potential being at Terminal 1 and Terminal 3 and at Terminal 2 and Terminal 4 respectively), the depletion region at the P/N junction between the P well 12'and the N-drift sub-region 21 between the trenches at Terminal 2 starts to expand because of the reverse bias at the P/N junction formed between the P well 12' and the N-drift region 21 at Terminal 2. The part of the Ndrift sub-region 21 between these trenches fully depletes at a low voltage because of the low trench spacing. As this depletion region expands above the trenches and reaches the depletion region between the N-and P-drift sub-regions 21, 22 (i. e. above the trenches at Terminal 2), the potential of each of the floating P-drift sub-regions 22 is related to that of the P wells 12'adjacent Terminal 2 and thus to that of Terminal 2. Given that the potential of each of the N-drift sub-regions 21 is related to that of Terminal 1 through the P
<Desc/Clms Page number 10>
well 12 at that end of the device 10, the lateral junctions between the N-and P-drift sub-regions 21, 22 are therefore reverse biased. Since the widths of the N-and P-drift sub- regions 21,22 are small (typically a few microns), the whole drift region 20 between the trenches at Terminal 1 and the trenches at Terminal 2 is fully depleted by these lateral junctions at a low voltage. Because of the charge balance condition given above, the electric field distribution in the drift region 20 is nearly uniform, as indicated in Figure 2 (b).
After the full depletion of the drift region 20, the switch 10 blocks voltage in a similar way to a 3D"RESURF" structure as discussed in for example F. Udrea, et. al.,"3D Resurf Double-Gate MOSFET : A Revolutionary Power Device Concept", Electronics Letters, Vol. 35, No. 8, April 1998 (or a"superjunction"or"CoolMos"structure as discussed in T.
Fujihira and Y. Miyasaka,'Simulated Superior Performances of
Semiconductor Superjunction Devices", Proceedings of ISPSD'98, pp. 423 and, L. Lorenz, M. Marz and G. Deboy,"COOL MOS-An Important Milestone towards a New Power MOSFET Generation", PCIM'98 respectively). However, since the N-and P-stripes in such a 3D RESURF structure are connected to the device terminals to facilitate lateral depletion, such a device can only block voltage in one direction. In contrast, in a structure like that shown in Figure I (a), the N-and P-drift sub-regions 21,22 are floating and their potentials can be automatically referenced to the correct terminal to block voltage from either direction.
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Another important advantage of the structure shown in Figure l (a) is that the typical reach-through problem in an AC switch is avoided by utilising the deep trenches. From the potential and electric field distributions shown in Figures 2 (a) and 2 (b), it can be seen that the electric field and the expansion of the depletion region are effectively stopped before reaching the right hand side P well in the drawing by the closely located trenches. Although deep trenches have been proposed in K. Matsushita, et. al., "Blocking Vol tage Design Consideration for Deep Trench MOS Gate High Power Devices", Proceedings of ISPSD'99, pp. 256 -260 to reduce field crowding at the trench corners and thus to increase the breakdown voltage, in the structure shown in Figure l (a) they are used to stop expansion of the depletion region. The drift region length of a structure like that shown in Figure l (a) is therefore only about half those of the traditional AC switches which use a non-punch-through structure to avoid the reachthrough problem. With a structure like that shown in Figure l (a), a 1000V AC switch can be achieved with a drift region length of about 55m. This greatly contributes to the significantly reduced on-state voltage drop of the device.
The Lateral Structure Referring now to the lateral structure shown in Figure l (b), the depletion of various parts of the switch 10 and the potential self-reference of the N-and P-drift sub-regions 21,22 and their charge balance all take place in the same way as described above for the vertical structure. However, because of the presence of the substrate 19, the voltage
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blocking characteristics of the lateral device 10 are different from that of the vertical device due to the threedimensional potential (electric field) distribution. In order to evaluate its voltage blocking capability, such a device was simulated in a three-dimensional device simulator.
The simulated silicon-on-sapphire lateral device 10 had the following parameters: thickness of the silicon layer:
ami thickness of the sapphire layer : 500pu ; width of the Nand P-drift sub-regions : 4m/4mi doping of the N-and P- drift sub-regions: 5xl0cm-3/5xl0"cm-3 ; spacing between two adjacent trenches: 2m.
The three-dimensional potential distribution of this device is shown in Figure 3 (a). In the structure shown, field oxide and passivation oxide have been added and the metal of both terminals has been extended to form field plates.
It can be seen from Figure 3 (a) that the potential lines (or, more strictly, potential planes) in the lateral structure do not distribute as evenly along the drift region 20 as those shown in Figure 2 (a) for the vertical structure. This is caused by bending of the potential planes in the sapphire substrate 19 at both ends of the switch 10. As a result, potential planes crowd at both ends of the drift region 20 and cause two electric field peaks as shown. The high permittivity of sapphire also contributes to the crowding and the electric field peak. This indicates that the close-touniform electric field distribution along the drift region 20
<Desc/Clms Page number 13>
for the vertical structure as shown in Figure 2 (a) cannot be obtained with a lateral structure. The drift region length
required to achieve the same breakdown voltage (1000V) is significantly increased (125m) when compared with that of the vertical structure (55jj, m).
In order to relieve the crowding of the electric field at both ends of the drift region 20, the gate trenches can be deepened in order to extend into the substrate 19. A structure with the gate trenches extending Sum into the substrate was therefore simulated. other parameters of this second lateral structure (with trenches into the substrate) were the same as for the first lateral structure (without trenches into the substrate) described above. The results are shown in Figure 3 (b). A comparison between Figures 3 (a) and 3 (b) suggests that the deep trenches stopped the bending of the potential planes in the top part of the substrate. This reduces the field crowding at both ends significantly. With this technique, a 1000V breakdown voltage can be achieved with a drift region length of 80pu.
FORWARD CONDUCTION Depending on the biases of the two Gates 1,2, the vertical and lateral devices 10 can operate in several different modes. Considering for the purposes of illustration the case when current flows from Terminal 1 to Terminal 2, Gate 2 should be positively biased via its Terminal 4
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(referenced to Terminal 2) to turn on the N-channel in the Ndrift sub-region 21. However, the bias of Gate 1 (via its Terminal 3) is not restricted.
If Gate 1 is shorted to Terminal 1, the device 10 operates in an IGBT mode with minority carrier injection. If Gate 1 is negatively biased, a P+ layer is formed around the oxide 15 of Gate 1 in the N-and P-drift sub-regions 21,22.
This enhances the hole injection from the P well (s) 12 at Terminal 1 and the device 10 operates in an enhanced IGBT mode. If Gate 1 is positively biased, injection of the minority carriers from the P well (s) 12 at Terminal 1 is inhibited and the device 10 operates in a MOSFET mode.
In the discussion that follows, all values are given for a device area of lcm2 unless stated otherwise.
The Vertical Structure The on-state I-V curve of the vertical structure 10 described above operating in IGBT mode is plotted in Figure 4 (a). Due to the short drift-region length and reasonably long carrier lifetime used, a very low on-state voltage (for example of around 1. IV) can be achieved at 200A/cm2, which is equivalent to a specific on-resistance of only around 5. 5mQcm2. The specific on-resistance of the device operating in 3D MOSFET mode is around 50mQcm2 for a 1015/em) N-/P-stripe doping.
<Desc/Clms Page number 15>
The Lateral Structures The on-state characteristics of the lateral structures
described above are shown in Figure 4 (b). Both lateral devices 10 have a breakdown voltage of 1000V. The devices 10 are operating in IGBT mode with a minority carrier lifetime of 200ns. For the second lateral device (with trenches into the substrate), a 2.8V voltage drop at 20A/cm2 indicates an equivalent on-resistance of 140mQcm2. The equivalent on-resistance of the first lateral device (without trenches in
the substrate) at the same current density is about 250mQcm2.
These specific-on-resistances can be further reduced if the devices 10 are operated in the enhanced IGBT mode.
It is worth noting that since only a thin layer of silicon (of thickness of say 2jim) is used for current conduction on the lateral devices, a 20A/cm2 effective current
density indicates a real current density of 1000A/cm2 and lS00A/cm2 in the silicon layer for the lateral devices 10 with and without trenches in the substrate 19 respectively.
In the lateral devices 10, increasing the length of the drift region 20 has the following two negative effects on the specific on-resistance. First, the resistance of the drift region 20 increases and the effect of minority carrier injection is weakened. Second, a higher current density has to be conducted in the silicon layer to achieve the same effective chip current density, as shown by the data above.
<Desc/Clms Page number 16>
The conduction ability of the device 10 operating in a MOSFET mode is similar to that of the 3D MOSFET discussed in F. Udrea, et. al., "3D Resurf Double-Ga te MOSFET: A Revolutionary Power Device Concept", Electronics Letters, Vol.
35, No. 8, April 1998. The specific on-resistance of the simulated lateral devices 10 in this mode are 1. 17Qcm2 and 1. 95Qcm2 respectively.
TURN-OFF Depending on the transient bias applied to the two Gates, the device 10 can be turned off in different modes. Four possible modes are listed in Table 1 below when the device 10 is turned off from IGBT conduction mode with current flowing from Terminal 1 to Terminal 2.
<Desc/Clms Page number 17>
No. Gate 1 Gate 2 Description 1 OV 10 to OV Normal IGBT turn-off 2 10 to-10V Extra hole sweep-out paths created; P-floating regions to P well of Terminal 2 3 0 to 10V 10 to OV Electrons extracted from gate 1 channel; holes swept-out from P well of Terminal 2 4 10 to-10V Electrons extracted from gate 1 channel; extra hole sweep-out paths created; P-floating regions to P well of Terminal 2 Table 1 Possible Turn-Off Modes of the Device From IGBT Conduction It can be seen that by applying a negative pulse to Gate 2, an inversion layer is created in the N-drift sub-region 21 around Gate 2. This provides extra hole sweep-out paths from the floating P-drift sub-regions 22 to the P well 12'and thus speeds up the whole turn-off process.
The Vertical Structure Waveforms of the vertical device 10 described above turning off in the first mode listed in Table 1 are shown in Figure 5. Because of the short drift region length, the turn-off transient is very short. A relatively long delay time is observed because of the large gate capacitance
<Desc/Clms Page number 18>
associated with the trenches. However, this can be improved by using negative gate bias turn-off and/or reducing the gate drive impedance (2Qcm2 being used in the simulation).
The Lateral Structure Waveforms of the lateral device 10 without deep trenches in the substrate 19 described above when turning off in the first and third modes listed in Table 1 are shown in Figure 6 (a). As mentioned in Table 1, when Gate 1 is forward biased to Terminal 1, its MOS channel is turned on and a path is provided for the electrons in the N-and P-drift sub-regions 21,22 to be extracted out. The effects of this mechanism can be clearly seen in Figure 6 (a) where turn-off behaviour in mode 1 and in mode 3 are compared. As can be seen, by extracting the electrons in the drift region 20 via the channel provided by Gate 1, the current tail duration is significantly reduced, thereby achieving rapid turn-off.
Similar effects can be found for the deep trench lateral device whose turn-off transients are shown in Figure 6 (b).
Because of the shorter drift region length and hence less stored charge, turn-off of the lateral device 10 with deep trenches is faster than for the lateral device 10 without deep trenches.
<Desc/Clms Page number 19>
ESTIMATE OF LOSSES IN A PRACTICAL APPLICATION A first order estimate can be made about the losses of the three devices (i. e. vertical and lateral with and without deep trenches into the substrate) described above. The estimates are made in a system with the following specifications: Average supply voltage: 600V DC load current: lOA Average switching frequency: 100kHz or 20kHz Average switching duty cycle: 50% Number of AC switches in the system: 3 In the following table, device areas, conduction loss, switching loss, total losses, junction temperatures, system efficiency and size, are estimated for the three AC switches simulated and a 4-device AC switch based on commercially available devices. In the table, the lateral devices with and without deep trenches are referred as Lateral 1 and Lateral 2 respectively. In the calculation, the input power of the system was assumed to be 3kW. Furthermore, the dynamic losses of the diodes in the 4-device AC switch was not included.
<Desc/Clms Page number 20>
Device Conduct-Switch-Total R Tjfa) Tj@ Effic-System Area ion loss ing loss @ (kil) 100kHz 20kHz iency@ size (cm2) power (W) loss 100kHz (. C) (. C) 100kHz (mJ) (W) vertical 0.1 0.93 0.1 19.3 2.5 75 55 98. 1% small Device Lateral 1 0.25 4 0. 15 35 2 97 73 96. 5% small Lateral 2 0.4 6 0. 2 50 1.8 117 95 95% small 2 IGBTs + 0. 4 2.5+1. 5 1.5 170 1.1 214 82 83% large 2 diodes (in (fail) (fail) total) Table 2 A Comparison for the Three Simulated AC Switches and a Conventional Counterpart Table 2 shows that the vertical device simulated is by far the most superior. Although the two lateral devices do not offer advantage in respect of the conduction voltage over the conventional device, their switching speed is about one order of magnitude faster than commercially available IGBTs.
Therefore, these lateral devices offer the best advantages at high frequency applications.
An embodiment of the present invention has been described with particular reference to the examples illustrated.
However, it will be appreciated that variations and modifications may be made to the examples described within the scope of the present invention.
<Desc/Clms Page number 21>
For example, the structures described herein can be used with other semiconductor materials, such as for example SiC, GaN, etc. The lateral structures can be formed on other substrates, such as for example SOI, DI (dielectric isolation), Silicon-on-Diamond, Sic, etc. More variations in operation are possible if for example the two Gate 1s and the two Gate 2s formed by the re-filled trenches (Figures l (a) and (b) ) are biased separately.
Although the P-and N-drift regions are drawn as strips in the figures, other variations such as hexagonal, circular and spiral could also be used.

Claims (8)

  1. CLAIMS 1. A bi-directional semiconductor switch that can selectively conduct current and block voltage in both directions, the switch comprising: a first terminal region of a first conduction type, the first terminal region having at least one highly doped region of a second conduction type formed therein; a second terminal region of the first conduction type, the second terminal region having at least one highly doped region of a second conduction type formed therein; a drift region comprising at least three adjacent voltage-floating drift sub-regions that alternate in conduction type transversely of the first and second terminal regions, the at least three drift sub-regions comprising a first drift sub-region of the second conduction type extending between the first and second terminal regions and second and third drift sub-regions each of the first conduction type and respectively located either side of the first drift subregion; a first gate to which a voltage can be applied to modulate charge in the first drift sub-region in the vicinity of the first terminal region; and, a second gate to which a voltage can be applied to modulate charge in the first drift sub-region in the vicinity of the second terminal region.
  2. 2. A switch according to claim 1, wherein at least one of the gates is provided by a trench having a dielectric-coated
    <Desc/Clms Page number 23>
    wall adjacent the portion of the drift sub-region in which the charge is modulated by applying a voltage to said gate.
  3. 3. A switch according to claim 1, wherein each gate is provided by a trench having a dielectric-coated wall adjacent the portion of the drift sub-region in which the charge is modulated by applying a voltage to said gate.
  4. 4. A switch according to any of claims 1 to 3, wherein the device is a vertical device with first and second terminals positioned on opposed end walls, the first terminal being in electrical contact with the first terminal region of the first conduction type and the highly doped region of the second conduction type provided therein, and the second terminal being in electrical contact with the second terminal region of the first conduction type and the highly doped region of the second conduction type provided therein.
  5. 5. A switch according to claim 1, wherein the device is a lateral device with the first terminal region of the first conduction type, the second terminal region of the first conduction type and the drift region all being provided at one surface of a substrate.
  6. 6. A switch according to claim 5, wherein at least one of the gates is provided by a trench having a dielectric-coated wall adjacent the portion of the drift sub-region in which the charge is modulated by applying a voltage to said gate, the at least one trench extending into the substrate.
    <Desc/Clms Page number 24>
  7. 7. A switch according to claim 5, wherein each gate is provided by a trench having a dielectric-coated wall adjacent the portion of the drift sub-region in which the charge is modulated by applying a voltage to said gate, each trench extending into the substrate.
  8. 8. A bi-directional semiconductor switch substantially in accordance with any of the examples as hereinbefore described with reference to and as illustrated by the accompanying drawings.
GB0113336A 2001-06-01 2001-06-01 Semiconductor switch Expired - Lifetime GB2380604B (en)

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US9742385B2 (en) 2013-06-24 2017-08-22 Ideal Power, Inc. Bidirectional semiconductor switch with passive turnoff
US9799731B2 (en) 2013-06-24 2017-10-24 Ideal Power, Inc. Multi-level inverters using sequenced drive of double-base bidirectional bipolar transistors
JP6491201B2 (en) 2013-06-24 2019-03-27 アイディール パワー インコーポレイテッド System, circuit, device, and method having bidirectional bipolar transistor
US11637016B2 (en) 2013-12-11 2023-04-25 Ideal Power Inc. Systems and methods for bidirectional device fabrication
US9355853B2 (en) 2013-12-11 2016-05-31 Ideal Power Inc. Systems and methods for bidirectional device fabrication
WO2016073957A1 (en) 2014-11-06 2016-05-12 Ideal Power Inc. Circuits, methods, and systems with optimized operation of double-base bipolar junction transistors

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US4574207A (en) * 1982-06-21 1986-03-04 Eaton Corporation Lateral bidirectional dual notch FET with non-planar main electrodes
US4622569A (en) * 1984-06-08 1986-11-11 Eaton Corporation Lateral bidirectional power FET with notched multi-channel stacking and with dual gate reference terminal means
US4622568A (en) * 1984-05-09 1986-11-11 Eaton Corporation Planar field-shaped bidirectional power FET
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US5793064A (en) * 1996-09-24 1998-08-11 Allen Bradley Company, Llc Bidirectional lateral insulated gate bipolar transistor
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US4622568A (en) * 1984-05-09 1986-11-11 Eaton Corporation Planar field-shaped bidirectional power FET
US4622569A (en) * 1984-06-08 1986-11-11 Eaton Corporation Lateral bidirectional power FET with notched multi-channel stacking and with dual gate reference terminal means
US5493134A (en) * 1994-11-14 1996-02-20 North Carolina State University Bidirectional AC switching device with MOS-gated turn-on and turn-off control
US5793064A (en) * 1996-09-24 1998-08-11 Allen Bradley Company, Llc Bidirectional lateral insulated gate bipolar transistor
US5977569A (en) * 1996-09-24 1999-11-02 Allen-Bradley Company, Llc Bidirectional lateral insulated gate bipolar transistor having increased voltage blocking capability

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CN105932050A (en) * 2016-06-13 2016-09-07 电子科技大学 Planar gate IGBT and manufacturing method therefor
CN105932050B (en) * 2016-06-13 2018-09-04 电子科技大学 A kind of planar gate IGBT and preparation method thereof

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