GB2294821A - Multilevel converter - Google Patents

Abstract

A multilevel convertor 30 for connection in shunt or in series with each phase of a single or multi-phase AC system is configured as a chain comprising a plurality of links, each of which comprises a voltage-commutated convertor providing a multilevel AC voltage, and a main control arrangement for controlling a switching sequence of the voltage-commutated convertor such as to provide a total voltage across the ends of the chain which is an aggregate of the individual multilevel voltages of the voltage-commutated convertors. Each voltage-commutated convertor may consist of a bridge and a DC source or sink. The DC source or sink may be either a capacitor, a battery or a DC-AC or AC-DC convertor. The multilevel convertor may also include voltage-balancing means to maintain desired absolute or relative voltage levels on the DC sources or sinks within the chain. The convertor may include GTO or IGB: devices and various circuits are described (Figs. 7 - 15). The control arrangement to regulate the convertor is described (Figs. 17 - 22). A capacitor clamping arrangement (Figs. 23 - 25) may be provided. <IMAGE>

Description

MULTILEVEL CONVERTOR The invention concerns a multilevel convertor for connection in shunt or in series with a single-phase, or with each phase of a multiphase, AC system.

Static VAr compensators (SVCs) are used in ratings typically from lMVAr to 100MVAr or more in AC power transmission and distribution systems to control and stabilise AC voltage. These are devices normally connected in shunt to the AC system and can generate variable lagging or leading reactive current, (or volt-amperes reactive (VAr)), in dependence on a control system. Since the effective source impedance of an AC power system is practically always inductive, the AC voltage can be changed, or alternatively can be held constant, for example, in the presence of varying ACsystem load currents, by appropriate control of SVC current.

Figure 1 shows an example of such an arrangement, in elementary form, in a single-phase system, in which the AC source is represented as an equivalent emf 10 which supplies a busbar 11 by way of a reactance 12. A load 13 is connected to the busbar 11. The load 13 may draw a varying current from the busbar, and the voltage of the latter may vary as a result. An SVC 14 is shown connected in shunt to the busbar 11 via a reactance 15 and by suitable adjustment of its reactive current the SVC can, for example, effectively hold the voltage level on busbar 11 constant.

Other system arrangements and control functions other than constant voltage can alternatively be implemented; for example, an SVC connected in shunt to the middle of a long transmission line connecting two AC generating systems can be controlled to change AC voltage, and consequently transmitted power, in a manner such as to damp electromechanical oscillations between the two systems.

Practical forms of SVC behave effectively as variable inductive or capacitive reactance. drawing variable reactive current but practically zero real current (neglecting SVC component losses). One well-known form of such a device is the thyristorcontrolled reactor.

Another form of SVC is the voltage-commutated (or "voltage-source" ) convertor. These use electronic switching devices which, for high ratings, are normally gate-turn-off thryristors (GTOs). In this circuit the AC side of the convertor is connected to the AC system terminals via an inductor, and the DC side is connected to a capacitor charged to an approximately constant DC voltage. A particular form of such circuit is known as a "multilevel convertor" in which a set of capacitors connected directly in series are each charged to a DC voltage, and multiple switching devices are arranged to connect the AC terminal to each capacitor junction (tapping point) in turn in a cyclic manner during each cycle of AC system frequency to generate a voltage waveform which is a stepped approximation to a sine wave.This can be defined as an n-level waveform if the waveform has n voltage levels per cycle of AC system frequency, including a zero voltage level, if any.

A known example of a switching circuit suitable for a multilevel convertor is disclosed in United States Patent No. 4,270,163. This has the disadvantage that it requires auxiliary diodes which, for high-voltage equipment with many series capacitors, are expensive since the sum of their ratings increases more rapidly, in relative terms, than the increase in the number of capacitors.

A further known example is given by French Patent No. 91,09582, in which there is also a set of capacitors, though these are not directly series connected and are charged to different DC voltages. For high plant ratings requiring large GTOs, the switching rate of the GTOs is practically limited to one turn-on and one turn-off per GTO per cycle at power frequency; large capacitors of high cost are therefore necessary in the convertor of FR 91,09582 in order to sustain voltage between switchings.

An SVC can be considered to comprise a variable reactive impedance connected in shunt to the AC system. It is also known to connect such a variable reactive impedance in series with a transmission line in an AC system. usually to interconnect two parts of the AC system. so as to improve system stability by control of AC system voltages. The general arrangement of this is shown in Figure 2. where one AC system is represented by an emf 17 and an impedance 18. the other similarly by an emf 19 and an impedance 20. The variable series impedance is shown as 21. Where the latter includes capacitors controlled by thyristors, it is generally known as a thyristorcontrolled series capacitor.

In accordance with the invention there is provided a multilevel convertor for connection in shunt or in series with a single-phase, or with each phase of a multiphase, AC system, in which the multilevel convertor is configured as a chain, the chain comprising a plurality of links each of which comprises a voltage-commutated convertor providing a multilevel AC voltage, and a main control arrangement for controlling a switching sequence of the voltage-commutated convertors such as to provide a total multilevel AC voltage across the ends of the chain which is an aggregate of the individual multilevel AC voltages of the voltage-commutated convertors.

The chain may comprise m links having respective multilevel voltages of levels flp where p=l, 2,...m and the main control arrangement is arranged to control the switching sequence of the voltage-commutated convertors such as to provide a total multilevel AC voltage across the ends of the chain having a number of levels N equal to:

In the special case where all the links have the same number of levels, n, the total number of levels in the chain, N, is given by: N = m (n - 1) + 1.

Each voltage-commutated convertor may comprise a plurality of switching means, which may be constituted by an electronic switch such as, for example, a GTO thyristor for higher powers. or an insulated-gate bipolar transistor for lesser ratings and a DC source or sink. the main control arrangement being arranged to render each DC source active in the chain over at least two separate time intervals during the period of an AC waveform of the AC system to which the multilevel convertor is connected.

The DC source or sink may be, for example, a capacitor. The electronic switches may be bi-directional switches, i.e. they may be capable of passing current in both directions. Such a bi-directional switch may comprise a GTO or an insulated-gate bipolar transistor together with a reverse parallel connected diode.

A major advantage of the chain-configuration multilevel convertor is that it can be constructed in indefinitely large plant-voltage and volt-amp ratings by adding identical chain links in series, without the problems associated with direct connection of GTOs or other switch types directly in series, because the DC capacitors are relatively large and tolerances on GTO internal charge-storage or firing times have negligible effect on voltage sharing between switches.

It is a further advantage of the chain arrangement that, in the event of failure of an electronic switch, which in high-power ratings will be to a short-circuit condition, the capacitor voltage in the particular chain link will collapse practically to zero and the link will make no significant further contribution to AC voltage. If the number of chain links is large, say ten or more, the resulting increase in voltages in other links will generally be acceptable. Harmonic distortion will increase, but it can be arranged to increase only to an extent corresponding to the relevant reduction in the effective number of levels in the AC voltage waveform.

Each np-level voltage-commutated convertor may comprise 2(np-1) switching means arranged as first and second parallel-connected branches in a bridge configuration, each branch comprising np-l series-connected switching means, one end of the parallel-connected branches forming a DC positive bridge terminal, the other end forming a DC negative bridge terminal, (np-1)/2 DC sources or sinks being connected in series to form a third branch in parallel with the first and second branches, a positive pole of the third branch being connected to the DC negative terminal of the first and second branches and a negative pole of the third branch being connected to the DC positive terminal of the first and second branches. first and second sets each of nr-3 diodes connecting tapping points of the first and second branches. respectively. to tapping points of the third branch, the AC terminals of the bridge being taken from midpoints of the first and second branches.

When no=3, the voltage-commutated convertor is a simple 4-switch bridge with one DC source or sink.

flp may equal 5, in which case the first and second sets of diodes will each comprise a first diode connected between a first tapping point on respective first and second branches and a midpoint of the third branch and a second diode connected between a third tapping point on respective first and second branches and the midpoint of the third branch, the midpoint of the first and second branches forming the remaining tapping point thereof and the first diodes being connected with their anodes towards the third branch and the second diodes being connected with their cathodes towards the third branch.

In one form of the multilevel convertor, in which the basic bridge configuration is modified, the chain may comprise two parallel branches between the ends of the chain, each branch comprising a plurality of switching means connected in series, corresponding junctions of the switching means in the two branches being linked together by a DC source or sink, the polarity of which is reversed at successive junctions going down the chain.

An advantage of this arrangement over the more usual bridge configuration is that there is a saving in the number of switches required for a given number of links.

Each chain link may comprise two or more parallel-connected bridge configurations connected to the same DC source or sink. When this is the case, corresponding AC terminals of the bridges of each link may be connected together by way of an inductance means to form respective ends of the link. This may apply throughout the chain. Alternatively, where link-ends adjoin each other inside the chain, the AC ends of one link may be connected to respective AC ends of the next link instead of to each other.

Where AC link-ends are connected together e.g. at the ends of the chain. the inductance means may take the form of a centre-tapped inductor or an interphase transformer, the centre-tap forming the single link-end. Where one of the ends of one link is connected to a corresponding end of the next link rather than to the other end of the same link, this connection may be made through a separate winding of an interphase transformer. Where there are two bridges in parallel, there will be two such windings connected up in antiphase with each other.

When the DC source or sink is a capacitor, there will be reactive power transfer only between the multilevel convertor and the AC system to which it is connected. The DC source or sink may, however, be a battery or a DC-AC or AC-DC convertor, in which case real power transfer is possible.

The multilevel convertor may comprise voltage-balancing means for maintaining the voltages across the DC sources or sinks at a desired relative or absolute value.

The voltage-balancing means may comprise a voltage equalisation means connected to each DC source or sink and arranged to maintain the voltages across the DC sources or sinks at a substantially equal value.

The voltage equalisation means may comprise an auxiliary voltage convertor having a DC port and an AC port the DC port being connected across the relevant DC source or sink and the AC port being connected to an auxiliary busbar arrangement, and an auxiliary control means, the auxiliary control means being arranged to control the various auxiliary voltage convertors of the chain such as to allow equalising currents to circulate between the DC sources or sinks of the chain by way of the busbar arrangement.

The voltage equalisation means may comprise a clamping means connected between each pair of DC sources or sinks and an auxiliary control means connected to the clamping means, the auxiliary control means being arranged to render the clamping means conductive, thereby shunting the relevant pair of DC sources or sinks across each other. at one or more points in the switching sequence of the voltage-commutated convertors.

The auxiliary control means may be arranged to render the clamping means conductive when the total voltage across the chain is substantially zero.

The clamping means may comprise a pair of bi-directional semiconductor switches in series-opposition connected in series with a resistive impedance between like poles of a pair of DC sources or sinks, the auxiliary control means being arranged to render the switch pair conductive when no main conductive path exists between said poles.

The voltage balancing means may comprise a subsidiary control loop arrangement arranged to combine first signals proportional to the mean DC voltage levels on the DC sources or sinks and second signals proportional to currents flowing through the DC sources or sinks, and to modulate the timing of the switching sequence of the voltagecommutated convertors in the chain by way of the main control arrangement in dependence on the result of the combination of the first and second signals such as to maintain the desired voltage values on the DC sources or sinks.

The subsidiary control loop arrangement may comprise a plurality of subsidiary control loops. each subsidiary control loop comprising a first combining means having a first input for receiving a first signal proportional to the difference between a mean DC voltage level on a respective DC source or sink and a further DC voltage level and a second input for receiving a second signal proportional to a current flowing through the chain during time slots which flank the active time interval of the respective DC source or sink.

The first combining means may be a multiplier and the subsidiary control loop may comprise a difference means having a first input for receiving the mean DC voltage level on the respective DC source or sink and a second input for receiving the further DC voltage level, an output of the difference means being connected to the first input of the first combining means.

The second input of the difference means may be arranged to receive a further DC voltage level which is proportional to a mean DC voltage level on another DC source or sink. the subsidiary control loop being thereby arranged to establish a desired relationship between the mean DC voltages on a respective pair of DC sources or sinks.

The number of subsidiary control loops may then be equal to one less than the number of DC sources or sinks in the chain.

The second input of the difference means may alternatively be arranged to receive a further DC voltage level which is a reference voltage level, the subsidiary control loop being thereby arranged to establish a desired absolute reference mean DC voltage level on the respective DC source or sink. For this case, the number of subsidiary control loops may be equal to the number of DC sources or sinks in the chain.

The subsidiary control loop, where it is required to establish a particular relationship between voltages on a pair of DC sources or sinks, may comprise a second combining means having an output connected to the second input of the first combining means and first and second inputs for receiving first and second signals proportional to the chain current during time slots which flank respective active time intervals of the respective pair of DC sources or sinks. The second combining means may be a subtractor.

The subsidiary control loop may comprise a weighting means in the first or second input of the second combining means, the weighting means serving to multiply the relevant first or second signal proportional to chain current by a desired weighting factor. The weighting means may be configured such as to multiply that signal proportional to chain current which is associated with a later-firing capacitor of the respective pair of capacitors by a factor of approximately two The subsidiary control loop may comprise a third combining means for providing the signal proportional to chain current, the third combining means having a first input for receiving a signal proportional to the chain current, a second input for receiving a strobe signal and an output connected to the second input of the first combining means.

The subsidiary control loop. where it is required to establish a particular relationship between voltages on a pair of DC sources or sinks. may alternatively comprise a pair of third combining means for providing first and second chain-current signals, the pair of third combining means having respective first inputs for receiving respective signals proportional to chain current, respective second inputs for receiving respective strobe signals and respective outputs connected to respective inputs of the second combining means. The first inputs of the third combining means may be connected together to receive a common signal proportional to chain current.

The multilevel convertor may comprise a current transformer in series with the chain, the current transformer having a secondary winding for providing the signal proportional to chain current.

The subsidiary control loops may comprise a respective second strobing means for deriving the first signal proportional to the voltage across the respective DC source or sink, the second strobing means having first and second inputs for receiving, respectively, a signal proportional to a phase voltage appearing across the chain and a strobe signal timed to coincide with a period during which the respective DC source or sink is rendered active in the chain, the second strobing means having an output for providing the first signal proportional to the voltage across the respective DC source or sink.

The multilevel convertor may comprise two chains connected in parallel by way of an inductance means. Where the convertor is employed in a three-phase AC system, there will be three such two-chain multilevel convertors in total.

The main control means may comprise a parameter-measuring means for measuring a parameter to be regulated by the multilevel convertor and a comparing means, the comparing means being arranged to compare an output of the parametermeasuring means with a desired value of the relevant parameter and forming from the comparison an error signal for adjusting firing angles of switching devices used in the voltage-commutated convertors of the chain such as to effect regulation of the relevant parameter.

The parameter-measuring means may comprise means for measuring AC or DC voltage or current or reactive power or real power or phase angle relating to one or more AC systems to which the multilevel convertor is connected. or to the convertor itself.

The invention will now be described, by way of example only, with reference to the drawings, of which: Figure 1 is a circuit diagram showing a basic arrangement of a static VAr compensator (SVC) in an AC system; Figure 2 is a circuit diagram showing a basic arrangement of a series controlled variable reactance in an AC system; Figure 3 is a circuit diagram of a first embodiment of the multilevel convertor according to the invention; Figure 4 is a diagrammatic representation of a bi-directional switch; Figure 5 is a waveform diagram for the link 31 in the multilevel convertor of Figure 3; Figure 6 is a waveform diagram for the complete 3-link convertor of Figure 3; Figure 7 is a circuit diagram of a second embodiment of the multilevel convertor according to the invention; Figure 8 is a circuit diagram of a third embodiment of the multilevel convertor according to the invention;; Figure 9 is a diagram of an interphase transformer for use with the circuit of Figure 8; Figure 10 is a circuit diagram of a fourth embodiment of the multilevel convertor according to the invention; Figure 11 is a diagram of an interphase transformer arrangement for use with the circuit of Figure 10: Figure 12 is circuit diagram of a fifth embodiment of the multilevel convertor according to the invention; Figure 13 is a diagram showing the use of two multilevel convertors according to the invention employed per phase: Figure 14 is a circuit diagram of the multilevel convertor arrangement of Figure 3 employing an auxiliary convertor for the equalisation of the DC sources: Figure 15 is a circuit diagram of a bi-directional auxiliary convertor:: Figure 16 is a waveform diagram showing waveforms used for the voltage balancing of a single capacitor; Figure 17 is a circuit diagram of part of a subsidiary control loop for use in the multilevel convertor of the invention; Figure 18 is a circuit diagram of a current strobing arrangement for use in the subsidiary control loop of Figure 17; Figure 19 is a waveform diagram showing waveforms used for the voltagebalancing of pairs of capacitors; Figure 20 is a circuit diagram of a weighting arrangement for use in the subsidiary control loop of Figure 17; Figure 21 is a circuit diagram of a voltage strobing arrangement for use in the subsidiary control loop of Figure 17; Figure 22 is a waveform diagram showing strobing waveforms obtained with the strobing arrangement of Figure 21;; Figure 23 is a circuit diagram of a capacitor clamping arrangement for use with a multilevel convertor according to the invention; Figure 24 is a representation of one type of clamp for use in the clamping arrangement of Figure 23, and Figure 25 is a representation of another type of clamp for use in the clamping arrangement of Figure 23.

Referring now to Figure 3, Figure 3 shows a first embodiment of a multilevel convertor 30 according to the invention. The convertor 30 is in the form of a chain having three links 31, 41, 51, the chain having two terminals 61 and 62. Thus the convertor 30 can be connected to a single-phase AC system in the same way as the convertors 14 and 21 in Figures 1 and 2.

Each link is a circuit comprising four electronic switching devices 32-35. 42-45, 52-55 configured as a single-phase bridge. A DC source or sink in the form of a capacitor 36. 46. 56 is connected to the DC side of the respective bridge. a positive pole of the capacitor being connected to the commoned anodes of the bridge GTOs, a negative pole to the commoned cathodes. The switching devices are required to be capable of bi-directional current conduction in the ON-state and are constituted by gateturn-off thryristors (GTOs) with reverse parallel diodes, as shown in Figure 4.

However, for the sake of simplicity, the switching devices in this and later drawings are shown simply as GTOs. For operation as an SVC, the chain is preferably connected to the AC system busbars by way of an inductance such as the inductance 15 in Figure 1. This may in practice be the leakage inductance of an isolating transformer (not shown) and may therefore not take the form of a separate device.

To explain the mode of operation, first consider link 31 alone. Assume capacitor 36 is charged to a substantially constant voltage V with polarity as shown. The switches 32-35 are turned ON and OFF via their gates from a control system (not shown) such as that shown in co-pending UK patent application 9400285.4. The contribution of link 31 to the total AC voltage VAC across the chain is shown as a waveform 65 in Figure 5. The AC current 66 is also shown and is assumed to be practically sinusoidal; as shown, it is leading the voltage, though in practice it may be lagging or leading as required.

The contribution of the single link 31 to the AC voltage VAC is +V, 0 or -V, as follows:

Switches turned Contribution to ON AC Voltage 33, 34 32, 34 or 33, 35 0 32, 35 -V The operation of the single link 31 can be characterised by a firing angle shown as 0 in Figure 5. This is the time in electrical degrees or radians of turning on switches 33. 34 in each cycle, the remaining switching times being assumed to be respectively at (7r-8,). (7r+0,) and (27r-0,) as shown so as to produce a symmetrical waveform in order to eliminate DC or even harmonics in it.Thus capacitor 36 is rendered "active" in the chain over two time intervals each of 'r-20i. The waveform of a single link is defined as a 3-level waveform, including the zero voltage level, and one link may be considered to be a 3-level voltage-commutated (or voltage-source) convertor operating at zero real power. The remaining chain links operate similarly but may have different characteristic firing angles 82 and 83.

The total AC voltage for the 3-link circuit of Figure 3 is then as shown in Figure 6, giving the 7-level voltage waveform 67 which, for equal voltages V on each capacitor, corresponds to an overall voltage at any instant in the set +3V, +2V, +V, 0, -V, -2V, -3V. The firing angles 8,, 82, 83 are normally chosen to produce a waveform which is a close approximation to a sine wave.

The currents in each capacitor 36, 46, 56 are shown as waveforms 68, 69 and 70, respectively, for one particular switching sequence of the capacitors 36, 46, 56. i.e.

the sequence:

- 36 36 36 36 36 36 36 36 36 11 ACTIVE 46 46 46 46 46 46 CAPACITORS Positive Negative CHAIN 56 0 | | 56 Due to the basic chain configuration of the multilevel convertor of the invention, the three currents 68-70 constitute the chain current 66 through the end terminals 61, 62 during those times when the respective capacitor is active in the chain.

A second embodiment of the invention is illustrated in Figure 7. This arrangement is very similar to that of Figure 3, but the four switches coupling one capacitor to the next in Figure 3, e.g. switches 34, 35, 42, 43. are replaced by two switches 81, 82 only. Likewise, switches 83, 84 replace switches 44,45, 52, 53 in Figure 3. In view of this modification of the basic topology, the capacitors must be reversed in polarity in sequence going down the chain, as shown. The gate switching pattern is necessarily different from that of the first embodiment, but again it can be arranged to provide a net voltage in the set +3V, +2V, +V, 0, -2V, -3V for the 3-link chain as before, with similar overall waveforms. Current waveforms 68-70 may be different depending on the order in which the capacitors are made active in the chain.

Figure 8 shows a third embodiment of the invention, this time showing two links 91, 101 only. This is similar to the first embodiment (Figure 3) except that in each link there are effectively two single-phase bridges connected in parallel to provide double the total AC current rating and sharing the same capacitor. The first bridge of the first link 91 is formed by switches 92A-95A, while the second bridge of the same link is formed by switches 92B-95B. To ensure equal current sharing of the switches, individual inductors 97A,B, 98A,B, 107A,B and 108A,B are shown in the AC connections to each bridge.This circuit can be operated with the switches in each bridge in any link gated synchronously, in which case circuit operation is identical to that of the first embodiment, except for the doubled current rating and the introduction of extra series inductance in the chain, which is generally beneficial. Alternatively, the two bridges in each link can be gated with different characteristic angles, whereby the effective number of voltage levels on the total phase voltage may be nearly doubled, giving the possibility of a reduction in the harmonics which are generated.

Each pair of inductors shown in Figure 8. e.g. inductors 98A, 98B, 107A and 107B and those at the ends of the chain may be replaced by an interphase transformer 110, as shown in Figure 9. Thus, for instance, inductors 107A and 107B are replaced by the two half-windings of the centre-tapped transformer 110 (see connection points C. D and E in Figure 8).

A fourth embodiment of the invention is shown in Figure 10, which again shows two links only. Here the four inductors coupling any pair of chain links in the third embodiment (Figure 8) are reduced to two. Again. the inductors may be replaced by interphase transformers. Those required at the chain ends are as shown in Figure 9.

The inter-link couplings, however, require a minor modification of the interphase transformer by arranging it to have separated windings as shown in Figure 11. In this arrangement, the transformer 111 in Figure 11 has its windings wired in antiphase with each other to their respective bridge-halves at points F, G and H, J.

In a fifth embodiment, shown in Figure 12, each link, of which only links 120, 140 are shown, comprises a 5-level multilevel convertor configured as a bridge. As shown, switches 121-124 in link 120 form the known type of 3-level biphase voltagecommutated convertor, in conjunction with the two-capacitor stack 129, 130. Switches 125-128 share the same capacitors and operate similarly, but may have a different set of firing angles. Diodes 131-134 are connected as two groups between the midpoint of the capacitor stack and the switch junctions of respective switch branches 135, 136.

The total voltage between terminals P and Q of link 120 is thus a 5-level waveform.

Two such links as shown with the four characteristic angles all different produces a net voltage from P to R having 9 levels.

Current sharing or voltage-level extension is also possible with this embodiment, as with the embodiments of Figures 8 and 10, by connecting further columns of switches in parallel sharing the same capacitor stack. As for the other circuits, the paralleling on the AC terminals of the switch columns is preferably by either inductors or interphase transformers.

It is also possible to connect two or more complete chain circuits in parallel, as the chain circuits 151, 152 in Figure 13. The circuits are here paralleled via individual inductors 153, 154, but one or more interphase transformers may alternatively be used.

In general, the effective number of steps in the AC voltage waveform increases as more switches are used, provided switches are not switched at the same time instants.

This applies whether link bridges are added in series or in parallel. As mentioned earlier. this allows for a reduction in generated harmonics.

Although described above in terms of their use in single-phase AC systems. the chain circuits may also be applied to a 3-phase system using three chains or groups of chains. In the case where the equipment is an SVC, it will usually be preferable to connect three chains in a star connection, though a delta connection is possible if there are internal inductances, as in the embodiments of Figures 8 and 10, or if inductors are specifically added in each chain. For use as a series device in an AC line in the manner of a thyristor-controlled series capacitor, three independent chains may be used, directly connected.

It will often be an advantage to connect the variable reactive impedances to highvoltage AC systems via isolating transformers, to provide for more convenient voltages and currents in the chain components.

In each of the embodiments described above, the DC source or sink has been a capacitor which can pass zero mean current and therefore zero mean power. It is, however, also possible to replace each capacitor by a device which is a source or sink of real power. One example is a battery, for which the main control system may, for example, be arranged to hold the batteries fully charged in most conditions, but to provide for delivery or absorption of real power at the main AC terminal during emergencies when generators or loads are lost in the power system, using firing-angle control methods known for voltage-commutation convertors.

Another possibility for a DC source is shown in Figure 14, in which part of a chain shown in Figure 3 is redrawn for convenience and an individual diode rectifier, shown as a block 161-163 for the three links concerned, is connected in parallel with or in place of each capacitor. Each rectifier is supplied from a second AC power system 164 via transformers 165-167, respectively, fed from common busbars 168.

With such a simple arrangement, power flow can only be unidirectional, i.e. from the second AC supply 164 to the main AC system. Bi-directional current flow can, however, be achieved by replacing each diode rectifier 161-163 by a set of bidirectional electronic switches, as in Figure 15. to form a further voltage-commutated convertor in each chain link.

The further voltage-commutated convertor 161 shown in Figure 15 is a bridge configuration similar to the convertor in the chain link 31 of Figure 3. for example. and shares the same capacitor 36. Convertor 161, however, is switched in dependence on the frequency of the AC supply 164 (see Figure 14) which may or may not be the same as the frequency of the main AC system to which the chain convertor is connected. The main voltage-commutated convertor of each link and its associated auxiliary convertor thus act as a back-to-back (i.e. AC-AC) convertor arrangement.

The AC system 164, busbars 168 and convertors 161-163 may all be configured for 3-phase instead of single-phase.

All voltage-commutated multilevel convertors using capacitors only as the AC source or sink (i.e. without means for real power flow) including the chain circuits discussed here, suffer from poor grading between the voltages on the various DC capacitors in the absence of special arrangements. For example, one convenient design method is for all capacitor DC voltages to be assumed equal and choice of the various firing angles may be for minimum harmonic generation based on this assumption. In reality, however, although the sum of all capacitor voltages may be held at a suitable value by a main control system, individual capacitor voltages can settle at values which are widely unequal, giving excessive harmonic generation and excessive voltages on some capacitors and their associated switches.

Various means of controlling the voltages of capacitors either to predetermined absolute values or to predetermined relative ratios (usually unity) will now be described.

The process of correcting for the above-mentioned trend towards divergent capacitor voltage values will hereinafter be referred to as "capacitor balancing".

A preferred method of effecting capacitor balancing is to employ subsidiary control loops along with the main control loop which regulates the quantity, e.g. AC system busbar voltage, which the multilevel convertor is required to control. Such a main control system is described in co-pending UK Patent Application 9400285.4. This system temporarily adjusts individual firing angles from the nominal values set by the main control system such that the portions of main AC current which flow in the capacitors are temporarily changed in a sense to produce mean DC currents in each capacitor in a direction to correct errors in the relative capacitor voltages.

The principle behind this correction method is illustrated in Figure 16, which shows the multilevel phase voltage 67 and phase current 66, i.e. the current through the chain, as in Figure 6, and also the current i46 which flows in the capacitor 46, purely as an example. If it is assumed that the subsidiary control system is arranged to hold the capacitor voltages in the chain at a fixed reference voltage, and the voltage across capacitor 46 is lower than that reference value, it is clear that by firing the relevant GTO switches associated with that capacitor such as to render the capacitor active in the chain earlier in the AC cycle, the net charge on the capacitor can be made to increase, thereby increasing its voltage towards the reference level.This change in firing timing is achieved as a modulation of the normal control loop timing and can be seen in Figure 16 as a change from the original firing- ON/firing- OFF times a,b and d,e to new times a',b' and d', e'. The above modulation takes place by an injection of a modulating signal into the main control loop, the modulating signal being in practice added to an error signal formed by the difference between a quantity to be controlled.

e.g. AC system voltage, and a reference value for that quantity.

It is assumed that the main control system has an integral characteristic, i.e. that the change of GTO firing time, for example the time t2 corresponding to the angle 82, is an integral function of the error in the main control loop (not shown - reference is made to Figure 4 of the earlier-mentioned co-pending UK Application) over the previous time segment that2, and similarly for all the other time segments, e.g. t2-t3, etc.

This is obtained, for example, by the use of an indirectly locked oscillator control system. the "oscillator" here referring to a VCO used in the main control loop as a timing generator for the various GTOs in the chain. In such an indirectly locked control arrangement, the VCO phase is locked via the main control loop and includes the entire main circuit and AC system. In this kind of system, the deviation of the VCO input voltage from zero tends to cause a proportional change in the frequency of the VCO. For other types of basic control system having a proportional rather than integral characteristic. the same effect can be obtained by adding a substantially integral function in the subsidiary loop in the path of the modulating signal Vm shown in Figure 17 (referred to below).

A suitable (idealised) form of modulating signal function Vlm is then as shown by the solid waveform in the lower part of Figure 16 and comprising rectangular pulses such as lmnp. The changes of timing at the end of each pulse are then proportional to the time-integral of these pulses. Such a fixed amplitude modulating signal can easily be generated using electronic logic components controlled in time from suitable outputs of a ROM driven from the VCO in the main control circuit, as shown in Figure 4 of co-pending UK 9400285.4. However, this has the drawback that, when the convertor is used, for example, as an SVC, such a fixed modulating signal is suitable only for one condition, e.g. operation in the leading AC current mode (the SVC acting as a capacitive reactive power source).If SVC operation were then required to change to the lagging AC current mode (SVC acting as an inductive reactive power source), it would be necessary to reverse the polarity of the modulating signal, otherwise the closed subsidiary control loop would have a positive loop gain and become unstable.

This drawback can be obviated by deriving the modulating signal Vlm from a measurement of the current flowing through the chain, i.e. current 66 in Figure 16.

This cures the problem, since when the AC current waveform reverses in direction, i.e.

goes from leading current through zero current to lagging current, and vice-versa, due for example to normal changes in the AC system, the polarity of the modulating signal automatically reverses and consequently the loop gain in the subsidiary loop can be arranged always to be negative, resulting in stable operation.

Such a derived waveform is shown as the dotted portion in Figure 16. The waveform for such a modulating signal differs in detail from the so-called "ideal" modulation signal lmnp, but since the main control system is assumed to have an integral response, only the areas underneath the pulses, not the pulse shapes themselves, are relevant.

A balancing circuit arrangement to achieve the above voltage-balancing process is shown in Figure 17. In Figure 17, one of a number of subsidiary control loops is shown comprising a subtractor 171, a multiplier 172 and an adder 173. The subtractor 171 has on its two inputs a first voltage V46 proportional to the mean DC voltage on, in this case, capacitor 46, and a second voltage VREF, which is a reference voltage. The output of the subtractor 171 feeds one input of the multiplier 172, while the other input of the multiplier 172 receives a modulating signal Vlm mentioned earlier in connection with the derivation of the modulating chain current signals for modifying the firing of the GTOs.The output of the multiplier 172 is summed with similar multiplier outputs from the other subsidiary control loops in adder 173, these other control-loop outputs being fed to input 174 of adder 173. The sum signal at the output of adder 173 is fed to a controlling input of the VCO in the main control loop (not shown).

In the case of a subsidiary control loop which is intended to hold capacitor voltage at a reference value, as in the above case, the signal Vlm on the second input of the multiplier 172 is derived directly from the chain current by means of a strobing circuit. In this control scheme there are as many subsidiary control loops as there are DC sources or sinks.

Such a strobing circuit is shown in Figure 18. In Figure 18, a multiplier 181 is connected via one of its inputs to the secondary winding of a current transformer 182, and via the other input to a strobing signal. In this case, since the subsidiary control loop in question is that governing the voltage on capacitor 46, the strobe signal consists of voltage pulses occurring at times t,-t2 and t5-t6. The output of multiplier 181 is the modulating signal Vlm which, as mentioned above, feeds the second input of the multiplier 172.

Similar strobing arrangements are employed for the other subsidiary control loops in the system, the strobing time intervals in each case corresponding to the time segments flanking either side of the capacitor current waveform, as shown in Figure 16.

In a situation where the subsidiary control loop is to regulate the relative voltages appearing across a pair of DC sources or sinks. e.g. capacitors 36 and 46 in Figure 3 (in which case there is one fewer subsidiary control loop than there are DC sources or sinks). the subtractor 171 in Figure 17 is fed on one input with a voltage V36 proportional to the mean DC voltage level on capacitor 36 and on the other input, not with the reference voltage VREF, but with a voltage V46 proportional to the mean DC voltage level on capacitor 46. In addition, it is required that two chain-current signals be fed to the second input of the multiplier 172 in order to pull the incorrect voltages of both capacitors 36 and 46 towards their correct relative value.

The principle behind the application of the two chain-current signals is illustrated in Figure 19. It is assumed first of all that the voltage on capacitor 36 is too high and that on capacitor 46 is too low. Analogous to the situation illustrated in Figure 16, the firing times for capacitor 46 need to be advanced, while those for capacitor 36 need to be retarded. The chain-current modulation signal Vlm therefore needs to be as shown in the lower part of Figure 19.

It should be noted that retarding the firing times for capacitor 36 also has the automatic effect of retarding those for capacitor 46 as well. Because of this, the portions P2 and P3 of the signal V'm which are aimed at correcting the voltage on capacitor 46 require to be approximately twice the amplitude of the portions P, and P4 relating to capacitor 36, and of the opposite sign, so as to provide an equal and opposite shift, i.e. toward the left, of the waveform 69.

As in Figure 16, the actual signal V'm follows the dotted contour, not the idealised solid contour.

In order to produce portions P-P4 of the signal V'm of the correct polarity and weight, a current strobe circuit such as that shown in Figure 18 is employed in this case also. A number of such circuits are required, namely three for a 3-link chain as shown in, for example, Figure 3. The outputs of these strobe circuits do not then directly represent the signal V'm as such, as was the case where the subsidiary control loops were holding capacitor voltage at a reference level but they are merely a measure of the currents flowing through respective capacitors. i.e. currents i36, i46 and i56.

respectively. Pairs of these currents are then fed to the input of a weighting arrangement shown in Figure 20. There are three such weighting arrangements in a 3-link chain such as that shown in Figure 3. In Figure 20, the weighting arrangement comprises first and second weighting means 185, 186 fed respectively by signals i46 and i36 from respective multipliers 181. The weighting means 185 and 186 provide the necessary weighting coefficients as described above in connection with Figure 19. The outputs of the weighting means are then summed in a combining means 187, shown as a summer, the output of which is taken to the second input of the multiplier 172 (Figure 17) as modulating signal V'rn.

In practice, the functions of weighting means 186 and adder 187 are combined into one by employing a subtractor as the combining means 187 and feeding the current signal associated with capacitor 36 into the inverting input of the subtractor.

The measurement of individual capacitor voltages for inputting to the subtractor 171 in Figure 17 is by means of a strobing method similar to that shown in Figure 18 for the chain current. This strobing arrangement, shown in Figure 21, comprises a number of multipliers 191, as many as there are DC sources or sinks in the chain, in this case three, each of which is fed on one input with a voltage proportional to the voltage across the chain, which may be designated as the phase voltage VPH. This is derived by way of a voltage divider in order to bring the voltage down to a value that can be conveniently handled by analogue electronic elements. The other inputs of the multipliers receive a respective strobing signal Vsl-Vs3 in the form of a pulse which occurs during the active time interval (e.g. t,-t2) of the respective capacitor in the chain.

This is illustrated in Figure 22, which shows two of the three strobing signals, Vs, and Vs2 and the corresponding outputs Vo, and Vo2 of the respective multipliers 191. Note that all voltages are relative to the voltage on the other end of the chain.

The outputs of the multipliers 191 are taken to respective sample-and-hold units 192 where the respective output voltages Vo1-Vo3 are sampled and stored on command of a control signal derived from, for example the respective input strobe signals Vsl-Vs3 and occurring at some point during the active time interval of the respective capacitor. The outputs of the sample-and-hold units 192 are fed to difference amplifiers 193 as shown such as to form at the outputs of the amplifiers difference signals of respective pairs of sample-and-hold units 192 representing the voltages across capacitors 46 and 56, respectively. The voltage across capacitor 36 corresponds to the output of the sample-and-hold strobed by the signal Vs,. These outputs are then taken to the appropriate inputs of respective subtractors 171 in Figure 17.

A second method of capacitor balancing is possible in which auxiliary convertors are employed which are connected between each capacitor and a common auxiliary busbar by way of a transformer, in a manner similar to the arrangement of Figure 14, the convertors, however, being of a rating which is only a small fraction of that of the main link convertor. It is convenient to use a voltage-commutated type convertor, as that shown in Figure 15, using bi-directional switches which may include a GTO, as in Figure 4, or which may, in view of the low rating of these particular convertors.

include an insulated-gate bipolar transistor. Whichever is used, a reverse-parallel diode may also be included across each switching device.

An auxiliary control means is connected to the control electrodes of the bidirectional switches of the auxiliary convertors and in operation, the auxiliary control means applies plain square-wave gating to these switches synchronous with the auxiliary supply voltage. Any differences in the capacitor voltages then cause different currents to flow in the DC and therefore also the AC sides of the auxiliary convertors, these currents circulating via common busbars similar to the busbars 168 shown in Figure 14.

As a result, individual positive or negative DC currents flow in each capacitor such as to tend to equalise their voltages. This is effectively a passive method of capacitor voltage balancing.

An active version of this balancing scheme measures the voltage across each of the capacitors and compares this to the average of these voltages. An error signal is thus formed in each case which is fed to a respective control amplifier having a suitable frequency and gain response. the output of the amplifier then being used to change the amplitude - by pulse-width modulation - and/or the phase of the output of the auxiliary convertor associated with the divergent capacitor.

In this balancing scheme (whether active or passive). an auxiliary AC supply such as the supply 164 shown in Figure 14 is not strictly necessary to the balancing action. However, it may be convenient to provide such a supply in order to allow the capacitors to be charged up before the main plant is started up. The AC voltages at the convertor side of each auxiliary transformer (similar to the transformers 165-167), or on associated secondary windings, may also be used to provide auxiliary supplies to the gating circuits of each main GTO in the associated chain link.

A third method of balancing the capacitor voltages is shown in Figure 23, with reference to the first embodiment of the invention (Figure 3), only two links being shown. In this arrangement, clamps 200 are provided between like-polarity ends of respective pairs of capacitors. Thus the clamp 200 may be connected across the positive ends of the capacitors 36 and 46, as shown, or across the negative ends (see dotted clamp connection in Figure 23). In a three-link chain, such as that shown in Figure 3, a total of two clamps would be used.

Each clamp comprises a bi-directional switch Sp in series with a low impedance Zp. As with the second balancing method above, an auxiliary control means controls the switching on the switch control electrodes. The auxiliary control means is arranged to gate each switch Sp synchronously with the gates of the main chain switches 32-35, 42-45, such that it is effectively closed when main switches 34 and 42 are closed and switches 35 and 43 are open. This condition normally occurs at least once per cycle, during a time period when the net contribution of the relevant links to phase voltage is zero, i.e. when the respective capacitors are not active in the chain.

During this time, the action of the switch Sp is to connect the two capacitors it is bridging, i.e. capacitors 36 and 46 in this case, in parallel, without otherwise affecting operation of the main circuit. If there is a voltage difference between capacitors 36 and 46, a current will flow through the switch Sp circulating between the two capacitors, the current being of a polarity such as to tend to equalise their voltages.

The purpose of the impedance Zp is to limit the current in the switch Sp to reasonable values within the switch ratings. As a result. there may not be a full equalisation of capacitor voltages over any one paralleling period. but equalisation will eventallv be reached over a number of such periods.

In practice, the clamping action is allowed to occur at a time when none of the capacitors is rendered active in the chain, i.e. when all the switches down one side of the chain - including, for example, switches 32, 34, 42 and 44 - are closed. Under these circumstances, equalisation (at least in steady state) of all capacitors occurs simultaneously.

Figure 24 shows a relatively direct method of implementing the clamp circuit.

In Figure 24, two GTOs 211 and 212 are shown in series-opposition, each with a reverse-parallel diode 213, 214 across it. The GTOs are effectively gated ON together at the appropriate times, as described above. Thus, switching GTO 211 ON allows equalising current to circulate clockwise via this GTO and diode 214, and switching GTO 212 ON allows such anticlockwise current to circulate via diode 213 and GTO 212 itself.

Since current may still be flowing in a GTO at turn-off, the impedance Zp is arranged to be a resistor 215 in order to avoid excessive voltage across it at turn-off.

The resistor 215 does not add extra losses to the installation. If capacitor voltages are temporarily different, then equalising them will cause an energy loss anyway; the use of a resistor merely concentrates most of this loss in itself. In steady state, capacitor voltages will be practically equal, giving negligible current, and therefore negligible dissipation, in the resistor 215.

An alternative clamp arrangement is shown in Figure 25. This arrangement employs two conventional thyristors 217 and 218 connected in reverse-parallel. For this case, the gate pulse pattern of the main chain link switches is arranged such that switches 32, 34, 42 and 44 (see Figure 23) are ON and others OFF, twice per AC current cycle, both in the positive-going and negative-going zero-voltage regions of the main chain voltage. The two thyristors are gated on alternately, respectively at the beginning of each zero in the phase voltage. By choosing the correct half-cycles for this. the natural action of the main circuit switches is to drive the anode-cathode voltage on each thyristor negative at the end of the respective zero-voltage region, thereby forcing a natural current zero in it if there is any residual current.Because of this action, it is possible to use a substantially pure inductance 219 for impedance Zp.

This last method of balancing may be applied also to the embodiments of the invention shown in Figures 8 and 10. The coupling inductors used in these embodiments are advantageous in that they already act as the inductance 219 in Figure 25 since they are located in the circulation path of the clamping current, thereby rendering the provision of a separate inductance in the clamp circuits unnecessary. The same applies if interphase transformers are used, the effective clamping-circuit inductance being then the leakage inductance of the interphase transformers.

In a fourth method of voltage balancing, the GTO firing pattern of the main voltage-commutated convertors is changed in a cyclical fashion. This takes advantage of the fact that all the chain links are essentially identical and differ only in the timing of the gate pulses applied to the GTOs in each link, i.e. the timing of the various angles Oi, 2... In this method, firing angle fl, for instance, is adopted by successive links in the chain, instead of just the first link, and similarly for the other firing angles in the series. Thus the whole firing-angle sequence shifts periodically down through all the links in the chain in turn.It is convenient to change the selection of links at regular intervals of either a half-cycle or a full cycle; the change is best made at instants when total chain voltage is zero. Since the tendency for a capacitor voltage to drift from nominal in steady state depends on the position (i.e. firing angle) in the time sequence, by changing the firing angle of each GTO regularly in a progressive manner, each capacitor will on average experience all possible firing angles for equal times, hence any tendency for relative drift of all capacitors will be nullified.

Where the multilevel convertor according to the invention is used in an SVC application and capacitors are used in each chain link. the complete multilevel convertor can in principle be controlled by a small change of a fraction of one degree in the firing angle of all its switching devices together. relative to the phase of the AC system voltage. This causes an increase or decrease in all capacitor voltages, which in turn changes the AC voltage of each chain. so that AC reactive current changes to a new value. The sensitivity of this action in practical systems is so high that it is effectively an integral control, requiring therefore a closed-loop to form a main control.The nature of this main control loop, i.e. the forming of an error signal from the difference of an actual value of a parameter to be stabilised and an ordered or reference value of that parameter, and the application of that error signal to a firing-angle generating circuit such as a phase-locked VCO, has already been mentioned.

Where batteries or convertors are used as the source or sink in each chain link, the firing angle changes required are larger than in the case of capacitors, but control is generally similar.

Quantities that may be controlled by the main control loop of the multilevel convertor include the following: - AC voltage magnitude, - power or reactive power in part of the AC system such as a nearby transmission line, - real or reactive power or current of the multilevel convertor itself, - DC voltages or currents in the sources or sinks of the multilevel convertor, - difference of the real and reactive currents of the multilevel convertor from the real and reactive current in an adjacent load in the AC system, - phase angle between two points in the AC system.

In general, the main control loop will control only one quantity at a time, but extra control loops may be added in a known manner such that they normally have no effect, but take over control in the event that an internal quantity such as current, or capacitor DC voltage, attempts to exceed a predetermined value.

A variable multilevel convertor according to the invention may be operated with additional passive inductors or capacitors. For example, when used as an SVC, a series inductor may be added to reduce AC harmonic currents and also the maximum transient overcurrent in the device. As already mentioned this may be the leakage inductance of a transformer. Also. an additional capacitor bank may be added in parallel with the SVC to extend the net reactive current range further in the leading direction; this may be configured as a shunt harmonic filter.

When operated as a series device in, for example, an AC transmission line, the multilevel convertor may be provided with series inductors to limit AC harmonic currents caused by the convertor, and also to limit maximum current in the AC system and the convertor in the event of an AC-system short-circuit. It is possible in this case to control the convertor during the fault such that its impedance is either practically zero, in order to limit the voltages appearing across the electronic switches and capacitors, or such that its voltage is the maximum permitted by its components so as to limit current as far as possible.

While the main switching devices in the chain links have been assumed to be GTOs, it is possible to employ other switching elements such as the insulated-gate bipolar transistor, just as this may be routinely used, for example, in auxiliary convertors where such are employed for the voltage-balancing sections of the invention.

A reverse-parallel diode is, of course, necessary in the interests of bi-directionality.

It has also been assumed that the GTOs are turned ON once per cycle and OFF once per cycle, i.e. switching actions per cycle. However, it is also possible to control the gating of each GTO to give more than two switching actions per cycle in order to provide further control possibilities, such as a reduction in selected harmonics, and control of the fundamental frequency component of voltage independently from that provided by changes in capacitor voltage.

In addition, whereas it has been assumed that the mean DC value of capacitor voltages is measured by the strobing technique described earlier, it is also possible to employ pairs of high-voltage potential dividers connected between each side of each capacitor to ground. The outputs of the divider pairs are taken to the inputs of respective difference amplifiers in order to furnish signals representative of the voltage across a respective capacitor.

Claims (42)

1. A multilevel convertor for connection in shunt or in series with a singlephase, or with each phase of a multiphase, AC system, in which the multilevel convertor is configured as a chain, the chain comprising a plurality of links each of which comprises a voltage-commutated convertor providing a multilevel AC voltage, and a main control arrangement for controlling a switching sequence of the voltagecommutated convertors such as to provide a total multilevel AC voltage across the ends of the chain which is an aggregate of the individual multilevel AC voltages of the voltage-commutated convertors.

2. A multilevel convertor as claimed in Claim 1, in which the chain comprises m links having respective multilevel voltages of levels np, where p=l, 2,... m and the main control arrangement is arranged to control the switching sequence of the voltage-commutated convertors such as to provide a total multilevel AC voltage across the ends of the chain having a number of levels N equal to:

3. A multilevel convertor as claimed in Claim 1 or Claim 2, in which each voltage-commutated convertor comprises a plurality of switching means and a DC source or sink, the main control arrangement being arranged to render each DC source active in the chain over at least two separate time intervals during the period of an AC waveform of the AC system to which the multilevel convertor is connected.

4. A multilevel convertor as claimed in Claim 3, in which each flp.level voltage-commutated convertor comprises 2(np-1) switching means arranged as first and second parallel-connected branches in a bridge configuration, each branch comprising np-l series-connected switching means, one end of the parallel-connected branches forming a DC positive bridge terminal, the other end forming a DC negative bridge terminal, (np-l)/2 DC sources or sinks being connected in series to form a third branch in parallel with the first and second branches, a positive pole of the third branch being connected to the DC negative terminal of the first and second branches and a negative pole of the third branch being connected to the DC positive terminal of the first and second branches, first and second sets each of np-3 diodes connecting tapping points of the first and second branches, respectively, to tapping points of the third branch, the AC terminals of the bridge being taken from midpoints of the first and second branches.

5. A multilevel convertor as claimed in Claim 4, in which np=3.

6. A multilevel convertor as claimed in Claim 4, in which flp =5 and the first and second sets of diodes each comprise a first diode connected between a first tapping point on respective first and second branches and a midpoint of the third branch and a second diode connected between a third tapping point on respective first and second branches and the midpoint of the third branch, the midpoint of the first and second branches forming the remaining tapping point thereof and the first diodes being connected with their anodes towards the third branch and the second diodes being connected with their cathodes towards the third branch.

7. A multilevel convertor as claimed in Claim 3, in which the chain comprises two parallel branches between the ends of the chain, each branch comprising a plurality of switching means connected in series, corresponding junctions of the switching means in the two branches being linked together by a DC source or sink, the polarity of which is reversed at successive junctions going down the chain.

8. A multilevel convertor as claimed in any one of Claims 4 to 6, in which each chain link comprises two or more parallel-connected bridge configurations connected to the same DC source or sink.

9. A multilevel convertor as claimed in Claim 8 in which corresponding AC terminals of the bridges of each link are connected together by way of an inductance means to form respective ends of the link.

10. A multilevel convertor as claimed in Claim 9, in which the inductance means is a centrc-tapped inductor.

11. A multilevel convertor as claimed in Claim 8, in which those AC terminals of the two or more bridges which are connected to a following link in the chain are connected to respective AC terminals of the two or more bridges of that following link.

12. A multilevel convertor as claimed in Claim 11, in which respective AC terminals are connected by way of an inductance means.

13. A multilevel convertor as claimed in Claim 12, in which there are two bridges in each link and the inductance means is an interphase transformer having two windings, one winding being connected up in antiphase to the other.

14. A multilevel convertor as claimed in any one of Claims 4 to 13, in which each DC source or sink is a capacitor or a set of capacitors.

15. A multilevel convertor as claimed in any one of Claims 4 to 13, in which each DC source or sink is an electrical battery or a set of batteries.

16. A multilevel convertor as claimed in any one of Claims 4 to 13, in which each DC source or sink is an AC-DC or DC-AC convertor.

17. A multilevel convertor as claimed in any one of Claims 4 to 16, in which the switching means are bidirectional electronic switches.

18. A multilevel convertor as claimed in Claim 17, in which the bidirectional electronic switches each comprise a semiconductor device such as a gate-turn-off thyristor or an insulated-gate bipolar transistor connected in parallel with a reverseconnected diode.

19. A multilevel convertor as claimed in any one of the preceding claims, comprising voltage-balancing means for maintaining the voltages across the DC sources or sinks at desired relative or absolute values.

20. A multilevel convertor as claimed in Claim 19, in which the voltagebalancing means comprises a voltage equalisation means connected to each DC source or sink and arranged to maintain the voltages across the DC sources or sinks at a substantially equal value.

21. A multilevel convertor as claimed in Claim 20, in which the voltage equalisation means comprises an auxiliary voltage convertor having a DC port and an AC port, the DC port being connected across the relevant DC source or sink and the AC port being connected to an auxiliary busbar arrangement, and an auxiliary control means, the auxiliary control means being arranged to control the various auxiliary voltage convertors of the chain such as to allow equalising currents to circulate between the DC sources or sinks of the chain by way of the busbar arrangement.

22. A multilevel convertor as claimed in Claim 20, in which the voltage equalisation means comprises a clamping means connected between each pair of DC sources or sinks and an auxiliary control means connected to the clamping means, the auxiliary control means being arranged to render the clamping means conductive, thereby shunting the relevant pair of DC sources or sinks across each other, at one or more points in the switching sequence of the voltage-commutated convertors.

23. A multilevel convertor as claimed in Claim 22, in which the auxiliary control means are arranged to render the clamping means conductive when the total voltage across the chain is substantially zero.

24. A multilevel convertor as claimed in Claim 23, in which the clamping means comprises a pair of bidirectional semiconductor switches in series-opposition connected in series with a resistive impedance between like poles of a pair of DC sources or sinks, the auxiliary control means being arranged to render the switch pair conductive when no main conductive path exists between said poles.

25. A multilevel convertor as claimed in Claim 19, in which the voltagebalancing means comprises a subsidiary control loop arrangement arranged to combine first signals proportional to the mean DC voltage levels on the DC sources or sinks and second signals proportional to currents flowing through the DC sources or sinks and to modulate the timing of the switching sequence of the voltage-commutated convertors in the chain by way of the main control arrangement in dependence on the result of the combination of the first and second signals such as to maintain the desired voltage values on the DC sources or sinks.

26. A multilevel convertor as claimed in Claim 25, in which the subsidiary control loop arrangement comprises a plurality of subsidiary control loops, each subsidiary control loop comprising a first combining means having a first input for receiving a first signal proportional to the difference between a mean DC voltage level on a respective DC source or sink and a further DC voltage level and a second input for receiving a second signal proportional to a current flowing through the chain during time slots which flank the active time interval of the respective DC source or sink.

27. A multilevel convertor as claimed in Claim 26, in which the first combining means is a multiplier and the subsidiary control loop comprises a difference means having a first input for receiving the mean DC voltage level on the respective DC source or sink and a second input for receiving the further DC voltage level, an output of the difference means being connected to the first input of the first combining means.

28. A multilevel convertor as claimed in Claim 27, in which the second input of the difference means is arranged to receive a further DC voltage level which is proportional to a mean DC voltage level on another DC source or sink, the subsidiary control loop being thereby arranged to establish a desired relationship between the mean DC voltages on a respective pair of DC sources or sinks, the number of subsidiary control loops in the chain being equal to one less than the number of DC sources or sinks in the chain.

29. A multilevel convertor as claimed in Claim 27, in which the second input of the difference means is arranged to receive a further DC voltage level which is a reference voltage level, the subsidiary control loop being thereby arranged to establish a desired absolute reference mean DC voltage level on the respective DC source or sink, the number of subsidiary control loops in the chain being equal to the number of DC sources or sinks in the chain.

30. A multilevel convertor as claimed in Claim 28. in which the subsidiary control loop comprises a second combining means having an output connected to the second input of the first combining means and first and second inputs for receiving first and second signals proportional to the chain current during time slots which flank respective active time intervals of the respective pair of DC sources or sinks,

31. A multilevel convertor as claimed in Claim 30, in which the second combining means is a subtractor.

32. A multilevel convertor as claimed in Claim 31, in which the subsidiary control loop comprises a weighting means in the first or second input of the second combining means, the weighting means serving to multiply the relevant first or second signal proportional to chain current by a desired weighting factor.

33. A multilevel convertor as claimed in Claim 32, in which the weighting means is configured such as to multiply that signal proportional to chain current which is associated with a later-firing capacitor of the respective pair of capacitors by a factor of approximately two.

34. A multilevel convertor as claimed in Claim 29, in which the subsidiary control loop comprises a third combining means for providing the signal proportional to chain current, the third combining means having a first input for receiving a signal proportional to the chain current, a second input for receiving a strobe signal and an output connected to the second input of the first combining means.

35. A multilevel convertor as claimed in Claim 31, in which the subsidiary control loop comprises a pair of third combining means for providing first and second chain-current signals, the pair of third combining means having respective first inputs for receiving respective signals proportional to chain current, respective second inputs for receiving respective strobe signals and respective outputs connected to respective inputs of the second combining means.

36. A multilevel convertor as claimed in Claim 35, in which the first inputs of the third combining means are connected together to receive a common signal proportional to chain current.

37. A multilevel convertor as claimed in Claim 34 or Claim 36. comprising a current transformer in series with the chain. the current transformer having a secondary winding for providing the signal proportional to chain current.

38. A multilevel convertor as claimed in any one of Claims 27 to 37, in which the subsidiary control loops comprise a respective second strobing means for deriving the first signal proportional to the voltage across the respective DC source or sink, the second strobing means having first and second inputs for receiving, respectively, a signal proportional to a phase voltage appearing across the chain and a strobe signal timed to coincide with a period during which the respective DC source or sink is rendered active in the chain, the second strobing means having an output for providing the first signal proportional to the voltage across the respective DC source or sink.

39. A multilevel convertor as claimed in any one of the preceding claims, comprising two chains connected in parallel by way of an inductance means.

40. A multilevel convertor as claimed in any one of the preceding claims, in which the main control means comprises a parameter-measuring means for measuring a parameter to be regulated by the multilevel convertor and a comparing means, the comparing means being arranged to compare an output of the parameter-measuring means with a desired value of the relevant parameter and forming from the comparison an error signal for adjusting firing angles of switching devices used in the voltagecommutated convertors of the chain such as to effect regulation of the relevant parameter.

41. A multilevel convertor as claimed in Claim 40, in which the parametermeasuring means comprises means for measuring AC or DC voltage or current or reactive power or real power or phase angle relating to one or more AC systems to which the multilevel convertor is connected, or to the convertor itself.

42. A multilevel convertor substantially as hereinbefore described with reference to Figures 3 to 25 of the drawings.