GB2176070A - Digital to analogue converter - Google Patents

Abstract

A D/A converter is followed by a low-pass filter. To convert the digital signal values with a small amount of circuitry to an analogue signal that permits high-quality reproduction (e.g. stereo sound), the D/A converter is preceded by a coding circuit which transforms the digital signal values into pulse packets (22) each consisting of a number of pulses following each other without interruption. The repetition rate of these pulse packets is a multiple of the repetition rate of the signal values. The pulse packets (22) are largely symmetrical with respect to centerlines (ML) spaced at equal time intervals. A pulse on one and/or the other side of the centerline (ML) has an amplitude smaller than or equal to a maximum value, and all other pulses of the pulse packet (22) have the maximum value. The voltage-time area of each pulse packet (22) corresponds to the respective digital signal value. <IMAGE>

Description

SPECIFICATION Digital to analogue converter circuit arrangement and method of digital to analogueconvertion The present invention relates to digital to analogue convertion in which low pass filtering is effected after convertion. Such a procedure may permitsignalswhich were originally analogue signals, e.g. audio signals, and which have been digitised, e.g. by pulse-code modulation,-for bettertransmission in a telecommunication network, to be converted back at a receiver into analogue signals necessary for reproduction.

In the planned broadband integrated-services digital network, BISDN, stereophonic signals of high quality are to be transmitted. To digitise such signals, finer quantisation levels must be used, so that each transmitted sample value has a word length of, e.g. 15 bits. To convertthe digital signal values back into analogue audio signals priorto reproduction at the receiver, 1 5-bit digital-to-analogue (D/A) converters are needed which meet stringent linearity requirements. Such D/A converters, however, are extremely expensive to fabricate.

In a prior art D/A converter (British Patent 1 444 21 6), the sampling rate of the incoming digital values is therefore increased, and the word length of the signal values is reduced. A pulse stream is produced whose mean density is proportional tothesignal amplitude. From this pulse stream, the analogue signal can be reconstructed by means of a low-pass filter. To process high-quality stereophonic signals, however, a high sampling frequency of 32 kHz is required, which, in the prior art converter, results in very high pulse repetition rates (8to 16 MHz) and, thus, in an equally high system clockfrequency if 15-bitamplitude quantisation is used.

in addition, a very-high-precision pulse shaper is necessary before the analogue postfiltering to make the area ofthe pulses constant, taking accountofleading and trailing edges. Such a pulse shaper, however, isof complicated design and difficult to implement.

The present invention seeks to convert digitised signalsto an analogue signal with a small amount of circuitry and in such a way that high-qualityreproduction is possible.

According to one aspect of the invention there is provided a digital to analogue circuit arrangement comprising a digital-to-analogue converter followed by a low-pass filter, characterised in thatthe digital-to-analogue converter is preceded by a coding circuit in which the digital signal values are transformed into pulse packets which consist of a number of pulses following each other without interruption and having a repetition frequency equal to a multiple ofthe repetition frequency ofthe signal values, thatthe pulse packets have a shape which is largely symmetrical with respect two equidistant centerlines, that a pulse on one and/or the other side of the centerline of the pulse packet has an amplitude smallerthan or equal to a maximum value, while all other pulses ofthe pulse packet have the maximum value andthatthetime integral over a pulse packet corresponds to the digital signal value at the inputofthe coding circuit.

The invention also includes a method for converting a digital signal to an analogue signal employing such a converter comprising the following steps: increasing the repetition frequency of the incoming signal values by interpolation, reducing the word length ofthe signal values of increased repetition frequency, deriving an error signal from the difference between the interpolated signal values of increased repetition frequency and the signal values having a reduced number of bits and the same repetition frequency, band limiting the error signal by digital filtering adding the band limited errorsignal to the signal values of increased repetition frequency, converting the signal values of increased repetition frequency to an analogue signal, and suppressing the clock-frequency components by analogue postfiltering, characterised in that the signal values having a reduced number of bits and increased repetition frequency are converted to pulse packets ofthe same repetition frequency which are symmetrical with respect to instants following each other atthe increased repetition frequency, and thatthetime integrals of the amplitudes of the individual pulse packets correspond to the amplitudes ofthe incoming digital signal values.

The circuit ofthe invention is well suited for integration. Where clock frequencies ofabout 512kHz to 2048 MHz are employed, these can be readily implemented with MOS technology. A D/A converter with a maximum word length of 8 bits is suited for implementation in MOStechnology, too, because it need not meet any stringent linearity requirements. The amount of circuitry required for analogue postfiltering is extremely small because of the oversampling.

In order that the invention and its various other preferred features may be understood more easily, some embodiments thereof will now be described, by way of example only, with reference to the drawings, in which Figure lisa block diagram of a digital to analogue converter in accordance with the invention, Figure2 is a graph showing the relative power density of the noise signal, reduced by quantisation-error feedback, with fourfold oversampling, Figure 3 is a graph showing the relative power density ofthe noise signal, reduced by quantisation-error feedback, with eightfold oversampling, Figure4shows three embodiments of error filter which can be used in the converter of Figure 1, Figure5shows a firstform of signal pulses delivered bythe converter of Figure 1, Figure 6shows details ofthesignal pulses of Figure 5, Figures 7a, 7b and 7c are graphs illustrating the linearity improvement achieved by the invention, Figure 8 shows a second form of signal pulses delivered by the converter of Figure 1, Figure 9 shows a third form of signal pulses delivered by the converter of Figure 1, Figure 10 shows a modification of a portion of the converter of Figure 1.

Figure 1 shows a transmission line 1,which forexampleformspartofa BISDN network, overwhich PCM-coded stereophonicsignals are transmitted to a digital-to-analogue converter, constructed in accordance with the invention,wherethey are converted to analogue signals. The D/Aconverterforms part of a terminal which is connected to the network and with which the received stereophonic signals are reproduced via loudspeakers.

The digital signal orsamplevaluesarriving serially on the line 1 are fed to a serial-to-parallel converter 2, in which they are converted to parallel form with a word length of q bits. In the embodiment, q = 15; accordingly, the transmission line has q parallel wires. The sequence ofincoming sample values is denoted in Figure 1 by P(N),whereN is the sequence index.

The sample values P(N) are received at a repetition rate offc = 32 kHz. In an interpolation filter 3, they are converted to an interpolated signal-valuesequence Q(K) with the same quantisation q but at a repetition ratef0 increased by an oversampling factor U.

The output ofthe interpolation filter 3 is connected via an adderstage 4to the input of a quantiser 6. In the quantiser 6, the signal values S(K) from the adderstage4, which arrive as parallel word containing q = 15 bits and will be explained below, are reduced in words length, sothat r-bit parallel words (e.g. r= 11) are provided atthe output.

In a subtracter8, a quantisation-errorsequence D(K) informed bysubtracting the outputsignalsY(K) ofthe quantiser 6 from the input signals S(K). In the embodiment,the quantisation-errorvalues consistofthe separated least significant bits of S(K). In an error filter 10,feedbackvalues F(K) are derived from the quantisation-errorvalues D(K). They are added in the adder stage 4to the output-signal values Q(K) from the interpolating filter 3 to obtain the input-signal values S(K) forthe quantiser 6.Ifthe error filter 10 has a suitable time response; the quantisation-errorfeedback,which is known perse, causes that component ofthe quantisation noise spectrum in the outputsignal Y(K) ofthe quantiser 6 which lies in the audible range to be shifted toward higherfrequencies, i.e. outside the audible range.

To a first approximation, it can be assumed thatthe quantisation noise of a D/Aconvertercorrespondsto white noise and is not correlated with the input signal. The quantisation gives a noise signal Ystwhich adds to the useful signal YNutz at the output ofthe quantiser.through the feedback of the quantisation errorto the input ofthe quantiser6, one obtains Y = YNUtZ [1 - G(Z)]*Yst whereZ = ej2 # f= cos(2#f + j.sin (2#f) fo fn fo f--noise frequency fo = U*fc = output rate OfY(K) The relative noise amplitude is YYNUtz = Y' st = 1-G)Z) Yst Yst If a simple delay element (Z-1) is used forthe errorfilter,then Y'st= -Z1 Yst An error filter of degree M can be implemented, for example, by setting 1-G(Z)= [l-Z-1]M ltcan be shown that the relative power density D of the corrected noise signal is then given by D=1 *22M*sin2M(ir fmax U.fc In Figures 2 and 3, the relative power density D ofthe corrected noise signal is plotted againstfrequency, wfth the filter degree M as a parameter. Figure 2 holdsforan oversamplingfactorofU = 4, and Figure3foran oversampling factor of U = 8. The scale factor 1/fmax of the ordinate corresponds to the noise signal of-a D/A converterwithoutquantisation-errorfeedback. In Figure 3, this scale value lies outsidethe drawing because of the enlarged ordinate scale.

From Figures 2 and 3 it can be seen that the area belowthe curves and, thus, the power density of the noise signal decrease rapidly with increasing oversampling factor U and increasing filter degree M.

For M=4 and U=4,the improvement in signal-to-noise ratio resulting from the quantisation-errortreatment and the oversampling amountsto 18.6dB + 6dB = 24.6dB. ForM=2and U=8, the improvement is already23.3 dB + 9 dB = 32 dB. The word length ofthe sample values may be reduced by one bit per6 dB improvement. In the first case, the reduced word length is only 11 bits instead of 15 bits, and in the second case only 10 bits.

According to the power-density spectra illustrated in Figures 2 and 3, a considerably greaterword-length reduction still would be possible. In deriving the power-density spectra, however, it is assumed that the quantisation noise is not correlated with the useful signal. This assumption is only conditionallytrue, however.

Particularly at a very low noise level, there is such a correlation, which limits the word-length reduction.

Therefore, the curves of Figures 2 and 3 and the signal-to-noise improvements derived therefrom can only b regarded as coarse estimates. They are only to illustrate thetrend. If M=4, the equation for the filtertype proposed is 1 -G(Z) [1 -Z-1]4 =1-42-'+62-2-42-3$2-4 G(Z) = 4*Z-'-6Z-2+4z-3~z-4 Figure 4 shows three embodiments of such errorfilters, namely a filter of degree 1 atthetop, andfilterof degree 2 in the middle, and a filter of degree 4 at the bottom.

The sample-value sequence Y(K) at the output ofthe quantiser 6 (Figure 1) could be provided via a commercially available D/A converter with correspondingly reduced quantisation, but this D/Aconverter would have to have a very high linearity. Such D/A converters are very expensive to manufacture and are not suited for MOS or CMOS integration.

The invention makes it possible to use D/A converters with lower linarity and lower resolution.

The output ofthe quantiser 6 is connected to the input of a coding circuit 12. In the latter,thesignal-value sequence Y(K) is transformed into a value sequence W(U) increased by the factor 2P, which, after being convertedfrom digital to analogue form and low-pass-filtered, forms the analogue output signal NF.

The coding circuit 12 contains a read-only memory (ROM) 14, in which a code conversion is performed according to a rule to be explained below, and a counter 16, which provides the addressesforthe ROM 14. The counter 16 has a word length of p bits, i.e. it has p parallel outputs. In the embodiment, p = 3 or4. Iftheword length ofthesignal valuesy(K) is r bits, it is reduced inthecoding circuit 12to s bits,wheres=r-p.

The counter 16 is clocked at a frequency f= 2P*fo = 2P*U*fC and reset at the freq uency fc.

The signal values presented at the output of the coding circuit 12 are transferred two a converter 18. The output of the latter provides pulse packets 22, which are shown in Figures 5 and 6.

The pulse packets 22 are composed of voltage pulses 23 offrequencyf. Each pulse packet is symmetrical about a vertical centerline ML. the centerlines are spaced T2 = 1 U*fc apart.

The packet repetition rate is thus equal to the repetition rate of the sample values Y(K), and the time integral of the voltage pulses in the representation f Figures Sand 6 the voltage-time area of a pulse packet- corresponds exactly to the digital signal value Y(K).

The pulse packet shown, 22, correspond to an over-sampling factor of U=4. The period corresponding to the input repetition frequencyfc i & hus T=4*T2 The low-pass filter 20following the output of the D/Aconverter 18 suppresses the sampling frequency 1 =128kHz T2 The pulse output of the d/A converter according to the invention is a mixed pulse-amplitude-pulse-width modulation, with the pulse width being quantised, too. Figure 5 shows pulse packets 22 whose area increases from left to right. Onlythetwo outer pulses N1(K) and N2(K) of a pulse packet (Figure 6) are amplitude-modulated,whilethe pulses 23 havethe maximum amplitude. The number of inner pulses ofthe pulse packet is 2*P(K).

The signal valueY(K) is represented by the values 0 to 10.

Y(K) = Y10Y9Y8Y7Y6Y5Y4Y3Y2Y1Y0 P(K) N1(K), i.e. P(K) is represented bythe three most significant bits Y10 toY8, and N1 (K) bythe bits Y7 to1.

If, for example, a pulse consists of 27 = 128 sub-areas, and the maximum number of pulses of a packet is 2P = 16, the geometry ofthe pulse packet can be represented in a simple manner: Nmax= 128 P(K) = YaoYgY8 (three mostsignificant bits) N1(K)=Y7Y7...Y1 N2(K) = N1(K) if T0= O N2(K)=N1(K)+ 1 ifY0=1 In the ROM 14 ofthe coding circuit 12,the pulse heights corresponding tothe signal values Y(K) are stored in locations 0 to 15, whose addresses are formed by the counter 16.The latter, as mentioned above, is clockedat the frequencyfa and reset atthe frequency ft. Since, with such a simple lawforforming the individual signal-amplitude values W(U), the code table in the ROM 14 shows great redundancy, the RQM 14 may be replaced.by a PLA (programmable logic array) device, which requires considerably fewer locations.

Figure 7a shows the linearity error of aconventional D/A converter, the error having the form of a sagging curve. This curve is transversed repeatedlywith increasing AF amplitude as the outer pairs of bars of the pulse packet 22 grow. This results in a repeated image of the curves of Figure 7a as shown in Figure 7b. Referred to the finial value YmaX, the linearityerrorwith this form of signal output is reduced to # #1=2p-1 where p = number of bits of the counter 16 2P-1 = maximum number ofpairs of bars per pulse packet.

Figure 7cshows an additional non linearity #2 in the form of a step error, which, according to the formation law justexplained, is caused by the factthat, in an n-bit D/Aconverter, for example, a bar has n height steps but only n-1 sub-areas between the height steps.

The following table 1 illustrates this problem in the binary number system.

TABLE 1

Y(K) , 5K(K),ftK) N1(K) Y10Y9Y8 Y7...Y1Y0 257 001 00000001 256 001 00000000 255 000 11111111 254 000 11111110 253 000 11111101 5 000 00000111 4 000 00000100 3 000 00000011 2 000 00000010 1 000 00000001 0 000 00000000 TABLE 2

Y(K) P(K) N1(K) Y10Y9Y8 Y7...Y1Y0 255 001 00000001 254 001 00000000 253 000 11111101 252 000 11111100 5 000 00000101 4 000 00000100 3 000 00000011 2 000 00000010 1 000 00000001 0 000 00000000 Asignal value N1 (K) reaches its maximum numerical value already atY(K) = 254, and cannot bye further increased atY(K) = 255. Atthesignal value Y(K) = the high-order bit group P(K) increases from binary 000 to 001, so that, according to the formation law explained above, the maximum bar height of N1 (K)maX = 127 is set again. At the three signal valuesY(K) = 254,255 and 256, the bar height is thus equal to 127.The monotonous increase of the function is thus disturbed over two positions, as can be seen from Figure7c.

The additional non-linearity can be eliminated by adding a bit representing the 128th height step to theword length of the D/Aconverter 18. Within the range of validity ofthe bit group P(K), the D/A converter 1 8then outputs the value 100000002. if the value N1 (K) = 11111112, andY0 = 1,this highest-order current source will be activated an additional time atthe right-hand partial pulse N2(K).

This has the disadvantage that, to represent only one missing quantisation step, the accuracy of the DA converter must be increased by a factor of 2 (one additional bit). To avoid this disadvantage, the base ofthe number system is changed from 2sHl to 25+1 -2, where s = word length ofthe D/Aconverter.

In the present embodiment, wheres = 7, the base ofthe number system is reduced from 256 to 254. This is illustrated in table 2. The carry from P(K) = Oto P(K) = 1 takes place atY(K) = 254. Again.

N2(K) = NI(K) if Y0 = 0, and N2(K)=N1(K)+1 if Y0=1 Thus, ifYK) = 253,then N1(K) = 126 and N2(K) = 127.

IfYK) = 254, then N1(K) = N2(K) = 0, but P(K) = 1,wherebyan innner pair of bars is set to the maximumvalue 127. For Y(K) = 255, a new outer pair of bars begins because N1(K) = 0, and N2(K) = 1. The area of the pulse packet 22 thus increases continuously.

The total representable number of steps Y(K)maX, however, is reduced from 16 x 128 = 2048 to 16 x 127 = 2032. TheAF dynamic range is thus reduced by about 8%. This, however, is practically negligible. The base conversion is stored also in the form of an allocation table in the ROM 14.

Another advantage ofthe conversion of signal values to pulse packets lies inthefactthatthis preventsthe occurrence of undesired voltage spikes in the D/A converter 18. These are generally caused by delay differences in the current switches ofthe D/A converter, particularly if the latter switch alternately, between the digital values 1000000 and 0111111 .This causes transientcurrents which result in undesired spikes-also known as "glitches" - in the analogue signal and, thus, impair the signal-to-noise ratio of the entire circuit.

Part ofthe current sources of the D/A converter are turned on at point A of the pulse packet 22 (Figure 6, atthe right), and the remainder ofthecurrent sources are turned on at point B. At point C, only partofthecurrent sources are turned off, and at point D,the remainder ofthecurrent sources are turned off.

Alternate turn-on and tu rn-off can occur only at a very high AF input level if two successive pulse packets follow each other without interruption. This case is statistically very rare, however. In addition, the undesired noise thus caused is then masked by the high loudness level. Figure 8 shows a second pulse outputform. In each ofthe pulse packets 22a, unlike in the pulse packets 22 of Figure 6, only one outer bar increases in height with continuously increasing amplitude, this amplitude-modulated bar 23a adjoining alternately the right- and left-hand sides ofthe pulse packet. Despite this asymmetry, the centres ofthe pulse packets 22a remain largely equidistant. the time error is greaterthan with the pulse outputform of Figures 5 and 6 but still small compared with the period T ofthe AF cycle.

The maximum time error is 1 - 1 Atmax 2.f1 2+1U.fc where2Pisthe maximum numberofpulses per pulse packet.

Thefollowing relation holds: Atmax = fNF TNF 2p+1.U.fc At an audio frequency offNF=1/4*fc= 8kHz, #tmax = 1 TNF,in 2+3.U If an oversampling factor of U = 8 and a count length of p = 3 are chose as in the case ofthe pulse packets of Figure 8,the maximum time error referred to theAF period is only 0.2%. The distortion factor is small compared with this time error and, thus, negligible. The advantage of this pulse outputform over that of Figures 5 and 6 lies in the fact that,for the same factor U and the sameword length p, the number of partial curves (cf. Figure 7b) doubles. the linearity error, referred to the maximum output, level is thus halved, i.e.

A 1 2P On the other hand, with an unchanged linearity requirement,the oversampling factor U can be doubled without having to double the output pulse repetition frequencyf1. As explained above, this reduces the word length r ofthe value sequence Y(K) to, e.g. 10 bits, and the resolution sof the D/A converter to 7 bits..The address range p + rof the ROM 14 is reduced by 2 bits.

To eliminate the need for an additional bit in the D/A converter to represent the 25th sub-area of a bar, the base ofthe numbersystem can again be converted by means of an allocation table in the memory 14 or a PLA device. Since individual bars ratherthan pairs of bars are constructed here in succession, the base must be reduced from 2# to 25-1.

Figure 9 shows a third outputform of pulse packets 22b. The pulses are symmetrical with respect to a reference voltage of, e.g.1/2*Umax. Depending on the sign ofthe amplitude ofthe AF signal, the pulses, referred to the reference voltage, are positive or negative. Figure 9a shows the zero crossingof an AFwave of small amplitude. It can be seen that there is no time error at lowAF input levels. The time error occurs only at large amplitudes, at which it is neutralised by the well-known masking effect. A zero crossing of an AFwave of large amplitude is shown in Figure 9b.

Here, a particular advantage is that, at small amplitudes, also the harmonic content produced bythe sampling frequency is small. The ratio ofthe harmonics to the amplitude oftheAFsignal isthuslargely constant The analogue low-pas filter 20 can therefore be chosen to be of a lower degree than with the first pulse outputforms. The formation ruleforthethird pulse outputform,too, is stored in the form of an allocation tableintheROM 14.

With a 7-bit D/A converter,forexample,the centerline 1/2 Umax corresponds to the digital value 10000002,for example. Afterthe zero crossing of the AFwave,the digital value is slightly smaller, e.g. 0111111. However, this transition, as mentioned above, results in an undesired transientvoltage spike because in this case all I current sources of the D/A converter switch atthe same instant.

Such voltage pulses can be avoided with the arrangement of Figure 10. In this arrangement, the coding circuit 12 includes a ROM 24 whose two outputs are connected to a gate circuit 27 bylines 25 and 26, respectively. Ofthe output data ofthe memory 24, the absolute value is fed to the gate circuit 27 over the line 25, and the sign overthe line 26. The outputs of the gate circuit 26 are connected to afirst DIA converter 29 by a line 28, and to a second D/Aconverter 31 by a line 30. Each ofthese D/A converters 29,31 has halfthe resolution ofthe D/A converter 18 of Figure 1.The outputs ofthe two D/A converters 29,31 are added in a summing circuit 32, and the sum is fed to the low-pass filter 20, whose output providestheAF signal.

Ifthe sign is positive, the gate circuit 27 applies the absolute value overthe line 28 to the inputofthefirstD/A converter 29, and the highestabsolutevalue 1111112 as afixed value overthe line 30to the inputofthesecond D/A converter 31. If the sign is negative, the gate circuit negates the absolute value bit by bit, i.e. itformsthe binary complement and feeds itto the second D/A converter 31, while all bits transferred overthe line 28 to the first D/A converter 29 are changed to logic 0.

To eliminate the need forthe additional bit required in the present example to representthe 26th sub-area, in the embodimentof Figure-10,too,the base ofthe number system can be changed from 26 = 64to 26-1 = 63, preferably also by means of an allocation table stored in the ROM 24.

Claims (12)

1. A digital to analogue circuit arrangement comprising a digital-to-analogue converterfollowed buy a low-pass filter, characterised in that the digital-to-analogue converter is preceded by a coding circuit in which the digital signal values aretransformed into pulse packets which consist of a number of pulses following each other without interruption and having a repetition frequency equal to a multiple ofthe repetition frequency of the signal values, thatthe pulse packets have a shape which is largely symmetrical with respect to equidistant centerlines,thata pulse on one and/orthe other side ofthe centerline ofthe pulse packet has an amplitude smallerthan or equal to a maximum value, while all other pulses ofthe pulse packet have the maximum value and thatthetime integral over a pulse packet corresponds to the digital signal value at the input of the coding circuit.

2. A circuit arrangement as claimed in claim 1, characterised in thatthe coding circuit contains a read-only memory and acounterwhich addressesthe read-only memory.

3. A circuit arrangement as claimed in claim 1, characterised in thatthe pulses are constructed bythe coding circuit alternately on both sides ofthe centerline ofthe pulse packet.

4. A circuit arrangement as claimed in claim 3, characterised in that the pulse packets are composed of pulses in the form of bars arranged in pairs aboutthecenterline.

5. Acircuitarrangementas claimed in claim 1, comprising an interpolating filter in which the digital signal values received at a first repetition frequency are changed into signal values of increased repetition frequency, a quantiser in which the number of parallel bits constituting the individual signal values is reduced, an error filter in which quantisation-errorvalues are formed from the difference between the input- and output-signal values ofthe quantiserand fed backtothe inputofthe quantiser, a digital-to-analogue converter in which the signal values delivered by the quantiserare converted to an analogue signal, and a low-passfilterwhich suppresses the sampling-frequency components in the analogue signal, characterised in that between the outputofthe qantiserand the inputofthe digital-to-analogue converter, a coding circuit is inserted inwhich the outputsignal values of te quantiser are transformed into pulse packets ofthe increased repetition frequency, that said pulse packets are symmetrical with respect to instants following each other at the increased repetition frequency, and that the time integral ofthe amplitudes of each of the pulse packets corresponds to the amplitudes ofthe digital signal values of increased repetition frequency.

6. Acircuit arrangement as claimed in claim 2, characterised in thatthe counter is clocked at afrequency which is greaterthan the repetition frequency ofthe output-signal values ofthe quantiser by a factor of 2P, where the number p is equal to the numberofoutputs ofthe counter, andthatthe counter is reset atthe repetition frequency of the incoming signal values.

7. Acircuit arrangement as claimed in claim 1, characterised inthatthe coding circuit has two outputs connected via a gate circuit to the inputs of first digital-to-analogue converter and a second digital-to-analogue converter, and that the outputs ofthe digital-to-analogue converters are connected to a summing unit.

8. Acircuitarrangementas claimed in claim 7, characterised in thatthe signs ofthe output-signal values and the absolute output-signal values of the coding circuit are transferred to the gate circuit over a first line and a second line, respectively, that, if the sign is positive, the absolute value is fed to thefirstdigital-to-analogue converter, and the highest possible absolute value (11111112) tothesecond digital-to-analogue converter,and that, if the sign is negative, the absolute value is negated bit by bit and fed to the second digital-to-analogue converter, while the first digital-to-analogue converter is presented exclusively with zero bits.

9. A digital-to-analogue circuit arrangement substantially as described herein with reference to the drawings.

10. A method for converting a digital signal to an analogue signal using a circuit arrangement as claimed in any one ofthe preceding claims, comprising the following steps: increasing the repetition frequencyofthe incoming signal values by interpolation, reducing the word length ofthe signal values of increased repetition frequency, deriving an error signal from the difference between the interpolated signal values of increased repetition frequency and the signal values having a reduced number of bits and the same repetitionfrequency, band limiting the error signal by digital filtering adding the band limited error signal to the signal values of increased repetition frequency, converting the signal values of increased repetition frequency to an analogue signal, and suppressing the clock-frequency components by analogue postfiltering, characterised in that the signal values having a reduced number of bits and increased repetition frequency are converted to pulse packets ofthe same repetition frequencywhich are symmetrical with respect to instants following each other at the increased repetition frequency, andthatthetime integrals ofthe amplitudes ofthe individual pulse packets correspond to the amplitudes ofthe incoming digital signal values.

11. A method as claimed in claim 9, characterised in thatthe repetition frequencyofthe digital signal values is increased by an oversampling factor of 2 to 8.

12. A method for converting a digital signal to an analogue signal substantially as described herein with reference to the drawings.