GB2125242A - Analog-to-digital converter - Google Patents

Abstract

A continuous integration analog- to-digital converter is provided in which a feedback signal is summed at the input of the integrator with the input analog signal to be digitalized, with the resultant integrated signal being processed by a computer to provide an updated feedback signal which tends to maintain the output of the integrator within the operational limits of the integrator, and with the computer calculating a digital representation of the input analog signal as a function of the value of the feedback signal. <IMAGE>

Description

SPECIFICATION Continuous integration analog-to-digital converter Background of the invention I Field of the invention The present invention relates to a device which provides for conversion of a continuous time analog voltage or current into a discrete-time digital sequence through use of an integration function.

II Description of the prior art In one form of digital representation of an analog signal, an analog signal is integrated over a given time interval, and the resultant integral is converted into a digital sequence. Theoretically, such integration could nun indefinitely. However, in reality an integrator would shortly reach operational limits and would cease to function effectively.

Prior art devices are known which reset such an integrator for each of successive time intervals, thereby precluding the integrator from exceeding operational limits during any individual time interval. However, such prior devices require finite time to reset the integrator during which time the input analog signal is lost to integration.

Another known prior art device is called a dual slope analog-to-digital converter. In such a device, integration is undertaken on an input analog signal for a known period of time T, whereafter the input analog signal is removed and in its place a known current of opposite polarity is applied, forcing the integrator to return to a zero output. A counter accumulates timing pulses until the integrator output again crosses zero, at which time the accumulated count provides a digital output proportional to the analog input during the known time period T. An actual conversion of the accumulated counts to a real number representing the input analog signal may be achieved either through mathematical calculation or by choosing a reference current which permits direct output reading.This form of prior art converter, however, also suffers from losing access to the analog input signal during the period of time in which the known current is applied to the integrator.

It is, accordingly, an object of the present invention to provide an integration analog-todigital converter which allows for continuous integration of an input analog signal, without interruption, and without having the integrator exceed its operational limits.

Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

Summary of the invention To achieve the foregoing objects, and in accordance with the purposes of the invention, as embodied and broadly described herein, the continuous integration analog-to-digital converter of the present invention comprises integrator means for continuously integrating an input analog signal; sampling means for successively determining the output of the integrator means without interrupting the continuous operation of the integrator means; and circuit means responsive to the output of the sampling means for supplying a feedback signal to the integrator means which permits continuous operation of the integrator means by maintaining the output of the integrator means within the operational limits of the integrator means, the circuit means further supplying a digital output signal representative of the input analog signal as a function of the feedback signal.

In the illustrated preferred embodiment there is included an analog-to-digital converter of Y-bit resolution coupled between the sampling means and the circuit means, and a digital-to-analog converter of X-bit resolution coupled between the circuit means and the integrator means, wherein X is greater than Y and wherein the circuit means has an X-bit resolution digital output signal.

The sampling means may operate either with constant time intervals or with synchronized time intervals, thereby rendering the converter of the subject invention less susceptible to coherent interference components. Moreover, the feedback signal may be held constant or may be of a more complex function.

In a more narrow sense, the continuous integration analog-to-digital converter of the subject invention comprises integrator means for continuously integrating an input analog signal i5; trigger means for determining the start of a plurality of sampling intervals N; sampling means for determining the output eel,, and e(N+1) of the integrator means at the beginning of successive sampling intervals N and N+1, respectively, without interrupting the continuous operation of the integrator means; an analog-to-digital converter for converting said outputs e(N) and e(N+1) into digital signals E(N) and E respectively, of Y-bit resolution; and circuit means for: (i) providing digital feedback signals 1FB(N) and iFB(N+1) for application in analog form to the integrator means for each sampling interval N and N+1, respectively, which permit continuous operation of the integrator means by tending to maintain eel,, and e(N+,) during sampling intervals N and N+1 within the operational limits of the integrator and sampling means; (ii) storing the feedback signal 1FB(N) for each sampling period N; (iii) storing a digitalized form of the output of the integrator means for the start, E(N). and the start, E(N+1), of successive sampling intervals N and N+ 1; (iv) updating the feedback signal 1FB(N) at the beginning of each subsequent sampling interval N+1 to provide a new feedback signal 1FB(N+1) as a function of iFB(N), E(ND, and EN+!; and (v) providing a digital output signal representative of the input analog signal as a function of the feedback signal 1FB)N) Preferably, the feedback signal is updated in a manner to maintain the output of the integrator means constant and even more preferably, the feedback signal is updated in a manner to maintain the output of the integrator means at zero.

Description of the drawings A greater appreciation of the objects and advantages of the invention may be understood by a detailed description of the preferred embodiment of the invention taken in conjunction with the drawings wherein: Fig. 1 illustrates a block diagram of a continuous integration analog-to-digital converter utilizing the teachings of the present invention; and Fig. 2 is a flow chart demonstrating the preferred operation of the computer illustrated in Fig. 1.

Detailed description of the preferred embodiment Referring to Fig. 1, there is shown a pair of input terminals 10, 12 across which is supplied an input analog signal eS. A resistor 14 is coupled to terminal 10, across which there appears an input analog signal is. For purposes of the subject invention, the input analog signal may take either the form of a voltage signal eS, or a current signal is.

There is provided in Fig. 1 an integrator 1 5 for continuously integrating the input analog signal is. This integrator is shown in Fig. 1 in the form of an operational amplifier 1 6 and a capacitor 18 coupled between the output of operational amplifier 16. Resistor 14 is also coupled to the inverting input of operational amplifier 16, whereas the non-inverting input is shown in Fig. 1 coupled to ground. As is well-known to those skilled in the art, during any particular time period AtN a voltage 0(N) is accumulated across capacitor 1 8 which is the integral of the input analog signal is, provided the operational limit of integrator 1 5 is not exceeded.More specifically:

where: voltage at imput resistor 1 4 t,=the time at the start of a sampling interval N t2=the time at the end of sampling interval N R=the resistance of resistor 1 4 C=the capacitance of capacitor 1 8.

If the voltage across capacitor 1 8 is sampled and represented as e(NI at the beginning of any sampling interval N, the voltage at the beginning of the subsequent sampling interval N+1 may be represented as e (E+1)' wherein elN+1)=e{N) [At(N)/C] [15(N)], with C=to the capacitance of capacitor 18, At equal to the length of sampling interval N, and isle) equal to the total input current supplied to the negative input terminal of operational amplifier 16 during sampling interval N.

In accordance with the present invention there is provided sampling means for successively determining the output of the integrator means of the subject invention without interrupting the continuous operation of the integrator means. As illustratively shown in Fig. 1, there is provided a sample and hold circuit 20, including a capacitor 22, and a trigger circuit 24. The output of operational amplifier 1 6 is coupled to the input of sample and hold circuit 20, and trigger circuit 24 is coupled to selectively operate sample and hold circuit 20.This is well-known to those skilled in the art, sample and hold circuit 20 may operate under the control of trigger 24 to successively hold the output of the operational amplifier 1 6 across capacitor 22, without in any way interfering with the continuous operation of integrator 1 5. Accordingly, trigger 24 provides a triggering pulse to sample and hold circuit 20 for each sampling interval N.

Further, in accordance with the present invention, there is provided a circuit responsive to the output of the sampling means for supplying a feedback signal to the integrator means which permits continuous operation of the integrator means by maintaining the output of the integrator means within the operational limits of the integrator means. This circuit further provides a digital output signal representative of the input analog signal as a function of the feedback signal.

As illustratively shown by way of example and not limitation in Fig. 1, there is provided an analog-todigital converter 26, a computer 28, a digital-toanalog converter 32, a time interval meter 34, a resistor 36, and an output display 38. Analog-todigital converter 26, digital-to-analog converter 32, time interval meter 34, and output display 38 are all controlled via I/O ports of computer 28.

The output of sample and hold circuit 20 is coupled to the input of analog-to-digital converter 26. Analog-to-digital converter 26 preferably has a Y-bit resolution. Computer 28 and digital-toanalog converter 32 preferably have an X-bit resolution wherein X is greater than Y. The output of digital-to-analog converter 32 is coupled through resistor 36 to the negative input of operational amplifier 1 6. Trigger 24 is coupled not only to sample and hold cirucit 20 but also to computer 28 and is further coupled to an interrupt of computer 28 through time interval meter 34.

In operation, upon sampling of the output of operational amplifier 1 6 by sample and hold circuit 20 through control of trigger 24, the voltage held across capacitor 22 is converted from analog form, esN), to digital form, E(N), by analog-to-digital converter 26. Digital signal E(N) is provided as an input signal to computer 28.

Computer 28 during every sampling interval N provides, as will be explained below, an output digital feedback signal IFB(NI to digital-to-analog converter 32 wherein digital feedback signal IFB(N) is converted to an analog signal iFB(N) which is introduced to the inverting input of operational amplifier 1 6 through resistor 36.

In addition to receiving a sequence of digital input signals E (N)' computer 28 also receives from time interval meter 34 a signal At(N) which indicates the length of time of any given sampling interval N.

In accordance with the present invention, digital feedback signal 1FB(N) for any given sampling interval N is calculated by computer 28 in a manner such that corresponding analog feedback current iFB(N) when united with input analog signal is tends to keep integrator 15 within operational limits, and preferably tends to drive the output of integrator 15 to zero. To achieve this objective, computer 28 may, for example, be programmed to store successive input signals E(N), E)N+l) from analog-to-digital converter 26, to store the digital feedback signal 1FB)N) for the last sampling period N, and receive the time interval signal At(N) for the last sampling period N.

At the end of a given sampling interval N, which is also the beginning of the next sampling interval N+1, computer 28 needs to calculate a feedback number IFB(N) which would result in the output of analog-to-digital converter 26, at the beginning of the next sampling interval N+2, falling within the operating limits of integrator 15, sample and hold circuit 20, and analog-to-digital converter 26. For example, analog-to-digital converter 26 output E(N+2) at the beginning of the N+2 sampling interval (i.e., the end of the N+1 sampling interval) may be set equal to zero by computer 28.More specifically, the output of analog-to-digital converter 26 at the end of sampling interval N+1 (namely at the beginning of time N+2)) is equal to the output of analog-todigital converter 26 at the beginning of the N+1 sampling interval (namely E)N+l)) minus the negative integration voltage accumulated on capacitor 18 during the N+1 sampling interval.

Accordingly: E(N+2)=E(N+1)-[#t(N+1)/C].[IS(N+1)+ IFB(N+1)] wherein At)N+l( equals the length of sampling interval N+1,and C equals the capacitance of capacitor 18, and IS(N+1I and 1s)N+1) are digital representations of the input currents iFB(N+1) and iFB(N -1) supplied to integrator 15 during the N+1 sampling interval.If E)N+2) is set equal to zero then: IFB(N+1)=[C/#t(N+1)]. E(N+1)-IS(N+1) (1) The value of the output of analog-to-digital converter 26 at the beginning of sampling interval N+1, E)N+l(, is known to equal the value of the output of analog-to-digital converter 26 at the beginning of the previous sampling interval, N, minus the negative voltage drop accumulated on capacitor 18 during the sampling interval N.

Accordingly: E)N+l)=E)N)-[At)NVC] . [IS(N)+IFB(N)] (2) Therefore IS(N)=[C/#t(N)] . [E(N)-E(N+1)]-IFB(N) (3) Assuming that 1s)N) approximately equals IS(N+1) and using equation (3) in equation (1):

Assuming that the time period At(N+1) is not significantly different from the time period At then: IFB(N+1)=[C/t(N)] [2 . E(N+1) E(N)]+IFB(N) Since at the beginning of sampling interval N+1, E(N+1); E(N}; 1FB)N): and At)N) are all known, computer 28 may calculate 1F6)N+1)' and thereafter the stored values of IFB and E may be updated.

It should be noted that at the end of any given sampling interval N a certain finite amount of time is necessary in order for sample and hold circuit 20 to obtain a new value e(N+1) and for converter 26 to convert that value into E(N+l) and for computer 28 to operate upon that value. Similarly, it takes a finite amount of time for time interval meter 34 to provide At(N. If the length #t(N) of each sampling interval N is chosen sufficiently large with respect to the calculation time required, then the calculation time may be ignored, since it is not necessary that the output of integrator 15 be maintained exactly at zeroall that is required is that the output of integrator 15 be kept within operational limits.However, when the length At(N) of a sampling interval N is required to be short with respect to the calculation time period, the feedback signal IFB may be calculated for sampling interval N+1 using information obtainable at the beginning of sampling interval N since, as set forth above, it is not necessary that the output of integrator 1 5 be driven exactly to zero.

A summary of the operation of computer 28 is illustrated by the flow diagram of Fig. 2 wherein there is illustrated the steps of reading At)N from time interval meter 34; reading EN+l) representing th value of analog-to-digital converter 26 at the end of any given sampling interval N; calculating the feedback signal 1F8(N+1) as set forth above; determining whether this feedback number exceeds the limit of analog-to-digital converter 32 and adjusting the feedback signal to remain within the outer limits of converter 32, if necessary; delivering the feedback signal to digital-to-analog converter 32; and then updating E(N), E )N+1) and 1FB)N) for the next calculation of the digital feedback signal when the sampling interval N+1 is completed.

The accuracy of feedback signal 1FB)N) is dictated by the stability of the values of resistors 14 and 36, the stability of the values of capacitor 18, and the accuracy of converters 26 and 32.

However, the overriding requirement for satisfactory operation is simply that the length Xt(NI of each sampling interval N be sufficiently short as to prevent integrator 1 5 from exceeding its operational limits, and that the calculation of the feedback signal be of a magnitude sufficient to tend to hold the output of integrator 1 5 within those operational limits. Since the amount of feedback voltage is known during the entirety of each sampling interval, the amount of charge delivered to capacitor 1 8 by resistor 36 is known, and computer 28 can operate to calculate the total charge delivered to capacitor 1 8 during each sampling interval.By subtracting the known charge delivered by resistor 38 through the feedback signal, the total charge delivered by resistor 14 is readily calculated for any sampling interval. The average value of is over the sampling interval can then easily be calculated, based upon the duration of the sampling interval and supplied as an output signal Y(N) by computer 28 to output display 36.In the alternative, output Y(N} may be calculated as an average of is over a selected number of sampling intervals N with YIN} again being a function of the feedback signal, since the amount of charge delivered by the feedback signal to capacitor 18 must be subtracted in order to obtain an output signal Y(N} representative of the input analog signal 1S)N) or It is important to note that 1FB)N) serves only one purpose: to ensure that neither the integrator 1 5 nor track and hold circuit 20 nor analog-to-digital converter 26 is ever driven outside a linear operating range. So long as 1FB)N( is approximately programmed to accomplish this end, the subject invention operates.In other words, the exact algorithm used for producing 1FB)N) as a function of E)N) is not particularly important. Some algorithms may prove better than others. As a practical matter, for purposes of describing the subject invention, it is convenient to maintain IFB(N) constant over each sampling interval. In other words, 1FB)N( has been assumed to change only at the conclusion of each sampling interval although this constraint is by no means essential to the operation of the subject invention.

Since integrator 1 5 is never actually reset or zeroed, nor is the input analog signal eS or is ever removed, a continuous time signal may be converted to a discrete time digital signal, readily suitable for further digital processing.

For single conversion (i.e., computation of a single estimate of the average value eS or is over a single sampling interval) by the accuracy of the circuit of the present invention is controlled by the accuracy of capacitor 18, the accuracy of analogto-digital converter 26, and the accuracy with which the sampling interval is known. In computing the average of a number of estimates of eS or is, the accuracy of the digital-to-analog converter 32 dominates. For example, if analogto-digital converter 26 has a resolution of Y-bits and digital-to-analog converter 32 has a resolution of X-bits, X being greater than Y, then the resolution of output signal Y(N) over a number of sampling intervals N will approach X-bit resolution.There is obviously a transition region where, for more than one but fewer than "many" sampling periods N, the accuracy of the digital representation of eS or is depends upon all these parameters.

Accordingly, the resolution of the system in an averaging mode is independent of the resolution of the analog-to-digital converter 26.

Rather, the resolution is determined (1) by the size of the integrating capacitor 1 8; and (2) the total duration of a number of sample intervals if averaging is performed.

Although for purposes of the above description, trigger 24 was assumed to operate at a constant time period, in fact, it may be preferable to operate trigger 24 to provide varying times, or to synchronize the operation of trigger 24 with a source of coherent noise, to make the output of integrator 1 5 independent of any effects of such coherent noise.

In summary, the system of the present invention contains only a single integrator which functions continuously. The output of the integrator is maintained nominally at zero by continuously sampling its output and returning a feedback signal recalculated to maintain the output at zero for subsequent sampling time periods. Although each successive estimate of the analog input current does not depend exactly upon offsetting the input signal with a feedback signal, the accuracy of an average number of estimates of the input signal depends only upon the accuracy of the feedback signal. There is, in effect, a "fractional bit carry-over" during each time period, which permits a resolution of estimates of the input signal to be equal to or greater than the resolution of the feedback signal established by the digital-to-analog converter.

While a particular embodiment of the present invention has been shown and described, it will, of course, be obvious to one skilled in the art that certain advantages and modifications may be effected without departing from the spirit of the invention, and, accordingly, it is intended that the scope of the invention not be determined by the foregoing examples, but only by the scope of the appended claims.

Claims (14)

Claims

1. A continuous integrator analog-to-digital converter comprising: (a) integrator means for continuously integrating an input analog signal; (b) sampling means for successively determining the output of said integrator means without interrupting the continuous operation of said integrator means; and (c) circuit means responsive to the output of said sampling means for supplying a feedback signal to said integrator means which permits continuous operation of said integrator means by maintaining the output of said integrator means within the operational limits of said integrator means, said circuit means further supplying a digital output signal representative of said input analog signal as a function of said feedback signal.

2. The converter of Claim 1 further including an analog-to-digital converter of Y-bit resolution coupled between said sampling means and said circuit means.

3. The converter of Claim 2 further including a digital-to-analog converter of X-bit resolution coupled between said circuit means and said integrator means wherein X is greater than Y.

4. The converter of Claim 3 wherein said circuit means has a X-bit resolution digital output signal.

5. The converter of Claim 1, 2, 3 or 4 wherein said sampling means operates at constant time intervals.

6. The converter of Claim 1, 2, 3 or 4 wherein said sampling means operates at variable time intervals.

7. The converter of Claim 5 wherein said feedback signal is constant during said time intervals.

8. The converter of Claim 6 wherein said feedback signal is constant during said time intervals.

9. The converter of Claim 5 wherein said feedback signal is variable during said time intervals.

10. The converter of Claim 6 wherein said feedback signal is variable during said time intervals.

11. A continuous integration analog-to-digital converter comprising: (a) integrator means for continuously integrating an input analog signal is; (b) trigger means for determining the start of a plurality of sampling intervals N; (c) sampling means for determining the output e(N) and yen+,) of said integrator means at the beginning of successive sampling intervals N and N+ 1, respectively, without interrupting the continuous operation of said integrator means; (d) an analog-to-digital converter for converting said outputs e(N) into digital signals ERIN) and E)N+l(, respectivley, of Y-bit resolution; and (e) circuit means for: (i) providing digital feedback signals 1FB(N) and IFH(N+1) for application in analog form to said integrator means for each sampling interval N and N+1, respectively, which permit continuous operation of said integrator means by tending to maintain 0)N) and e(N+,) during said sampling intervals N and N+1, respectively, within the operational limits of said integrator and sampling means; (ii) storing said feedback signal IFB(N) for each sampling interval N; (iii) storing a digitized form of the output of said integrator means for the start, E)N), and the start, E )N+1)' of successive sampling intervals N and N+1;; (iv) updating said feedback signal 1FB)N) at the beginning of each subsequent sampling interval N+1 to provide a new feedback signal 1FB)N+1) as a function of IFB(N), E(N), and E(N+1); and (v) providing a digital output signal representative of the input analog signal as a function of said feedback signal 1FB)N)

1 2. The converter of Claim 10 wherein said feedback signal is updated in a manner to maintain the output of said integrator means constant.

13. The converter of Claim 11 wherein said feedback signal is updated in a manner to maintain the output of said integrator means at zero.

14. The converter of Claim 13 wherein: IFBIN+,)a[C/\t(N)] [2 EIN+1) E(N)]+IFB(N) wherein C represents a constant determined by the operating characteristics of said integrator means; and \t(N( represents the length of said sampling intervals for each sampling and interval N.