GB2120869A - Controlling the output level of an electrical power supply - Google Patents

Abstract

The output level of a load (12) is varied by controlling the proportion of time, during an arbitrary time interval, when the output is energized, thus controlling the average output level of the load. The zero crossings of an AC energizing source waveform (11) are detected (30, Fig. 2) to trigger an interval timer (28, Fig 2a) producing pulses which are coupled to an on/off input (line B) of the load; the duration of each "on" time interval is adjustable (by resistor 28', Fig 2a) to control the portion of the arbitrary time interval during which the load is "on". In the embodiment a discharge lamp (12) driven by an inverter (not shown) is the load. Pulses on line B saturate Q20 to interrupt inverter operation. Inverter frequency and hence maximum light output may be controlled by a variable resistor connected between terminals AA'. A photoisolator (Fig 2) is used to couple pulses from the timing means to line B. An astable multivibrator (Fig 2d) is used to supply all timing information when the inverter is supplied from a continuous DC source, e.g. a battery. <IMAGE>

Description

SPECIFICATION Method of, and apparatus for, controlling the output level of a variable output level load The present invention relates to load control methods and apparatus and, more particularly, to a novel method of, an apparatus for, variable controlling the output level of a variable output level load.

The ability to continuously control the output level of a load, particularly from a remote location, facilitates many economic advantages in this day and age of conservation of energy. Specifically, the ability to set the output of a plurality of light sources, located at various locations in one or more buildings, either at the source locations or from a central facility, as highly desirable. With the advent of variable-output gas discharge lamps, such as mercury-vapor-discharge fluorescent lamps and associated ballasts, it is highly desirable to provide both a method of, and apparatus for, substantially con tinuouslyvariable controlling the output level of the variable output level lighting loads.

In accordance with the invention, a method for controlling the output level of a variable output level load, such as a ballast-lamp combination, includes the steps of: establishing a time interval of preselected duration; and controlling the load to the energy-consumptive condition for a variable portion of that preselected time interval, to vary the average energy consumed by load and therefore establishing the average load output level. By varying the energy-consumptive interval, for a substantially fixed duration total interval, the output load level is made variable.

In one preferred embodiment, wherein a ballastlamp load combination is controlled between the on and off conditions by the magnitudes of the resistance connected between an on/off ballast terminal and a ballast common terminal, the load "on" time interval is established by detecting the zero crossings of the load energizing AC waveform to trigger a monostable multivibrator of controllable (or programmable) duration. In one preferred embodiment, the programmable timer output is coupled to the load on/off input terminals via an isolator, preferably of the optoelectronic type.

Accordingly, it is an object of the present invention to provide a novel method for controlling the output level of a variable output level load.

It is another object of the present invention to provide a novel apparatus for controlling the output level of a variable output level load.

These and other objects of the present invention will become apparent upon consideration of the following detailed description when read in conjunction with the drawings.

Figure lisa schematic diagram of a portion of a variable output level load (a dimmable fluorescent lamp and ballast) and useful in understanding principles of operation of the present invention; Figures 7a and it are coordinated graphs respectively illustrating the source voltage applied to the ballast-lamp circuit of Figure 1 and the voltage applied by the ballast to the lamp, for the maximum load output level condition; Figure 2 is a schematic block diagram of a novel load level control circuit, in accordance with the principles of the present invention, as attached to the on/off input terminals of the ballast of Figure 1; Figure 2a is one embodiment of a timing means for use in the apparatus of Figure 2;; Figure 26 and 2c are coordinated graphs respectively illustrating the control waveforms applied to the on/off input control terminals of the load of Figure 1 for various load output levels, and the resulting load voltages; and Figure 2d is one embodiment of a timing means for use in the apparatus of Figure 2, when the load is powered by a DC potential.

Referring initially to Figure 1, a variable-output level load is represented by a ballast 10 connected between an electrical energy source 11 and one or more gas discharge lamps, such as a fluorescent lamp 12. Ballast 10, of which only the power supply section 10a and control section 10b are shown, is configured to control the luminous output of fluorescent lamp 12 as a function of an externally-provided parameter, such as the magnitude of an impedance (e.g. an electrical resistance) connected between control terminals A and A', and with the on-off function of the ballast-lamp combination being controlled by the impedance between an on-off terminal B and a ballast common line terminal C.

One method for providing a variable (dimmable) fluorescent lamp light level is described and claimed in U.S.A. application serial number 177,835 and one embodiment of an inverter-type ballast utilizing that method for fluorescent lamp light level control is described and claimed in U.S.A. application serial number 177,942 both of which applications were filed August 1980, are assigned to the assignee of the present invention and are incorporated herein by reference to their entirety.As described in the aforementioned patent applications, the AC energy source 11 is coupled to a bridge rectifier 14, comprised of diodes D1-D4, and a filter capacitor Cl, which forms a power supply section 10a providing DC potential to the ballast, including a ballast di/dt control circuit section 10b and a ballast high-power inverter section (not shown) which is controlled by section lOb to provide relatively high-frequency energizing waveforms to fluorescent lamp 12. The level of light produced by fluorescent lamp 12 is a function of the frequency of the high-power inverter, which frequency is controlled by circuit section 10b.

The control section lOb includes a di/dt sensor, or detector, consisting of transistors Q12 and 013; resistors R15, R16, R17, R18, and R19; and dual transformer windings L3A and L3B. The di/dtsensing control circuit has a threshold, or trip, point, which is the point at which the voltages at points X and Y drop to a low enough value to turn off both of transistors Q12 and 013.Accordingly, the pair of transformer windings are wound upon a portion of the inverter transformer (not shown), such that if the voltage across transformer winding L3A is positive at the dotted end, a current will flow from point X, through resistor R16, and turn on transistor Q13, while the voltage across winding L3B is simul taneously positive at the dotted end, whereby transistor Q12 is turned off. Similarly, if the voltage across winding L3B is positive at the undotted end, a current will flow from point Y, through resistance R15, turning on transistor Q12, while the voltage across winding L3A is negative at the dotted end, applying a negative voltage to the base electrode of transistor Q13, which transistor is cutoff.As the windings L3A and L3B are of an equal number of turns, it will be appreciated that the voltages at points X and Y (obtained by coupling both windings to the same transformer core with substantially equal coupling coefficients) are substantially equal in magnitude but of opposite polarity, as indicated by the phasing dots. Thus, when the voltage at point X drops below a predetermined threshold value, transistor 013, which was previously conducting, will turn off. At the same time, the voltage at point Y is equal in magnitude, but of opposite polarity, such that transistor Q12 is not conducting, whereby a node Z is at a voltage above common line C potential, since neither transistor 012 nor transistor 013 are conducting. As node Z is not at common line C potential, transistor 014 is caused to conduct.This initiates a reversal of inverter load voltage, as described in more detail in the aforementioned patent applications. The load voltage reversal reverses the polarity of the voltage across windings L3A and L3B, whereby transister 012 is caused to conduct and turn off transistor Q14. The point X voltage changes until, at the preset threshold value, transistor 012 turns off and again raises the voltage at node Z, again causing transistor Q14 to turn on to initiate reversal of the load voltage. The abovesummarized action continues in cyclic fashion, with transistors Q12 and Q13 being alternately turned off when the absolute amplitude of the voltage at one of points X and Y reaches a preset threshold value. This preset threshold value is established by the turns ratio of windings L3A and L3B.Resistances R15, and R16, of substantially equal magnitude, are utilized to convert the voltages at points X and Y to currents for driving the base electrodes of respective transistors Q12 and 013. The threshold value, at which the load voltage is switched (and which therefore establishes the light output of load 12) may be changed by the connection of a resistance between (a) each of the base electrodes of transistors Q12 and 013, and (b) either common line C potential or the opposite transistor base electrode.Thus, connection of a resistance R between input terminals A and A' causes the instantaneous positive potential at one of terminals A or A' to be reduced, upon application of the associated winding voltage to the associated base electrode of respective transistors Q12 or 013, via the voltage divider provided by resistances R1 5 and R16 and the resistance between terminals A and A'. The voltage divider action is further enhanced by the connection of the opposite and of resistance R back to the instantaneous negative voltage at the remaining one of terminals A or A', respectively.By means of this voltage divider action, the voltage, across that one of windings L3A and L3B associated with the transistor to be turned off, is applied to the base electrodes with decreasing magnitude for decreasing magnitudes of resistance R, whereby a particular polarity of voltage is applied to the load for increasing shorter time intervals before load voltage switching occurs, thereby increasing the load driving frequency and reducing the light output from fluorescent light 12.If the resistance betweenterminals A and A' is substantially zero (a short-circuit) the voltages at the base electrode of both transistors Q12 and 013 will be substantially zero, with respect to their emitter electrodes, since the voltages at points X and Y are always of substantially the same magnitude but of opposite polarity, and as resistances R15 and R6 are of substantially equal value. In this condition, transistors Q12 and 013 are always cutoff and a maximum inverter frequency (minimum lamp output) condition occurs.Conversely, if the resistance between input terminals A and A' is of a relatively high value, the transistor base electrodes will then be essentially isolated from one another and the respective transistors 012 and Q13 will be alternately turned on with relatively low absolute voltage magnitudes across the associated one of windings L3A and L3B; this corresponds to a relatively low frequency of inverter operation whereby fluorescent light load 12 operates at substantial constant maximum power and produces a substantially constant maximum light output, as further described and claimed in U.S. Patent No. 4,060,752 (wherein the base electrodes of the control transistors are in no way coupled to each other), which patent is assigned to the assignee of the present invention and incorporated in its entirety by reference hereto.

As previously described, the inverter portion of the ballast switches the voltage across load 12 responsive to transistor 014 entering the cutoff condition.

By paraileling transistor Q14 with another transistor 020, inverter switching (and therefore the existence of a periodic waveform necessary to cause load power consumption) may be defeated if parallel transistor Q20 remains in the saturated condition, preventing the voltage at line W (the common collector connection between transistors Q14 and 020) from rising. Thus, if the magnitude of a resistance R25 is chosen such that transistor Q20 normally receives sufficient base electrode current to remain in the saturating condition, the load 12 is turned off.If input terminal B, connected to the base electrode of transistor Q20, via resistance R26 (which may, but need not, be of relatively low value) is connected to system common line C, the base electrode current of transistor Q20 is shunted to common and, if resistance R26 is small, transistor Q20 is cutoff, allowing the load to be turned on and the light output thereof controlled by the resistance of element 20a between input terminals A and A'.

Conversely, if input terminal B is disconnected (allowed to float) from the ballast common terminal C, or if resistance R26 is of sufficiently large magnitude, transistor Q20 receives enough base electrode drive current to reenter saturation and turn off load 12. This "output off" condition occurs whenever transistor Q20 is saturated, regardless of the output level set by the impedance between input terminals A and A'. The output level is determined by the terminals A-A' impedance only when the ballast is in the "output on" condition, i.e. with transistor Q20 cutoff. Thus, in addition to the variable resistance provided between input terminals A and A' to establish the level of load light output, switching of input terminal B between a relatively low and a relatively high resistance condition, to ballast common terminal C, is required.

Power supply capacitor C1 may have a relatively small capacitance value, whereby the power supply section output voltage V1 (Figure la) is a full-waverectified sinusoidal waveform 15. Accordingly, the voltage V' across load 12 is, as shown in Figure 1 b, a periodic burst having an envelope 16 containing the high-frequency ballast output waveform 17. An output voltage burst occurs only when the power supply section output voltage V1 exceeds some load starting voltage magnitude Vs, whereby the load (lamp 12) is turned on and off during every half cycle of the source 11 waveform.Thus, at the starting time to of a first half-cycle of the power supply section output waveform 15, the voltage has substantially zero magnitude and a rising slope; the voltage, being less than the starting voltage magnitude Vs, is insufficient to "start" the load, and the load voltage V' is substantially zero. At some time t1, the power supply output waveform 15 reaches the starting voltage magnitude Vs, and the load voltage suddenly increases, with the burst envelope 16 obtaining a peak value, in region 16a, for a start interval T6, during which start time interval lamp discharge is initiated.At the end of the start time interval T5, the lamp discharge is maintained with a substantially constant envelope value, in region 16b, until times2, when the power supply section output voltage waveform 15 decreases to be less than a required maintaining voltage V5 (here assumed to be the starting value, for purposes of simplicity). At this time, the lamp voltage suddenly decreases substan tially to zero, in region 16c, and the load is turned off, after a total "on" time interval Ton, where TON = t2-t1. The power supply section output voltage waveform 15 decreases substantially to zero at time to', at which time a second half-cycle commences.

The load remains in the off condition until time t1' when the rising waveform again obtains the start voltage magnitude Vs, and the next burst of high frequency waveform 17, with envelope shape 16, occurs. Thus, the load is in the off condition for a time interval TOFF, where TOFF = t1'-t2, for a total cycle time interval TAC = TON + TOFF. For a source 11 having a 60 Hz. frequency, and with full-wave rectified power supply section output waveform 15 having a 120 Hz. frequency, the burst-to-burst time interval TAC iS on the order of eight and one-third milliseconds.It will be seen that, as long as the load (lamp 12) is not adversely affected by such rapid and frequent turn-on and turn-off activity, the hereina bove described method and apparatus provides useful output load level control; particularly in a fluorescent lighting system, the fluctuation in lamp output is sufficiently rapid to be substantially unde tectable by the human eye.

The foregoing utilizes a variable impedance be tween load input terminals A and A' to adjust the load output level magnitude during the load-on time intervals. Such variable impedance systems are described and claimed in copending applications RD-11559 and RD-12202, filed on even date herewith, assigned to the assignee of the preset application and incorporated herein in their entirety by reference. It is desirable to provide an even lower cost method and apparatus for controlling the load output level; accordingly, in our novel method the input terminals A and A' are not connected to a load-level control impedance, and our apparatus 20 (of Figure 2) is connected only between load on/off control terminal B and common line terminal C.As previously discussed hereinabove, the effect of removing a load-controlling impedance from between load input terminals A and A' will cause the load output level to be at the maxiumum output level, when the load in enabled by forming a sufficiently low-resistance connection between load terminals B and C, such that transistor 020 is placed in the cut-off condition. We have found that the effective (average) load output level is controllable by controlling the load-on time interval TON (Figure 1 b). Control apparatus 20 thus includes means 22 for providing a resistance between load terminals B and C with controllable low and high resistance between terminals 22a and 22but respectively turn on and off load 10.Advantageously, as the load common terminal C may not be referenced to ground potential, means 22 provides electrical isolation between its output terminals 22a and 22b (connected to the load), which may be floating, and a pair of input terminals 22c and 22d.

In one presently preferred embodiment, isolationand-switched-resistance means 22 is an optoeiectronic isolator having a phototransistor 24 with a collector-emitter circuit between output terminals 22a and 22b and having the resistance thereof controlled responsive to the magnitude of light emitted from a light-emitting diode 26, connected between input terminals 22c and 22d. Thus, if a relatively low magnitude of a current I is caused to flow from input terminal 22c, through light-emitting diode 26, to output terminal 22d (which may be connected to ground potential), a relatively low amount of light is received by phototransistor 24.

The phototransistor collector-emitter circuit is accordingly in a relatively high resistance condition, whereby insufficient current is shunted from the base electrode of load control transistor Q20, and the load is in the off condition. When a relatively high magnitude of current I is caused to flow through diode 26, a relatively great amount of light is produced thereby and received by phototransistor 24, whereby a relatively low magnitude of resistance appears in the collector-emitter circuit thereof, between output terminals 22a and 22b, and also between load control terminals B and C. Accordingly, transistor 020 is switched to the cut-off condition and operation of the load at full output occurs.

Switching current I is provided by a TON timing means 28, having an output 28a coupled to isolation means input 22c, and having an input 28b receiving a train of trigger pulses from the output 30a of a zero-crossing detector 20, receiving the source 11 periodic waveform 11 a at its input. Thus, each time source waveform 11 a obtains a zero amplitude, at one of zero crossings 30', zero crossing detector 30 issues a pulse to timing means input 28b. Respon siveto each pulse, timing means 28 provides a pulse of current I, to the light emitting diode 26, of time interval TON. Responsive to each pulse of current from timing means 28, the resistance between load on/off terminals B and C is reduced and the load operates during the power supply section half-cycle associated with the particular zero crossing 30', to provide the load voltage burst of Figure 1 b.

The load output level is adjustably varied by operation of a timing control portion 28' of timing means 28 to vary the time duration of the TON pulse of current during each power supply section halfcycle. In one preferred embodiment, shown in Figure 2a, timing means 28 is an integrated circuit monostable multivibrator 32, connected between a source of operating potential of magnitude +V, and ground potential. The monostable multivibrator has a trigger T input and a 0 output at which a pulse of voltage, substantially of magnitude +V, appears, commencing at a time to substantially identical to the time t,, at which a positive-going pulse is received at trigger input T.The duration TON of pulse 32a is determined by the magnitude of a timing capacitance C and the magnitude of a timing resistance R, set by variable control mechanism 28', connected to multivibrator 32. A series resistance Ro is connected between multivibrator output 0 and isolation-and-switching-resistance means input 22c, to convert the monostable multivibrator output voltage pulse to a pulse of current I flowing through light-emitting diode 26.

Referring now to Figures 2b and 2c, operation of load-level-control circuit 20 commences with the detection of one of zero crossings 30' at time to. Zero crossing detector 30 issues a pulse (such as the to pulse in Figure 2a) to timing means 28 input 28b.

Response to each zero-crossing pulse, a pulse of current I is supplied by means 28 to light emitting diode 26 and the voltage VB between load input on/off control terminals B and C falls from the Voff magnitude to the substantially zero Von magnitude, and remains at the V,, magnitude for the time duration of the output pulse from timing means 28.

Assuming initially that the duration of the timing means output pulse is for a time interval To, at least as long as the time duration from the start of a half-cycle at time to, until the source 11 waveform 15' (shown in broken line in Figure 2c) decreases to be less than the sustaining Vs, at tome time ta. In the initial portion of each To time interval, i.e. from zero crossing time to until source waveform 15' reaches the starting voltage Vs magnitude, the load voltage V' is substantially zero.When the power supply section output voltage exceeds starting voltage Vs, normal operation of the ballast-lamp combination occurs, with a burst of high-frequency waveform 17, having an envelope 16, including a starting peak portion 1 6a, a substantially constant amplitude portions 16b and a decreasing amplitude portion 16c (the latter portion occurring as the half-wave power supply section output waveform 15' falls toward the starting voltage magnitude). As the duration of each "on" pulse is sufficiently long such that the To pulse is still present at time ta when the power supply output waveform drops below the Vs level, a complete load-energizing high-frequencywaveform burst 16 occurs for each To pulse.Thus, at time ta the voltage across the load on/off input terminals VB returns to the Voff level, as the load is turned off until the next half-cycle commences.

Timing means TON control 28' may be adjusted to reduce the time duration of the "on" pulse to a time interval T1, measured between zero crossing time to' and another time tb, at which time tb the power supply section outputwaveform 15' has an amplitude greater than the start voltage Vs magnitude. In this condition, the load-energizing burst 16' has the normal starting voltage peak section 16a' and has at least a portion of the substantially-constant amplitude center section 16b'.However, because the load on/off input terminal voltage VB returns to the "off" voltage Voff level at time tb, before the energizing waveform burst terminal portion 16c has occurred, the load energizing waveform is abruptly terminated at "off" time tb, whereby the total on time of the load is a reduced portion of each half-cycle of the power supply section of the output waveform. Accordingly, the amount of average load energy consumption (and the amount of average light produced by a light lamp 12) decreases, relative to the full-on case with a timing means To interval.

If the timing means control 28' is adjusted to even further decrease the "on" time interval (to a relatively short time interval T2 commencing at a zero crossing time to" and terminating at a time tc, e.g. at a time when the power supply output section waveform 15' reaches a peak) then the highfrequency burst envelope 16" still contains the starting peak portion 16a" and a small amount of the substantially-constant amplitude center portion 16b", butthe load is abruptly turned off a relatively short time after load energization has occurred.It will be seen that the average amount of energy consumed by the load, and therefore the average resulting load output (lamp light, in the illustrated example) is less in this case then in the case with a somewhat longer "on" time interval T1, and both the T1 and T2 time interval cases provide less load output than the full-conduction time interval To case.

As the "on" time interval TON can be adjusted continuously or in relatively small steps, the percentage of load "on" time to total time can be controlled and thus the average load output level can be varied.

It should be understood that the timing means control 28' may be a manually adjustable control and/or a relatively programmably adjustable control.

For example, timing resistance R (Figure 1 a) may be a potentiometer with a manually operable control shaft or may be a set of resistors and switches controlled by a computer. Similarly, as the function oftiming resistance R may, in a particular timing means, be to set the charging current into timing capacitor C, a manually-, or programmably-, variable current source (including, perhaps, a digital-toanalog converter) may be utilized to vary TON.

The foregoing assumes that a relatively unfiltered AC waveform appears at the ballast-load energizing potential point (the power supply portion 1 a output, across capacitor C1), with the toad "off" time intervals being established either by the decrease of the periodic voltage below a predetermined level (the start voltage Vs level), or as the time interval remaining after a TON time interval, itself established by characteristics of a periodic waveform (the zero crossings of the source sinusoid). For loads operating from a non-periodic or DC source potential, the load output level control circuit 40 of Figure 2d, may be utilized. Circuit 40 utilizes an astable multivibrator having a variable-duty-cycle square-wave output waveform, coupled via a resistor Ro to input 22c of the isolation-and-resistance-magnitude means 22.

The astable multivibrator has a pair of inputs 40b and 40c, at each of which the magnitude of a resistance coupled to either operating potential (as shown) or to ground potential (not shown), determines the duration of the respective TON and TOFF time intervals. By connecting the ends of a potentiometer 42 to inputs 40b and 40c and connecting the potentiometer wiper arm to the required potential (being operating potential in the circuit as shown), the effective timing resistances (and therefore the on and off time intervals) may be varied, with one of the "on" and "off" time intervals being increased as the other is simultaneously decreased, and vice versa.

Thus, even with a load operating on a DC potential, the load output level can be continuously varied in accordance with the invention.

While several presently preferred embodiments of our novel invention have been set forth with particularity herein, many modifications and variations may now occur into those skilled in the art. It is our intent, therefore, to be limited only by the scope of the appending claims and not by the specific details disclosed herein.

Claims (18)

1. A method for varying the average output level of a load having an input controlling the load output between on and off conditions, comprising the steps of: establishing a time interval of preselected duration; providing a signal to said load input to control the load to and on condition for a variable first portion of the preselected time interval; causing the load input signal to control the load to and off condition for a remaining second portion of each preselected time interval; and selecting the duration of the variable first portion of the preselected time interval during which the load is controlled to the on condition to establish a desired average load output level.

2. The method as set forth in Claim 1, wherein the preselected time interval is established by successive zero crossings of a signal having a periodic waveform.

3. The method as set forth in Claim 2, wherein the periodic waveform signal is utilized to energize the load.

4. The method as set forth in Claim 2, wherein the periodic waveform is an AC powerline sinusoid waveform.

5. The method of Claim 1, wherein the load is energized by a DC potential, and further including the step of providing an oscillatory circuit, energized by said DC potential, to establish at the load input the time duration of each of said first and second time interval portions during each of a succession of preselected time intervals.

6. Apparatus for variably controlling the output level of a load having an input terminal at which a signal having respectively first and second levels will control the load output between respective on and off conditions, comprising: means for generating a succession of trigger signals, successive ones of said triggering signals having substantially equal time intervals therebetween; means for applying said signal to said load input terminal at said first level for a determinable time duration responsive to each of said trigger signals and for applying said signal at said second level to said load inputterminal at all othertimes;; and means for adjusting the time duration of application of said first level signal to said load input terminal during a preselected time interval to control the ratio of load on to off times to vary the average load output level.

7. The apparatus as set forth in Claim 6, further including means for electrically isolating said load input terminal from said signal applying means.

8. The apparatus of Claim 7, wherein said isolating means is a photoisolator having an input receiving said applying means signal, and an output coupled to said load input.

9. The apparatus as set forth in Claim 7, wherein said isolating means is a photoisolator having means for emitting optical flux of magnitude responsive to the output level of said applying means; and means receiving at least a portion of the emitting means flux for providing a signal varying between said first and second levels at said input terminal responsive to the received magnitude of emitting means flux.

10. The apparatus as set forth in Claims 6 or 9, wherein said applying means includes a monostable multivibrator having an input receiving said trigger signal and an output providing said signal responsive to each of said trigger signals.

11. The apparatus as set forth in Claim 10, wherein said adjusting means is a potentiometer operatively coupled to said multivibrator to set said variable on duration thereof.

12. The apparatus as set forth in Claim 10, wherein said load is energized by an AC sinusoid and said triggering means includes means for detecting the zero crossings of the AC sinusoid to provide a trigger signal at each said zero crossing.

13. The apparatus as set forth in Claim 6, wherein said applying means is an astable multivibrator.

14. The apparatus as set forth in Claim 13, wherein said adjusting means is a potentiometer coupled to said astable multivibratorto respectively increase and decrease the time duration of said first level and simultaneously decrease and increase the time duration of said second level of said signal.

15. The apparatus of Claim 6, wherein said adjusting means is adapted for manual control.

16. The apparatus of Claim 6, wherein said adjusting means is adapted for programmable control from a remote location.

17. The method of Claim 1, substantially as herein before described with reference to the drawings.

18. The apparatus of Claim 6 substantially as hereinbefore described with reference to and as illustrated in the drawings.