ES2735723T3 - Multilevel Power Converter - Google Patents

Abstract

Multilevel converter that includes at least one arm (B) formed by several stages (Et1, Et2, ...., Etn) of rank one to n (integer greater than one) mounted in cascade, the stage (Et1) of rank 1 to be connected to a current source (I) and the stage (Etn) of rank n being destined to be connected to a voltage source (VCC), characterized in that stage (Et1) of rank one includes a single structure (Ce10) switchgear of four voltage levels and a stage of range i (i comprised between two and n) includes i structures (Cei1, Cei2, ... Ceii) for switching four identical voltage levels mounted in series, including each of these switching structures a cell (T1, T2, T1 ', T2', C12) of the floating capacitor type with three voltage levels comprising a quartet of elementary switches (T1, T2, T1 ', T2') in series possessing a middle node (S), two base cells (T3u, T3'u; T3l, T3'l) each formed by a pair of switches (T3u , T3'u; T3l, T3'l) elementary series have two terminals (N6, N7; N8, N9) ends and a midpoint and bridge (C9, C10, C11) capacitive divider that has two ends formed by a triplet of energy storage devices (C9, C10, C11) mounted in series between which the two energy storage devices (C9, C11) are in extreme position, each energy storage device (C9, C11) in extreme position being connected to the end terminals (N6, N9) of a different base switching cell, connecting a midpoint of each base switching cell to a different end of the quartet of elementary switches (T1, T2, T1 ', T2'), with the mid-node of each floating capacitor-type cell of range stage i connecting to one end of the capacitive divider bridge of a four-voltage level switching structure of the range stage i-1.

Description

DESCRIPTION

Multilevel Power Converter

Technical field

The present invention relates to multilevel power converters more particularly intended to operate in the medium voltage field.

Prior art

Known medium voltage power converters generally use semiconductor switches in series to allow a voltage rise. The main difficulty of serializing these semiconductor switches is to obtain identical voltages at the terminals of all these semiconductor switches at every moment. If transient or permanent overloads appear, the destruction of semiconductor switches may occur.

Techniques have been developed based on the interlocking of the orders of the switches associated with the use of transformers, allowing to manage the distribution of the voltages and reconstitute the waveforms. But the transformers have a non-negligible cost and prevent the realization of compact converters.

Another solution arises, it is NPC type cells (by neutral point clamped or neutral fixation) with two pairs of semiconductor switches in series, two diodes in series connected on one side to the common point between the two switches of the first pair and on the other to the common point between the two switches of the second pair. There is also a series of two capacitors connected to the terminals of the assembly formed by the pairs of semiconductor switches. The common point between the two diodes in series is connected to the common point between the two capacitors in the series.

This type of cell leads to a satisfactory waveform and a reduction in voltage restrictions on semiconductor switches. On the contrary, voltage imbalances in the capacitor terminals can occur.

There are improvements to the original NPC topology, replacing the two diodes with a pair of semiconductor switches. This topology is called ANPC of 3 voltage levels.

To further increase the acceptable voltage level, it has been proposed to put more switches in series and add capacitors, which leads to the topology called ANPC of 5 voltage levels. The 5-voltage ANPC type cells are currently limited to voltage levels of the order of 6.9 kV, which is clearly not enough.

Modular multilevel converters (MMC for modular multilevel converter) are also known in which each arm to be mounted on the terminals of a DC voltage source includes two sets in series, having a common terminal to be connected to an alternating current source. Each set includes several modules, each consisting of at least two elementary switches in series and a capacitor connected in parallel with them. A connection is made between the common point for the two elementary switches of a module and one end of the series of elementary switches of the neighboring module. Depending on the conductive or blocked state of the elementary switches of the module, the capacitor is shorted or in the circuit. The capacitors have the same value and an identical supported voltage equal to the ratio between the continuous voltage applied to an arm divided by the number of modules in the arm. The value of the capacitors depends on the frequency of the output signal on the alternating side in the case of an operation as an inverter or the input signal in the case of an operation as a rectifier. Its supported voltage is limited to what limits the overvoltages generated by its parasitic inductances. In the case of a variable speed drive, the motor supply frequency varies from zero to the nominal value, which makes it impossible to avoid a reasonable value capacitor. It has also been proposed to make floating condenser type cells, also known under the name of embedded elementary cells. Such a floating capacitor type cell allows a voltage source to be linked to a current source by associating any number of elementary cells in series. Each elementary cell includes two semiconductor switches in series and a capacitor that connects two neighboring elementary cells to each other in the manner of a scale. However, this solution has drawbacks linked to the presence of the floating condenser between two elementary cells. The more the number of elementary cells increases, the more the extra cost linked to the capacitors increases and the greater the amount of energy stored in these capacitors. The capacitors have the same value, but their supported voltages are different, the supported voltage increases with the range of the elementary cell, it is worth kE / n being k the range of the elementary cell, where n is the total number of elementary cells and E the voltage applied to the input of the elementary cell of rank one. The value of the capacitors is essentially linked to the cutoff frequency. The size of the capacitors is all the greater the higher its supported voltage. This is the same for the parasitic inductance they possess. These parasitic inductances are at the origin of switching overvoltages, the highest overvoltages will therefore appear on the elementary range cells high.

In articles [1], [2] whose references are at the end of the description, a cell of three semiconductor switches in series has been proposed that allow 4 voltage levels to be obtained including a floating capacitor type cell. However, it is currently limited, with existing semiconductor switches, to voltage levels of the order of 6.6 kV which is not sufficient in certain applications, this level not corresponding to more than a fraction of the useful range of the medium voltage . The number of voltage levels acts on the resistance over time of the motor insulation that will be fed by the cell. The smaller the number of voltage levels, the shorter the lifetime of the insulators. They are subject to high-voltage tension steps.

Exhibition of the invention

The present invention aims to propose a multilevel converter that can work with voltage levels higher than those of the prior art, without having to resort to transformers, or multiply the number of semiconductor switches put in series.

Another object of the invention is to propose a multilevel converter that is less expensive and more reliable than prior art multilevel converters, for a given voltage level.

Another object of the invention is also to propose a multilevel converter that uses a set of standard capacitors with limited supported voltage.

A supplementary object of the invention is to propose a multilevel converter that limits the appearance of parasitic inductances and their influence.

To achieve this, the present invention proposes to realize a multilevel converter that includes at least one arm formed by several stages of range one an (n integer greater than one) mounted in cascade, the stage of stage 1 being destined to be connected to a current source and the range stage being intended to be connected to a voltage source. The stage one stage includes a single switching structure of four voltage levels. A stage of range i (i between two and n) includes switching structures of four identical voltage levels mounted in series. Each of these switching structures includes a three-level floating capacitor type cell comprising a quartet of elementary switches in series having a middle node, presenting two base cells each formed by a pair of elementary switches in series two end terminals and a midpoint and a capacitive divider bridge that has two ends that include a triplet of energy storage devices mounted in series between which the two energy storage devices are in extreme positions. Each energy storage device in the extreme position is connected to the end terminals of a different base switching cell, a midpoint of each base switching cell is connected to a different end of the elementary switch quartet. The middle node of each floating capacitor type cell of the range stage i is connected to one end of the capacitive divider bridge of a four voltage level switching structure of the range stage i-1.

The converter thus defined allows to reach a voltage level of the order of 13.8 kV with currently available limited supported voltage switches (6.5 kV), limiting the number of stages to two and therefore using only six elementary switches in series.

To balance the four voltage level switching structures in tension, the energy storage devices of the same capacitive divider bridge have the same energy storage capacity and the same supported voltage.

To respect the connection rules between the voltage source and the current source, the middle node of at least one floating capacitor type cell of the range stage i is connected to one end of the capacitive divider bridge of the range stage i- 1 through an inductance.

When several inductances connect the stage of rank i to the stage of range i-1, these inductances have the same value.

The two pairs of elementary switches of the two base switching cells of the same stage have the same switching function.

In operation, the elementary switches of the same pair are always in complementary states except for the value of the dead time.

In the quartet of elementary switches of a floating capacitor type cell, two are in the extreme position and two are in the middle position, the two elementary switches in the extreme position are always in complementary states and the two elementary switches in the medium position are always in complementary states, being one conductor and the other being blocked.

The elementary switches each include a controllable power electronic switch associated with a diode connected in anti-parallel.

Energy storage devices are chosen from a capacitor, a battery, a fuel cell.

The present invention also relates to a speed variator that includes a cascade with a converter thus characterized by operating as an AC / DC rectifier and a converter thus characterized by operating as a DC / AC inverter, connected to each other by its continuous sides by means of a voltage source.

Brief description of the drawings

The present invention will be better understood by reading the description of exemplary embodiments given for purely indicative purposes and in no case limiting by referring to the accompanying drawings in which:

- Figure 1A illustrates, in a very schematic manner, a multi-level converter arm object of the invention with n cascade-mounted stages, Figure 1B is a single-phase multi-level converter that includes two arms similar to those of Figure 1A;

- Figure 2 shows switching structures of 4 voltage levels of the multilevel converter object of the invention;

- Figure 3A shows an arm of a converter object of the invention of two stages in an operation as an inverter and Figure 3B shows an arm of a converter object of the invention of two stages in an operation as a rectifier;

- Figures 4.1 to 4.13 illustrate chronograms of the Vref setpoint signal (Fig. 4.1), of the carriers used with the setpoint voltage Vref for the control of the elementary switches of the 4 voltage level switching structure of the Figure 2: K1, K1 '(Fig. 4.2), K2, K2' (Fig. 4.3), K3u, K3'u, K3l, K3'l (Fig. 4.4), control signals of the elementary switches of the 4 voltage level switching structure of Figure 2: K1 (Fig. 4.5), K1 '(Fig. 4.6), K2 (Fig. 4.7), K2' (Fig. 4.8), K3u (Fig. 4.9), K3'u (Fig. 4.10), K3l (Fig. 4.11), K3'l (Fig. 4.12), of the output voltage Vs of the switching structure of 4 voltage levels (Fig. 4.13), in one operation DC / AC conversion;

- Figures 5.1 to 5.14 illustrate schedules of the Vref setpoint signal (Fig. 5.1), of the carriers used with the setpoint voltage Vref for the control of the elementary switches of the arm of the multilevel converter of Figure 3A: T1, T1 '(Fig. 5.2), T2, T2' (Fig. 5.3), T3u, T3'u, T3l, T3'l (Fig. 5.4), T4u, T4'u, T4l, T4'l (Fig. 5.5 ), T5u, T5'u, T5l, T5'l (Fig. 5.6), T6u, T6'u, T6l, T6'l, T7u, T7'u, T7l, T7'l (Fig. 5.7), some functions used to control the elementary switches of the arm of the multilevel converter of Figure 3A: F10 (Fig. 5.8), F20 (Fig. 5.9), F30 (Fig. 5.10), F40 (Fig. 5.11), F50 ( Fig. 5.12), F60 (Fig. 5.13), of the output voltage Vs of the multilevel converter arm of Fig. 3A (Fig. 5.14) in a DC / AC conversion operation;

- Figure 6 illustrates an example of a speed variator that associates two multilevel converters object of the invention, one working as a rectifier and the other as an inverter.

Detailed exposition of particular embodiments

Reference is made to Figure 1A which shows an electrical scheme of an arm B of a multilevel converter object of the invention, in a general structure. It allows working with voltages in the medium voltage field up to approximately 13.8 kV while the supported voltage of existing semiconductor switches is currently limited to 6.5 kV.

It will first be described in an example of a DC / AC converter arm.

The multilevel converter object of the invention, such as that illustrated in Figure 1B, includes one or more arms B similar to that shown in Figure 1A. They are intended to branch each of two same power supplies, including a VCC voltage source and a current source I. Two arms are used in a single phase converter. Three arms would be used in a three-phase converter.

The arm B of Figure 1A is intended to be connected between the VCC voltage source and the current source I. The converter can then function as a DC / AC converter (inverter) or as an AC / DC converter (rectifier). In the case of a DC / AC converter, the current source is alternating and can be for example an electric motor, for example, and the voltage source is continuous and can be for example a branched direct current bus at the output of a rectifier

In the case of an AC / DC converter, the current source is alternating and can be, for example, the power supply and the voltage source is continuous and can be, for example, a capacitor or a battery.

The arm B of the converter includes n stages Et1, Et2, _Eti, .... Etn connected together in cascade. n is an integer greater than or equal to two. The first stage Et1 or output stage, in the inverter application, is intended to be branched to the current source I. It is represented by a resistor R and an inductance L in series in Figure 3A.

The range stage n Etn or input stage, in the inverter application, is intended to be branched to the voltage source VCC.

In an AC / DC converter configuration, the first stage Et1 or input stage would branch to a current source and the range stage n Etn or input stage would branch to a voltage source. The input and output of the converter are reversed when it is switched from operation as an inverter to operation as a rectifier and vice versa.

The description that follows is based on Figure 1A and the operation as a DC / AC converter.

The range one stage Et1 includes a single switching structure of four voltage levels Ce10.

A stage of range i (i integer between 2 and n) Eti includes i structures Cei1, Cei2 ... Ceii switching four voltage levels, identical, connected in series. Each of the structures Cei1, Cei2 ... Ceii of switching of four voltage levels of the stage of rank i Eti is connected by means of an inductance Lauxi1, Lauxi2, ...., Lauxii to the stage of rank i -one. The stage of rank i-1 is not represented. Thus in Figure 1A, the stage of rank 2, Et2 includes two structures Ce21, Ce22 of switching of four voltage levels that are joined through two inductors Laux21, Laux22 to the stage of rank 1 Et1.

The range stage n Etn includes n structures Cen1, Cen2, .... Cen (n-1), Cenn switching of four voltage levels that are connected through n inductances Lauxn1, Lauxn2, .... Lauxn ( n-1), .... Lauxnn to the n-1 rank stage. The stage of rank i-1 is not represented. Each of these inductances is assimilable to a current source to respect the rules of connection between voltage source and current source. The inductances that connect two same stages are of the same value. On the contrary, some inductances that do not connect two same stages do not necessarily have the same values, but for reasons of simplification, they can be chosen of the same value. It is possible that the linkage of a switching structure of any stage of any range with the preceding stage is carried out directly without the presence of an inductance. It is sufficient that one or more inductances remain between this stage of any range and the stage that precedes it. The inductance (s) that remain will then have an increased value in relation to what they would have if all the inductances were present between the two stages. It is done so that the total value of the inductances that connect two successive stages is the same regardless of the number of inductances. It has been represented to illustrate this principle, in Figure 1A, the dotted Laux22 inductance, which means that it can be omitted.

It is observed that the voltage VCC applied to the stage of rank n Etn has been split into n equal voltages associated in series. These are the input voltages of the four voltage level switching structures of the n-stage stage. These voltages are referenced En1, En2, En (n-1), Enn.

Each Ce10 to Cenn four-level voltage switching structure includes, as will be seen below, with reference to the description of Figure 3A, a capacitive divider bridge that materializes a voltage source. These capacitive divider bridges are referenced Ca10, for the four-voltage switching structure Ce10.

As a variant, it is possible that the voltage source VCC is formed with n elementary branched voltage sources each in one of the n Cen1 structures, ... Cenn switching of four voltage levels of stage n Etn, in the terminals of each of the capacitive divider bridges. The voltages En1, En2, En (n-1), En are the voltages at the terminals of the capacitive divider bridges of the range n stage.

The outputs of the Cen1 to Cenn switching structures of four voltage levels are considered as floating voltage sources. They are connected through the inductances to the capacitive divider bridges of the four voltage level switching structures of the n-1 range stage. These four voltage level switching structures of the n-1 range stage are also considered as floating voltage sources. The inductances between the stage of rank n and the stage of rank n-1 are similar to current sources to respect a voltage source-current source alternation.

The components of the nth stage Etn are chosen so that the input voltage VCC is split into n equal input voltages applied to each of the n Cen1 to Cenn switching structures of four voltage levels. VCC / n is thus applied to each of the four voltage level switching structures of the nth stage Etn.

A conversion function f associated to each four voltage level switching structure can be defined, links the input voltage Ve applied to said four voltage level switching structure with the voltage Vs present at the output of said voltage structure. switching Vs = f * See being -1 <f <1. At each stage, the switching structures of four voltage levels are configured and controlled so that their associated conversion functions are equal. Thus, the voltages applied at the input of each of the four voltage level switching structures are equal to VCC / n. All four voltage level switching structures of the converter must withstand this voltage VCC / n. Respond to initial objective of reducing the voltage restrictions on the semiconductor switches for a given continuous voltage applied to the stage of rank n.

A four-voltage switching structure of the multilevel converter object of the invention will be described with reference to Figure 2. This four voltage level switching structure includes a three voltage level floating capacitor type cell 20, a first and a second base switching cell 21 and 22 and a capacitive divider bridge 23.

The floating capacitor type cell 20 includes a quartet of elementary switches mounted in series called K1, K2, K1 ', K2'. In this quartet, a first elementary switch K2 and a second elementary switch K2 'are in the extreme position and a first elementary switch K1 and a second elementary switch K1' are in the middle position, the two elementary switches K1, K1 'in the middle position are directly connected to each other in a middle node M. In the quartet, an elementary switch in the extreme position is connected directly to an elementary switch in medium possession. This link allows defining a first midpoint M1 between the first elementary switch K2 in the extreme position and the first elementary switch K1 in the middle position and a second midpoint M1 'between the second elementary switch K2' in the extreme position and the second switch K1 ' elementary in medium position. The ends of the switch quartet K1, K2, K1 ', K2' in series are called M2 and M2 ', the end M2 being on the side of the elementary switch K2 and the end M2' being on the side of the switch K2 'elementary.

It is connected to an energy storage device C between the first midpoint M1 and the second midpoint M1 '.

Two switching functions are defined in the floating condenser type cell 20. The first switching function F1 is used for the control of a first pair of switches comprising the first elementary switch K1 in medium position and the second elementary switch K1 'in medium possession. The second switching function F2 is used for the control of a second pair of switches comprising the first elementary switch K2 in the extreme position and the second elementary switch K2 'in the extreme position. The two elementary switches of the same pair are always in complementary states, conductive or blocked, except for the value of the dead time. This dead time will be explained later in relation to figures 5.

The elementary switches K1, K2, K1 ', K2' of the floating capacitor type cell 20 are semiconductor switches and each include a controllable power switch Tr1, Tr2, Tr1 ', Tr2', such as a transistor IGBT (Insulated Gate Bipolar Transistor) power for example associated with a diode D1, D2, D1 ', D2' connected in anti-parallel. Instead of the IGBT transistors, other power electronic switches such as some MOSFET transistors or others can be designed.

The switching function F1 is valid 1 when the elementary switch K1 is conductive and the elementary switch K1 'is locked and is worth 0 when the elementary switch K1 is locked and the elementary switch K1' is conductive.

The switching function F2 is worth 1 when the elementary switch K2 is conductive and the elementary switch K2 'is locked and is worth 0 when the elementary switch K2 is locked and the elementary switch K2' is conductive.

Each of the base switching cells 21, 22 includes a pair of elementary switches mounted in series. K3u, K3'u for the first base switching cell 21 and K3l, K3'l for the second base switching cell 22 are referenced. In a pair, the two switches have a midpoint. For the base switching cell 21, the midpoint is connected at the M2 end of the quartet of the floating condenser type cell 20. For the base switching cell 22, the midpoint is connected at the M2 'end of the quartet of the floating condenser type cell 20.

Each base switching cell 21, 22 also includes a first and second end terminals. The first end terminal is called M3, the second end terminal is called M4 for the first base switching cell 21. The first end terminal is called M3 ', the second end terminal is called M4' for the second base switching cell 22. The first two terminals M3 and M3 'ends form the two input terminals of the four voltage level switching structure, while terminal M forms the output terminal in a DC / AC conversion operation.

The elementary switches K3u, K3'u, K3l, K3'l of the two base switching cells 21, 22 are also semiconductor switches and each include an electronic controllable power switch, such as an IGBT power transistor ( Insulated Gate Bipolar Transistor), for example, associated with a diode connected in anti-parallel. These diodes and power transistors have not been referenced so as not to overload the figure. Instead of IGBT transistors, other power electronic switches such as some MOSFET transistors or others can also be designed.

A third switching function F3 is defined to control the elementary switches of the base switching cells 21 and 22. The elementary switch K3u and the elementary switch K3l are controlled identically.

The two elementary switches K3u, K3'u elementary of the base switching cell 21 are always in opposite states. It is the same for switches K3l, K3'l of the base switching cell 22.

The switching function F3 is worth 1 when the elementary switches K3u, K3l are conductive and the elementary switches K3'u, K3'l are locked and is worth 0 when the elementary switches K3u, K3l are locked and the switches K3'u, K3 ' The elementals are conductive.

The bridge 23 capacitive divider includes a triplet of C100, C200 and C300 power storage devices connected in series. The first energy storage device C100 is mounted on the terminals of the first base switching cell 21, between the terminals M3, M4 ends. The third energy storage device C300 is mounted on the terminals of the second base switching cell 22, between its first and its second terminals M3 ', M4' ends. The second energy storage device C200 is mounted between the first base switching cell 21 and the second base switching cell 22, between the second end terminals of these base switching cells. The capacitive divider bridge 23 has two terminals M3 and M3 'ends that are common respectively to the first base switching cell 21 and the second base switching cell 22.

The energy storage devices of this four voltage level switching structure are chosen from a capacitor, a battery, a fuel cell. The storage devices of the capacitive divider bridge 23 have the same storage capacity and the same supported voltage.

According to the states of the elementary switches of the switching structure of Figure 2, the switching structure of four voltage levels can take eight different states that lead to four different voltage levels: 0, Ve / 3, 2Ve / 3, Go.

The following table regroups these eight states numbered 1 through 8. The switching function f mentioned above depends on the switching functions F1, F2 and F3.

With the foregoing, the input voltage Ve that is applied to the terminals of the capacitive divider bridge 23 is subdivided into three equal voltages E1, E2, E3 that are applied respectively to the terminals of one of the devices C100, C200, C300 energy storage. The output voltage Vs is expressed by:

Vs = (F1 F2 F3) Ve / 3

The voltage Vs is taken between node M and node M'3.

Figure 4.1 shows the aspect of the setpoint signal, also called the setpoint voltage Vref, which will mainly be used to determine the switching instants of all the elementary switches of the four voltage level switching structure illustrated in Figure 2. This setpoint voltage Vref will be used in several comparisons, as will be seen later. It is sinusoidal and the output voltage Vs illustrated in Figure 4.13 is in phase with this setpoint voltage Vref.

A schedule of the carrier Car1 used with the setpoint voltage Vref to perform the switching function F1 and determine the switching moments of the elementary switches K1, K1 'of the floating condenser type cell 20 is shown in Figure 4.2. . It is a triangular carrier whose amplitude is between -1 and 1.

A chronogram of the Car2 carrier used with the setpoint voltage Vref to perform the switching function F2 and determine the switching moments of the elementary switches K2, K2 'of the floating capacitor type cell 20 is shown in Figure 4.3. . It is a triangular carrier whose amplitude is between -1 and 1. The two carriers Car1 and Car2 are out of phase in a half-period of cutting. The cutting frequency is much higher than the frequency of the output voltage Vs illustrated in figure 2. A schedule of the carrier Car3 used with the set voltage Vref has been shown in figure 4.4 to perform the switching function F3 and determine the switching moments of the elementary switches K3u, K3'u, K3l, K3'l of the base switching cells 21, 22. It is a constant signal of amplitude 0.6.

The switching instants of the elementary switches are obtained by comparison between the triangular and constant carriers and the setpoint Vref signal. It is possible to define as a rule, for example, an elementary switch switching instant appears after the setpoint signal is strictly higher than the carrier. It could of course have been established as a rule that a switching instant of the elementary switch appears from the setpoint signal is greater than or equal to the carrier.

Figure 4.5 is a chronogram of the control signal of the elementary switch K1 of the floating capacitor type cell 20. It is a battlement signal whose period is equal to that of the setpoint Vref signal. The elementary switch K1 is conductive as long as the setpoint voltage Vref is greater than the carrier Car1.

Figure 4.6 is a chronogram of the control signal of the elementary switch K1 'of the floating capacitor type cell 20. It is a beacon signal in phase opposition in relation to the control signal of the elementary switch K1 except for the dead time value.

Figure 4.7 is a chronogram of the control signal of the elementary switch K2 of the floating capacitor type cell 20. It is a battlement signal whose period is equal to that of the setpoint Vref signal. The elementary switch K2 is conductive as long as the setpoint voltage Vref is higher than the carrier Car2.

Figure 4.8 is a chronogram of the control signal of the elementary switch K2 'of the floating capacitor type cell 20. It is a beacon signal in phase opposition in relation to the control signal of the elementary switch K2 except for the dead time value.

Figure 4.9 is a chronogram of the control signal of the elementary switch K3u of the base switching cell 21. It is a signal in the battlement whose period is equal to that of the setpoint Vref signal. The elementary switch K3u is conductive as long as the setpoint voltage Vref is greater than the Car3 carrier. It is not a conductor more than one time per period of the setpoint Vref signal.

Figure 4.10 is a chronogram of the control signal of the elementary switch K3'u of the base switching cell 21. It is a beacon signal in phase opposition in relation to the control signal of the elementary switch K3u except for the dead time value.

Figure 4.11 is a chronogram of the control signal of the elementary switch K3l of the base switching cell 22. It is a signal in the battlement whose period is equal to that of the setpoint Vref signal. The elementary switch K3l is conductive as long as the setpoint voltage Vref is greater than the Car3 carrier. It is not a conductor more than one time per period of the setpoint Vref signal.

Figure 4.12 is a chronogram of the control signal of the elementary switch K3'l of the base switching cell 22. It is a beacon signal in phase opposition in relation to the control signal of the elementary switch K3l except for the dead time value.

A timetable of the output voltage Vs of the four voltage level switching structure of Figure 2 is shown in Figure 4.13 in which the four voltage levels are clearly visible: 0 V, 2000 V, 4000 V, 6000 V.

The attention is now directed to an example of the arm B of the converter object of the invention that does not include more than two stages Et1, Et2 and therefore three structures Ce10, Ce21, Ce22 of switching of four voltage levels as described in the figure two.

This arm will be succinctly described with reference to Figure 3A. This arm is configured to perform a DC / AC conversion. In the description that follows, to simplify, energy storage devices have been called capacitors. This is not limiting. The only four voltage level switching structure Ce10 of the range one stage Et1 includes a floating capacitor type cell formed by extreme elementary switches T2, T2 ', middle elementary switches T1, T1' and by capacitor C12 , a first basic switching cell with the elementary switches T3u and T3'u, a second basic switching cell with the elementary switches T3l and T3'l, a capacitive dividing bridge with the capacitors C9, C10, C11. The capacitor C9 and the capacitor C10 have a common node N7, the capacitor C10 and the capacitor C11 have a common node N8.

The first four voltage level switching structure Ce21 of the second stage Et2 connected through the Laux21 inductance to the first base switching cell of the first stage Et1 at the level of node N6 includes a floating capacitor type cell formed by switches T5u, T5'u elementary ends, switches T4u, T4'u elementary means and capacitor C7, a first base switching cell with switches T6u and T6'u elementary, a second base switching cell with the elementary switches T7u and T7'u, a capacitive divider bridge with capacitors C1, C2, C3. The capacitor C1 and the capacitor C2 have a common node N1, the capacitor C2 and the capacitor C3 have a common node N2.

The second four voltage level switching structure Ce22 of the second stage Et2 connected through the Laux22 inductance at the level of node N9 to the second base switching cell of the first stage Et1 includes a floating capacitor type cell formed by switches T5l, T5'l elementary ends, switches T4l, T4'l middle elemental and capacitor C8, a first basic switching cell with switches T7l and T7'l elementary, a second basic switching cell with the elementary switches T6l and T6'l, a capacitive divider bridge with capacitors C4, C5, C6. The capacitor C3 and the capacitor C4 have a common node N3, the capacitor C3 and the capacitor C6 have a common node N5.

The two bridges C1-C3, C4-C6 capacitive dividers of the second stage Et2 are connected in series.

The voltage source VCC is intended to be branched between the end terminals of the two capacitive divider bridges. Thus, the E + terminal corresponds to a capacitor terminal C1 not connected to another capacitor and the E- terminal corresponds to a capacitor terminal C6 not connected to another capacitor.

In the following, for reasons of simplification, the reference VCC will represent both the voltage source and the voltage at the edges of this voltage source.

The voltage VCC has been split into two groups of three equal voltages E1-E3 and E4-E6, the voltage E1 being applied to the terminals of the capacitor C1, the voltage E2 being applied to the terminals of the capacitor C2, the voltage E3 being applied to the terminals of the capacitor C3, the voltage E4 being applied to the terminals of the capacitor C4, the voltage E5 being applied to the terminals of the capacitor C5, the voltage E6 being applied to the terminals of the capacitor C6. The voltage at the terminals of capacitor C7 is called E7. The voltage at the terminals of capacitor C8 is called E8. The voltage at the terminals of capacitor C12 is called E12.

A floating voltage Ef is available between terminals N6, N9 of the Laux21, Laux22 inductances, on the side of the four voltage level switching structure of the first stage Et1. This floating voltage Ef is used as the input voltage of the first stage Et1, it is subdivided into three equal floating voltages E9, E10, E11 that are applied respectively to the terminals of capacitors C9, C10, C11.

The conversion function that links the input voltage Ef and the output voltage Es of the four-voltage switching structure Ce10 of the first stage Et1 is called fc1. The input voltage Ef of the switching structure Ce10 corresponds to E9 + E10 + E11. The output voltage of the switching structure Ce10 is taken between node N9 and node S.

The conversion function that links the input voltage VCC / 2 and the output voltage Vn ³ N ⁶ of the first four-level switching structure Ce21 of the second stage Et2 is called fc2. The input VCC / 2 voltage of the Ce21 four-voltage switching structure corresponds to E1 + E2 + E3. The output voltage V ⁿ⁶ N ³ of the switching structure Ce21 is taken between node N3 and node N6.

The conversion function that links the input voltage VCC / 2 and the output voltage V ^e - ⁿ⁹ of the second four-level switching structure Ce22 of the second stage Et2 is called fc3. The input voltage VCC / 2 of the four-voltage switching structure Ce22 corresponds to E4 + E5 + E6. The output voltage Vn ⁹ e- of the conversion structure Ce22 is taken between node E- and node N9.

Choosing the components of the two voltage structures Ce21 and Ce22 of four voltage levels of the second stage Et2 so that the voltages applied to the terminals of the two capacitive divider bridges are equal to VCC / 2 and choosing functions fc2 and equal conversion fc3, the voltages applied at the input of each of the three Ce10, Ce21, Ce22 switching structures of four voltage levels are equal to VCC / 2. There is a balanced distribution of the tensions between each switching structure of four voltage levels. These four voltage level switching structures do not then have to support more than half of the input voltage, which corresponds to the target set.

On the arm illustrated in Figure 3A, the controls of the elementary switches T3u and T3l are identical, the controls of the elementary switches T4u and T4l are identical, the controls of the elementary switches T5u and T5l are identical, the controls of the switches T6u and T6l elementary are identical, the controls of the T7u and T7l elementary switches are identical. In addition, as stated above during the description of Figure 2, the commands of the elementary switches T6u and T7u are identical and the controls of the elementary switches T6l and T7l are identical.

With its three switching structures of four voltage levels, such an arm B has six functions F10, F20, F30, F40, F50, F60 switching.

The switching function F10 is used for the control of the pair of elementary switches T1, T1 'in the medium position of the floating capacitor type cell of the four voltage level switching structure of the first stage Et1.

The switching function F20 is used for the control of the pair of elementary switches T2, T2 'in the extreme position of the floating capacitor type cell of the four voltage level switching structure of the first stage Et1.

The switching function F30 is used for the control of the elementary switches T3u, T3'u, T3l, T3'l of the base switching cells of the four voltage level switching structure of the first stage Et1.

The switching function F40 is used for the control of the pairs of switches T4u, T4'u, T4l, T4'l in the middle position of the two floating capacitor type cells located in the switching structures of four voltage levels of the second stage Et2.

The switching function F50 is used for the control of the pairs of switches T5u, T5'u, T5l, T5'l in extreme position of the two floating capacitor type cells located in the four voltage level switching structures of the second stage Et2.

The F60 function is used for the control of the elementary switches T6u, T6'u, T7u, T7'u, T7l, T7'l, T6l, T6'l of the basic switching cells of the four-level switching structures voltage of the second stage Et2. Reference can be made to the description of Figure 2 in regard to the values taken by these switching functions depending on the conductive or blocked state of the elementary switches. The converter of figure 3A allows to obtain 7 different voltage levels 0, VDC / 6, 2VDC / 6, 3VDC / 6, 4VDC / 6, 5VDC / 6, VCC between nodes S and E- and 64 states in the output function of the conductive or blocked state of its elementary switches.

The 64 different states have been regrouped in the following table as well as the 7 corresponding voltage levels Vs at the output of the first stage Et1. The voltage Vs is taken between node S and terminal E-. The output voltage, Vs, is expressed by:

Vs = [F10 F20 F30 F40 F50 F60] VCC / 2

continuation

Analyzing this table, it is observed that different states and therefore different configurations of the elementary switches lead to the same voltage Vs. This degree of freedom is interesting to maintain the balancing of the floating tensions. This degree of freedom will be used to maintain the balance of the capacitor voltages.

Figure 5.1 shows the aspect of the setpoint voltage Vref, which will mainly be used to determine the switching moments of all the elementary switches of the arm B illustrated in Figure 3A. Corresponds to that illustrated in Figure 4.1. It is in phase with the voltage Vs at the output of stage Et1 taken between node S and node E-, illustrated in Figure 5.14.

A schedule of the Car10 carrier used with the setpoint voltage Vref has been shown in Figure 5.2. to perform the switching function F10 and determine the switching moments of the switches T1, T1 'elementary of the Ce10 four-voltage switching structure of the first stage Et1. It is a triangular carrier whose amplitude is between -1 and 1.

A schedule of the Car20 carrier used with the setpoint voltage Vref to perform the switching function F20 and determine the switching instants of the elementary switches T2, T2 'in the extreme position of the type cell is shown in Figure 5.3. floating capacitor of the Ce10 switching structure of four voltage levels of the first stage Et1. It is a triangular carrier whose amplitude is between -1 and 1. The Car20 carrier is offset by 1 or 2fsw in relation to the Car10 carrier. The magnitude fsw represents the cutting frequency, it is much higher than the frequency of the output voltage Vs illustrated in Figure 5.14.

A schedule of the Car30 carrier used with the setpoint voltage Vref to perform the switching function F30 and determine the switching moments of the switches T3u, T3'u, T3l, T3'l of the elementary elements is shown in Figure 5.4. base switching cells of the Ce10 four-level voltage switching structure of the first stage Et1. The Car30 carrier is offset by n / 2 or 1 / fsw relative to the Car10 carrier.

A schedule of the Car40 carrier used with the setpoint voltage Vref to perform the switching function F40 and determine the switching instants of the elementary switches T4u, T4'u, T4l, T4'l in position is shown in Figure 5.5. median of the two floating capacitor type cells located in the Ce21, Ce22 switching structures of four voltage levels of the second stage Et2. It is a constant signal of amplitude -2/3.

A schedule of the Car50 carrier used with the setpoint voltage Vref to perform the switching function F50 and determine the switching moments of the elementary switches T5u, T5'u, T5l, T5'l in position is shown in Figure 5.6. end of the two floating capacitor type cells located in the Ce21, Ce22 switching structures of four voltage levels of the second stage Et2. It is a constant signal of zero amplitude.

A schedule of the Car60 carrier used with the setpoint voltage Vref to perform the switching function F60 and determine the switching moments of the switches T6u, T6'u, T7u, T7'u, T7l, is shown in Figure 5.7. T7'l, T6l, T6'l elementary base switching cells of structures Ce21, Ce22 switching four voltage levels. It is a constant signal of amplitude 2/3.

The switching instants of the elementary switches are obtained by comparison between the triangular and constant carriers and the setpoint Vref signal. It can be defined as a rule, for example, that a switching instant of an elementary switch occurs after the setpoint signal is strictly superior to the carrier. It could of course have been established as a rule that a switching instant of the elementary switch occurs after the setpoint signal is greater than or equal to the carrier.

Figure 5.8 is a chronogram of the switching function F10 used for the control of the pair of elementary switches T1, T1 'in a medium position of the floating capacitor type cell of the four stage voltage switching structure of the first stage. Et1. It is a battlement signal whose period is equal to that of the fsw frequency of chopping. The switching function F10 is at a level 1 while the set voltage Vref is higher than the Car10 carrier.

The controls of the two switches T1 and T1 'of the pair are obtained from the switching function F10. The control of the elementary switch T1 is similar to the switching function F10 with the difference that the rising front of the battlements is delayed in a dead time relative to the rising front of the battlements of the switching function F10. On the contrary, the falling front of the battlements for the control of the elementary switch T1 is synchronized with that of the battlements of the switching function F10. The control of the elementary switch T1 'is similar to the complementary function of function F10 with the difference that the rising front of the battlements is delayed in the dead time relative to the rising front of the battlements of the complementary function. On the contrary, the falling front of the battlements for the control of the elementary switch T1 'is synchronized with that of the battlements of the complementary function of the switching function F10. The two elementary switches T1, T1 'of the pair are in complementary states except for the value of the dead time.

Figure 5.9 is a schedule of the switching function F20 used for the control of the pair of elementary switches T2, T2 'of the four-voltage switching structure Ce10 of the first stage Et1. It is a battlement signal whose period is equal to that of the fsw frequency of chopping. The switching function F20 is at level 1 while the set voltage Vref is higher than the Car20 carrier. What has just been explained for the control of the elementary switches T1, T1 'and dead times is applied for the control of the pair of elementary switches T2, T2' on the basis of the flange signal of the switching function F20. The two elementary switches T2, T2 'of the pair are in complementary states except for the value of the dead time.

Figure 5.10 is a schedule of the switching function F30 used for the control of the switch pairs (T3u, T3'u) and (T3l, T3'l) of the basic switching cells of the switching structure Ce10 four voltage levels of the first stage Et1. It is a battlement signal whose period is equal to that of the fsw frequency of chopping. The switching function F30 is at a level 1 while the set voltage Vref is higher than the Car30 carrier. What has just been explained for the control of the elementary switches T1, T1 'and dead times is applied for the control of the pairs of switches (T3u, T3'u) and (T3l, T3'l) elementary on the base of the beacon signal of the switching function F30. The two elementary switches (T3u, T3'u) and (T3l, T3'l) of each pair are in complementary states except for the value of the dead time.

Figure 5.11 is a schedule of the switching function F40 used for the control of the pairs of switches (T4u, T4'u) and (T4l, T4'l) in the middle position of the two floating condenser type cells located in the structures Ce21, Ce22 switching four voltage levels of the second stage Et2. It is a battlement signal whose period is equal to that of the setpoint Vref signal. The switching function F40 is at a level 1 while the set voltage Vref is higher than the Car40 carrier. What has just been explained for the control of the elementary switches T1, T1 'and dead times is applied for the control of the pairs of switches (T4u, T4'u) and (T4l, T4'l) elementary on the base of the beacon signal of the switching function F40. The two elementary switches (T4u, T4'u) and (T4l, T4'l) of each pair are in complementary states except for the time-out value.

Figure 5.12 is a schedule of the switching function F50 used for the control of the pairs of switches (T5u, T5'u) and (T5l, T5'l) in the extreme position of the two floating capacitor type cells located in the structures Ce21, Ce22 switching four voltage levels of the second stage Et2. It is a battlement signal whose period is equal to that of the setpoint Vref signal. The switching function F50 is at level 1 while the set voltage Vref is higher than the Car50 carrier. What has just been explained for the control of the elementary switches T1, T1 'and dead times is applied for the control of the pairs of switches (T5u, T5'u) and (T5l, T5'l) elementary on the base of the beacon signal of the switching function F50. The two elementary switches (T5u, T5'u) and (T5l, T5'l) of each pair are in complementary states except for the value of the dead time.

Figure 5.13 is a schedule of the switching function F60 used to control the switch pairs (T6u, T6'u), (T7u, T7'u) and (T6l, T6'l), (T7l, T7 ' l) elementary of the base switching cells of the Ce21, Ce22 switching structures of four voltage levels of the second stage Et2. It is a battlement signal whose period is equal to that of the setpoint Vref signal. The switching function F60 is at a level 1 while the set voltage Vref is higher than the Car60 carrier. What has just been explained for the control of the switches T1, T1 'elementary and dead times is applied for the control of the pairs of switches (T6u, T6'u), (T7u, T7'u) and (T6l, T6'l), (T7l, T7'l) elementary based on the battlement signal of the switching function F60. The two switches (T6u, T6'u), (T7u, T7'u) and (T6l, T6'l), (T7l, T7'l) of each pair are in complementary states except for the dead time value .

A schedule of the output voltage Vs of the converter arm illustrated in Figure 3A is shown in Figure 5.14 in which seven voltage levels are clearly visible: 0 V, 1000 V, 2000 V, 3000 V, 4000 V, 5000 V, 6000 V. The voltage varies in steps, from 1000 V in the example described.

The converter arm of Figure 3B will not be described in more detail. It has the same structure as that of Figure 3A with the exception that the node S that would correspond to the output in Figure 3A is now called node E since it now corresponds to the input. It is intended to be connected to an alternating current source (not shown). Likewise, the input terminals E +, E- in figure 3A, at which level the voltage source VCC is to be connected are now called S + and S- in figure 3B, correspond to the output of the converter and are intended to supply a DC voltage source (not shown). In operation as a rectifier, an IE current flows from node E to the output terminals S + and S- while in operation as an inverter, IE + and IE- currents would circulate from terminals E +, E- to node S. In operation as a rectifier IS + and IS- currents would appear on terminals S + and S-, they are output currents and in undulating operation the output current called Is would appear on node S.

Various types of controls can be used to make conductors or block elementary switches and thus ensure conversion. A traditional control based on PWM pulse width modulation can be used. Of course, homologous elementary switches of the two Ce21, Ce22 switching structures of four voltage levels of the second stage Et2 are controlled in the same manner.

In Figures 3A, 3B, a single source of continuous VCC voltage is shown. It is understood that this continuous VCC voltage source could consist of several independent elementary continuous voltage sources, each mounted on the terminals of at least one C1 to C6 energy storage device. These DC sources could be rectifiers. This configuration is interesting in a non-reversible conversion system with a multi-winding transformer.

With reference to figure 6, a speed variator is shown which cascades a converter 1 object of the invention operating as an AC / DC rectifier and a converter 2 object of the invention operating as a DC / AC inverter by placing between the two, on the continuous side, a voltage source 3 such as an energy storage device. The rectifier 1 is intended to be connected at the input to an alternating power network Re assimilable to a current source. The inverter 2 is intended to be connected at the output to a user device assimilable to a current source such as an alternating current motor Mo. Figure 6 illustrates an example in which the two converters 1 and 2 are three-phase. Each would include three arms such as those depicted in Figures 3A, 3B.

The multilevel converter object of the invention is much more compact and lighter than the prior art converters with transformer. It is much easier to install and transport. Can be used with or without isolation transformer.

It allows to minimize the harmonic contamination of the power grid and the correction of the power factor when using an active regenerative rectifier. The converter object of the invention is compatible with the alternating network up to 13.8 kV given the voltage supported by the existing semiconductor components today, either operating as an inverter or as a rectifier. Due to this, it is not mandatory to use a voltage level adaptation transformer, a solution that is classically used.

The DC / AC converter object of the invention can be used to power asynchronous or synchronous motor parks, whether new or existing.

The converter object of the invention has a modular structure thanks to the use of the four voltage level switching structures such as those in Figure 2. From which it turns out that the maintenance costs are reduced and the reliability is good.

The load waveform of the load is of good quality and the surges on the side of the current source are limited and are linked only to the cables of the links.

The common DC bus can be used to power several converters object of the invention.

Documents cited

[1] “A novel hybrid-clamped four-level converters,” Kui Wang et al, Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE, 5-9 Feb. 2012, pages 2442-2447.

[2] “Voltage balancing control of a four-level hybrid-clamped inverter using modified phase-shifted PWM” Kui Wang et al, Power Electronics and Applications (EPE), 2013 15th European Conference on Power Electronics and Applications, 2-6 sept . 2013, pages 1-10.

Claims (10)

1. Multilevel converter that includes at least one arm (B) formed by several stages (Et1, Et2, ...., Etn) of range one an (n integer greater than one) mounted in cascade, the stage (Et1) being destined ) of rank 1 to be connected to a current source (I) and the stage (Etn) of rank na being destined to be connected to a voltage source (VCC), characterized in that the stage (Et1) of rank one includes a single structure ( Ce10) switching of four voltage levels and a stage of range i (i between two and n) includes i structures (Cei1, Cei2, ... Ceii) switching of four identical voltage levels mounted in series, including each of these switching structures a cell (T1, T2, T1 ', T2', C12) of three voltage level floating capacitor type comprising a quartet of switches (T1, T2, T1 ', T2') elementary in series which have a middle node (S), two base cells (T3u, T3'u; T3l, T3'l) each formed by a pair of interru ptores (T3u, T3'u; T3l, T3'l) in elementary series have two terminals (N6, N7; N8, N9) ends and a midpoint and a bridge (C9, C10, C11) capacitive divider that has two ends formed by a triplet of energy storage devices (C9, C10, C11) mounted in series between which the two energy storage devices (C9, C11) are in an extreme position, each energy storage device (C9, C11) being connected in an extreme position to the terminal (N6, N9) ends of a different base switching cell, connecting a midpoint of each base switching cell at a different end of the switch quartet (T1, T2, T1 ', T2'), the middle node of each floating capacitor type cell of the range stage ia being connected to one end of the capacitive divider bridge of a four voltage level switching structure of the range stage i-1. 2. Multilevel converter according to claim 1, wherein the devices (C9, C10, C11) of the same capacitive divider bridge have the same energy storage capacity and the same supported voltage. 3. Multilevel converter according to one of claims 1 or 2, wherein the middle node of at least one floating capacitor type cell of the range stage i is connected to one end of the capacitive divider bridge of the range stage i -1 through an inductance (Laux21, Laux22). 4. Multilevel converter according to claim 3, wherein when several inductances connect the stage of rank i to the stage of range i-1, these inductances have the same value. 5. Multilevel converter according to one of claims 1 to 4, wherein the two pairs of switches (T3u, T3'u; T3l, T3'l) of the two basic switching cells of the same stage have the same switching function 6. Multilevel converter according to one of claims 1 to 5, wherein in operation, the elementary switches of the same pair are in complementary states except for a time-out value. 7. Multilevel converter according to one of claims 1 to 6, wherein in the quartet of switches (T1, T2, T1 ', T2') elementary of a floating capacitor type cell two are in extreme position and two are in medium position, the two elementary switches (T2, T2 ') in the extreme position are always in complementary states and the two elementary switches (T1, T1') in the middle position are always in complementary states, being one conductor and the other being locked. 8. Multilevel converter according to one of claims 1 to 7, wherein the elementary switches (T1, T2, T1 ', T2') each include a controllable power electronic switch with a diode connected in anti-parallel. 9. Multilevel converter according to one of claims 1 to 8, wherein the energy storage devices (C1-C12) are chosen from a capacitor, a battery, a fuel cell. 10. Speed variator that includes a cascade with a converter (1) according to one of the preceding claims operating as an AC / DC rectifier and a converter (2) according to one of the preceding claims operating as a DC / AC inverter, connected to each other by its sides continue through a voltage source (3).