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The present invention relates to a transmission and reception apparatus for digital signals and method thereof.
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It is known in prior art the use of galvanically isolated interfaces between a transmitter and a receiver, in which the signals are wirelessly transmitted. The digital signal transmission must be of the high bitrate type for transmitting data between one chip and another, while ensuring galvanic isolation. Typical bitrate values are 50-100Mbit/s, while the required isolation is in the range of 2-5kV.
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Various apparatuses for providing the galvanic isolation currently exist.
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One of these consists in using an integrated transformer. The latter is made by means of a pile structure in which the secondary winding generally consists of the metal layer arranged at the bottom level, the primary winding of the metal layer arranged at the upper level and the isolation between the two windings consists of various dielectric layers arranged between the two metal layers, the thickness of which depends on the desired level of isolation. Alternatively, the secondary winding may be made of the metal layer arranged on the upper level, the dielectric layer is inserted thereon and finally the primary winding is made of an additional metal layer. The isolation transformer is formed on the receiver die. The driver die contains the transmitter which, through the bonding, is connected to the primary of the isolation transformer. The secondary of the transformer is connected to the receiver which processes the transmitted signal. The data flow may also occur from the secondary to the primary, if a two-way channel is desired. The signals must be appropriately processed by means of a modulation technique in order to transfer information through the isolated interface. This type of component allows to obtain a high bitrate, good reliability and isolation capacity. However, this configuration requires the addition of processing steps for obtaining the transformer (e.g. for increasing the thickness of the isolating layer in order to achieve the required degree of isolation), as well as the use of bonding wires for connecting the transmitter of the driver die to the transformer itself.
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Another galvanic isolation apparatus, described in patent
US 2008/0311862 , comprises a structure which is based on a transmission of wireless type. The two chips are reciprocally assembled and the isolation is obtained by means of an interposed insulating layer. The electromagnetic coupling is made by means of a pair of coils, in particular by means of the magnetic field produced by the current which flows over the transmission coil. The thickness of the upper chip (e.g. the transmitter chip) is reduced by lapping in order to maximize the coupling between the two coils. The signals must be appropriately processed by means of a modulation technique in order to transfer information through the isolated interface. This configuration has the advantage of requiring neither additional processing steps nor bonding wires between the two chips. However, it has the disadvantage of a low coupling coefficient and high variability thereof which depends on the thickness tolerance after lapping the die, the thickness tolerance of the insulating layer and the alignment tolerance between the two chips.
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A further galvanic isolation apparatus, again described in patent
US 2008/0311862 , comprises a structure which is based on a transmission of wireless type. In this case, the two chips are assembled side-by-side and the isolation is obtained by means of an insulating layer placed below the two chips. The electromagnetic coupling is made by means of a pair of coils, in particular by means of the magnetic field produced by the current which flows over the transmission coil. The signals must be appropriately processed by means of a modulation technique in order to transfer information through the isolated interface. This configuration also has the advantage of requiring neither additional processing steps nor bonding wires between the two chips. However, it has the advantage of a highly variable, lower coupling coefficient as compared to the previous structure, according to the alignment tolerance between the two chips and the distance tolerance between the two chips.
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Regardless of the structure used for making the coupled inductors, today there exist two main approaches for transmitting a signal through the channel.
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A first technique is of the narrowband type, in which the signal is transmitted on a carrier. Thereby, a high signal/noise ratio, or SNR, may be obtained to the detriment of a high circuit complexity due to the use of radio frequency circuits, such as an oscillator, a low-noise amplifier, a mixer, a filter, etc.
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A second technique is of the wideband type, in which wideband pulses (UWB Pulses) are transmitted. Thereby, the circuit complexity of the transceiver is reduced, but the signal/noise ratio is worse.
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A transmission technique which may be implemented with a relatively simple system is the on-off keying (OOK) technique, in which information is encoded in the form of transmitted signal absenee-presence. Figure 1 shows a block diagram of the system with a transmitter 100 on the die 101, a receiver 200 on the die 241, a wireless interface 300, an input signal Sin to the transmitter 100 and an output signal Sout from the receiver.
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If a narrowband approach is used, the input signal to the interface 300 enables an oscillator which generates the OOKW carrier. The signal is amplified and processed in the receiver in order to extract the envelope.
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If a wideband approach is used, a pulse TP is generated at each (positive and negative) wave-front of the input signal to the interface 300.
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The signal is amplified and processed in the receiver to extract the polarity thereof. Thereby, for example, a positive wave-front is decoded if the received pulse has positive polarity, otherwise a negative wave-front is decoded. Figures 2 and 3 show the main waveforms of the signals in a system of this type, with narrowband and wideband techniques, respectively.
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Such a system, i.e. a system based on the recognition of the signal presence-absence, which allows to obtain an isolated channel through which the transmission of a digital signal characterized by two levels (high and low) is possible, is referred to as "two-level isolated digital channel". The previously mentioned applications require isolated digital channels in which the synchronization signal (clock) may be transmitted in addition to the data signal itself. The simplest, but more expensive solution is to employ two channels: one for transmitting the clock and one for transmitting the data. In actual fact, there are more advantageous solutions, which use appropriate modulation techniques to transmit the clock and data on a single channel: ASK modulation, FSK modulation, etc. ASK modulation allows the simultaneous transmission of the clock and data in a relatively simple system, by implementing the narrowband approach. Figure 4 shows a block diagram of a system, which allows the transmission and reception of the clock and data on a single channel, e.g, based on ASK modulation.
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The Clock signal, at interface input, enables an oscillator which generates an ASKW carrier, the amplitude of which is modulated by the Data signal. For example, if the transmitted data is "zero", the peak-to-peak amplitude of the carrier is equal to Vdd/2 (where Vdd is the supply voltage of the transmitter); if the transmitted data is "one", the peak-to-peak amplitude of the carrier is equal to Vdd.
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The received signal is amplified and processed in order to extract the envelope. Such an envelope is compared, by means of a comparator, with two thresholds: a low threshold VthL and a high threshold VthH. If the amplitude of such a signal is comprised between the low threshold VthL and the high threshold VthH, the demodulated datum is "zero", while if the amplitude is higher than the high threshold VthH, the demodulated datum is "one". At the same time, the envelope must exceed one of the two thresholds to extract the clock. Figure 5 shows the main waveforms of a system which uses the ASK modulation technique, i.e. the input clock signal ClockIN to the transmitter, the input data signal DataIN to the transmitter, the carrier ASKW, the envelope ASKENV, the output clock signal ClockOUT from the receiver, and the output data signal DataOUT from the receiver.
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In order to ensure a good interference immunity, the amplifier gain and the threshold values VthL and VthH must be appropriately fixed. In particular, once the values of the thresholds VthL and VthH have been fixed, the gain is chosen so that the amplitude of the input signal to the comparator, when zero is received, is equal to (VthH+VthL)/2. The received signal amplitude depends on the transmitted signal amplitude and coupling coefficient of the coils. Therefore, in the case of the pile or planar structure, the amplitude of the received signal is highly variable because, as previously mentioned, the coupling coefficient depends on the assembly quality. Therefore, the circuitry of the receiver must be complicated, e.g. by inserting a variable gain amplifier (VGA) and a gain control loop to compensate for such a variability. Furthermore, before transmitting the data itself, the carrier with a known amplitude must be transmitted for a time interval so that the system may appropriately adjust the VGA gain. Unfortunately, such an increase of circuit complexity of the receiver thwarts the use of the ASK modulation technique, which is indeed chosen for its simplicity.
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Given the prior art, it is the object of the present invention to provide a transmission and reception apparatus for digital signals which is less complex than those known and which is not affected by the high variability of the coupling coefficient of the pair of coils of the galvanically isolated interface.
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In accordance with the present invention, such an object is achieved by means of a transmission and reception apparatus for at least one digital data signal, said digital data signal being characterized by two logical levels, first and second logical levels, with said second logical level higher than the first logical level, said apparatus comprising a transmitter, a receiver and a galvanically isolated wireless interface arranged between the transmitter and the receiver, said wireless interface comprising a transmitting antenna and a receiving antenna formed by a pair of coils, said transmitter, receiver and wireless interface being arranged so as to form a two-level isolated digital channel, said transmitter comprising first means adapted to send a synchronization signal to the receiver, said receiver comprising second means adapted to synchronize the receiver and the transmitter by means of the received synchronization signal, characterized in that said transmitter comprises further means adapted to sends said digital data signal to the receiver, after the synchronization of receiver and transmitter, and said second means of the receiver comprise at least one memory element configured to memorize, during the reception of said digital data signal, information relative to the received synchronization signal.
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The features and advantages of the present invention will be apparent from the following detailed description of a practical embodiment thereof, shown by way of non-limitative example in the accompanying drawings, in which:
- figure 1 is a diagrammatic view of a data transmission and reception system with a galvanically isolated wireless interface;
- figure 2 shows the involved signals in the apparatus in figure 1 with narrowband modulation;
- figure 3 shows the involved signals in the apparatus in figure 1 with broadband modulation;
- figure 4 is a diagrammatic view of the apparatus in figure 1 with signals transmitted and received according to ASK modulation;
- figure 5 shows the involved signals in the apparatus in figure 4 according to ASK modulation;
- figure 6 shows a transmission and reception apparatus for digital signals in accordance with the present invention;
- figure 7 shows the apparatus in figure 6 more in detail;
- figure 8 shows time diagrams of the signals of the transmitter die in the apparatus in figure 7;
- figure 9 shows time diagrams of the signals of the receiver die in the apparatus in figure 7;
- figure 10 shows the DLL of the apparatus in figure 7;
- figure 11 shows a sample and hold diagram used in the DLL in figure 10;
- figure 12 is a circuit implementation of the DLL in figure 10;
- figure 13 is a diagram of the PFD used in the DLL in figure 12;
- figure 14 shows time diagrams of the involved signals in the DLL in figure 12.
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Figure 6 shows a transmission and reception apparatus for digital signals in accordance with the present invention. The apparatus comprises a two-logical-level (high and low) digital signal transmission circuit comprising a transmitter 1 and a circuit block 6 having the synchronization signal CLOCK and the data signal DATA at the input and connected to the transmitter 1; both transmitter 1 and circuit block 6 are arranged on a die 2. The apparatus comprises a two-level (high and low) digital signal reception circuit comprising a receiver 3 and a block 7 having the CLOCK and DATA output signals and connected to the receiver 3; both receiver 3 and circuit block 7 are arranged on a die 4. Dice 2 and 4 may be assembled either side-by-side or one on top of the other in the same package. The apparatus further comprises a wireless interface 5 arranged between the transmitter 1 and the receiver 3, so as to form a two-level galvanically isolated digital channel therewith, preferably a single two-level isolated digital channel. The CLOCK and DATA signals are transmitted in subsequent time instants, i.e. there is a delay D for sending the DATA signal once the CLOCK signal has been sent; the maximum delay is preferably 2 microseconds. The CLOCK signal allows the synchronization of receiver 3 and transmitter 1, while the DATA signal comprises the information in digital format which must be transmitted by transmitter 1 to receiver 3. The wireless interface comprises a transmitting microantenna connected to the transmitter 1 and a receiving microantenna connected to the receiver 3; the microantennas are made of a pair of coils or coupled inductor. The transmitting circuit and the transmitting antenna are integrated in die 2, and the reception circuit and the receiving antenna are integrated in die 4, and dice 2 and 4 are encapsulated in a single package and separated from each other by insulating material.
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Figure 7 shows the apparatus in figure 6 more in detail.
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The circuit block 6 comprises a selector 61, preferably a multiplexer, having the input DATA signal, a timer 62, preferably a counter, having the input CLOCK signal and the output END_LOCK signal, and a logical block 63 having the input CLOCK signal and the output synchronization SYNC signal.
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The circuit block 7 comprises a synchronizer 71 with a memory element for memorizing information relative to the synchronization signal, preferably a Delay Locked Loop circuit, or DLL, 71 and a timer 72, preferably a counter, adapted to receive the output signal from the receiver 3. The High/Low signal is the output signal from the transmitter 1 and the output signal from the receiver 3.
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The transmission and reception apparatus for a digital signal through a galvanically isolated interface operates as follows.
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In a first step of locking, the SYNC signal, i.e. the synchronization signal which is derived from the CLOCK signal by means of the logical circuit 63, is transmitted from transmitter 1 to receiver 3, so that the DLL circuit 71 is locked, i.e. synchronized with the transmission circuit preferably in a prefixed time.
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During the second step, the DATA signal, preferably a determined length bit sequence, is transmitted and the receiver synchronization is kept by means of the memory element of the synchronizer 71, that is information relative to the synchronization is stored in the memory element of the DLL 71 during the reception of the data signal DATA. At the beginning of transmission, during the step of locking, the END_LOCK signal is at the low logical level and through the circuit 61 the SYNC signal, which depends on the CLOCK signal, drives the transmitter 1 of the two-level isolated digital channel. In die 4, the SYNC signal received from receiver 3 is demodulated and supplied to the DLL circuit 71 so that said circuit is synchronized. After a few clock cycles have elapsed, i.e. after a delay D has elapsed, which preferably is determined by the timer and which depends on both the maximum latency of the transmission circuit and the DLL circuit or depends on the acquisition speed of the signal SYNC depending on the circuit structure of the receiver, on the clock frequency and on the bit rate, the DLL circuit 71 is locked to the transmitter. Thus, the step of sending the data by sending the DATA signal is started. The count of the clock cycles needed for locking is carried out by the counters 62 and 72. The delay D is chosen according to the maximum latency required for transmitting a bit frame, i.e. according to the combination of synchronization and data transmission, tolerated by the application in which interface 5 is inserted; once such a latency is known, the DLL 71 is designed so as to have an adequate locking time.
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Passing from the step of locking to that of data sending is by means of the output END_LOCK signal of the counters 62 and 72, which reaches the high logical level. In die 2, such a signal allows to switch the circuit 61 on the DATA signal for driving the transmitter 1. In die 4, the END_LOCK signal communicates to the downstream circuits that DATA signal reception will start when the logical level is reached. Counter 72 simultaneously sends the HOLD signal to the high logical level to make the DLL circuit work in hold mode, i.e. the feedback loop is opened so as to be indifferent to the input signal, which is now the DATA signal and no longer the SYNC signal from die 2, but still keeps the output CLOCK synchronization signal to which it had locked during the preceding step, that is it memorizes information relative to the signal CLOCK.
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Figure 8 shows the time diagrams of the waveforms of the signals related to die 2. The High/Low signal during the step of locking is equal to the SYNC signal. In particular, such a signal has a frequency which is half that of the CLOCK signal. During the step of sending the data, instead, when the END_LOCK signal is at the high logical level, the High/Low signal is equal to the DATA signal of the transmitter.
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Figure 9 shows the time diagrams of the waveforms of the signals related to die 4. The High/Low signal in the step of locking is equal to the SYNC signal of the transmitter; the DLL circuit 71 is locked to the phase of this signal and synthesizes a frequency equal to double thereof. After the time interval needed for the DLL circuit to be locked, the END_LOCK and HOLD signals reach the high logical level and the method goes to the next step of transmitting the data. During this step, the High/Low signal (or DATA signal) of the receiver 3 is equal to the DATA signal of die 2, while the synchronization is kept by the DLL circuit 71 and is represented by the CLOCK signal. In this case, the information existing in the DATA signal may be derived by sampling the High/Low signal at each negative wave-front of the CLOCK signal.
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Figure 10 shows the block diagram of the DLL circuit 71. The latter comprises a phase-frequency detector (PFD) 701, which may be either analog or digital and supplies a signal proportional to the difference between the input frequency and the frequency indicated by the feedback signal FB; the PFD 701 has an input terminal IN on which the received High/Low signal insists and has the feedback signal FB at the input. The DLL 71 comprises a loop filter 702, which attenuates the higher order harmonics produced by the PFD 701 and stabilizes the loop. The DLL 71 comprises a voltage-controlled oscillator (VCO) 704 which outputs a signal, the oscillation of which is frequency-controlled by the input voltage from the PFD 701 through the loop filter 702. The DLL 71 comprises a frequency divider 705, which supplies a signal FB, the frequency of which is divided by a factor N with respect to the frequency of the output signal from the VCO 704, and exists on the output terminal OUT of the PFD. The value of N depends on what is being transmitted during the step of locking, thus on the SYNC signal. If the CLOCK signal is directly transmitted, then N=1, otherwise, as in the case of figures 8 and 9, if a signal the frequency of which is equal to half the CLOCK signal is transmitted, then N=2.
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The DLL circuit 71 comprises a hold circuit 703 having the input terminal IN3 connected to the output of filter 702, and the output terminal OUT3 connected to the input terminal of VCO 704; the hold circuit 703 allows to interrupt the feedback loop, to sample the output voltage of the filter at the instant of time in which the hold mode is enabled and to hold such a value at the input of VCO 704 so that it is able to supply a signal synchronized with the CLOCK signal of die 2, by virtue of the preceding step of locking. The hold circuit 705 may be implemented by means of a Sample and Hold consisting of a switch S and a capacitor C, as shown in figure 11. When the Hold signal is at the low logical level, the switch is closed and the feedback loop is formed; thereby, the DLL circuit 71 is locked to the phase of the input signal. When the Hold signal reaches the high logical level, the switch S opens and the feedback loop is interrupted. The capacitor keeps the output voltage value of the filter 702, which was present when the loop was interrupted. Thereby, if the locking transient is extinct, the VCO 704 supplies a signal which is phased with the CLOCK signal of die 2.
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Figure 12 shows a preferably circuit implementation of the DLL in figure 10. The DLL comprises PFD 701, VCO 704, divider 705 and loop filter 702 consisting of a resistor R1 having one terminal connected to the output terminal of the PFD 701 and the other terminal connected to the input terminal of the VCO 704, and a series of a resistor R2 and a capacitor C connected to ground GND. The DLL 71 comprises a logical block 706 and a switch S used for pre-charging the loop filter 702; the Hold, Sync signals and a PreCh signal are inputted to the logical block 706, which signals are initially at low logical level. When the transmission is enabled, the PreCh signal is set to a high logical level for pre-charging the filter 702 at a voltage preferably of 2 Volts by closing the switch S for a period Ts of preferably about 500 nanoseconds; in such a way the lock time is reduced. Once the step of pre-charging the filter has been ended, the switch S is opened and the Sync signal is led to the high logical level for the DLL to lock to the phase or frequency of the signal at input IN and synthesize a frequency equal to the double thereof. After the time interval needed for the DLL circuit to lock, the Hold signal is led to the high logical level and the method goes to the next step of transmitting the data. The Hold signal at the high logical level keeps the PFD 701 in a tri-state, i.e. locked to the frequency of the Sync signal also during the step of transmitting the data; the logical block 706 sends an EN signal, which is the reverse of the Hold signal, to the PFD 701 to keep it in the tri-state.
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As shown in greater detail in figure 13, PFD 701 comprises two flip-flops of D or FF- D type 711 and 712 having outputs UPn and DOWNn. The signal on the IN terminal and the EN signal are inputted to an AND gate 713, the output of which is the input to the flip-flop 711, while the FB signal and the EN signal are inputted to an AND gate 714, the output of which is the input to the flip-flop 712. Assuming the two UPn and DOWNn outputs initially at high logical level, a signal up-edge on the IN terminal, with the EN signal at the high logical level, implies that the UPn signal reaches the low logical level; this indicates that the frequency of VCO 704 must be increased to be equal to the frequency of the signal at the input terminal. On the other hand, an up-edge of the FB signal, with the EN signal at the high logical level, implies that the DOWNn signal reaches the low logical level; this indicates that the frequency of VCO 704 must be decreased to be equal to the frequency of the signal at the input terminal. When the UPn and DOWNn outputs are at the low logical level, a NOR gate sends a reset signal to the D-type flip- flops 711 and 712 to take the PFD back to the initial state.
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The PFD 701 comprises two transistors Mp and Mn having the drain terminal in common and with the source terminal of the transistor Mp connected to the supply voltage Vdd, and the source terminal of the transistor Mn connected to ground GND. The Mp transistor is driven by the UPn signal, while the Mn transistor is driven by the reverse of the DOWNn signal when the EN signal is at the high logical level.
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When the EN signal is at the low logical level, i.e. the Hold signal is at the high logical level, the PMOS transistor Mp has the supply voltage Vdd on the gate terminal and is thus off, while the NMOS transistor Mn has the reverse of the supply voltage Vdd on the gate terminal and is thus off; thereby the PFD is kept in the tri-state, i.e. does not provide any output signals, and the control voltage of the VCO 704 is stored by the capacitance C of the loop filter 702 and thus the synchronization is kept. Since the PFD 701 is triggered by the up-edges of the input signals, in order to ensure the end of the charging transient of the loop filter, the Hold signal must reach the high logical level at the down-edges of the signal on the OUT terminal of the DLL. At the end of transmission, the Hold, Sync and PreCh signals are at the low logical level.
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The capacitor C2 connected between the input terminal of the VCO 704 and the ground GND is used to introduce a high-frequency pole and to attenuate the harmonics generated by the PFD output.
The time diagrams of the involved signals in the DLL in figure 12 are shown in figure 14, where the frequency of the V(IN) signal on the input terminal IN is 7.5 Mhz and that of the V(OUT) signal on the OUT output terminal is of 15 Mhz and V(VinVCO) is the voltage on the input terminal of the VCO 704.
