EP2273659A1 - Procédé et appareil pour obtenir des informations activant la détermination du point d'alimentation maximum d'une source d'alimentation - Google Patents

Procédé et appareil pour obtenir des informations activant la détermination du point d'alimentation maximum d'une source d'alimentation Download PDF

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Publication number
EP2273659A1
EP2273659A1 EP09165145A EP09165145A EP2273659A1 EP 2273659 A1 EP2273659 A1 EP 2273659A1 EP 09165145 A EP09165145 A EP 09165145A EP 09165145 A EP09165145 A EP 09165145A EP 2273659 A1 EP2273659 A1 EP 2273659A1
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EP
European Patent Office
Prior art keywords
capacitor
snubber
voltage
power source
determination
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Application number
EP09165145A
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German (de)
English (en)
Inventor
Gustavo Buiatti
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Mitsubishi Electric Corp
Mitsubishi Electric R&D Centre Europe BV Netherlands
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Mitsubishi Electric Corp
Mitsubishi Electric R&D Centre Europe BV Netherlands
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Priority to EP09165145A priority Critical patent/EP2273659A1/fr
Publication of EP2273659A1 publication Critical patent/EP2273659A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Definitions

  • the present invention relates generally to a method and an apparatus for obtaining information enabling the determination of the maximum power point of a power source like a photovoltaic cell or an array of cells or a fuel cell.
  • a photovoltaic cell directly converts solar energy into electrical energy.
  • the electrical energy produced by the photovoltaic cell can be extracted over time and used in the form of electric power.
  • the direct electric power provided by photovoltaic cell is provided to conversion devices like DC-DC up/down converter circuits and/or DC/AC inverter circuits.
  • the current-voltage droop characteristics of photovoltaic cells cause the output power to change nonlinearly with the current drawn from photovoltaic cells.
  • the power-voltage curve changes according to climatic variations like light radiation levels and operation temperatures.
  • the near optimal point at which to operate photovoltaic arrays is at or near the region of the current-voltage curve where power is greatest. This point is denominated as the Maximum Power Point (MPP).
  • MPP Maximum Power Point
  • the MPP also changes according to climatic variations.
  • Charge pumps also known as DC/DC converters or boost converters composed of plural bridge devices use capacitors as energy storage elements.
  • DC/DC converters also known as inductive switching DC/DC converters, which also use inductors as energy storage elements, charge pumps offer unique characteristics that make them attractive for certain end-user applications.
  • Boost converters composed of plural bridge devices are sometimes used for converting the electric energy provided by a power source into another form.
  • the present invention aims at providing a method and an apparatus for obtaining information enabling the determination of the maximum power point of a power source without adding an important number of components, or even without adding any extra component, to existing boost converters composed of plural bridge devices.
  • the present invention concerns an apparatus for obtaining information enabling the determination of the maximum power point of a power source providing current intended to a boost converter composed of a number n of bridge devices connected in series, each bridge device being composed of plural switches and a capacitor, the boost converter comprising a snubber circuit comprising a snubber capacitor, characterised in that the apparatus for obtaining information enabling the determination of the maximum power point of the power source comprises means for monitoring the voltage of the snubber capacitor in order to obtain information enabling the determination of the maximum power point of the power source.
  • the present invention concerns also a method for obtaining information enabling the determination of the maximum power point of a power source providing current intended to a boost converter composed of a number n of bridge devices connected in series, each bridge device being composed of plural switches and a capacitor, the boost converter comprising a snubber circuit comprising a snubber capacitor, characterised in that the method for obtaining information enabling the determination of the maximum power point of the power source comprises the step of monitoring the voltage of the snubber capacitor in order to obtain information enabling the determination of the maximum power point of the power source.
  • the snubber circuit further comprises a snubber resistor and a snubber diode, the snubber diode and the snubber resistor being connected in parallel, the anode of the snubber diode being connected to the positive terminal of the power source, the positive terminal of the snubber capacitor being connected to the snubber resistor and to the cathode of the snubber diode, the negative terminal of the snubber capacitor being connected to the negative terminal of the power source.
  • the apparatus for obtaining information enabling the determination of the maximum power point of the power source further comprises an additional capacitor, the positive terminal of which being connected to the positive terminal of the snubber capacitor, the negative terminal of which being connected to a first terminal of an additional switch, the second terminal of the additional switch being connected to the negative terminal of the snubber capacitor.
  • the total capacitance value is significantly increased particularly when the capacitance value of the additional capacitor is much higher than the capacitance of the snubber capacitor.
  • Information enabling the determination of the maximum power point of the power source like the voltage-current/voltage-power droop characteristics are more accurate without the need of expensive devices which would be able to sample the voltage at very high sampling frequencies.
  • the means for monitoring the voltage of the snubber capacitor monitor the voltage charge of the snubber capacitor and of the additional capacitor.
  • the measured voltage at consecutive samples surrounding a given sample are processed using a fitted mathematical function obtained by minimizing the sum of the squares of the difference between the measured voltages at consecutive samples and mathematical functions in order to obtain a processed voltage for the given sample.
  • the noise that might appear on the measured voltage sample is already filtered by the polynomial function resulting in an improved voltage estimation for that sample.
  • the mathematical functions are polynomial functions of a given order with real coefficients.
  • the current for the given sample is determined by multiplying the total capacitance value of the snubber capacitor and of the additional capacitor by the derivative of the fitted mathematical function for the given sample.
  • the anode of the snubber diode is connected to the positive terminal of the power source and the cathode of the snubber diode is connected to the positive terminal of the snubber capacitor enabling the snubber capacitor to be charged by a current going through snubber diode and avoiding that a discharge current of the capacitor goes through the snubber diode.
  • the snubber diode allows to charge the capacitor(s) and also allows to discharge the capacitor(s) through the parallel snubber resistor since it is not possible to have reverse current conduction through the snubber diode.
  • the boost converter is connected to a load, each switch of each bridge is put in a non conducting state in order to disconnect the load from the power source.
  • the load is disconnected from the power source during the charge of the snubber capacitor and of the additional capacitor.
  • the apparatus further comprises means for determining the charge current of the snubber capacitor and of the additional capacitor from the monitored voltage charge of the snubber capacitor and of the additional capacitor.
  • Information enabling the determination of the maximum power point of the power are the voltage-current/voltage-power droop characteristics of the power source obtained through the pairs of estimated current and measured voltage during the charging time period.
  • At least a part of the switches of each bridge are put in a conducting state, enabling the first terminal of the snubber resistor to be connected to the negative terminal of the snubber capacitor.
  • the means for determining the voltage of the snubber capacitor monitor the discharge of the snubber capacitor and of the additional capacitor in order to determine the equivalent capacitance value of the snubber capacitor and the additional capacitor.
  • the boost converter is also named Reactor Less Boost Converter or an inductor less boost converter, herein named RLBC.
  • the present invention is described in a RLBC connected to a photovoltaic module.
  • the present invention is also applicable in any system wherein power source has a MPP.
  • the inductor of the conventional DC/DC Boost converter is replaced by "k" bridge devices connected in series.
  • Each bridge device is composed of four switches and a capacitor as shown in Fig. 1 . It has to be noted here that two switches may be under the form of diodes acting as switches Si1 and Si3, where i denotes the bridge device Bi .
  • This individual bridge structure is also named "bit”. The last bit B3 can be simplified in the number of switches as shown in Fig. 1 .
  • the boost converter composed of plural bridge devices also contains an output stage comprising a diode Do and a capacitor Co.
  • Fig. 1 three bits or bridge devices B1, B2 and B3 are shown and are connected in series; the third bit B3 is connected to the output stage.
  • a boost converter comprising a more important number of bridge devices can be obtained by duplicating the bit B1 as much as necessary.
  • the bit B1 is composed of four switches S 11 , S 12 , S 13 and S 14 and one capacitor C 1 .
  • the switches S 11 and S 14 are the switches of the high side of the bit B1 and the switches S 12 and S 13 are the switches of the low side of the bit B1.
  • the switches S 11 and S 12 are the switches of one leg of the bit B1 and the switches S 14 and S 13 are the switches of the other leg of the bit B1.
  • the bit B2 is composed of four switches S 21 , S 22 , S 23 and S 24 and one capacitor C 2 .
  • the switches S 21 and S 24 are the switches of the high side of the bit B2 and the switches S 22 and S 23 are the switches of the low side of the bit B2.
  • the switches S 21 and S 22 are the switches of one leg of the bit B2 and the switches S 24 and S 23 are the switches of the other leg of the bit B2.
  • the bit B3 is composed of three switches S 31 , S 32 and S 33 and one capacitor C 3 .
  • the first terminal of the switch S i1 is connected to the second terminal of the switch S i2 .
  • the second terminal of the switch S i1 is connected to the second terminal of the switch S i4 and to the positive terminal of the capacitor C i .
  • the first terminal of the switch S i2 is connected to the negative terminal of the capacitor C i and to the first terminal of the switch S i3 .
  • the first terminal of the switch S i4 is connected to the second terminal of the switch S i3 .
  • Electric DC providing means like photovoltaic modules provide an input voltage Vin.
  • the positive terminal of electric DC providing means is connected to the first terminal of the switch S 11 .
  • the first terminal of the switch S 31 is connected to the second terminal of the switch S 32 .
  • the second terminal of the switch S 31 is connected to the anode of the diode D O and to the positive terminal of the capacitor C 3 .
  • the first terminal of the switch S 32 is connected to the negative terminal of the capacitor C 3 and to the second terminal of the switch S 33 .
  • the first terminal of the switch S 33 is connected to the negative terminal of electric DC providing means.
  • the cathode of the diode D O is connected to the positive terminal of the capacitor C O .
  • the negative terminal of the capacitor C O is connected to the negative terminal of electric DC providing means.
  • the first terminal of the switch S 14 is connected to the first terminal of the switch S 21 .
  • the first terminal of the switch S 24 is connected to the first terminal of the switch S 31 .
  • the voltage on the capacitor C O is equal to Vout.
  • Vb1 The difference of voltage between the input and the output of B1 is named Vb1
  • Vb2 the difference of voltage between the input and the output of B2
  • Vb3 the difference of voltage between the input and the output of B3 is named Vb3.
  • Vb3 equals Vb3* when switch S 33 is on, and equals Vb3** when switch S 33 is off.
  • V C1 The difference of voltage in C 1 is named V C1
  • V C2 the difference of voltage in C 2
  • V C3 the difference of voltage in C 3
  • the RLBC further comprises a snubber circuit.
  • Snubber circuits are frequently used in electrical systems with an inductive load where the sudden interruption of current flow often leads to a sharp rise in voltage across the device creating the interruption.
  • This sharp rise in voltage is a transient and can damage and lead to the failure of the semiconductor device.
  • a spark is likely to be generated (arcing) and to cause electromagnetic interference.
  • the snubber circuit prevents this undesired voltage by conducting transient current around the device.
  • the role of the snubber circuit is to avoid voltage oscillations on its input caused by the dead-time imposed between the switching of the complementary switches of each leg on each bit. Avoiding voltage oscillations, the power generation efficiency around the MPP is improved.
  • the snubber circuit comprises at least a capacitor C S .
  • the snubber circuit is composed of a resistor R S and a capacitor C S .
  • the snubber circuit is composed of a diode D S , a resistor R S and a capacitor C S .
  • the positive terminal of power source PV is connected to the anode of the diode D S and to the first terminal of the resistor R S .
  • the cathode of the diode D S is connected to the second terminal of the resistor R S and to a first terminal of the capacitor C S .
  • the second terminal of the capacitor C S is connected to the negative terminal of the power source PV.
  • the RLBC further comprises means for measuring the voltage V1 of the capacitor C S of the snubber circuit.
  • the charge of the capacitor C S is monitored. According to a particular mode of realisation of the present invention, the charge of the capacitor C S is monitored in order to determine the current going through the capacitor C S in order to determine information enabling the determination of the maximum power point of the power source PV.
  • Information enabling the determination of the maximum power point of the power source PV are the voltage-current/voltage-power droop characteristics of the power source PV.
  • the discharge of the capacitor C S is monitored in order to determine the capacitor C S value.
  • a supplementary capacitor C UI having a larger capacitance value is connected in parallel with the capacitor C S when the voltage-current/voltage-power droop characteristics and consequently the MPP of the power source PV or equivalent capacitance value determination of both capacitors needs to be performed.
  • the positive terminal of the capacitor C UI is connected to the positive terminal of the capacitor C S and the negative terminal of the capacitor C UI is connected to the second terminal of a switch S UI .
  • the first terminal of the switch S UI is connected to the negative terminal of the capacitor C S .
  • V CO is the stepped-up output voltage
  • the switching pattern of the switches of each bridge Bi is defined so as to offer a voltage Vbi at the connectors of the bridge that equals + Vci, -Vci, or 0, where Vci is the voltage of the capacitor C i .
  • n ratios can finally be higher than 2 k .
  • the switching patterns are applied on the switches S 11 , S 12 , S 13 , S 14 , S 21 , S 22 , S 23 , S 24 , S 31 , S 32 and S 33 .
  • Fig. 2 is an example of a curve representing the output current variations of a power source according to the output voltage of the power source.
  • Fig. 2 On the horizontal axis of Fig. 2 , voltage values are shown. The voltage values are comprised between null value and the open-circuit voltage Voc.
  • the current values are shown on the vertical axis of Fig. 2 .
  • the current values are comprised between null value and the short circuit current I SC .
  • Fig. 3 represents an example of a device comprising a boost converter composed of plural bridge devices.
  • the device 30 has, for example, an architecture based on components connected together by a bus 301 and a processor 300 controlled by the programs related to the algorithms as disclosed in the Figs. 6 , 8 and 10 .
  • the device 30 is, in a variant, implemented under the form of one or several dedicated integrated circuits which execute the same operations as the one executed by the processor 300 as disclosed hereinafter.
  • the bus 301 links the processor 300 to a read only memory ROM 302, a random access memory RAM 303, an analogue to digital converter ADC 306 and the RLBC converter as the one disclosed in Fig. 1 .
  • the read only memory ROM 302 contains instructions of the program related to the algorithm as disclosed in the Figs. 6 , 8 and 10 which are transferred, when the device 30 is powered on to the random access memory RAM 303.
  • the read only memory ROM 302 memorizes the tables shown in Figs. 4 and 5 .
  • the RAM memory 303 contains registers intended to receive variables, and the instructions of the programs related to the algorithms as disclosed in the Figs. 6 , 8 and 10 .
  • the analogue to digital converter 306 is connected to the RLBC and converts voltages representative of the voltage V1 and/or the output voltage Vout into binary information.
  • Fig. 4 represents a table representing the switching states of the switches of the boost converter in order to obtain different voltages on the bridges of the boost converter.
  • the columns 400 to 404 are related to the bit B1
  • the columns 405 to 409 are related to the bit B2
  • the columns 410 to 412 are related to the bit B3.
  • the line 413 shows that for a voltage Vb1 which is equal to Vc1, the switches S 11 and S 13 are in conductive state and the switches S 12 and S 14 are in non conductive state, for a voltage Vb2 which is equal to Vc2, the switches S 21 and S 23 are in conductive state and the switches S 22 and S 24 are in non conductive state, for a voltage Vb3* in Fig. 1 which is equal to Vc3, the switches S 31 and S 33 are in conductive state and the switch S 32 is in non conductive state.
  • the line 414 shows that for a voltage Vb1 which is equal to null value, the switches S 11 and S 14 are in non conductive state and the switches S 12 and S 13 are in conductive state, for a voltage Vb2 which is equal to null value, the switches S 21 and S 24 are in non conductive state and the switches S 22 and S 23 are in conductive state, for a voltage Vb3* in Fig. 1 which is equal to null value, the switches S 32 and S 33 are in conductive state and the switch S 31 is in non conductive state, for a voltage Vb3** in Fig. 1 which is equal to null value, the switches S 31 is in conductive state and the switch S 32 and S 33 are in non conductive state
  • the line 415 shows that for a voltage Vb1 which is equal to -Vc1, the switches S 11 and S 13 are in non conductive state and the switches S 12 and S 14 are in conductive state, for a voltage Vb2 which is equal to -Vc2, the switches S 21 and S 23 are in non conductive state and the switches S 22 and S 24 are in conductive state, for a voltage Vb3** in Fig. 1 which is equal to -Vc3, the switches S 31 and S 33 are in non conductive state and the switch S 32 is in conductive state.
  • Fig. 5 is an example of voltage values on the bridges of the boost converter composed of three bridges in order to have a first step-up ratio when the periodical pattern is decomposed into eight time intervals.
  • Vb1 V ref
  • Vb1 V ref
  • Vb1 V ref
  • Fig. 6 is an example of an algorithm for obtaining information enabling the determination of the maximum power point of the power source according to a particular mode of realisation of the present invention.
  • the present algorithm is executed by the processor 300.
  • Information enabling the determination of the maximum power point of the power source may be the voltage-current/voltage-power droop characteristics of the power source PV.
  • the processor 300 checks if it is time to characterize and evaluate the MPP of the power source PV.
  • the MPP may be evaluated periodically or on particular events like climatic conditions variations or under the request by a maintenance system or a person in charge of the maintenance of the system.
  • the processor 300 commands the switches of the RLBC in order to configure the RLBC in a first configuration PH1.
  • the capacitor C S is discharged.
  • the switches S 12 , S 13 , S 22 , S 23 , S 32 and S 33 are put in ON state, i.e. in a conducting mode and the switch S UI is kept in OFF state, i.e. in non conducting mode.
  • capacitor C S The discharge of capacitor C S is shown in Figs. 7a and 7b .
  • Fig. 7a is an example of snubber capacitor voltage variations measured according to the present invention.
  • the time is represented on horizontal axis of the Fig. 7a and the voltage is represented on the vertical axis of the Fig. 7a .
  • the voltage V1 represents the voltage on C S .
  • Fig. 7b is an example of power source current variations obtained according to the present invention.
  • the time is represented on horizontal axis of the Fig. b and the current is represented on the vertical axis of the Fig. b.
  • the current represents the output current of the power source PV.
  • the voltage and the current provided by the power source PV correspond to previously determined MPP.
  • capacitor C S is discharged through resistor R S .
  • the voltage V1 decreases from V MPP to null value.
  • the current I MPP moves to I SC current value, since the voltage on the power source PV is at the null value due to the short-circuit created by switches S 12 , S 13 , S 22 , S 23 , S 32 and S 33 .
  • the processor 300 checks if it is time to stop the setting of the RLBC in the first configuration.
  • the setting of the RLBC in the first configuration has to be stopped once the capacitor C S is completely discharged.
  • the processor 300 commands the switches of the RLBC in order to configure the RLBC in a second configuration PH2.
  • the capacitor C S or the capacitors C S and C UI are charged.
  • the switches S 11 , S 12 , S 13 , S 14, S 21 , S 22 , S 23, S 24 , S 32 , S 32 and S 33 are put in OFF state, i.e. in a non conducting mode.
  • the capacitor C S is charged or if the supplementary capacitor C UI is used, the switch S UI is put in ON state, i.e. in a conducting mode and both capacitors C S and C UI are charged.
  • the capacitor C S is or capacitors C S and C UI are charged through the diode D S from zero voltage until V OC , the open-circuit voltage value of the power source at a current from I SC to null value as disclosed in Figs. 7a and 7b .
  • step S604 the processor 300 commands the sampling of the voltage V1 in order to determine the voltage-current/voltage-power droop characteristics and consequently the MPP of the power source PV as it will be disclosed in reference to Fig. 8 .
  • the processor 300 checks if it is time to stop the setting of the RLBC in the second configuration.
  • the setting of the RLBC in the first configuration has to be stopped once the capacitor C S or capacitors C S and C UI are completely charged.
  • step S606 When the setting of the RLBC in the second configuration has to be stopped, the processor 300 moves to step S606.
  • the processor 300 commands the switches of the RLBC in order to configure the RLBC in a third configuration PH3.
  • the capacitor C S or the capacitors C S and C UI are discharged.
  • the switches S 12 , S 13 , S 22 , S 23 , S 32 and S 33 are put in ON state, i.e. in a conducting mode.
  • the capacitor C S is discharged or if the supplementary capacitor C UI is used, the switch S UI is kept in ON state, i.e. in a conducting mode and both capacitors C S and C UI are discharged.
  • the capacitor C S is or capacitors C S and C UI are discharged through the resistor R S from V OC voltage until zero at a current I SC on the power source as disclosed in Figs. 7a and 7b .
  • the processor 300 commands the sampling of the voltage V1 in order to determine the capacitance value of capacitor C S or the equivalent capacitance value of both capacitors C S and C UI as it will be disclosed in reference to Fig. 10 .
  • the processor 300 checks if it is time to stop the setting of the RLBC in the third configuration.
  • the setting of the RLBC in the third configuration has to be stopped once the capacitor C S or capacitors C S and C UI are completely discharged.
  • step S609 When the setting of the RLBC in the third configuration has to be stopped, the processor 300 moves to step S609.
  • a next step S609 the samples are processed in order to determine the MPP of the power source as disclosed in Fig. 8 and also the capacitance value of capacitor C S or capacitors C S and C UI as disclosed in Fig. 10 .
  • a new MPP point will be determined and applied to the power source in a fourth phase PH4 as shown in Figs. 7 .
  • Fig. 8 is an example of an algorithm for determining information enabling the determination of the maximum power point of the power source according to a particular mode of realisation of the present invention.
  • Information enabling the determination of the maximum power point of the power source may be the voltage-current/voltage-power droop characteristics of the power source PV.
  • the present algorithm is executed by the processor 300.
  • the algorithm for determining the current-voltage droop characteristics and consequently the maximum power point of the power source according to the particular mode of realisation of the present invention uses the voltage V1 in order to determine the current going through the capacitor C UI .
  • the processor 300 commands the sampling of voltage V1.
  • the sampling is executed during the time period PH2 of Figs. 7 .
  • the processor 300 gets the samples obtained at step S800 during the time period PH2.
  • Each sample is bi-dimensional vector the coefficients of which are the voltage value and time to which voltage is measured.
  • the processor 300 determines the size of a moving window.
  • the size of the moving window indicates the number Npt of samples to be used for determining a curve based on the fitting of suitable mathematical functions, for example polynomial functions with real coefficients.
  • the size of the moving window is odd. For example, the size of the moving window is equal to seventy one.
  • Fig. 9a is an example of a first window which is used to determine a curve based on the fitting of suitable mathematical functions, for example polynomial functions with real coefficients, according to a particular mode of realisation of the present invention.
  • Fig. 8a the horizontal axis represents time and the vertical axis represents measured voltage V1.
  • Each cross represents a sample.
  • the window W1 is the moving window and the function f1 is the mathematical function which will be determined by the present algorithm.
  • the processor 300 determines the central point Nc of the moving window.
  • step S804 the processor 300 sets the variable i to the value Npt.
  • step S805 the processor 300 sets the variable j to i-Nc+1.
  • the processor 300 sets the variable k to one.
  • the processor 300 sets the value of x(k) to the time coefficient of sample j.
  • step S808 the processor 300 sets the value of y(k) to the voltage coefficient of sample j.
  • the processor 300 increments the variable k by one.
  • the processor 300 increments the variable j by one.
  • the processor 300 checks if the variable j is strictly lower than the sum of i and Nc minored by one.
  • step S807 If the variable j is strictly lower than the sum of i and Nc minored by one, the processor 300 returns to step S807. Otherwise the processor 300 moves to step S812.
  • the mathematical function for example the second degree polynomial function, is the function f1 shown in Fig. 8a.
  • the processor 300 obtains then the a, b and c real coefficients of the second degree polynomial function ([a,b,c] ⁇ 3 ).
  • step S814 the processor 300 increments the variable i by one unit.
  • step S815 the processor 300 checks if i is strictly lower than N minored by Nc wherein N is the total number of voltage samples obtained at step S801.
  • step S805 the processor 300 will displace the moving window by one sample as it is disclosed in reference to Fig. 9b .
  • Fig. 9b is an example of a second window which is used to determine a curve based on the fitting of suitable mathematical functions, for example polynomial functions with real coefficients, according to a particular mode of realisation of the present invention.
  • the horizontal axis represents time and the vertical axis represents measured voltage V1.
  • Each cross represents a sample.
  • the window W2 is the window W1 moved by one sample and the function f2 is the mathematical function which will be determined by the present algorithm at step S812 through the samples available on W2.
  • the processor 300 will execute the loop constituted by the steps S805 to S815 as far as i is strictly lower than N minored by Nc.
  • the window will be moved by one sample.
  • Fig. 9c is an example of a third window which is used to determine a curve based on the fitting of suitable mathematical functions, for example polynomial functions with real coefficients, according to a particular mode of realisation of the present invention.
  • Fig. 9c the horizontal axis represents time and the vertical axis represents measured voltage V1.
  • Each cross represents a sample.
  • the window W3 is the window W3 moved by one sample and the function f3 is the mathematical function which will be determined by the present algorithm at step S812 through the samples available on W3.
  • the processor 300 gets all the voltage and current values determined at the previous steps and forms a curve as the one shown in Fig. 2 .
  • the processor 300 determines the MPP thanks to the voltage and current values obtained at step S816.
  • the new MPP can then be used for an efficient use of the power source PV.
  • Fig. 10 is an example of an algorithm for determining the capacitance value of the capacitor(s) used for obtaining the voltage-current/voltage-power droop characteristics of the power source according to a particular mode of realisation of the present invention.
  • Electrolytic capacitors are the usual choice on DC/DC converters, and so is the capacitor C UI .
  • the accuracy of the calculated current strongly depends on the accuracy of the capacitance value. It is then desirable to accurately estimate the capacitance value, for example, every time that the algorithm disclosed in Fig. 8 will be executed.
  • V1 is monitored.
  • V1(t) is the voltage V1 at instant t.
  • V MPP 0.367879.
  • the constant time ⁇ R UI C UI can be estimated by the processor 300. Some filtering of the measurements is desired in order to reduce error caused by noise as it will be shown in the algorithm of Fig. 10 .
  • C UI value is estimated from ⁇ and R UI .
  • resistor R UI is a high precision power resistor.
  • the tolerance of resistor R UI is between ⁇ 0.05% and ⁇ 1%.
  • the processor 300 commands the sampling of voltage V1.
  • the sampling is executed during the time period PH3 of Figs. 7 .
  • the processor 300 gets the samples obtained at step S1000 during the time period PH2.
  • Each sample is bi-dimensional vector the coefficients of which are the voltage value and time to which voltage is measured.
  • the processor 300 determines a size of a moving window.
  • the size of the moving window indicates the number Npt of samples to be used for determining a curve based on the fitting of suitable polynomial functions.
  • the size of the moving window is odd. For example, the size of the moving window is equal to twenty one.
  • the processor 300 determines the central point Nc of the moving window.
  • the processor 300 sets the variable I to the value Npt.
  • step S1005 the processor 300 sets the variable j to i-Nc+1.
  • the processor 300 sets the variable k to one.
  • the processor 300 sets the value of x(k) to the time coefficient of sample j.
  • step S1008 the processor 300 sets the value of y(k) to the voltage coefficient of sample j.
  • the processor 300 increments the variable k by one.
  • the processor 300 increments the variable j by one.
  • the processor 300 checks if the variable j is strictly lower than the sum of i and Nc minored by one.
  • step S1007 If the variable j is strictly lower than the sum of i and Nc minored by one, the processor 300 returns to step S1007. Otherwise the processor 300 moves to step S1012.
  • the processor 300 determines the mean of the y(k) values accumulated every time that the step S1008 is executed for the value i under process.
  • the processor 300 increments the variable i by one unit.
  • the processor 300 checks if i is strictly lower than N minored by Nc wherein N is the total number of samples obtained at step S1001.
  • step S1005 the processor 300 will displace the moving window by one sample.
  • the window will be moved by one sample.
  • the processor 300 gets the voltage values determined every time that the step S1012 is executed.
  • C UI can then be determined.
EP09165145A 2009-07-10 2009-07-10 Procédé et appareil pour obtenir des informations activant la détermination du point d'alimentation maximum d'une source d'alimentation Withdrawn EP2273659A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2515423A1 (fr) * 2011-04-19 2012-10-24 Mitsubishi Electric R&D Centre Europe B.V. Appareil pour le contrôle du courant traversant un inducteur d'un dispositif de conversion d'énergie

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040264225A1 (en) * 2003-05-02 2004-12-30 Ballard Power Systems Corporation Method and apparatus for determining a maximum power point of photovoltaic cells

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040264225A1 (en) * 2003-05-02 2004-12-30 Ballard Power Systems Corporation Method and apparatus for determining a maximum power point of photovoltaic cells

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2515423A1 (fr) * 2011-04-19 2012-10-24 Mitsubishi Electric R&D Centre Europe B.V. Appareil pour le contrôle du courant traversant un inducteur d'un dispositif de conversion d'énergie

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