EP1383103B1 - Automatic adaptation of the supply voltage of an electroluminescent panel depending on the desired luminance - Google Patents

Automatic adaptation of the supply voltage of an electroluminescent panel depending on the desired luminance Download PDF

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Publication number
EP1383103B1
EP1383103B1 EP03300065A EP03300065A EP1383103B1 EP 1383103 B1 EP1383103 B1 EP 1383103B1 EP 03300065 A EP03300065 A EP 03300065A EP 03300065 A EP03300065 A EP 03300065A EP 1383103 B1 EP1383103 B1 EP 1383103B1
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Prior art keywords
voltage
signal
pol
current
column
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EP03300065A
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German (de)
French (fr)
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EP1383103A1 (en
Inventor
Celine Mas
Eric Benoit
Olivier Scouarnec
Olivier Le Briz
Danika Chaussy
Philippe Maige
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STMicroelectronics SA
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STMicroelectronics SA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3216—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present invention relates to electroluminescent display matrix screens composed of a set of light-emitting diodes. These are for example screens composed of organic diodes ("OLED" of the English Organic Light Emitting Display) or polymer ("PLED” of the English Polymer Light Emitting Display).
  • OLED organic diodes
  • PLED polymer
  • the present invention relates more particularly to the regulation of the supply voltage of the control circuits of the light-emitting diodes of such screens.
  • the figure 1 represents a matrix screen comprising n columns C 1 to C n and k lines L 1 to L k for addressing n * k light-emitting diodes d whose anodes are connected to a column and the cathodes to a line.
  • Line control circuits CL 1 to CL k are used to bias lines L 1 to L k respectively . Only one line is activated at a time, and is biased to ground. The unactivated lines are biased to a voltage Vlign.
  • Column control circuits CC 1 to CC n are used to bias the columns C 1 to C n, respectively .
  • the columns addressing the light-emitting diodes that it is desired to activate are biased by a current at a voltage V col greater than the threshold voltage of the light-emitting diodes. of the screen.
  • the columns that we do not want to activate are grounded.
  • a light emitting diode connected to the activated line and a polarized column V-neck is then busy, and emits light.
  • the line voltage V is sufficiently high so that the light-emitting diodes connected to the non-activated lines and to the columns with the voltage V col are not conductive and do not emit light.
  • the figure 2 represents a column control circuit CC and a line control circuit CL respectively addressing a column C and a line L connected to a light emitting diode d of the screen.
  • the line control circuit CL comprises a power inverter 1 controlled by a line control signal ⁇ L.
  • the power inverter 1 comprises an NMOS transistor 2 making it possible to discharge the line L when ⁇ L is at the high level and a PMOS transistor 3 making it possible to charge the line L at the bias voltage V line when ⁇ L is at the low level.
  • the column control circuit CC comprises a current mirror made in the present example with two transistors 4, 5 of the PMOS type.
  • the transistor 4 constitutes the reference branch of the mirror and the transistor 5 constitutes the duplication branch.
  • the sources of transistors 4 and 5 are connected to a bias voltage V pol of the order of 15 V for OLED screens.
  • the gates of transistors 4 and 5 are connected to each other.
  • the drain and the gate of transistor 4 are connected to each other.
  • the transistor 4 is therefore diode-mounted, the source-gate voltage (Vsg 4 ) being equal to the source-drain voltage (Vsd 4 ).
  • the current flowing through the transistor 4 is set by a current source 6 connected to the drain of the transistor 4.
  • the current source 6 supplies a current I l called "luminance".
  • the drain of the transistor 5 is connected to the column C via a column selection circuit composed of a PMOS transistor 7 and an NMOS transistor 8.
  • the source of the PMOS transistor 7 is connected to the drain of the transistor 5 and the drain of the transistor 7 is connected to the column C.
  • the source of the transistor 8 is grounded and its drain is connected to the column C.
  • a column control signal ⁇ C is connected to the gate of the PMOS transistor 7 and to the gate of the NMOS transistor 8.
  • the column control signal ⁇ C When the column control signal ⁇ C is high, the transistor 8 discharges the column C. When it is at the low level, the transistor 7 is on and the column C is charged until to reach the voltage V col .
  • the line control signals ⁇ L and column ⁇ C are respectively high and low, the light emitting diode d is on and the current flowing through the diode is equal to the luminance current I l .
  • the bias voltage V pol is equal to the sum of the source-drain voltage Vsd 2 of the transistor 2, the voltage V d across the electroluminescent diode d, the source-drain voltage Vsd 7 of the transistor 7 and the source-drain voltage Vsd 5 of the transistor 5.
  • the transistor 5 When the copy of the current I l is correct, the transistor 5 is in saturation mode and the voltage Vsd 5 is at least equal to the source-drain voltage Vsd 4 of the transistor 4.
  • a correct copy therefore requires that the bias voltage V pol is at least equal to the sum mentioned above when the current flowing through it is equal to the luminance current I l . If the bias voltage V pol is too low, the current flowing through the light-emitting diode d is lower than the current I l and the luminance of the diodes is insufficient.
  • the luminance current I 1 supplied by the current source 6 can generally vary according to the desired luminance for the screen.
  • the source-drain voltage Vsd 4 of the diode-connected transistor 4 increases and the voltage V d of the light-emitting diode d also increases. It follows that the voltage of V polarity must be large enough that the transistor 5 is in saturation irrespective of the luminance current.
  • the document US5594463A discloses a matrix screen with light-emitting diodes in which the voltage difference on one of the light-emitting diodes is measured and the bias voltage of the current mirror is adapted accordingly.
  • JP2000347613A and JP11272223A describe light emitting diode matrix screens in which the voltage at the output of the current source for one or more light-emitting diodes is measured and the bias voltage of the current sources is adapted accordingly.
  • An object of the present invention is to provide a column control circuit whose bias voltage V pol is the lowest possible regardless of the aging of the light emitting diodes of the screen.
  • Another object of the present invention is to provide a control circuit of simple design.
  • the present invention provides a device for regulating the bias voltage of column control circuits of a matrix screen composed of light-emitting diodes each connected to one of the rows and to one of the columns of the screen, such as as set forth in claim 1.
  • the present invention also provides a method for regulating the bias voltage of column control circuits of a matrix screen composed of light-emitting diodes each connected to one of the rows and to one of the columns of the screen, as stated in FIG. claim 7.
  • the figure 3 is a diagram of an embodiment of column control circuits and polarization voltage regulator device V pol according to the present invention.
  • the column control circuits comprise a current mirror 9 composed of a reference branch b ref and n duplication branches b 1 to b n .
  • Each branch is composed of a PMOS transistor, P ref for the reference branch and P 1 to P n for the branches b 1 to b n.
  • the sources of the transistors of each of the branches are connected to the bias voltage V pol and the gates are connected to each other.
  • the drain and the gate of the transistor P ref of the reference branch are connected to a reference current source 10 at a point C ref .
  • the reference current source 10 provides a luminance current I 1 .
  • each transistor P i i being between 1 and n, is connected to a column C i of the screen via a column selection circuit as described in relation to the figure 2 .
  • the set of column selection circuits are represented by a selection device 11 controlled by a column signal ⁇ C.
  • Each column C 1 to C n is connected to the anode of a diode respectively D 1 to D n .
  • the cathodes of the diodes D 1 to D n are connected to a current source 15 at a point C o .
  • the current source 15 provides a so-called observation current I ob chosen small relative to the minimum luminance current.
  • the connection point C ref is connected to the anode of a diode D ref identical to the diodes D 1 to D n
  • the cathode of the diode D ref is connected at a point C oref to a current source 16 providing a current equal to the observation current I ob .
  • the points C ref and C oref are connected to two inputs of an adjustment circuit CR which supplies the bias voltage V pol .
  • the light-emitting diodes can, even when they are crossed by the same current, have different voltage drops across their terminals. In particular, this voltage drop tends to increase when the light-emitting diodes age.
  • the object of the present invention is to adjust the voltage V pol to take account of these voltage variations and to ensure that the selected luminance current I I circulates in all the selected columns, V pol remaining as small as possible.
  • the diodes D 1 to D n corresponding to the selected columns tend to be conductive.
  • the diode connected to the column having the highest voltage imposes the voltage V o on the cathodes of the diodes D 1 to D n .
  • Others diodes are therefore not conductive because the voltage at their terminals is lower than their threshold voltage.
  • the voltage V o is the image of the voltage on the column at the highest potential offset from a diode threshold voltage.
  • the voltage V oref at the connection point C oref is the image of the voltage Vref shifted by a diode threshold voltage.
  • the adjustment circuit CR then raises the bias voltage V pol until the voltages V o and V oref are equal.
  • the adjustment circuit reduces the bias voltage V bias to the minimum voltage V pol ensuring a circulation of the luminance current I l in all selected columns.
  • the figure 4 is a diagram of the bias voltage adjusting circuit V pol as a function of the difference between the voltages V o and V oref .
  • the adjustment circuit comprises an error amplifier 20, an operational amplifier 21 and an RS flip-flop 22 operating with a low supply voltage, for example 3.3 V.
  • the error amplifier 20 receives on a positive input , the voltage V o and on a negative input, the voltage V oref .
  • the levels of the voltages V o and V oref are very high for the error amplifier 20, it will be possible to provide a voltage converter providing voltages proportional to the voltages V o and V oref , over a voltage range greater than low.
  • the error amplifier 20 amplifies the difference between V o and V oref and provides an error signal er which varies for example between 1 and 2 V.
  • the error signal is for example 1.5 V. the higher the voltage V o is high with respect to V oref, and the error signal er is high and vice versa.
  • the signal er is applied to the positive input of the differential amplifier 21.
  • the output of the differential amplifier 21 is connected to the reset terminal R (reset) of the RS flip-flop 22.
  • the output of an oscillator osc is connected to the activation terminal S (set) of the RS flip-flop 22.
  • the output Q is at the high logic level (for example 3.3 V) when the activation terminal S is at the high level and at the logic low level ( eg 0V) when the reset terminal R is high. When both S activation and R reset terminals are low, the Q output retains the last level set.
  • the output of the RS flip-flop 22 is connected to the gate of an NMOS transistor Tf.
  • a resistor R is placed between the source of the transistor Tf and the ground.
  • a coil L is placed between the drain of the transistor Tf and the supply terminal at a voltage V bat , for example at 3.3 V.
  • the anode of a diode D f is connected to the drain of the transistor Tf and its cathode is connected to a first electrode of a capacitor C.
  • the second electrode of the capacitor C is connected to ground.
  • the first electrode of the capacitor C provides the voltage V pol .
  • the source of the transistor Tf is connected to the negative input of the differential amplifier 21.
  • the Q output of the RS flip-flop 22 goes high.
  • the transistor Tf closes and the voltage across the coil L passes rapidly from 0 to V bat .
  • the voltage V R across the resistor R and the current in the coil L are initially zero.
  • the current in the coil L increases gradually, so the voltage V R also increases.
  • the amplifier 21 changes state and goes high.
  • the Q output of the RS flip-flop 22 goes low and the transistor Tf opens.
  • the voltage on the drain of the transistor Tf increases sharply.
  • the diode Df becomes conducting and the capacitor C is charged.
  • the charging current is higher as the current flowing through the coil L is high when the transistor Tf opens.
  • the signal er When the voltage V o is greater than the voltage V oref , the signal er is relatively high. As a result, the transistor Tf remains longer and the current flowing in the coil L at the moment of the opening of the transistor Tf is important. The capacitor C is charged and the voltage V pol increases. Conversely, when the voltage V o is lower than the voltage V oref , the voltage V pol decreases.
  • the bias voltage V pol is adjusted according to the temporal variations of the voltage across the light emitting diodes of the screen.
  • An advantage of the control device according to the present invention is that the bias voltage is always minimal, which allows energy savings.
  • Another advantage of such a device is that its design is very simple.
  • the figure 5 is a scheme of column control circuits identical to those of the figure 3 and a diagram of an alternative embodiment of the polarization voltage regulator device V pol which overcomes the following problem.
  • V pol When a line of the screen is "black", that is to say that no light-emitting diode of the selected line is conducting, the voltage V o at the point C o of the control circuit of the figure 3 decreases because none of the diodes D 1 to D n is passing.
  • the voltage V o decreasing, the adjustment circuit CR decreases the bias voltage V pol .
  • the bias voltage V pol can greatly decrease.
  • the light-emitting diodes conducting "lighted" lines may then receive a current lower than the luminance current. The overall brightness of the screen decreases.
  • the device for regulating the bias voltage V pol is identical to that of the figure 3 except that the point C o is connected to the adjustment circuit CR via a switch 31.
  • a capacitor 32 is placed between the input of the adjustment circuit CR and the ground.
  • Switch 31 is controlled to be off when a line of the screen is black, i.e. when no light emitting diode of the selected line is conductive.
  • the capacitor 32 retains the value of the voltage V o corresponding to the last non-black line.
  • the control device of the switch not shown, analyzes the column signal ⁇ C to know if at least one column is selected and therefore that at least one diode is conductive.
  • control device of the switch analyzes the control signals of the line control circuits so as to turn on the switch 31 once the voltages of the selected columns have changed from their precharge voltages to their "operating" voltages corresponding to the voltages induced by each of the conductive light emitting diodes.
  • the figure 6 is a diagram of an embodiment of the error amplifier 20 of the CR adjustment circuit of the figure 4 which makes it possible to overcome the following problem.
  • the voltage V o can be very close to the bias voltage V pol .
  • Such a fault leads not only to a disproportionate increase in the bias voltage V pol but also to overvoltages likely among other things to damage the adjustment circuit CR.
  • a wear defect it may be interesting to detect the fault in order to avoid damaging the rest of the circuit and to avoid increasing the power consumption to provide a high voltage V pol .
  • the detection of a manufacturing defect makes it possible to detect the faulty circuits before their marketing.
  • the error amplifier represented in figure 6 comprises two PMOS transistors 40 and 41 whose gates respectively receive the voltages V o and V oref of the control device represented in FIG. figure 3 .
  • Two identical current sources 42 and 43 are placed between the bias voltage V pol and the sources of the transistors 40 and 41.
  • a resistor R1 is placed between the sources of the transistors 40 and 41.
  • the drains of the transistors 40 and 41 are connected to a conversion device 44 which provides the error signal er.
  • a PMOS transistor 45 is placed in parallel on the transistor 40.
  • the source of the transistor 45 is connected to the source of the transistor 40 and the drain of the transistor 45 is connected to the drain of the transistor 40.
  • the gate of the transistor 45 receives a voltage of protection V protect which is provided by a device not shown.
  • the protective voltage V protect corresponds to the maximum voltage V o corresponding to correct operation of the screen and the column and line control circuits.
  • the voltage V o is lower than the protection voltage V protect .
  • the transistors 40, 41 and 45 are such that when they conduct a current equal to that supplied by the current sources 42 and 43, their gate-source voltages is substantially equal to the threshold voltage of a PMOS transistor. Thus, when the voltage V o is lower than the voltage V protect , the transistor 45 is non-conductive. Similarly, when voltages V o and V oref are different the voltages on the sources of transistors 40 and 41 are different. The resistance R1 is then crossed by a current which is higher as the difference between the voltages V o and V oref is high.
  • the conversion device 44 analyzes the current differences in the transistors 40 and 41 and provides an error signal er which is all the greater as the current in the transistor 40 is small relative to the current in the transistor 41 and vice versa.
  • the voltage V o can be very close to the bias voltage V pol .
  • the transistor 45 becomes conductive and the transistor 40 is non-conductive.
  • the bias voltage V pol is then maximal.
  • the maximum value of the voltage V pol depends on the choice of the voltage V protect and the voltage V oref which is a function of the desired luminance current.
  • the presence of the transistor 45 makes it possible to ensure that the bias voltage V pol does not exceed a given maximum value and also makes it possible to eliminate any overvoltages that may damage the adjustment circuit CR.
  • the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art.
  • one skilled in the art will realize a current mirror different from that described, for example using two transistors per branch.

Description

La présente invention concerne des écrans matriciels à affichage électroluminescent composés d'un ensemble de diodes électroluminescentes. Il s'agit par exemple d'écrans composés de diodes organiques ("OLED" de l'anglais Organic Light Emitting Display) ou polymère ("PLED" de l'anglais Polymer Light Emitting Display). La présente invention concerne plus particulièrement la régulation de la tension d'alimentation des circuits de commande des diodes électroluminescentes de tels écrans.The present invention relates to electroluminescent display matrix screens composed of a set of light-emitting diodes. These are for example screens composed of organic diodes ("OLED" of the English Organic Light Emitting Display) or polymer ("PLED" of the English Polymer Light Emitting Display). The present invention relates more particularly to the regulation of the supply voltage of the control circuits of the light-emitting diodes of such screens.

La figure 1 représente un écran matriciel comportant n colonnes C1 à Cn et k lignes L1 à Lk permettant d'adresser n*k diodes électroluminescentes d dont les anodes sont connectées à une colonne et les cathodes à une ligne.The figure 1 represents a matrix screen comprising n columns C 1 to C n and k lines L 1 to L k for addressing n * k light-emitting diodes d whose anodes are connected to a column and the cathodes to a line.

Des circuits de commande de lignes CL1 à CLk permettent de polariser respectivement les lignes L1 à Lk. Seule une ligne est activée à la fois, et est polarisée à la masse. Les lignes non activées sont polarisées à une tension Vligne.Line control circuits CL 1 to CL k are used to bias lines L 1 to L k respectively . Only one line is activated at a time, and is biased to ground. The unactivated lines are biased to a voltage Vlign.

Des circuits de commande de colonnes CC1 à CCn permettent de polariser respectivement les colonnes C1 à Cn. Les colonnes adressant les diodes électroluminescentes que l'on souhaite activer sont polarisées par un courant à une tension Vcol supérieure à la tension de seuil des diodes électroluminescentes de l'écran. Les colonnes que l'on ne souhaite pas activer sont mises à la masse.Column control circuits CC 1 to CC n are used to bias the columns C 1 to C n, respectively . The columns addressing the light-emitting diodes that it is desired to activate are biased by a current at a voltage V col greater than the threshold voltage of the light-emitting diodes. of the screen. The columns that we do not want to activate are grounded.

Une diode électroluminescente reliée à la ligne activée et à une colonne polarisée à Vcol est alors passante et émet de la lumière. La tension Vligne est prévue suffisamment élevée afin que les diodes électroluminescentes reliées aux lignes non activées et aux colonnes à la tension Vcol ne soient pas conductrices et n'émettent pas de lumière.A light emitting diode connected to the activated line and a polarized column V-neck is then busy, and emits light. The line voltage V is sufficiently high so that the light-emitting diodes connected to the non-activated lines and to the columns with the voltage V col are not conductive and do not emit light.

La figure 2 représente un circuit de commande de colonne CC et un circuit de commande de ligne CL adressant respectivement une colonne C et une ligne L reliées à une diode électroluminescente d de l'écran. Le circuit de commande de ligne CL comprend un inverseur de puissance 1 commandé par un signal de commande de ligne φL. L'inverseur de puissance 1 comprend un transistor NMOS 2 permettant de décharger la ligne L quand φL est au niveau haut et un transistor PMOS 3 permettant de charger la ligne L à la tension de polarisation Vligne quand φL est au niveau bas.The figure 2 represents a column control circuit CC and a line control circuit CL respectively addressing a column C and a line L connected to a light emitting diode d of the screen. The line control circuit CL comprises a power inverter 1 controlled by a line control signal φ L. The power inverter 1 comprises an NMOS transistor 2 making it possible to discharge the line L when φ L is at the high level and a PMOS transistor 3 making it possible to charge the line L at the bias voltage V line when φ L is at the low level.

Le circuit de commande de colonne CC comprend un miroir de courant réalisé dans le présent exemple avec deux transistors 4, 5 de type PMOS. Le transistor 4 constitue la branche de référence du miroir et le transistor 5 constitue la branche de duplication. Les sources des transistors 4 et 5 sont connectées à une tension de polarisation Vpol de l'ordre de 15 V pour des écrans OLED. Les grilles des transistors 4 et 5 sont reliées l'une à l'autre. Le drain et la grille du transistor 4 sont reliés l'un à l'autre. Le transistor 4 est donc monté en diode, la tension source-grille (Vsg4) étant égale à la tension source-drain (Vsd4). Le courant traversant le transistor 4 est fixé par une source de courant 6 connectée au drain du transistor 4. La source de courant 6 fournit un courant Il dit de "luminance". Le drain du transistor 5 est relié à la colonne C par l'intermédiaire d'un circuit de sélection de colonne composé d'un transistor PMOS 7 et d'un transistor NMOS 8. La source du transistor PMOS 7 est reliée au drain du transistor 5 et le drain du transistor 7 est relié à la colonne C. La source du transistor 8 est à la masse et son drain est connecté à la colonne C. Un signal de commande de colonne φC est relié à la grille du transistor PMOS 7 et à la grille du transistor NMOS 8. Quand le signal de commande de colonne φC est au niveau haut, le transistor 8 décharge la colonne C. Quand il est au niveau bas, le transistor 7 est passant et la colonne C se charge jusqu'à atteindre la tension Vcol. Quand la ligne L et la colonne C sont activées, les signaux de commande de ligne φL et de colonne φC sont respectivement haut et bas, la diode électroluminescente d est passante et le courant traversant la diode est égal au courant de luminance Il.The column control circuit CC comprises a current mirror made in the present example with two transistors 4, 5 of the PMOS type. The transistor 4 constitutes the reference branch of the mirror and the transistor 5 constitutes the duplication branch. The sources of transistors 4 and 5 are connected to a bias voltage V pol of the order of 15 V for OLED screens. The gates of transistors 4 and 5 are connected to each other. The drain and the gate of transistor 4 are connected to each other. The transistor 4 is therefore diode-mounted, the source-gate voltage (Vsg 4 ) being equal to the source-drain voltage (Vsd 4 ). The current flowing through the transistor 4 is set by a current source 6 connected to the drain of the transistor 4. The current source 6 supplies a current I l called "luminance". The drain of the transistor 5 is connected to the column C via a column selection circuit composed of a PMOS transistor 7 and an NMOS transistor 8. The source of the PMOS transistor 7 is connected to the drain of the transistor 5 and the drain of the transistor 7 is connected to the column C. The source of the transistor 8 is grounded and its drain is connected to the column C. A column control signal φ C is connected to the gate of the PMOS transistor 7 and to the gate of the NMOS transistor 8. When the column control signal φ C is high, the transistor 8 discharges the column C. When it is at the low level, the transistor 7 is on and the column C is charged until to reach the voltage V col . When the line L and the column C are activated, the line control signals φ L and column φ C are respectively high and low, the light emitting diode d is on and the current flowing through the diode is equal to the luminance current I l .

Cependant, pour que le circuit de commande de colonne CC fonctionne tel que décrit précédemment, il est nécessaire que la tension Vpol soit suffisamment élevée pour que la recopie du courant Il soit correcte. La tension de polarisation Vpol est égale à la somme de la tension source-drain Vsd2 du transistor 2, de la tension Vd aux bornes de la diode électroluminescente d, de la tension source-drain Vsd7 du transistor 7 et de la tension source-drain Vsd5 du transistor 5.However, in order for the column control circuit CC to function as described above, it is necessary that the voltage V pol is sufficiently high for the copying of the current I 1 to be correct. The bias voltage V pol is equal to the sum of the source-drain voltage Vsd 2 of the transistor 2, the voltage V d across the electroluminescent diode d, the source-drain voltage Vsd 7 of the transistor 7 and the source-drain voltage Vsd 5 of the transistor 5.

Quand la recopie du courant Il est correcte, le transistor 5 est en régime de saturation et la tension Vsd5 est au minimum égale à la tension source-drain Vsd4 du transistor 4. Une recopie correcte impose donc que la tension de polarisation Vpol soit au moins égale à la somme précédemment mentionnée quand le courant la traversant est égal au courant de luminance Il. Si la tension de polarisation Vpol est trop faible, le courant traversant la diode électroluminescente d est inférieur au courant Il et la luminance des diodes est insuffisante.When the copy of the current I l is correct, the transistor 5 is in saturation mode and the voltage Vsd 5 is at least equal to the source-drain voltage Vsd 4 of the transistor 4. A correct copy therefore requires that the bias voltage V pol is at least equal to the sum mentioned above when the current flowing through it is equal to the luminance current I l . If the bias voltage V pol is too low, the current flowing through the light-emitting diode d is lower than the current I l and the luminance of the diodes is insufficient.

Le courant de luminance Il fourni par la source de courant 6 peut de façon générale varier en fonction de la luminance souhaitée pour l'écran. Quand le courant de luminance Il augmente, la tension source-drain Vsd4 du transistor 4 monté en diode augmente et la tension Vd de la diode électroluminescente d augmente aussi. Il s'ensuit que la tension de polarisation Vpol doit être suffisamment importante pour que le transistor 5 soit en saturation quel que soit le courant de luminance.The luminance current I 1 supplied by the current source 6 can generally vary according to the desired luminance for the screen. When the luminance current I l increases, the source-drain voltage Vsd 4 of the diode-connected transistor 4 increases and the voltage V d of the light-emitting diode d also increases. It follows that the voltage of V polarity must be large enough that the transistor 5 is in saturation irrespective of the luminance current.

Toutefois, par souci d'économie d'énergie électrique, on cherche à réduire la tension de polarisation Vpol, ce qui permet ensuite de réduire la tension Vligne des circuits de commande de ligne.However, for the sake of saving electrical energy, it is sought to reduce the bias voltage V pol , which then reduces the line voltage V line control circuits.

Il existe des circuits de commande qui ont une tension de polarisation Vpol fixe et déterminée en fonction du courant de luminance Il maximum souhaité. L'inconvénient de tels circuits est leur forte consommation d'énergie électrique.There are control circuits which have a fixed bias voltage V pol and determined according to the desired maximum luminance current Il. The disadvantage of such circuits is their high power consumption.

Il existe d'autres circuits de commande pour lesquels la tension de polarisation Vpol varie en fonction du courant de luminance I1 souhaité. Si le courant I1 est faible, la tension Vpol est faible et inversement. Toutefois, il est nécessaire de prévoir une marge de sécurité pour tenir compte du vieillissement des diodes électroluminescentes de l'écran. En effet, à courant égal dans la diode électroluminescente d, la tension Vd aux bornes de la diode augmente avec le temps. Pour une même luminance, correspondant à un courant de luminance donné, la tension de polarisation minimale Vpol nécessaire augmente donc progressivement avec le temps. Les économies d'énergie obtenues pour ces circuits ne sont donc pas optimales.There are other control circuits for which the bias voltage V pol varies as a function of the desired luminance current I 1 . If the current I 1 is weak, the voltage V pol is low and vice versa. However, it is necessary to provide a safety margin to take account of the aging of the light-emitting diodes of the screen. Indeed, at equal current in the light emitting diode, the voltage V d at the terminals of the diode increases with time. For the same luminance, corresponding to a given luminance current, the minimum polarization voltage V pol required therefore increases progressively with time. The energy savings obtained for these circuits are therefore not optimal.

Le document US5594463A décrit un écran matriciel à diodes électroluminescentes dans lequel la différence de tension sur une des diodes électroluminescentes est mesurée et la tension de polarisation du miroir de courant est adaptée en conséquence.The document US5594463A discloses a matrix screen with light-emitting diodes in which the voltage difference on one of the light-emitting diodes is measured and the bias voltage of the current mirror is adapted accordingly.

Les documents JP2000347613A et JP11272223A décrivent des écrans matriciels à diodes électroluminescentes dans lesquels la tension à la sortie de la source de courant pour une ou plusieurs diodes électroluminescentes est mesurée et la tension de polarisation des sources de courant est adaptée en conséquence.The documents JP2000347613A and JP11272223A describe light emitting diode matrix screens in which the voltage at the output of the current source for one or more light-emitting diodes is measured and the bias voltage of the current sources is adapted accordingly.

Un objet de la présente invention est de prévoir un circuit de commande de colonne dont la tension de polarisation Vpol est la plus faible possible quel que soit le vieillissement des diodes électroluminescentes de l'écran.An object of the present invention is to provide a column control circuit whose bias voltage V pol is the lowest possible regardless of the aging of the light emitting diodes of the screen.

Un autre objet de la présente invention est de prévoir un circuit de commande de conception simple.Another object of the present invention is to provide a control circuit of simple design.

Pour atteindre ces objets, la présente invention prévoit un dispositif de régulation de la tension de polarisation de circuits de commande de colonnes d'un écran matriciel composé de diodes électroluminescentes reliées chacune à une des lignes et à une des colonnes de l'écran, tel qu'énoncé en revendication 1.To achieve these objects, the present invention provides a device for regulating the bias voltage of column control circuits of a matrix screen composed of light-emitting diodes each connected to one of the rows and to one of the columns of the screen, such as as set forth in claim 1.

La présente invention prévoit aussi un procédé de régulation de la tension de polarisation de circuits de commande de colonnes d'un écran matriciel composé de diodes électroluminescentes reliées chacune à une des lignes et à une des colonnes de l'écran, tel qu'énoncé en revendication 7.The present invention also provides a method for regulating the bias voltage of column control circuits of a matrix screen composed of light-emitting diodes each connected to one of the rows and to one of the columns of the screen, as stated in FIG. claim 7.

Ces objets, caractéristiques et avantages, ainsi que d'autres de la présente invention seront exposés en détail dans la description suivante de modes de réalisation particuliers faite à titre non-limitatif en relation avec les figures jointes parmi lesquelles :

  • la figure 1, précédemment décrite, représente un écran électroluminescent matriciel ;
  • la figure 2, précédemment décrite, représente un circuit de commande de colonne et un circuit de commande de ligne adressant une diode électroluminescente d'un écran ;
  • la figure 3 illustre un exemple de réalisation du dispositif de régulation selon la présente invention ;
  • la figure 4 illustre un exemple de réalisation plus détaillé d'un élément du dispositif de la figure 3 ;
  • la figure 5 illustre un autre exemple de réalisation du dispositif de régulation selon la présente invention ; et
  • la figure 6 est un exemple de réalisation plus détaillé d'un élément du dispositif de la figure 4.
These and other objects, features, and advantages of the present invention will be set forth in detail in the following description of particular embodiments given as a non-limiting example in connection with the accompanying drawings in which:
  • the figure 1 , previously described, represents a matrix electroluminescent screen;
  • the figure 2 , previously described, represents a column control circuit and a line control circuit addressing a light-emitting diode of a screen;
  • the figure 3 illustrates an exemplary embodiment of the control device according to the present invention;
  • the figure 4 illustrates a more detailed embodiment of an element of the device of the figure 3 ;
  • the figure 5 illustrates another embodiment of the control device according to the present invention; and
  • the figure 6 is a more detailed embodiment of an element of the device of the figure 4 .

La figure 3 est un schéma d'un mode de réalisation de circuits de commande de colonne et du dispositif de régulation de la tension de polarisation Vpol selon la présente invention. Les circuits de commande de colonne comprennent un miroir de courant 9 composé d'une branche de référence bref et de n branches de duplication b1 à bn. Chaque branche est composée d'un transistor PMOS, Pref pour la branche de référence et P1 à Pn pour les branches b1 à bn. Les sources des transistors de chacune des branches sont connectées à la tension de polarisation Vpol et les grilles sont reliées les unes aux autres. Le drain et la grille du transistor Pref de la branche de référence sont reliés à une source de courant de référence 10 en un point Cref. La source de courant de référence 10 fournit un courant de luminance Il. Le drain de chaque transistor Pi, i étant compris entre 1 et n, est relié à une colonne Ci de l'écran par l'intermédiaire d'un circuit de sélection de colonne tel que décrit en relation à la figure 2. L'ensemble des circuits de sélection de colonne sont représentés par un dispositif de sélection 11 commandé par un signal de colonne φC.The figure 3 is a diagram of an embodiment of column control circuits and polarization voltage regulator device V pol according to the present invention. The column control circuits comprise a current mirror 9 composed of a reference branch b ref and n duplication branches b 1 to b n . Each branch is composed of a PMOS transistor, P ref for the reference branch and P 1 to P n for the branches b 1 to b n. The sources of the transistors of each of the branches are connected to the bias voltage V pol and the gates are connected to each other. The drain and the gate of the transistor P ref of the reference branch are connected to a reference current source 10 at a point C ref . The reference current source 10 provides a luminance current I 1 . The drain of each transistor P i , i being between 1 and n, is connected to a column C i of the screen via a column selection circuit as described in relation to the figure 2 . The set of column selection circuits are represented by a selection device 11 controlled by a column signal φ C.

Chaque colonne C1 à Cn est connectée à l'anode d'une diode respectivement D1 à Dn. Les cathodes des diodes D1 à Dn sont reliées à une source de courant 15 en un point Co. La source de courant 15 fournit un courant dit d'observation Iob choisi faible par rapport au courant de luminance minimal. Par ailleurs, le point de connexion Cref est relié à l'anode d'une diode Dref identique aux diodes D1 à Dn, la cathode de la diode Dref est connectée en un point Coref à une source de courant 16 fournissant un courant égal au courant d'observation Iob. Les points Cref et Coref sont reliés à deux entrées d'un circuit d'ajustement CR qui fournit la tension de polarisation Vpol.Each column C 1 to C n is connected to the anode of a diode respectively D 1 to D n . The cathodes of the diodes D 1 to D n are connected to a current source 15 at a point C o . The current source 15 provides a so-called observation current I ob chosen small relative to the minimum luminance current. Furthermore, the connection point C ref is connected to the anode of a diode D ref identical to the diodes D 1 to D n , the cathode of the diode D ref is connected at a point C oref to a current source 16 providing a current equal to the observation current I ob . The points C ref and C oref are connected to two inputs of an adjustment circuit CR which supplies the bias voltage V pol .

Comme on l'a indiqué précédemment, les diodes électroluminescentes peuvent, même quand elles sont traversées par un même courant, présenter à leurs bornes des chutes de tension différentes. Notamment, cette chute de tension tend à augmenter quand les diodes électroluminescentes vieillissent. La présente invention vise à ajuster la tension Vpol pour tenir compte de ces variations de tension et assurer que le courant de luminance Il choisi circule dans toutes les colonnes sélectionnées, Vpol restant aussi petit que possible.As indicated above, the light-emitting diodes can, even when they are crossed by the same current, have different voltage drops across their terminals. In particular, this voltage drop tends to increase when the light-emitting diodes age. The object of the present invention is to adjust the voltage V pol to take account of these voltage variations and to ensure that the selected luminance current I I circulates in all the selected columns, V pol remaining as small as possible.

Les diodes D1 à Dn correspondant aux colonnes sélectionnées tendent à être conductrices. Toutefois, la diode reliée à la colonne ayant la tension la plus élevée impose la tension Vo sur les cathodes des diodes D1 à Dn. Les autres diodes ne sont donc pas conductrices car la tension à leurs bornes est inférieure à leur tension de seuil. La tension Vo est l'image de la tension sur la colonne au potentiel le plus élevé décalée d'une tension de seuil de diode. De même, la tension Voref au point de connexion Coref est l'image de la tension Vref décalée d'une tension de seuil de diode.The diodes D 1 to D n corresponding to the selected columns tend to be conductive. However, the diode connected to the column having the highest voltage imposes the voltage V o on the cathodes of the diodes D 1 to D n . Others diodes are therefore not conductive because the voltage at their terminals is lower than their threshold voltage. The voltage V o is the image of the voltage on the column at the highest potential offset from a diode threshold voltage. Similarly, the voltage V oref at the connection point C oref is the image of the voltage Vref shifted by a diode threshold voltage.

Quand la tension Vo est supérieure à la tension Voref, ceci signifie que le courant dans au moins une des colonnes de l'écran est inférieur au courant de luminance Il choisi. Le circuit d'ajustement CR rehausse alors la tension de polarisation Vpol jusqu'à ce que les tensions Vo et Voref soient égales.When the voltage V o is greater than the voltage V oref , this means that the current in at least one of the columns of the screen is less than the luminance current I I chosen. The adjustment circuit CR then raises the bias voltage V pol until the voltages V o and V oref are equal.

Inversement, quand la tension Vo est inférieure à Voref, ceci implique que le courant de luminance Il choisi circule bien dans toutes les colonnes sélectionnées mais que la tension Vpol est trop élevée, ce qui entraîne une surconsommation d'énergie. Afin de réaliser des économies d'énergie électrique, le circuit d'ajustement diminue la tension de polarisation Vpol jusqu'à la tension Vpol minimale assurant une circulation du courant de luminance Il dans toutes les colonnes sélectionnées.Conversely, when the voltage V o is less than V O F O , this implies that the luminance current I l chosen circulates well in all the selected columns but that the voltage V pol is too high, which leads to an overconsumption of energy. In order to achieve economies of electric power, the adjustment circuit reduces the bias voltage V bias to the minimum voltage V pol ensuring a circulation of the luminance current I l in all selected columns.

La figure 4 est un schéma du circuit d'ajustement de la tension de polarisation Vpol en fonction de la différence entre les tensions Vo et Voref.The figure 4 is a diagram of the bias voltage adjusting circuit V pol as a function of the difference between the voltages V o and V oref .

Le circuit d'ajustement comprend un amplificateur d'erreur 20, un amplificateur opérationnel 21 et une bascule RS 22 fonctionnant avec une tension d'alimentation faible, par exemple 3,3 V. L'amplificateur d'erreur 20 reçoit sur une entrée positive, la tension Vo et sur une entrée négative, la tension Voref. Dans le cas où les niveaux des tensions Vo et Voref sont très élevés pour l'amplificateur d'erreur 20, on pourra prévoir un convertisseur de tension fournissant des tensions proportionnelles aux tensions Vo et Voref, sur une plage de tension plus faible.The adjustment circuit comprises an error amplifier 20, an operational amplifier 21 and an RS flip-flop 22 operating with a low supply voltage, for example 3.3 V. The error amplifier 20 receives on a positive input , the voltage V o and on a negative input, the voltage V oref . In the case where the levels of the voltages V o and V oref are very high for the error amplifier 20, it will be possible to provide a voltage converter providing voltages proportional to the voltages V o and V oref , over a voltage range greater than low.

L'amplificateur d'erreur 20 amplifie la différence entre Vo et Voref et fournit un signal d'erreur er qui varie par exemple entre 1 et 2 V. Quand les tensions Vo et Voref sont égales, le signal d'erreur vaut par exemple 1,5 V. Plus la tension Vo est élevée par rapport à Voref, et plus le signal d'erreur er est élevé et inversement. Le signal er est appliqué à l'entrée positive de l'amplificateur différentiel 21. La sortie de l'amplificateur différentiel 21 est reliée à la borne de réinitialisation R (reset) de la bascule RS 22. La sortie d'un oscillateur osc est reliée à la borne d'activation S (set) de la bascule RS 22. La sortie Q est au niveau logique haut (par exemple 3,3 V) quand la borne d'activation S est au niveau haut et au niveau logique bas (par exemple 0V) quand la borne de réinitialisation R est au niveau haut. Quand les deux bornes d'activation S et de réinitialisation R sont au niveau bas, la sortie Q conserve le dernier niveau positionné.The error amplifier 20 amplifies the difference between V o and V oref and provides an error signal er which varies for example between 1 and 2 V. When the voltages V o and V oref are equal, the error signal is for example 1.5 V. the higher the voltage V o is high with respect to V oref, and the error signal er is high and vice versa. The signal er is applied to the positive input of the differential amplifier 21. The output of the differential amplifier 21 is connected to the reset terminal R (reset) of the RS flip-flop 22. The output of an oscillator osc is connected to the activation terminal S (set) of the RS flip-flop 22. The output Q is at the high logic level (for example 3.3 V) when the activation terminal S is at the high level and at the logic low level ( eg 0V) when the reset terminal R is high. When both S activation and R reset terminals are low, the Q output retains the last level set.

La sortie de la bascule RS 22 est reliée à la grille d'un transistor NMOS Tf. Une résistance R est placée entre la source du transistor Tf et la masse. Une bobine L est placée entre le drain du transistor Tf et la borne d'alimentation à une tension Vbat, par exemple à 3,3 V. L'anode d'une diode Df est reliée au drain du transistor Tf et sa cathode est reliée à une première électrode d'un condensateur C. La seconde électrode du condensateur C est reliée à la masse. La première électrode du condensateur C fournit la tension Vpol. La source du transistor Tf est reliée à l'entrée négative de l'amplificateur différentiel 21.The output of the RS flip-flop 22 is connected to the gate of an NMOS transistor Tf. A resistor R is placed between the source of the transistor Tf and the ground. A coil L is placed between the drain of the transistor Tf and the supply terminal at a voltage V bat , for example at 3.3 V. The anode of a diode D f is connected to the drain of the transistor Tf and its cathode is connected to a first electrode of a capacitor C. The second electrode of the capacitor C is connected to ground. The first electrode of the capacitor C provides the voltage V pol . The source of the transistor Tf is connected to the negative input of the differential amplifier 21.

Sur un front montant du signal de l'oscillateur osc, la sortie Q de la bascule RS 22 passe au niveau haut. Le transistor Tf se ferme et la tension aux bornes de la bobine L passe rapidement de 0 à Vbat. La tension VR aux bornes de la résistance R et le courant dans la bobine L sont initialement nuls. Le courant dans la bobine L augmente progressivement, la tension VR augmente donc également. Quand la tension VR atteint le signal er de l'amplificateur différentiel 20, l'amplificateur 21 change d'état et passe au niveau haut. La sortie Q de la bascule RS 22 passe au niveau bas et le transistor Tf s'ouvre. La tension sur le drain du transistor Tf augmente brutalement. La diode Df devient passante et le condensateur C se charge. Le courant de charge est d'autant plus élevé que le courant traversant la bobine L est élevé au moment où le transistor Tf s'ouvre.On a rising edge of the osc oscillator signal, the Q output of the RS flip-flop 22 goes high. The transistor Tf closes and the voltage across the coil L passes rapidly from 0 to V bat . The voltage V R across the resistor R and the current in the coil L are initially zero. The current in the coil L increases gradually, so the voltage V R also increases. When the voltage V R reaches the signal er of the differential amplifier 20, the amplifier 21 changes state and goes high. The Q output of the RS flip-flop 22 goes low and the transistor Tf opens. The voltage on the drain of the transistor Tf increases sharply. The diode Df becomes conducting and the capacitor C is charged. The charging current is higher as the current flowing through the coil L is high when the transistor Tf opens.

Lors du front montant suivant de l'oscillateur osc, la sortie Q de la bascule RS 22 passe à nouveau au niveau haut et un cycle identique à celui précédemment décrit recommence.At the next rising edge of the oscillator osc, the Q output of the RS flip-flop 22 again goes high and a cycle identical to that previously described starts again.

Quand la tension Vo est supérieure à la tension Voref, le signal er est relativement élevée. En conséquence, le transistor Tf reste passant plus longtemps et le courant circulant dans la bobine L au moment de l'ouvertur du transistor Tf est important. Le condensateur C se charge et la tension Vpol augmente. Inversement, quand la tension Vo est inférieure à la tension Voref, la tension Vpol diminue.When the voltage V o is greater than the voltage V oref , the signal er is relatively high. As a result, the transistor Tf remains longer and the current flowing in the coil L at the moment of the opening of the transistor Tf is important. The capacitor C is charged and the voltage V pol increases. Conversely, when the voltage V o is lower than the voltage V oref , the voltage V pol decreases.

La tension de polarisation Vpol est donc ajustée en fonction des variations temporelles de la tension aux bornes des diodes électroluminescentes de l'écran.The bias voltage V pol is adjusted according to the temporal variations of the voltage across the light emitting diodes of the screen.

Un avantage du dispositif de régulation selon la présente invention est que la tension de polarisation est toujours minimale, ce qui permet de réaliser des économies d'énergie.An advantage of the control device according to the present invention is that the bias voltage is always minimal, which allows energy savings.

Un autre avantage d'un tel dispositif est que sa conception est très simple.Another advantage of such a device is that its design is very simple.

La figure 5 est un schéma de circuits de commande de colonne identiques à ceux de la figure 3 ainsi qu'un schéma d'une variante de réalisation du dispositif de régulation de la tension de polarisation Vpol qui permet de pallier au problème suivant. Quand une ligne de l'écran est "noire", c'est-à-dire qu'aucune diode électroluminescente de la ligne sélectionnée n'est conductrice, la tension Vo au point Co du circuit de régulation de la figure 3 diminue car aucune des diodes D1 à Dn n'est passante. La tension Vo diminuant, le circuit d'ajustement CR diminue la tension de polarisation Vpol. Dans le cas où un grand nombre de lignes consécutives de l'écran sont noires, la tension de polarisation Vpol peut fortement diminuer. Les diodes électroluminescentes conductrices des lignes "éclairées" risquent alors de recevoir un courant inférieur au courant de luminance. La luminosité globale de l'écran diminue.The figure 5 is a scheme of column control circuits identical to those of the figure 3 and a diagram of an alternative embodiment of the polarization voltage regulator device V pol which overcomes the following problem. When a line of the screen is "black", that is to say that no light-emitting diode of the selected line is conducting, the voltage V o at the point C o of the control circuit of the figure 3 decreases because none of the diodes D 1 to D n is passing. The voltage V o decreasing, the adjustment circuit CR decreases the bias voltage V pol . In the case where a large number of consecutive lines of the screen are black, the bias voltage V pol can greatly decrease. The light-emitting diodes conducting "lighted" lines may then receive a current lower than the luminance current. The overall brightness of the screen decreases.

Dans cette variante de réalisation, le dispositif de régulation de la tension de polarisation Vpol est identique à celui de la figure 3 excepté que le point Co est relié au circuit d'ajustement CR par l'intermédiaire d'un interrupteur 31. De plus, un condensateur 32 est placé entre l'entrée du circuit d'ajustement CR et la masse. L'interrupteur 31 est commandé de façon à être non passant quand une ligne de l'écran est noire, c'est-à-dire quand aucune diode électroluminescente de la ligne sélectionnée n'est conductrice. Le condensateur 32 conserve la valeur de la tension Vo correspondant à la dernière ligne non noire. Le dispositif de commande de l'interrupteur, non représenté, analyse le signal de colonne φC pour savoir si au moins une colonne est sélectionnée et donc qu'au moins une diode est conductrice. De plus, selon un mode de réalisation plus perfectionné, le dispositif de commande de l'interrupteur analyse les signaux de commande des circuits de commande de ligne de façon à rendre passant l'interrupteur 31 une fois que les tensions des colonnes sélectionnées sont passées de leurs tensions de précharge à leurs tensions de "fonctionnement" correspondant aux tensions induites par chacune des diodes électroluminescentes conductrices.In this variant embodiment, the device for regulating the bias voltage V pol is identical to that of the figure 3 except that the point C o is connected to the adjustment circuit CR via a switch 31. In addition, a capacitor 32 is placed between the input of the adjustment circuit CR and the ground. Switch 31 is controlled to be off when a line of the screen is black, i.e. when no light emitting diode of the selected line is conductive. The capacitor 32 retains the value of the voltage V o corresponding to the last non-black line. The control device of the switch, not shown, analyzes the column signal φ C to know if at least one column is selected and therefore that at least one diode is conductive. In addition, according to a more advanced embodiment, the control device of the switch analyzes the control signals of the line control circuits so as to turn on the switch 31 once the voltages of the selected columns have changed from their precharge voltages to their "operating" voltages corresponding to the voltages induced by each of the conductive light emitting diodes.

Un avantage d'un tel dispositif de régulation est qu'il permet d'ajuster la tension de polarisation Vpol en fonction des caractéristiques des diodes électroluminescentes de l'écran quel que soit le nombre de lignes noires consécutives de l'écranAn advantage of such a control device is that it makes it possible to adjust the bias voltage V pol as a function of the characteristics of the light-emitting diodes of the screen regardless of the number of consecutive black lines of the screen

La figure 6 est un schéma d'un mode de réalisation de l'amplificateur d'erreur 20 du circuit d'ajustement CR de la figure 4 qui permet de pallier au problème suivant. Lorsque l'écran ou les circuits de commande de colonnes ou de lignes comprennent un défaut de fabrication ou un défaut "d'usure" correspondant à une coupure entre une diode électoluminescente et une colonne ou une ligne, la tension Vo peut être très proche de la tension de polarisation Vpol. Un tel défaut conduit non seulement à une augmentation démesurée de la tension de polarisation Vpol mais aussi à des surtensions susceptibles entre autre de détériorer le circuit d'ajustement CR. Dans le cas d'un défaut d'usure, il peut être intéressant de détecter le défaut afin d'éviter de détériorer le reste du circuit et d'éviter d'augmenter la consommation électrique pour fournir une tension Vpol élevée. La détection d'un défaut de fabrication permet de détecter les circuits défaillant avant leur commercialisation.The figure 6 is a diagram of an embodiment of the error amplifier 20 of the CR adjustment circuit of the figure 4 which makes it possible to overcome the following problem. When the screen or the control circuits of columns or lines comprise a manufacturing defect or a "wear" defect corresponding to a cutoff between an electroluminescent diode and a column or line, the voltage V o can be very close to the bias voltage V pol . Such a fault leads not only to a disproportionate increase in the bias voltage V pol but also to overvoltages likely among other things to damage the adjustment circuit CR. In the case of a wear defect, it may be interesting to detect the fault in order to avoid damaging the rest of the circuit and to avoid increasing the power consumption to provide a high voltage V pol . The detection of a manufacturing defect makes it possible to detect the faulty circuits before their marketing.

L'amplificateur d'erreur représenté en figure 6 comprend deux transistors PMOS 40 et 41 dont les grilles reçoivent respectivement les tensions Vo et Voref du dispositif de régulation représenté en figure 3. Deux sources de courant identiques 42 et 43 sont placées entre la tension de polarisation Vpol et les sources des transistors 40 et 41. Une résistance R1 est placée entre les sources des transistors 40 et 41. Les drains des transistors 40 et 41 sont reliés à un dispositif de conversion 44 qui fournit le signal d'erreur er. Un transistor PMOS 45 est placé en parallèle sur le transistor 40. La source du transistor 45 est connectée à la source du transistor 40 et le drain du transistor 45 est connecté au drain du transistor 40. La grille du transistor 45 reçoit une tension "de protection" Vprotect qui est fournie par un dispositif non représenté. La tension de protection Vprotect correspond à la tension Vo maximale correspondant à un fonctionnement correct de l'écran et des circuits de commande de colonne et de ligne.The error amplifier represented in figure 6 comprises two PMOS transistors 40 and 41 whose gates respectively receive the voltages V o and V oref of the control device represented in FIG. figure 3 . Two identical current sources 42 and 43 are placed between the bias voltage V pol and the sources of the transistors 40 and 41. A resistor R1 is placed between the sources of the transistors 40 and 41. The drains of the transistors 40 and 41 are connected to a conversion device 44 which provides the error signal er. A PMOS transistor 45 is placed in parallel on the transistor 40. The source of the transistor 45 is connected to the source of the transistor 40 and the drain of the transistor 45 is connected to the drain of the transistor 40. The gate of the transistor 45 receives a voltage of protection V protect which is provided by a device not shown. The protective voltage V protect corresponds to the maximum voltage V o corresponding to correct operation of the screen and the column and line control circuits.

En fonctionnement normal, sans défaut du circuit, la tension Vo est inférieure à la tension de protection Vprotect. Les transistors 40, 41 et 45 sont tels que lorsqu'ils conduisent un courant égal à celui fourni par les sources de courant 42 et 43, leurs tensions grille-source est sensiblement égale à la tension de seuil d'un transistor PMOS. Ainsi, quand la tension Vo est inférieure à la tension Vprotect, le transistor 45 est non conducteur. De même, lorsque les tensions Vo et Voref sont différentes les tensions sur les sources des transistors 40 et 41 sont différentes. La résistance R1 est alors traversée par un courant qui est d'autant plus élevé que l'écart entre les tensions Vo et Voref est élevé. Le dispositif de conversion 44 analyse les différences de courant dans les transistors 40 et 41 et fournit un signal d'erreur er d'autant plus élevé que le courant dans le transistor 40 est faible par rapport au courant dans le transistor 41 et inversement.In normal operation, without circuit fault, the voltage V o is lower than the protection voltage V protect . The transistors 40, 41 and 45 are such that when they conduct a current equal to that supplied by the current sources 42 and 43, their gate-source voltages is substantially equal to the threshold voltage of a PMOS transistor. Thus, when the voltage V o is lower than the voltage V protect , the transistor 45 is non-conductive. Similarly, when voltages V o and V oref are different the voltages on the sources of transistors 40 and 41 are different. The resistance R1 is then crossed by a current which is higher as the difference between the voltages V o and V oref is high. The conversion device 44 analyzes the current differences in the transistors 40 and 41 and provides an error signal er which is all the greater as the current in the transistor 40 is small relative to the current in the transistor 41 and vice versa.

Dans le cas où le circuit présente un défaut, la tension Vo peut être très proche de la tension de polarisation Vpol. Lorsque la tension Vo dépasse la tension de protection Vprotect, le transistor 45 devient conducteur et le transistor 40 non conducteur. La tension de polarisation Vpol est alors maximale. La valeur maximale de la tension Vpol dépend du choix de la tension Vprotect et de la tension Voref qui est fonction du courant de luminance souhaité. La présence du transistor 45 permet d'assurer que la tension de polarisation Vpol ne dépasse pas une valeur maximale donnée et permet en outre de supprimer des surtensions éventuelles susceptibles d'endommager le circuit d'ajustement CR.In the case where the circuit has a fault, the voltage V o can be very close to the bias voltage V pol . When the voltage V o exceeds the protection voltage V protect , the transistor 45 becomes conductive and the transistor 40 is non-conductive. The bias voltage V pol is then maximal. The maximum value of the voltage V pol depends on the choice of the voltage V protect and the voltage V oref which is a function of the desired luminance current. The presence of the transistor 45 makes it possible to ensure that the bias voltage V pol does not exceed a given maximum value and also makes it possible to eliminate any overvoltages that may damage the adjustment circuit CR.

Bien entendu, la présente invention est susceptible de diverses variantes et modifications qui apparaîtront à l'homme de l'art. En particulier, on pourra prévoir d'autres dispositifs d'évaluation du courant circulant dans les diodes électroluminescentes de l'écran ainsi que d'autres dispositifs d'ajustement de la tension de polarisation Vpol en fonction des différences entre le courant de luminance souhaité et le plus petit courant traversant les diodes électroluminescentes de l'écran. On pourra notamment utiliser d'autres convertisseurs de tension DC-DC capables de fournir une tension de polarisation Vpol élevée quand le signal d'erreur er est élevé et inversement. En outre, l'homme de l'art saura réaliser un miroir de courant différent de celui décrit, en utilisant par exemple deux transistors par branche.Of course, the present invention is susceptible of various variations and modifications which will be apparent to those skilled in the art. In particular, it is possible to provide other devices for evaluating the current flowing in the light-emitting diodes of the screen as well as other devices for adjusting the bias voltage V pol as a function of the differences between the desired luminance current. and the smallest current flowing through the light-emitting diodes of the screen. It will be possible in particular to use other DC-DC voltage converters capable of supplying a high pol bias voltage V when the error signal is high and Conversely. In addition, one skilled in the art will realize a current mirror different from that described, for example using two transistors per branch.

Claims (8)

  1. A device for regulating the biasing voltage (Vpol) of column control circuits of a screen array made of LEDs, each coupled to one of the lines and one of the columns of the screen, the column control circuits comprising a current mirror having a reference branch (bref) and several duplication branches (b1 to bn), all the branches being coupled to the biasing voltage (Vpol), each duplication branch (bi) being coupled to a column (Ci) of the screen through a column select circuit (11), the reference branch being connected at a reference node (Cref) to a reference current source (10) providing a desired luminance current (I1), said device being characterized in that it comprises:
    first measuring means (D1 to Dn and 15) arranged for providing a first signal (VO) representative of the voltage of the column at the highest potential;
    second measuring means (Dref and 16) arranged for providing a second signal (Voref) representative of the voltage (Vref) of the reference node (Cref); and
    an adjustment circuit (CR) arranged for receiving the first signal (Vo) and the second signal (Voref) and being adapted to increase the biasing voltage (Vpol) when the first signal (Vo) is larger than the second signal (Voref), which means that the current in at least one of the columns of the screen is lower than the desired luminance current (I1), and adapted to reduce the biasing voltage (Vpol) when the first signal (VO) is lower than the second signal (Voref) , which means that the desired luminance current (I1) flows in all the selected columns but that the biasing voltage (Vpol) is too large.
  2. The device of claim 1, wherein each branch (bi) of the current mirror includes a PMOS field effect transistor (Pi), having a source connected to the biasing voltage, the gates of each branch being connected together, the drain and the gate of the transistor of the reference branch being connected to the reference current source (10), the drains of the transistors of the duplication branches being connected to the columns (C1 to Cn).
  3. The device of claim 1, wherein said first measuring means comprise for each column (Ci) a diode (Di) having an anode connected to the column (Ci) and having a cathode connected to a first observation current source (15) and to a first input of the adjustment circuit, and wherein the second measuring means comprise a diode (Dref) having an anode connected to the reference node and a cathode connected to a second observation current source (16) and to a second input of the adjustment circuit.
  4. The device of claim 3, wherein the cathodes of each diode (Di) are coupled to the first input of the adjustment circuit by a switch (31), a capacitor (32) being connected between the first input of the adjustment circuit (CR) and a fixed voltage node.
  5. The device of claim 3, wherein the adjustment circuit comprises an error amplifier (20) receiving the first signal on a positive input and receiving the second signal on a negative input, an output of error amplifier (er) being connected to a D.C./D.C. voltage converter outputting the biasing voltage (Vpol) and being adapted to increase the biasing voltage (Vpol) when the first signal is higher than the second signal and conversely.
  6. The device of claim 5, wherein error amplifier (20) comprises first and second PMOS transistors (40, 41) having their gates respectively connected to positive and negative inputs of the error amplifier, the source of each one of the first and second transistors being coupled to the biasing voltage (Vpol) by a current source (42, 43), the sources of first and second transistors being coupled by a resistor (R1), the drains of first and second transistors being connected to a converter (44) providing the error signal, the source and drain of a third PMOS transistor (45) being connected to the source and drain of the first transistor (40), the gate of the third transistor being biased at a fixed voltage (Vprotect).
  7. A method for regulating the biasing voltage (Vpol) of column control circuits of a screen array made of LEDs, each coupled to one of the lines and one of the columns of the screen, the column control circuits comprising a current mirror having a reference branch (bref) and several duplication branches (b1 to bn), all the branches being coupled to the biasing voltage (Vpol), each duplication branch (bi) being coupled to a column (Ci) of the screen through a column select circuit (11), the reference branch being connected at a reference node (Cref) to a reference current source (10) providing a desired luminance current (I1), said method being characterized in that it comprises the following steps:
    - providing through first measuring means (D1 to Dn and 15) a first signal (VO) representative of the voltage of the column at the highest potential;
    - providing through second measuring means (Dref and 16) a second signal (Voref) representative of the voltage (Vref) at the reference node (Cref); and
    - increasing the biasing voltage (Vpol) when the first signal (VO) is higher than the second signal (Voref), which means that the current in at least one of the columns of the screen is lower than the desired luminance current (I1), and reducing the biasing voltage (Vpol) when the first signal (VO) is lower than the second signal (Voref), which means that the desired luminance current (I1) flows in all the selected columns but that the biasing voltage (Vpol) is too large.
  8. The method of claim 7, wherein the first signal is an image of the voltage on the column at the higher potential shifted by a diode threshold voltage.
EP03300065A 2002-07-19 2003-07-17 Automatic adaptation of the supply voltage of an electroluminescent panel depending on the desired luminance Expired - Fee Related EP1383103B1 (en)

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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1675673B (en) * 2002-08-21 2010-05-05 皇家飞利浦电子股份有限公司 Display device
CN100405442C (en) * 2004-09-23 2008-07-23 普诚科技股份有限公司 Luminous dipolar body panel driving circuit having electric current compensation function
FR2879007A1 (en) * 2004-12-06 2006-06-09 St Microelectronics Sa AUTOMATIC ADAPTATION OF THE PRELOADING VOLTAGE OF AN ELECTROLUMINESCENT SCREEN
FR2879008A1 (en) * 2004-12-06 2006-06-09 St Microelectronics Sa AUTOMATIC ADAPTATION OF THE POWER SUPPLY VOLTAGE OF AN ELECTROLUMINESCENT SCREEN IN ACCORDANCE WITH THE DESIRED LUMINANCE
KR100636502B1 (en) * 2005-08-31 2006-10-18 삼성에스디아이 주식회사 Organic electro luminescence display for performing sheet unit test and testing method using the same
JP4809030B2 (en) * 2005-09-28 2011-11-02 株式会社リコー DRIVE CIRCUIT AND ELECTRONIC DEVICE USING THE DRIVE CIRCUIT
US20070088603A1 (en) * 2005-10-13 2007-04-19 Jouppi Norman P Method and system for targeted data delivery using weight-based scoring
TWI342542B (en) * 2006-03-27 2011-05-21 Himax Tech Inc Source driver for display and method of driving thereof
JP2008102404A (en) * 2006-10-20 2008-05-01 Hitachi Displays Ltd Display device
JP2008191353A (en) * 2007-02-05 2008-08-21 Oki Electric Ind Co Ltd Image display and its display method
GB2461916B (en) * 2008-07-18 2013-02-20 Cambridge Display Tech Ltd Balancing common mode voltage in a current driven display
KR101034690B1 (en) * 2009-09-02 2011-06-13 삼성모바일디스플레이주식회사 Organic Light Emitting Display Device and Driving Method Thereof
TW201345309A (en) * 2012-04-20 2013-11-01 Raydium Semiconductor Corp Driving circuit
CN103854596A (en) * 2012-11-29 2014-06-11 利亚德光电股份有限公司 Led display
CN103854597B (en) * 2012-11-29 2016-08-10 利亚德光电股份有限公司 Light-emitting diode display and LED control system
CN103018531B (en) * 2012-12-11 2015-04-08 京东方科技集团股份有限公司 Current detection circuit, temperature compensation device and display device

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB932173A (en) * 1960-05-23 1963-07-24 Gen Precision Inc Sub-miniature gyro
CA1319767C (en) * 1987-11-26 1993-06-29 Canon Kabushiki Kaisha Display apparatus
ATE151902T1 (en) 1992-05-19 1997-05-15 Canon Kk METHOD AND DEVICE FOR CONTROLLING A DISPLAY
US5594463A (en) 1993-07-19 1997-01-14 Pioneer Electronic Corporation Driving circuit for display apparatus, and method of driving display apparatus
US5708391A (en) * 1996-05-02 1998-01-13 Altmann; Michael High frequency differential filter with CMOS control
US5684368A (en) * 1996-06-10 1997-11-04 Motorola Smart driver for an array of LEDs
DE69825402T2 (en) * 1997-03-12 2005-08-04 Seiko Epson Corp. PIXEL CIRCUIT, DISPLAY DEVICE AND ELECTRONIC APPARATUS WITH POWER-CONTROLLED LIGHT-EMITTING DEVICE
JP3049061B1 (en) * 1999-02-26 2000-06-05 キヤノン株式会社 Image display device and image display method
JPH11272223A (en) 1998-03-26 1999-10-08 Toyota Motor Corp Power unit for light emissive display
US6628247B2 (en) * 1998-04-27 2003-09-30 Lear Automotive Dearborn, Inc. Display system with latent image reduction
JP2000347613A (en) 1999-06-03 2000-12-15 Mitsubishi Electric Corp Driving circuit for light emitting diode
US6259615B1 (en) * 1999-07-22 2001-07-10 O2 Micro International Limited High-efficiency adaptive DC/AC converter
JP2001042827A (en) * 1999-08-03 2001-02-16 Pioneer Electronic Corp Display device and driving circuit of display panel
JP2001331162A (en) 2000-05-19 2001-11-30 Mitsubishi Electric Corp Display controller
TW561445B (en) * 2001-01-02 2003-11-11 Chi Mei Optoelectronics Corp OLED active driving system with current feedback
SG107573A1 (en) * 2001-01-29 2004-12-29 Semiconductor Energy Lab Light emitting device
TWI248319B (en) * 2001-02-08 2006-01-21 Semiconductor Energy Lab Light emitting device and electronic equipment using the same
WO2003034384A2 (en) * 2001-10-19 2003-04-24 Clare Micronix Integrated Systems, Inc. Method and system for precharging oled/pled displays with a precharge latency
US6774723B2 (en) * 2002-01-25 2004-08-10 Analog Devices, Inc. Output stage with stable quiescent current
GB2389952A (en) * 2002-06-18 2003-12-24 Cambridge Display Tech Ltd Driver circuits for electroluminescent displays with reduced power consumption

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