DE202016102722U1 - Converter arrangement - Google Patents

Abstract

A converter arrangement (1) having an upper bridge branch disposed between a positive input terminal (+) and a center tap (0) and a lower bridge branch disposed between a negative input terminal (-) and the center tap (0), wherein the upper bridge branch has at least two controlled upper semiconductor elements (T1, T2) and the lower bridge branch has at least two controlled lower semiconductor elements (T3, T4), characterized in that in each of the two bridge branches the controlled semiconductor elements (T1, T2; T3, T4) with maximum overlap (z) are arranged parallel to each other.

Description

The present invention relates to an inverter arrangement having an upper bridge branch disposed between a positive input terminal and a center tap, and a lower bridge branch disposed between a negative input terminal and the center tap, the upper bridge branch having at least two controlled upper semiconductor elements lower bridge branch has at least two controlled lower semiconductor elements.

Such a converter arrangement is for example off DE 10 2010 008 426 B4 known.

Such a converter arrangement generates, for example, an AC voltage from a DC voltage. There are three voltage levels available, namely the positive input voltage, the negative input voltage and a voltage at the center tap or zero point. The AC voltage is then generated by a controlled switching of the controlled semiconductor elements.

Known converter topologies for such three-stage inverters are known as NPC1 and NPC2.

A converter arrangement is usually provided for one phase. If a multiphase system is to be fed, three such converter arrangements are needed.

By the controlled switching of the respective semiconductor elements, the current changes. A current change over time together with an inductance leads to a voltage, which in turn leads to losses.

The invention has for its object to provide an inverter with a low-inductance design.

This object is achieved in a converter arrangement of the type mentioned above in that the controlled semiconductor elements with maximum overlap are arranged side by side in each of the two bridge arms the controlled semiconductor elements.

A current change in a conductor creates an electric field. This field induces a current in a parallel conductor. This current causes a reduction in the inductance of the entire conductor loop. The semiconductor elements are now arranged so that they form such a conductor loop in a bridge branch. As a result, the inductance can be kept small. The larger the overlap between the semiconductors, the smaller the area within the conductor loop. The smaller this area can be held, the smaller the induced inductance can be kept. Thus, then the inductance of the entire circuit can be kept small. The distance between the controlled semiconductor elements depends on the circumstances. In particular, at higher currents of several tens or even more than 100 A, a distance may be necessary which allows sufficient heat dissipation. In this case, there is a minimum distance, for example of the order of 10 mm. The overlap takes place in such a way that, viewed in the direction of the current flow, an overlap region results. Perpendicular to the direction of the current flow, therefore, the two controlled semiconductor elements overlap.

Preferably, the two controlled semiconductor elements have an overall extension and a quotient between the overlap and the total extension is ≥ 0.1, in particular ≥ 0.6. The "total extension" is to be seen in the direction of the current flow from the end of a controlled semiconductor element to the opposite end of the other controlled semiconductor element.

Preferably, a maximum of one uncontrolled semiconductor element is arranged between the controlled semiconductor elements of a bridge branch. It can therefore be provided that a diode, which is used as a freewheeling diode, is arranged between the controlled semiconductor elements, without in this case appreciably increasing the inductance. This diode serves to take over current during the commutation and thus creates a path through which the inducing current or the induced current can flow.

Preferably, the controlled semiconductor elements are arranged in the same flow direction in each bridge branch. In the commutation then, in simple terms, one semiconductor element takes over the current from the other semiconductor element, so that the current through one semiconductor element decreases and increases through the other semiconductor element. The currents induced thereby influence each other positively.

Preferably, the controlled upper semiconductor elements are disposed on a common first substrate, and the controlled lower semiconductor elements are disposed on a common second substrate, and the first substrate and the second substrate are separated from each other. Thus, the switching functions of the converter arrangement are split into two subfunctions, and these subfunctions are also spatially separated from one another. In other words, so the upper bridge branch on a first substrate and the lower bridge branch is arranged on a second substrate. This can be achieved in a simple manner, a spatial separation of the two switching functions, so that a mutual influence of the upper bridge branch and the lower bridge branch does not adversely affect the inductance of the inverter assembly.

It is preferred that the first substrate and the second substrate are arranged on a common carrier. It is then possible to provide the respective connections, which are necessary for the supply and removal of the electrical energy and for the connection of control lines, on a single carrier.

Preferably, the upper bridge branch has at least two groups of controlled upper semiconductor elements connected in parallel, and the lower bridge branch has at least two groups of controlled lower semiconductor elements connected in parallel. Thus, the performance of the converter assembly can be dimensioned according to specifications practically arbitrary, without having to use each semiconductor elements that are designed for correspondingly high currents. Rather, one can switch several semiconductor element groups in parallel, which then each have to carry only a part of the current.

Preferably, at least two groups of each bridge branch are arranged on separate substrates. This facilitates the production. In this case, there are then a corresponding number of first substrates and a corresponding number of second substrates.

Preferably, controlled semiconductor elements disposed on like substrates have a distance from each other that is smaller than a distance between controlled semiconductor elements disposed on different substrates. The substrates may be formed for example by DCBs. These substrates are then arranged relative to one another in such a way that the coupling in of one substrate affects the adjacent substrate of the same type. However, a corresponding influence on first substrates and second substrates, ie substrates of the upper bridge branch and substrates of the lower bridge branch, is avoided by this arrangement.

Preferably, the carrier has upper control terminals for the controlled upper semiconductor elements and lower control terminals for the controlled lower semiconductor elements, wherein connections of the controlled upper semiconductor elements with the upper control terminals extend without intersection to connections of the controlled lower semiconductor elements with the lower control terminals. Thus, it is possible to use topologies for the upper bridge branch and the lower bridge branch, in which a plurality of semiconductor elements are connected in parallel without the drive signals crossing, more precisely the lines for the drive signals. The crossing of such lines could lead to different switching functions being controlled differently and uncontrolled states or oscillations could arise. This is prevented by the crossing-free guidance of the connections.

Preferably, the controlled upper semiconductor elements comprise a first controlled upper semiconductor element and a second controlled upper semiconductor element, and the upper control terminals have a first upper control terminal and a second control terminal, wherein a connection between the first controlled upper semiconductor element and the first upper control terminal without intersection Connection between the second controlled upper semiconductor element and the second upper control terminal extends. Here, too, the intersection-free guidance of the connections avoids interference due to mutual interference.

It is also preferable that the controlled lower semiconductor elements have a controlled first lower semiconductor element and a second controlled lower semiconductor element and the lower control terminals have a first lower control terminal and a second lower control terminal, wherein a connection between the first controlled lower semiconductor element and the first lower control terminal passes without intersection to a connection between the second controlled lower semiconductor element and the second lower control terminal. The same applies to the lower bridge branch as to the upper bridge branch.

Preferably, an imaginary line between the individual controlled semiconductor elements forms a comb-shaped structure. This is especially true when using multiple sets of controlled upper semiconductor elements or controlled lower semiconductor elements.

Preferably, the controlled semiconductor elements are formed as a transistor, IGBT or MOSFET. The semiconductor elements can therefore be designed as switches, which can be controlled by control signals.

Preferably, diodes are assigned to the controlled semiconductor elements. The diodes can then, for example, after the Turn off the controlled semiconductor elements take over the respective current.

The invention will be described below with reference to preferred embodiments in conjunction with the drawing. Herein show:

1 a circuit arrangement of a first embodiment of a converter arrangement,

2 A second embodiment of a circuit arrangement of a converter arrangement,

3 a schematic representation of the arrangement of elements of the inverter arrangement according to 1 .

4 a schematic representation of the arrangement of elements of the inverter arrangement according to 2 .

5 a schematic representation of the arrangement of elements of the inverter arrangement according to 2 in a modified embodiment and

6 a schematic representation for explaining the overlap.

1 schematically shows a circuit arrangement of a first embodiment of a converter arrangement 1 with an upper bridge branch disposed between a positive input terminal + and a center tap 0, and a lower bridge branch disposed between a negative input terminal - and the center tap.

The upper bridge branch has a first controlled upper semiconductor element T1 and a second controlled upper semiconductor element T2. The lower bridge branch has a first controlled lower semiconductor element T4 and a second controlled lower semiconductor element T3. The controlled semiconductor elements T1-T4 may be formed as transistors, as IGBTs, as MOSFETs or the like. The controlled semiconductor elements should be able to handle currents that are on the order of 100 A or more.

Antiparallel to the first controlled upper semiconductor element, a diode D1 is arranged and antiparallel to the second controlled upper semiconductor element, a diode D2 is arranged. Between the middle tap 0 and a point 2 between the two upper controlled semiconductor elements T1, T2, a diode D5 is arranged, whose forward direction of the middle tap 0 points away. In the lower bridge branch, a first controlled lower semiconductor element T4 and a second controlled lower semiconductor element T3 are arranged between the AC output AC and the negative input terminal. A diode D4 is connected in parallel with the first lower controlled semiconductor element T4, and a diode D3 is connected in antiparallel to the second lower controlled semiconductor element T3. Between a point 3 between the two controlled lower semiconductor elements T3, T4 and the center tap 0, a diode D6 is arranged, whose forward direction is directed to the center tap 0.

The controlled semiconductor elements T1-T4 are operated as electronic switches. In the 1 The converter arrangement shown is also described as "NPC1" topology. Other names are "I-Type" or "NPC". It is a three level inverter known per se.

1a shows here the complete topology of the inverter arrangement 1 ,

It is provided in this embodiment, to separate the upper bridge branch and the lower bridge branch from each other and to physically arrange the respective semiconductor elements of the two bridge branches on different substrates, as will be described below. This division is in the 1b and 1c shown.

2a shows another topology of a converter arrangement 1 , which is referred to as the "NPC2" topology. Other designations include T-type, MPC, "mixed voltage NPC" or "bi-directional switch NPC". Also this inverter arrangement 1 has an upper bridge branch, in which between a positive input terminal + and a change per output AC, a first upper controlled semiconductor element T1 and a second controlled semiconductor element T2 are connected in series.

In the upper bridge branch, a diode D1 is arranged antiparallel to the first controlled upper semiconductor element T1. In series with the second controlled lower semiconductor element T2, a diode D2 is arranged. Similarly, in the lower bridge branch, a diode D4 is arranged in antiparallel to the first controlled lower semiconductor element T4, and a diode D3 is connected in series with the second lower controlled semiconductor element T3.

Again, you can, as in the 2 B and 2c a division into the lower bridge branch ( 2 B ) and in the upper bridge branch ( 2c ) and physically separate the two bridge branches.

3 shows the physical arrangement of the individual semiconductor elements of the inverter assembly 1 to 1 , Same elements as in 1 are provided with the same reference numerals.

The upper semiconductor controlled elements T1, T2 are on a first substrate 4 arranged. The lower controlled semiconductor elements T3, T4 are on a second substrate 5 arranged.

Each bridge branch has in the present embodiment, three parallel groups of controlled semiconductor elements T1, T2; T3, T4 up. It can be seen that the substrates 4 . 5 are separated from each other, so that the two different bridge arms can also be arranged physically separated from each other.

On every substrate 4 . 5 are the controlled semiconductor elements T1, T2; T4, T3 with minimum distance parallel to each other, which will be explained in more detail below. Between the controlled semiconductor elements T1, T2; T4, T3 is a maximum uncontrolled semiconductor element, namely the diode D1, D4 arranged.

An imaginary line, shown in dashed lines and extending between the individual controlled semiconductor elements T1-T4, forms a comb-shaped structure.

The substrates 4 . 5 are on a common carrier 6 arranged.

4 shows a corresponding arrangement of the semiconductor elements in the embodiment of the circuit according to 2 , The NPC2 topology requires two fewer diodes than the NPC1 topology 1 ,

Again, the semiconductor elements T1, T2, D1, D2 of the upper bridge branch on a first substrate 4 arranged and the semiconductor elements T3, T4, D3, D4 of the lower bridge branch are on a second substrate 5 arranged. Again, there are again three parallel groups of semiconductor elements T1, T2, D1, D2; T3, T4, D3, D4 for the upper and the lower bridge branch, so that the individual semiconductor elements must each be designed for only one third of the maximum current.

On the carrier 6 Furthermore, control terminals are shown, namely a first upper control terminal G1 for the first controlled upper semiconductor elements T1, a second control terminal G2 for the second controlled upper semiconductor elements T2, a control terminal G4 for the first controlled lower semiconductor elements T4 and a fourth control terminal G3 for the second controlled lower semiconductor elements T3.

It can be seen that firstly the connections of the controlled upper semiconductor elements T1, T2 with the upper control terminals G1, G2 extend without intersection to the connections between the connections of the controlled lower semiconductor elements T4, T3 with the lower control terminals G4, G3. In addition, it can be seen that the connections between the control terminals and the controlled semiconductor elements also run without intersection in each bridge branch. The connection between the first upper control terminal G1 and the first controlled upper semiconductor element T1 extends without intersection to the connection between the second upper control terminal G2 and the second controlled upper semiconductor elements T2. Accordingly, a connection between the first lower control terminal G4 and the first controlled lower semiconductor elements T4 is seamlessly connected to connections between the second lower control terminal G3 and the second controlled lower semiconductor elements T3.

Again, a phantom drawn imaginary line between the individual controlled semiconductors forms a comb-shaped structure.

Also in the arrangement 4 are the controlled semiconductor elements T1, T2; T3, T4 in each of the two bridge branches with a minimum distance parallel to each other. It is at most a diode D1; D4, ie an uncontrolled semiconductor element, between the two controlled semiconductor elements T1, T2; T3, T4 provided.

In the arrangement according to 4 have the semiconductor elements T1, T2, which are on the same substrate 4 are arranged at a distance from one another which is smaller than a distance between semiconductor elements T3, T4, on the other substrate 5 are arranged.

The distance between controlled semiconductor elements T1, T2; For example, T3, T4 on a substrate may be on the order of 10 mm, while a spacing between semiconductor elements T1, T4 on different substrates 4 . 5 are arranged, may be on the order of 15 mm.

5 shows a modified embodiment of the semiconductor elements according to the circuit arrangement of 2 , Here are the controlled semiconductor elements T1, T2; T3, T4 even closer adjacent than in the embodiment of 4 , The connections between control terminals and the controlled semiconductor elements T1-T4 is for reasons of Overview omitted. On the other hand, the imaginary line between the semiconductor elements T1-T4, which in turn forms a comb-like structure, is shown by dashed lines.

The function is based on the leftmost substrate in 5 be explained.

It is assumed that at a certain time, the first controlled lower semiconductor element T4 conducts, so that a current flows from the AC output AC to the negative input terminal.

At a later time, the first controlled lower semiconductor element T4 is turned off and the second lower controlled semiconductor element T3 conducts, so that the current flows from the AC output AC to the center tap 0. Between these two times, the current through the first controlled lower semiconductor element T4 decreases and the current through the second controlled semiconductor element T3 increases. Both semiconductor elements T3, T4 are arranged with the same passage directions.

The change in current over time (di / dt) and the area in the loop between the first controlled lower semiconductor element T4 and the second controlled lower semiconductor element T3 are critical to the inductance of the device. The smaller this area, the smaller the inductance of the circuit is kept.

A current change in a conductor creates an electric field. This field induces a current in a parallel conductor. This current causes a reduction in the inductance of the entire conductor loop, which is formed by a connection of the two controlled lower semiconductor elements T3, T4 via the AC terminal AC.

The same effect also acts across substrates, ie the current change in the second controlled lower semiconductor element T3 affects the first controlled lower semiconductor element T4 of the adjacent substrate 5 accordingly. Accordingly, the inductance of the circuit arrangement can also be kept low by this overarching effect.

6 shows a schematic representation for explaining the overlap of the controlled semiconductor elements. The same elements as in the preceding drawings are provided with the same reference numerals.

Shown are the semiconductor elements T3, T4, which are arranged between the AC terminal AC and the negative input terminal minus and the center tap 0, respectively. The "conductor loop" which is "spanned" by the controlled semiconductor elements T3, T4 is shown hatched.

"Y" denotes the maximum extent of the controlled semiconductor elements T3, T4. The maximum extension is the length between the end of the one semiconductor controlled element T3 and the opposite end of the other semiconductor controlled element T4.

Furthermore, the overlap is indicated by "z". The overlap is the distance between the other two ends of the controlled semiconductor elements T3, T4, in other words, the coverage between the controlled semiconductor elements T3, T4 when viewed perpendicular to the direction of current flow. The current flow is always between the AC output AC and the negative input terminal - or the center tap 0.

An optimal size of the hatched loop shown can be influenced in two ways. On the one hand, one can minimize the distance "x" perpendicular to the direction of the current flow. On the other hand, it is also possible to minimize the extension of the controlled semiconductor elements T3, T4. This extension can be prevented by making the overlap small. Therefore one chooses the overlap so that
z ≥ 0.1 · y
Preferably one chooses the overlap z such that
z ≥ 0.6 · y.

The overlap is thus at least 10%, preferably at least 60% of the extent y. In this way, the size of the conductor loop, which is decisive for the inductance of the circuit arrangement, can be kept small.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 102010008426 B4 [0002]

Claims (15)

Inverter arrangement ( 1 ) having an upper bridge branch disposed between a positive input terminal (+) and a center tap (0) and a lower bridge branch disposed between a negative input terminal (-) and the center tap (0), the upper bridge branch being at least two controlled upper semiconductor elements (T1, T2) and the lower bridge branch has at least two controlled lower semiconductor elements (T3, T4), characterized in that in each of the two bridge branches the controlled semiconductor elements (T1, T2, T3, T4) with maximum overlap (Z) are arranged parallel to each other. Converter arrangement according to claim 1, characterized in that the two controlled semiconductor elements have an overall extension (y) and a quotient between the overlap (z) and the total extension y ≥ 0.1, in particular ≥ 0.6. Converter arrangement according to Claim 1 or 2, characterized in that a maximum of one uncontrolled semiconductor element (D1, D4) is arranged between the controlled semiconductor elements (T1, T2; T3, T4) of a bridge branch. Converter arrangement according to one of Claims 1 to 3, characterized in that the controlled semiconductor elements (T1, T2, T3, T4) are arranged in the same flow direction in each bridge branch. Converter arrangement according to one of claims 1 to 4, characterized in that the controlled upper semiconductor elements (T1, T2) on a common first substrate ( 4 ) are arranged and the controlled lower semiconductor elements (T3, T4) on a common second substrate ( 5 ) and the first substrate ( 4 ) and the second substrate ( 5 ) are separated from each other. Converter arrangement according to claim 5, characterized in that the first substrate ( 4 ) and the second substrate ( 5 ) on a common carrier ( 6 ) are arranged. Converter arrangement according to one of Claims 1 to 6, characterized in that the upper bridge branch has at least two groups of controlled upper semiconductor elements (T1, T2) connected in parallel and the lower bridge branch has at least two groups of controlled lower semiconductor elements (T3, T4) connected in parallel , Inverter arrangement according to claim 7, characterized in that at least two groups of each bridge branch on separate substrates ( 4 . 5 ) are arranged. Converter arrangement according to claim 7 or 8, characterized in that controlled semiconductor elements, which are arranged on the same substrates, have a distance from one another which is smaller than a distance between controlled semiconductor elements, which are arranged on different substrates. Converter arrangement according to one of Claims 6 to 9, characterized in that the carrier ( 6 ) upper control terminals (G1, G2) for the controlled upper semiconductor elements (T1, T2) and lower control terminals (G3, G4) for the controlled lower semiconductor elements (T3, T4), wherein connections of the controlled upper semiconductor elements (T1, T2) with the upper control terminals (G1, G3) without crossing to connections of the controlled lower semiconductor elements (T3, T4) with the lower control terminals (G3, G4) extend. Inverter arrangement according to Claim 10, characterized in that the controlled upper semiconductor elements (T1, T2) have a first controlled upper semiconductor element (T1) and a second controlled upper semiconductor element (T2), and the upper control connections (G1, G2) have a first upper control connection ( G1) and a second upper control terminal (G2), wherein a connection between the first controlled upper semiconductor element (T1) and the first upper control terminal (G1) without crossing to a connection between the second controlled upper semiconductor element (T2) and the second upper control terminal (G2) runs. Converter arrangement according to claim 10 or 11, characterized in that the controlled lower semiconductor elements (T3, T4) have a first controlled lower semiconductor element (T4) and a second controlled lower semiconductor element (T3) and the lower control terminals (G3, G4) have a first lower one Control terminal (G4) and a second lower control terminal (G3), wherein a connection between the first controlled lower semiconductor element (T4) and the first lower control terminal (G4) without crossing to a connection between the second controlled lower semiconductor element (T3) and the second lower control terminal (G3) runs. Converter arrangement according to one of Claims 1 to 12, characterized in that an imaginary line between the individual controlled semiconductors (T1-T4) forms a comb-shaped structure. Converter arrangement according to one of claims 1 to 13, characterized in that the controlled semiconductor elements (T1-T4) are formed as a transistor, IGBT or MOSFET. Converter arrangement according to one of claims 1 to 14, characterized in that the controlled semiconductor elements (T1-T4) are each associated with diodes (D1-D4).

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