DE112012007201T5 - Maximum Power Point Tracking Controllers and associated systems and methods - Google Patents

Abstract

A maximum power point tracking controller includes an input port for electrical coupling to an electrical power source, an output port for electrical coupling to a load, a control switching device, and a control subsystem. The control switching device is adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input port to the output port. The control subsystem is adapted to control the switching of the control switching device to control a voltage across the input terminal, the control being based, at least in part, on a signal representing a current flow from the output terminal to maximize a signal, the power from the output terminal represents.

Description

background

wobei

I_L

= photovoltaischer Strom

R_S

= Serienwiderstand

R_SH

= Nebenwiderstand

I₀

= Sperrsättigungsstrom

n

= Dioden-Idealitätsfaktor (1 für eine ideale Diode)

q

= Elementarladung

k

= Boltzmann-Konstante

T

= absolute Temperatur

I

= Ausgangsstrom an Zellenklemmen

V

= Spannung an Zellenklemmen

Für Silizium bei 25 °C, kT/q = 0,0259 Volt. Photovoltaic cells generate a voltage that varies with current, cell mode, cell physics, cell defects, and cell illumination. A mathematical model for a photovoltaic cell, as in 1 represented, models the output current as follows:

in which

I _L

= photovoltaic electricity

R _S

= Series resistance

R _SH

= Shunt resistance

I ₀

= Blocking saturation current

n

= Diode ideality factor (1 for an ideal diode)

q

= Elementary charge

k

= Boltzmann constant

T

= absolute temperature

I

= Output current at cell terminals

V

= Voltage at cell terminals

For silicon at 25 ° C, kT / q = 0.0259 volts.

Typical cell output voltages are low and depend on the bandgap of the material used to make the cell. Cell output voltages may be u. just half a volt for silicon cells, far below the voltage needed to charge batteries or operate most other loads. Because of these low voltages, cells are typically connected in series to form an assembly or assembly with an output voltage that is significantly higher than that produced by an individual cell.

Photovoltaic cells in practice often have one or more microscopic defects. These cell defects can cause mismatches of series resistance R _S , shunt resistance R _SH, and photovoltaic current I _L from one cell to another in an assembly. Further, cell lighting may vary from cell to cell in a system of photovoltaic cells and even cell to cell in an assembly, eg, for reasons such as shadows of trees, shading of parts of a cell or assembly by bird droppings, dust or dirt, and others effects. These discrepancies in lighting can vary from day to day and with the time of day. A shadow may shift over an assembly during a day, and rain may wash off any dust or debris that covers a cell.

According to Eq. 1, the output voltage is greatest at output current zero and the output voltage V falls non-linearly with increasing output current I. 2 shows the effect of increasing the current drawn from a photovoltaic device under constant illumination. When the current I is increased at constant illumination, the voltage V drops slowly, but when the current I is increased to an output current approaching the photocurrent I _L , the output voltage V sharply drops. Similarly, the cell power, the product of current and voltage, increases as the current I increases until the effect of the falling voltage V is greater than the effect of increasing the current, in which case further increases in the current I, that is is removed from the cell, causes the power P decreases rapidly. For a given lighting, each cell, assembly, and array of cells and assemblies therefore has a maximum power point (MPP) representing the combination of voltage and current that maximizes device output power. The MPP of a cell, assembly, or array changes with temperature and illumination, and thus the photovoltaic current I _{L changes} . The MPP of a cell, assembly, or assembly may also depend on factors such as shading and / or aging of the cell, assembly, or assembly.

Maximum Power Point Tracking (MPPT) controllers are proposed for operating a photovoltaic cell at its maximum power point or near its maximum power point. These controllers typically determine an MPP voltage and an MPP current for a photovoltaic device connected to its input and set its effective impedance to hold the photovoltaic device to its MPP. However, conventional MPPT controllers often have one or more disadvantages. For example, some proposed MPPT controllers may be relatively slow under certain conditions, thereby delaying MPP operation.

Summary

In one embodiment, a maximum power point tracking controller includes an input terminal for electrical coupling to an electrical power source, an output terminal for electrical coupling to a load, a control switching device, and a control subsystem. The control switching device is adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input port to the output port. The control subsystem is adapted to control the switching of the control switching device to control a voltage across the input terminal, the control being based, at least in part, on a signal representing a current flow from the output terminal to maximize a signal, the power from the output terminal represents.

In one embodiment, a power system includes an electrical power source and a maximum power point tracking controller. The maximum power point tracking controller includes an input port for electrical coupling to an electrical power source, an output port for electrical coupling to a load, a control switching device, and a control subsystem. The control switching device is adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the electrical power source to the output port. The control subsystem is adapted to control the switching of the control switching device to control a voltage across the input terminal, the control being based, at least in part, on a signal representing a current flow from the output terminal to maximize a signal, the power from the output terminal represents.

In one embodiment, a method of operating a maximum power point tracking controller, comprising an input terminal for electrical coupling to an electrical power source and an output terminal for electrical coupling to a load, comprises the steps of: (a) repeatedly switching a maximum power point control switching device Tracking controller between its conducting and non-conducting states to transfer power from the input port to the output port, and (b) controlling the switching of the control switching device at least in part based on a signal representing the current flowing out of the output port by an amount a voltage at the input terminal so that a signal representing power from the output terminal is maximized.

In one embodiment, a method of transferring electrical power between an electrical power source and a load using a maximum power point tracking controller includes the step of controlling the switching of a control switching device based at least in part on a signal that corresponds to an energy storage inductance of the maximum power point Tracking controller represents current flowing to regulate a voltage at the electrical power source, such that: (a) the voltage at the power source is greater than or equal to a voltage across the load and (b) a signal that is transmitted to the load Performance is represented, maximized.

In one embodiment, a multiplier includes first and second input terminals, an output terminal, a first field effect transistor, a second field effect transistor, a third field effect transistor, and a control circuit. The first field effect transistor is electrically connected in series with the first input terminal, the second field effect transistor is electrically connected in series with the second input terminal, and the third field effect transistor is electrically connected in series with the output terminal. The control circuit is adapted to control each of the first, second, and third field effect transistors such that an amount of current flowing into the output terminal is proportional to a product of (a) an amount of current flowing into the first input terminal, and (b) is an amount of the current flowing into the second input terminal.

In one embodiment, an electronic filter includes an integrator subsystem and a transconductance circuit. The integrator subsystem is capable of operating in a bipolar domain to filter an AC component of an input signal. The transconductance circuit is adapted to operate in a unipolar domain to produce an output current signal that is proportional to an average of the input current signal.

In one embodiment, a method of filtering an input signal comprises filtering an AC component of the input signal in a bipolar domain and generating a DC component of the input signal in a unipolar domain.

In one embodiment, a signal scaling system includes a transconductance subsystem and control logic. The transconductance subsystem is adapted to convert an input voltage signal to an output current signal, and the transconductance subsystem includes a programmable resistor capable of adjusting a gain of the transconductance subsystem. The control logic is adapted to adjust a resistance of the programmable resistor to adjust the gain of the transconductance subsystem such that an amount of the output current signal is at least as large as a first threshold.

In one embodiment, a signal level converter for converting complementary input voltage signals in a first power supply domain to complementary output voltage signals in a second power supply domain may include a transconductance stage and a load circuit. The transconductance stage in the first power supply domain is adapted to generate complementary current signals in response to the complementary input voltage signals. The load circuit is located in the second power supply domain and is adapted to generate the complementary output voltage signals in response to the complementary current signals. The load circuit includes first and second inverter circuits adapted to generate the complementary output voltage signals in response to the complementary current signals.

In one embodiment, a system for determining a signal representing power in a Maximum Power Point Tracking (MPPT) controller includes a voltage filter subsystem, a current filter subsystem, a voltage scaling subsystem, a current scaling subsystem, and a multiplier. The voltage filtering subsystem is adapted to generate a signal representing the average voltage at an output terminal of the MPPT controller by filtering a signal representing the voltage at the output terminal. The current filter subsystem is adapted to generate a signal representing the average current flowing from the output terminal by filtering a signal representing the current flowing out of the output terminal. The voltage scaling subsystem is adapted to generate a scaled signal representing the average voltage at the output port by scaling the signal representing whether the average voltage at the output port is within a first predetermined range of values. The stream scaling subsystem is adapted to generate a scaled signal representing the average current flowing out of the output port by scaling the signal representing whether the average current flowing out of the output port is within a second predetermined range of values. The multiplier is adapted to determine the signal representing power from a product of the scaled signal representing the average voltage at the output port and the scaled signal representing the average current flowing from the output port.

In one embodiment, a method for determining a signal representing power in a Maximum Power Point Tracking Controller (MPPT) comprises the steps of (a) filtering a signal representing the current flowing out of the output port of the MPPT controller, to obtain a signal representing the average current flowing out of the output terminal; (b) filtering a signal representing the voltage at the output terminal to obtain a signal representing the average voltage at the output terminal; (c) scaling the signal representing the average current flowing out of the output port to obtain a scaled signal representing the average current flowing out of the output port; (d) scaling the signal representing the average voltage at the output port to obtain a scaled signal representing the average voltage at the output port, and (e) multiplying the scaled signal representing the average current flowing from the output port, with the scaled signal representing the average voltage at the output port to obtain the signal representing the power.

Brief description of the drawings

1 shows a model of a photovoltaic cell.

2 Figure 11 shows a graph of voltage and power as a function of current for a photovoltaic cell.

3 FIG. 10 illustrates a power system with an MPPT controller according to one embodiment. FIG.

4 shows a block diagram of a control subsystem of the MPPT controller in 3 ,

5 illustrates a possible operation of the control subsystem of the MPPT controller in FIG 3 ,

6 FIG. 3 illustrates an example of the operation of a current scaling subsystem with a minimum seed condition in accordance with one embodiment.

7 illustrates an electronic filter according to an embodiment.

8th illustrates a signal scaling subsystem according to one embodiment.

9 illustrates a multiplier according to an embodiment.

10 FIG. 12 illustrates one possible implementation of the logic and driver circuit in one embodiment of the MPPT controller in FIG 3 wherein the control and freewheeling switching devices are implemented by N-channel field effect transistors.

11 shows a graph of switching node voltage as a function of time for the MPPT controller in FIG 3 ,

12 illustrates a signal level converter according to an embodiment.

13 FIG. 10 illustrates a power system according to an embodiment having multiple instances of the MPPT controller in FIG 3 includes.

Detailed description of the embodiments

Applicants have developed new MPPT controllers that can provide one or more advantages. For example, certain embodiments of the controllers may be operated with a variety of loads and may also relatively quickly converge to an MPP.

3 shows a power system 300 including an MPPT controller 302 that is between an electrical power source 304 and a load 306 is electrically coupled. As discussed below, MPPT is controller 302 suitable, the electrical power source 304 operate at their MPP or near their MPPs while using power from the electrical power source 304 to the load 306 transfers.

MPPT controller 302 includes an input port 308 with input terminals 310 . 312 and an output terminal 314 with output terminals 316 . 318 , A positive clamp 320 the electrical power source 304 is electrical with the input terminal 310 coupled and a negative terminal 322 the electrical power source 304 is electrical with the input terminal 312 coupled, so that the electrical power source 304 with the input connector 308 electrically connected in series. jam 310 . 320 form part of a positive power supply node or a positive power rail (Vddh) and terminals 312 . 322 form part of a reference power supply node or a reference power supply rail (Vss). Electric power source 304 is, for example, a photovoltaic device, such as a photovoltaic assembly comprising a plurality of interconnected photovoltaic cells, a single photovoltaic cell or a multiple photovoltaic cell. However, the system is 300 not limited to photovoltaic applications. For example, in some alternative embodiments, the electrical power source 304 one or more fuel cells or one or more batteries.

system 300 optionally includes one or more input capacitors 324 , which are via the input connection 308 are electrically coupled. capacitors 324 contribute to the ripple component of the input current Iin of the controller 302 to provide and thereby contribute to the amount of ripple current caused by the electrical power source 304 flows, minimize. A small amount of ripple current through the electrical power source 304 in turn contributes to a more efficient operation of the electrical power source. In certain embodiments, where MPPT controllers 302 switching at a relatively high frequency, for example at 500 kHz or greater, are capacitors 324 Multilayer ceramic capacitors, which promotes smaller capacitor size and longer capacitor life.

MPPT controller 302 includes a circuit 326 which is electrically connected to the input terminal 308 is coupled. circuit 326 includes a control switching device 328 between the input terminal 310 and a switching node Vx is electrically coupled, and a freewheeling switching device 330 connected between switching node Vx and input terminal 312 is electrically coupled. output terminal 316 is electrically coupled to switching node Vx. and output terminal 318 is electric with input terminal 312 coupled. As used herein, a switching device includes, but is not limited to, a bipolar transistor, a field effect transistor (eg, an N-channel or P-channel metal oxide semiconductor field effect transistor (MOSFET), such as a laterally diffused metal-oxide semiconductor Transistor (LDMOS), a junction field effect transistor, a metal-semiconductor field effect transistor), an insulated gate bipolar transistor, a thyristor or a controlled silicon rectifier.

load 306 is with output connection 314 electrically connected in series to form part of an output circuit 332 to form the load 306 electrically with circuit 326 coupled. load 306 For example, it includes an inverter or a battery charger. One or more output capacitors 334 are electrically parallel to the load 306 switched to absorb the ripple of the output current Iout. capacitors 334 However, in embodiments in which load can be 306 has a significant capacity, such as in embodiments in which load 306 An inverter with significant input capacity is optional. In certain embodiments, where MPPT controllers 302 switching at a relatively high frequency, for example at 500 kHz or greater, are capacitors 334 Multilayer ceramic capacitors, which promotes smaller capacitor size and longer capacitor life. output circuit 332 includes energy storage inductance 336 , In some embodiments, energy storage inductance includes 336 one or more discrete inductors, as symbolically in 3 is shown. However, in some other embodiments, the discrete energy storage inductors may be eliminated and "parasitic" coupling inductances associated with a loop-forming output circuit 332 as energy storage inductance 336 serve.

MPPT controller 302 further includes a control subsystem 338 , circuit 326 , Energy storage inductance 336 and capacitors 334 Together, they form a buck converter, which is controlled by subsystem 338 is controlled. Control subsystem 338 is suitable switching the circuit 326 so that the buck converter power from the input terminal 308 to the output terminal 314 transmits, eliminating power from the electrical power source 304 to the load 306 is transmitted. In particular, causes control subsystem 338 in that control switching device 328 repeatedly switches between its conducting and non-conducting states, typically at a frequency of at least 100 Kilohertz to power from input terminal 308 to output terminal 314 transferred to. switching device 328 is referred to as the "control switching device" because the ratio between input voltage Vin and output voltage Vout at the load 306 a function of the duty cycle of the switching device 328 is.

Control subsystem 338 also controls the switching of the freewheeling switching device 330 so that this performs a freewheeling function or, in other words, so that freewheeling switching device 330 a path for output current Iout between the output terminals 316 . 318 provides, when control switching device 328 is in its non-conductive state. In some alternative embodiments, freewheeling switching device is used 330 replaced by an alternative freewheeling device, such as a diode whose anode is electrically coupled to the reference node Vss and whose cathode is electrically coupled to the switching node Vx.

MPPT controller 302 further includes a stream reconstructor subsystem 340 suitable for providing a signal Io corresponding to that of output terminal 314 represents the flowing output current Iout. In some embodiments, current-reconstructor subsystem is used 340 for generating the signal Io systems and methods described in one or more of the US Patent Numbers 6,160,441 and 6,445,244 to Stratakos et al. and incorporated herein by reference. However, you can Current reconstructor subsystem 340 may be implemented in other ways without departing from the scope of the invention.

Control subsystem 338 further controls the switching of the control switching device 328 based in part on signal Io to the input voltage Vin at the input terminal 308 so that a signal, the power of output terminal 314 represents, is maximized. In other words, control subsystem 338 adjusts the amount of Vin so that MPPT controller 302 has an effective input impedance, as seen from the electrical power source 304 in the input connection 308 can be seen, where the input impedance is the power output terminal 314 at least substantially maximized. Maximizing the power of output terminal 314 maximizes the power to the load 306 and, in essence, also maximizes the power of the electrical power source 304 is taken as the power of output terminal 314 neglecting the losses in the MPPT controller 302 equal to the size of the electrical power in the input terminal 308 is. Accordingly, this can be the power of output port 314 representing signal either power in the input terminal 308 or power from the output port 314 represent as both values are equal when losses in the controller 302 be ignored. It should be noted that although power in the input terminal 308 and power from the output terminal 314 are substantially the same, the input current Iin and the output current Iout are different unless the control switching device 328 is operated at a duty cycle of one hundred percent.

In some embodiments this represents power from the output port 314 Signal representing the actual power from the output terminal or the actual power in the input terminal 308 , In some other embodiments, this represents power from the output port 314 however, the representative signal is the relative power from the output port or the relative power in the input port 308 , In these embodiments, the actual power of the output terminal or input terminal is effectively maximized by maximizing the relative power of the output terminal or input terminal.

In certain embodiments, some or all of the MPPT controllers are 302 implemented in a common integrated circuit to achieve a small size, low parasitic impedance between the components and a fast signal propagation time. In these embodiments, the integrated circuit is optionally located in a common housing with the electrical power source 304 to a small system size and minimum impedance between power source 304 and controllers 302 to achieve. However, the MPPT controller is 302 is not limited to implementation in an integrated circuit and instead may be partially or wholly formed from discrete components.

Although circuit 326 , Energy storage inductance 336 and capacitors 334 forming a buck converter may also be considered to form a buck converter with a negative "output current". In particular, since the input voltage Vin is controlled and is greater than or equal to the output voltage Vout, circuitry could be used 326 , Energy storage inductance 336 and capacitors 334 together as an up-converter, with load 306 is electrically coupled to the input of the boost converter and the electrical power source 304 is electrically coupled to the output of the boost converter. However, the output current of the boost converter is negative because input current Iin from the electric power source 304 in the MPPT controller 302 flows. Thus, circuit can 326 , Energy storage inductance 336 and capacitors 334 may be considered together either as a down-converter with a regulated input voltage Vin or as a step-up converter with a negative "output current" Iin, depending on the viewpoint.

4 shows a block diagram of the control subsystem 338 , Control subsystem 338 includes a current filter subsystem 402 which is suitable for filtering the ripple component from the signal Io and for generating a signal Io_mittel which is the middle one from the output terminal 314 represents flowing electricity. A power scaling subsystem 404 scales Io_mittel to generate a signal scaled_Io_mittel, which is the signal Io_mittel scaled to a first range of values. A voltage filter subsystem 406 filters out the output terminal voltage Vp, which is a waveform of approximately a rectangular shape, to produce a signal Vp_mittel, which is the average of the voltage Vp at the output terminal 314 represents. However, in some alternative embodiments, voltage Vp will be across the load 306 instead of via the output terminal 314 sampled, creating voltage filter subsystem 406 can be omitted. A voltage scaling subsystem 408 Vp_mittel scales to generate a signal scaled_Vp_mittel, which is the signal Vp_mittel scaled to a second range of values. The second value range of the scaling system 408 and the first value range of the scaling system 404 are typical identical to facilitate the multiplication of scaled_Io_mittel and scaled_Vp_mittel. Some possible examples of filter subsystems and scaling subsystems are described below with reference to FIGS 7 and 8th discussed.

Control subsystem 338 further comprises a multiplier 410 which is capable of multiplying the scaled_i__mittel and the scaled_vp_mit to produce a signal Po that has both power from the output port 314 as well as power to input terminal 308 represented and at least substantially proportional to them. An example of a possible implementation of the multiplier 410 will be referring below 9 discussed. MPPT controller circuit 412 generates a signal Vref command and a reference voltage generator 414 generates a reference voltage Vref in response to the Vref command signal. MPPT control circuit 412 and reference voltage generator 414 act together to adjust an amount of Vref to maximize signal Po, thereby reducing power from the output port 314 and the power in the input terminal 308 effectively maximized. An example of this MPPT functionality will be discussed below with reference to FIG 5 discussed.

An error amplifier 416 generates an error voltage Verr from a PWM comparator 418 is compared with a ramp signal Vramp to generate a PWM control signal PWM. Logic and driver circuit 420 generates signals 422 . 424 that the switching of the switching devices 328 . 330 from the signal PWM.

Error voltage Verr, that of error amplifier 416 is generated by: Verr = -Kv * (Vin-Vref) + Ki * Io Eq. 2 where Kv and Ki are scaling factors. These scaling factors are chosen such that the amount of Kv · Vin under expected operating conditions is greater than the amount of Ki · Io to maintain stability. Moreover, scaling factor Kv is typically large because the system bandwidth is approximately proportional to Kv * I / Cin, where Cin is the total capacitance value of the input capacitors 324 and I is the average value of the output current Iout. In some embodiments, the scaling factor Kv is chosen in inverse proportion to the expected amount of Vin, and Ki is chosen in inverse proportion to the expected average of the output current Iout. Scaling factors Kv and Ki may be constants, or one or both of these factors may be set dynamically, such as due to changes in operating condition.

In some alternative embodiments, error amplifier has 416 a slightly different transfer function, given by: Verr = -Kv * (Vin-Vref) + Ki * Iout_mittel Eq. 3 where Iout_mittel is an average of the current Iout. In certain of these embodiments, Iout_mittel is the signal Io_mittel from the stream filter subsystem 402 , In other of these embodiments, however, Iout_mittel is derived from another filter circuit, such as circuits similar to the current filter subsystem 402 are.

The fact that Verr is a function of Vin allows a fast system reaction and therefore helps to quickly establish MPP operation. In addition, the fact that Verr is a function of the signal Io helps attenuate the system and therefore helps to minimize or even eliminate overshoots at MPPT-related point jumps. In addition, the fact that MPPT is based on output / input power rather than just voltage or current can allow MPPT controllers 302 can be operated with a variety of different loads, including power source loads and power source loads.

Control subsystem 338 For example, depending on the implementation of the various subsystem blocks, it may be configured such that signals processed therein are voltage signals, current signals, or a combination of voltage and current signals. For example, signal Io coming out of output terminal 314 flowing current, depending on the execution of the current-reconstructor subsystem 340 be either a current signal or a voltage signal. As another example, Signal Po could be out of output port 314 flowing current, depending on the device of the multiplier 410 be either a current or a voltage signal. Furthermore, could Control subsystem 338 be designed such that the signals processed therein are analog signals and / or digital signals.

5 shows a method 500 for maximizing the out of the output port 314 taken power using control subsystem 338 , The procedure 500 can be considered as a "method of load steps" in which Vref is periodically perturbed and the effect of the perturbation is observed to determine in which direction the magnitude Vref should be adjusted to increase signal Po.

In step 502 become scaling subsystems 404 . 408 adjusted so that signals scaled_Io_mittel and scaled_Vp_mittel are within the first or second value range. Such signal scaling maximizes the dynamic range of the multiplier 410 in the generation of signal Po. In step 504 scans MPPT controller circuit 412 Multiplier output signal Po and stores it for use as a reference before the disturbance of Vref. In step 506 changes MPPT controller circuit 412 the amount of Vref by a first step size by changing the signal Vref command to disturb Vref. This Vref interference is either positive or negative, depending on whether the last Vref interference resulted in an increase or decrease in Po. More specifically, if the last Vref interference resulted in an increase in Po, Vref is changed by one step in the same direction. However, if the last Vref interference resulted in a decrease in Po, Vref is changed by one step in the opposite direction. In step 508 scans control circuit 412 again Po from and determines if the Vref fault of step 506 Po has increased or decreased. The procedure 500 is repeated from time to time, thereby achieving control subsystem 338 the electrical power source 304 at their MPP or near their MPP.

It should be noted, however, that control subsystem 338 by other methods than methods 500 could be operated. For example, could MPPT control circuit 412 alternatively, be able to determine MPP operating conditions by periodically adjusting the signal Vref command to change Vref over a range of values, determining signal Po at each of these values, and determining for which value of Vref the largest value of the signal Po is achieved.

Some embodiments of the MPPT controller 302 can be operated so that they operate with a duty cycle of one hundred percent of the control switching device 328 support. In these embodiments, the method of load steps of 5 modified so that the amount of Vref is always around step 506 is reduced when the control switching device 328 is at a duty cycle of one hundred percent. This modification of the method 500 is required because an increase in Vref at one hundred percent duty cycle does not alter the operating conditions of MPPT controllers 302 because the duty cycle increases with increasing Vref and the duty cycle can not go beyond one hundred percent.

In some situations, the magnitude of the Io signal for scaling in the first range of values may be too small, even with a maximum gain setting of the current scaling subsystem 404 , A small value of scaled_Io_mittel, in turn, may make it difficult or impossible to determine signal Po from the product of scaled_Io_mittel and scaled_Vp_mittel. Accordingly, current scaling subsystem 404 optionally, arranged such that the amount of scaled_Io_mittel does not fall below a minimum threshold, no matter how small the amount Io_mittel is. In these embodiments, signal scaled_Io_ mean will not change in response to a disturbance of Vref at small values of the output current Iout and the average voltage at the output terminal 314 , and not the output power, is therefore maximized under these conditions. This technique of handling MPP operation at low Iout values advantageously does not require that MPPT controller circuit 412 Modify modes to support low levels of Iout or to introduce a discontinuity in the Iout transfer function.

6 shows an example of the operation of an embodiment in which the signal scaled_i__mittel is not allowed to fall below a threshold. In this embodiment, the stream scaling system is 404 is designed to retain signal scaled_i__mittel within a first range of values defined by upper and lower thresholds 602 . 604 is limited, no matter how small the amount of the signal Io_mittel. Within the entrance area 606 the magnitude of the Io_mittel signal is so small that the current scaling subsystem 404 the signal scaled_Io_mittel corresponding to the lower threshold 604 to its minimum threshold. A dashed line 608 represents the amount scaled_Io_mittel would have if stream scaling subsystem 404 the minimum value of scaled_Io_mittel not to the lower threshold 604 would restrict.

In some other embodiments, stream scaling subsystem 404 is suitable for adding a positive offset value to scaled_i__mittel with a small amount of Io_mittel so that scaled_Io_mittel does not fall below a minimum threshold. For example, consider the entrance area again 606 from 6 , In alternative particular embodiments, stream scaling subsystem is 404 suitable for adding a positive offset value to scaled_Io_mittel, if Io_means in the input value range 606 so that scaled_Io_mittel is not below the lower threshold 604 falls. In these embodiments, scaled_Io_mittel retains the same form as Io_mittel. Thus, the section would be of dashed line 608 remain a diagonal line, but section 608 would be moved to the range of values from the upper and lower thresholds 602 . 604 is limited.

Control subsystem 338 optionally further includes additional Vref control circuitry 426 to one or more additional functions of the controller 302 perform. Although additional Vref control circuit 426 is shown symbolically as a discrete block, this is optionally in one or more of the other blocks of the control subsystem 338 as in MPPT control circuit 412 , integrated.

Additional Vref control circuit 426 is optionally capable of preventing Vin from falling below a minimum level and / or rising above a maximum level. It may be desirable to limit the maximum value of Vin to ensure proper operation of the MPPT controller 302 to support. On the other hand, it may be desirable to limit the maximum value of Vin to damage to electrical power source 304 and / or MPPT controllers 302 due to a high state of tension to prevent and / or to ensure safety. Accordingly, in some embodiments, additional Vref control circuitry is included 426 suitable, MPPT control circuit 412 to overdrive and prevent Vref from continuing to fall, or even increase Vref if Vin falls below a threshold, or if a fall of Vref would cause Vin to fall below the threshold. Similarly, in some embodiments, additional Vref control circuitry is included 426 suitable, MPPT controller circuit 412 to override and prevent further increase in Vref if Vin rises above a threshold or if rising Vin would cause Vref to rise above the threshold.

Furthermore, in some embodiments, additional Vref controller circuitry is included 426 suitable, MPPT control circuit 412 to overdrive and decrease Vref when an amount of signal Io falls below a threshold, thereby preventing potentially unreliable operation associated with a very small amount of output current Iout. In a particular embodiment, the threshold is set just above an amount of the minimum output current Iout provided by the current reconstructor subsystem 340 is resolvable. For example, consider an embodiment in the current scaling subsystem 404 is designed so that the amount of scaled_Io_mittel does not fall below a minimum threshold. In this embodiment, as discussed above, the average voltage at the output terminal becomes 314 , and not the output power, maximized when the signal Io falls below the threshold. Such maximization of the mean voltage at the output terminal 314 however, it may not maximize the power of the electrical power source 304 ; instead, it becomes an electrical power source 304 possibly operated at a point of high voltage and low current below its MPP. However, falling Vref becomes the duty cycle of the control switching device 328 increase, whereby the amount of output current Iout is increased, and thus power source 304 is operated closer to its point of maximum power. Falling Vref can also potentially increase the amount of output current Iout so that normal MPPT can be resumed. Accordingly, some embodiments incorporate both (1) circuits to prevent the scaled_Io mean from falling below a threshold and (2) circuits to decrease Vref when the magnitude of the signal Io falls below a threshold.

In certain embodiments, the control subsystem is 338 suitable, control switching device 328 operate at a fixed duty cycle when signal Io falls below a threshold indicating a potential negative output current. The operation of switching device 328 at a fixed duty cycle, reverse current operation facilitates when Iout has a negative value rather than a positive value. Backflow conditions may occur in applications where one or more additional electrical power sources are electrically connected to the output port 314 coupled, such as in applications that include chains of parallel connected photovoltaic devices. It is expected that control subsystem 338 Control switching device 328 at a large fixed duty cycle, such as at a ninety-five or one hundred percent duty cycle, when signal Io indicates a potential negative output current. The threshold indicative of a potential negative output current is typically set lower than the other low output current thresholds, such as the threshold at which Vref is decreased when Io falls below a threshold, as discussed above.

In some situations, it may be desirable to increase the magnitude of the high duty cycle Vref disturbances of the control switching device 328 to promote a more robust MPPT, since large Vref increments at high duty cycle may result in undesirable operation. As from Eq. 2 and 4 As can be seen, the change of the duty cycle in response to a certain Vref step is not necessarily constant, since the duty cycle may vary depending on Io and other factors. The change in duty cycle is typically greater at low Io values than at high Io values, and low Io values typically correspond to high duty cycle operation. Thus, given a high duty cycle, a given Vref step will often cause a relatively large step in the duty cycle. A large duty cycle step can in turn cause the MPPT and / or the operation of the load 306 influence negatively.

Accordingly, in some embodiments, additional Vref control circuitry operates 426 with MPPT controller circuit 412 so together, that MPPT controller circuit 412 Vref changes at a high duty cycle by a smaller step size than at a lower duty cycle. In particular, the circuits effect 412 . 426 in that Vref at the MPPT is changed by a first step size when a command, a duty cycle of the control switching device 328 under a first threshold, and the circuits 412 . 426 cause Vref at the MPPT to be changed by a second step size when a command, a duty cycle of control switching device 328 to control over a second threshold. The second step size is less than the first step size and the first threshold is less than or equal to the second threshold. It is contemplated that in many embodiments, the first threshold will be less than the second threshold to achieve hysteresis between large and small Vref step size modes. The command for controlling the duty ratio of the control switching device 328 becomes, for example, signal 422 derived from logic and driver circuitry 420 is produced.

It may also be desirable to reduce the magnitude of the Vref noise when operating at the MPP or near the MPP, as Vref noise in such a case can lead to the electric power source 304 is temporarily not operated on their MPP. Thus, in some embodiments, additional Vref control circuitry may be provided 426 with MPPT controller circuit 412 so interact that MPPT controller circuit 412 Vref changes by a smaller step size when using an electrical power source 304 is near their MPP, as if the electrical power source 304 far from their MPP. In particular, circuits cause 412 . 426 in that Vref at MPPT is changed by a first step size when a difference in Po between successive Vref disturbances is below a first threshold, and circuits 412 . 426 cause Vref at the MPPT to be changed by a second step size when a difference in Po between successive Vref disturbances is above a second threshold. The second step size is greater than the first step size and the first threshold is less than or equal to the second threshold. It is contemplated that in many embodiments, the first threshold will be less than the second threshold to achieve hysteresis between large and small Vref step size modes.

In many applications, it is desirable to quickly achieve MPP operation. Therefore, in certain embodiments, control subsystem 338 Designed to quickly change Vref when MPPT controller 302 operating at extreme points that are unlikely to represent MPP operation, such as during startup, thereby achieving rapid convergence against MPP operation. In these embodiments, MPPT controller circuitry act 412 and additional Vref control circuitry 426 so together, that MPPT controller circuit 412 Vref changes faster when control switching device 328 is in a state of extreme duty cycles, as when the control switching device 328 is in a state of normal duty cycles. In particular, circuit changes 412 Vref at a first speed, if a command, the duty cycle of the control switching device 328 is within a first range of values, and a circuit 412 changes Vref at a second speed when a command, the duty cycle of the control switching device 328 within a second range of values. The second speed is greater than the first speed and the second range represents an extremely large or small duty cycle command, while the first range represents a normal duty cycle command. For example, in one embodiment, the first range of values represents a command that the duty cycle of the control switching device 328 between zero and one hundred percent, while the second range of values represents a command that the duty cycle of the control switching device 328 less than zero or greater than 100 Should be percent.

In embodiments in which electrical power source 304 is a photovoltaic device, it may be possible to approximate the MPP of the device from its open circuit voltage before the MPPT controller 302 begins to shift. In particular, the MPP of a photovoltaic device is typically in the range of eighty percent to ninety five percent of the open circuit voltage. The initial adjustment of Vref to this range of open circuit voltage of the photovoltaic device may accelerate MPP operation.

Therefore, in some embodiments, additional Vref control circuitry is included 426 suitable when commissioning the MPPT controller 302 an initial value of Vref based at least in part on an initial average voltage at the input terminal 308 adjust. For example, in some embodiments, additional Vref control circuitry 426 suitable to set an initial value of Vref at start-up, so that control switching device 328 initially operated at a duty cycle, which is the average voltage at the input terminal 308 approximately at a fraction of its initial value, for example from 80 to 95 percent of the initial value. MPPT controller circuitry then adjusts the magnitude of Vref to achieve MPP operation, as discussed above with reference to FIG 5 was discussed.

In certain embodiments, control circuitry includes 328 and / or freewheeling switching device 330 one or more switching devices that are dynamically matched field effect transistors (FETs). Such dynamically adjusted FETs each include a number of individually controllable elements in the form of individual FETs electrically connected in parallel, and the number of these individual FETs that are active can be varied to dynamically adjust the size of the FET. The FET properties can be varied by changing its size, that is, by the number of its individual FETs that are active. For example, the overall FET channel resistance can be reduced by increasing the FET size, ie by increasing the number of individual FETs that are active. However, the more of the individual FETs are active, the greater the gate capacitance and the associated switching loss are (provided that each individual FET is driven by a common driver). For each duty cycle, there is typically an optimal FET size that minimizes the sum of losses due to resistance and gate capacitance.

In some embodiments, the one or more dynamically adjusted FETs and power reconstructor subsystem 340 include, reduce control subsystem 338 the FET size, ie it reduces the number of active individual FETs when the magnitude of the signal Io_mittel falls below a threshold, around the gain of the current-reconstructor subsystem 340 to change. In these embodiments, the gain of the current-reconstructor subsystem is dependent 340 at least in part from the number of individual FETs that are active, and the gain increases as the number of active individual FETs decreases. Thus, decreasing the FET size increases the gain of the reconstructor and the magnitude of the Io_mittel signal, thereby compounding difficulties associated with a small amount of the Io_mittel / Io_mittel_skaliert signals, such as those discussed above with respect to FIG 6 difficulties, potentially reduced or even eliminated. Accordingly, the reduction in FET size may be to the control subsystem 338 allow MPPT to be performed at lower levels of output current Io than would be possible without reducing the FET size.

7 illustrates an electronic filter 700 , Each of the current and voltage filter subsystems 402 . 406 includes, for example, an instance of the filter 700 , Filter subsystems 402 and or 406 however, can alternatively be implemented with other filter types. For example, in some other embodiments, the voltage filter subsystem is 406 implemented with an RC filter for simplicity and low cost. Furthermore, electronic filter 700 not to use in control subsystem 338 limited.

filter 700 can be operated to provide an output current signal 702 to generate the average of an input current signal 704 represents. Output current signal 702 is in normal operation a unipolar signal, even in situations where input current signal 704 is a bipolar signal, such as when the input current signal 704 a small DC component (DC) and a large AC component (AC). In the context of this document, a unipolar signal remains either positive or negative. In other words, a unipolar signal does not switch between positive and negative values. A bipolar signal, on the other hand, changes between positive and negative values. As is known in the art, it is often much easier to process a unipolar signal than a bipolar signal. For example, a two-transistor current mirror may be used to scale a unipolar signal, while much more complicated circuitry is required to scale a bipolar signal. Accordingly, the fact that the output current signal 702 is unipolar in normal operation, be particularly advantageous in certain applications.

filter 700 includes an integrator subsystem 706 and a transconductance circuit comprising first and second transconductance amplifiers 708 . 710 , Integrator subsystem 706 includes an integrator 712 with inverting and non-inverting input terminals, a resistance device 714 which is electrically coupled to the input terminals of the integrator, and a constant voltage source 716 that is between the non-inverting input of the integrator and a reference node 718 is electrically coupled. The inverting input of the integrator is electrical with a node 724 coupled. An AC component 720 of the input current signal 704 flows through resistance device 714 in the knot 724 , causing an AC signal between the input terminals of the integrator 712 is produced. integrator 712 integrates this AC signal and produces an integrator signal AVG which is the average of the input current signal 704 represents.

Second transconductance amplifier 710 generates a current signal in response to integrator signal AVG 722 that in the knot 724 flows, leaving the integrator subsystem 706 and the second transconductance amplifier 710 together form a closed low-pass filter. current signal 722 represents the DC component of the input current signal 704 , so that DC signal 722 and AC signal 720 together input current signal 704 form that out of knots 724 flows. First transconductance amplifier 708 is also controlled by integrator signal AVG so that it output current signal 702 generates the DC signal 722 and therefore proportional to the average of the input current signal 704 is.

Accordingly, integrator subsystem 706 operated in a bipolar domain to the bipolar or AC component of the input current signal 704 while filtering the first and second transconductance amplifiers 708 . 710 in a unipolar domain to the unipolar or DC component of the input current signal 704 to process. This separate processing of the bipolar and unipolar components of the input current signal 704 simplifies the filtering of the bipolar AC component of the input current signal 704 while maintaining the accuracy of the unipolar DC component.

8th illustrates a signal scaling subsystem 800 , Each of the power and voltage scaling subsystems 404 . 408 includes, for example, an instance of scaling subsystem 800 , Scaling subsystems 404 and or 408 however, could alternatively include other scaling circuits. Furthermore, signal scaling subsystem 800 not to use in control subsystem 338 limited.

subsystem 800 includes an amplifier 802 , a control transistor 804 , a programmable resistor 806 and mirror transistors 808 . 810 , In the context of this document, field effect transistor terminals labeled G, D, and S correspond to the gate, drain, and source terminals, respectively. An exit 812 of the amplifier 802 drives the control transistor 804 that is between mirror transistor 808 and programmable resistance 806 is electrically coupled. mirror transistor 808 is electrically connected between a high-side power supply node or a high-side rail 814 and control transistor 804 coupled and programmable resistance 806 is electrically between control transistor 804 and a reference node or reference rail 816 coupled. An inverting input of the amplifier 802 is electrically connected to a node 818 , the control transistor 804 and programmable resistance 806 connects, coupled, and a non-inverting input of the amplifier 802 receives an input voltage signal 820 ,

amplifier 802 controls the operation of the control transistor 804 such that a current signal 822 that by transistor 804 and programmable resistance 806 flows, causing a voltage on the programmable resistor 806 equal to the input voltage signal 820 is. Thus, amplifier controls 802 the voltage across the variable resistor 806 in response to the input voltage signal 820 , transistor 810 reflects current signal 822 to an output current signal 824 to generate proportional to the current signal 822 is. A resistance value of the programmable resistor 806 is from the control logic 826 set. Thus form amplifiers 802 , Control transistor 804 , programmable resistance 806 and mirror transistors 808 . 810 a transconductance subsystem that is suitable input voltage signal 820 in output current signal 824 convert, using the control logic 826 the resistance of the programmable resistor 806 to control the gain of the transconductance subsystem.

As the gain range increases, so does the number of gain stages required to achieve a desired gain change with each stage. Thus, in certain embodiments, programmable resistance 806 and control logic 826 chosen so that the gain at each gain stage changes by a factor equal to the square root of two to achieve a compromise between a large control range and the number of gain stages.

subsystem 800 further includes an additional mirror transistor 826 , the current signal 822 reflects. A comparator 828 compares the mirrored current signal with a reference current signal 830 , and comparator 828 outputs a GainOK signal if the mirrored current signal is at least as large as the reference current signal. When an ENABLE enable signal is asserted, control logic sets 826 the programmable resistor 806 to its maximum resistance, which sets the gain to a minimum value. The control logic 826 then gradually reduces the resistance of the programmable resistor 806 in response to a CLK clock signal, whereby the gain gradually increases until a GainOK signal from the comparator 828 is created. Thus, scale scaling subsystem scales 800 Output current signal 824 to an amount at least as large as the reference signal 830 is when the ENABLE signal is applied. In embodiments of the control subsystem 338 , the instances of subsystem 800 As scaling subsystems, for example, the ENABLE signal becomes in the execution of step 502 of procedures 500 created ( 5 ).

In certain embodiments of control subsystem 338 , the instances of subsystem 800 As scaling subsystems, a Vref disturbance could cause a large increase in scaled_Io_mittel and / or scaled_Vp_mittel before scaling subsystems 404 . 408 rescale their outputs. Such a large increase in signal size may be multipliers 410 saturate, causing inaccurate MPPT operation. Accordingly, subsystem includes 800 optionally further mirror transistor 832 , Comparator 834 and reference current source 836 to a large increase in the magnitude of the output current signal 824 that can cause improper MPPT operation.

In particular, mirror transistor reflects 832 current signal 822 , and comparator 834 compares the mirrored current signal with a reference current signal 836 that is greater than the reference current signal 830 is. In some embodiments, the reference current signal is 836 four times the reference current signal 830 and represents a threshold at which the magnitude of the output current signal 824 is considered excessive. comparator 834 outputs a GainHi signal when the amount of mirror current is at least as large as the magnitude of the reference current signal 836 is.

In certain embodiments of control subsystem 338 , the instances of subsystem 800 as scaling subsystems, MPPT controller circuitry responds 412 on a GainHi message, assuming that the perturbation increases the amount of Po, without comparing Po amounts before and after the perturbations. As discussed above, a Po calculation after a large signal rise according to a GainHi message may be inaccurate, and comparing Po values after a GainHi message may result in erroneous MPPT operation.

Certain embodiments of the signal scaling subsystem 800 can achieve one or more benefits that would not necessarily be realized with conventional scaling subsystems. For example, the gain of the subsystem 800 inversely proportional to the resistance of the programmable resistor 806 , creating subsystem 800 by simply changing the resistance of the programmable resistor 806 can achieve a wide gain range.

As another example, the configuration supports subsystem 800 a fast settling of the gain after a gain step change with a settling time that remains relatively constant as the gain changes. In particular, control transistor acts 804 neglecting second order effects as a nearly unity gain amplifier, regardless of the resistance of the programmable resistor 806 , Therefore, the loop gain of the amplifier 802 when changing the resistance 806 almost constant, reducing the bandwidth and settling time of the amplifier 802 also relatively independent of the resistance of the resistor 806 remains. Accordingly, amplifier can 802 typically be chosen to provide a sufficiently fast settling time without having to consider changes in gain.

9 illustrates a multiplier 900 , multipliers 410 of the control subsystem 338 for example, using the multiplier 900 realized. However, multipliers could 410 alternatively be realized in a different way. Furthermore, multiplier 900 not to use in control subsystem 338 limited.

multipliers 900 includes a first input port 902 , a second input terminal 906 and an output terminal 910 , A first input current signal 904 flows into a first input port 902 , a second input current signal 908 flows into the second input terminal 906 and an output current signal 912 flows into the output port 910 , A first field effect transistor 914 is with the first input port 902 electrically connected in series, a second field effect transistor 916 is with the second input terminal 906 electrically connected in series and a third field effect transistor 918 is with the output connector 910 electrically connected in series. As discussed below, multiplier includes 900 a control circuit adapted to control each of the first, second and third transistors to operate the transistors in their linear region or triode region and the magnitude of the output current signal 912 is proportional to the product (a) of the magnitude of the first input current signal 904 and (b) the magnitude of the second input current signal 908 ,

The control circuit comprises a fourth, fifth and sixth field effect transistor 920 . 922 . 924 as well as amplifiers 926 . 928 , The gates of the first and third transistors 914 . 918 are electrically connected to each other at a common node 932 coupled while the gates of the second, fourth and fifth transistors 916 . 920 . 922 electrically with each other at another common node 940 are coupled. The fourth and fifth transistor 920 . 922 each have x matched unit cell transistors, where x is an integer greater than zero. Accordingly, the transistors 920 . 922 have the same channel resistance when operated at the same gate-source voltage, since both transistors have the same number of matched unit cell transistors. The first, second and third transistors 914 . 916 . 918 on the other hand, m * x have matched unit cell transistors, where m is an integer greater than one. Accordingly, each of the transistors has 914 . 916 and 918 a channel resistance equal to R / m, where R is the channel resistance of the transistor 920 or 922 is, assuming that each of the transistors 914 . 916 . 918 . 920 , and 922 is operated at a common gate-source voltage.

amplifier 926 is suitable, the gate of the first transistor 914 so that its channel resistance R914 is controlled by the voltage at the reference node 938 and the first input current signal 904 is determined. In particular, amplifier forces 926 the voltage at the first transistor 914 which is equal to the voltage at the node 934 is equal to the voltage at the fourth transistor 920 to be so that: R914 = V938 / I904 Eq. 4 where V938 is the voltage at the node 938 and I904 the magnitude of the first input current signal 904 is. Every transistor 914 . 918 has the same channel resistance since both transistors have mx x matched unit cell transistors and a common gate-source voltage from the amplifier 926 to be driven.

amplifier 928 controls the gate of the sixth transistor 924 so that the voltage on the second transistor 916 the same as the voltage at the third transistor 918 which is equal to the voltage at the node 930 is. Accordingly, the magnitude of the output current signal 912 given by: I912 = V942 / R914 = V942 / (V938 / I904) = I904 * (V942 / V938) Eq. 5 where I912 is the magnitude of the output current signal 912 and V942 the voltage at the node 942 is. The voltage at the reference node 938 is given by the following equation: V938 = (Iref / m) * R920 Eq. 6 where R920 is the channel resistance of the fourth transistor 920 is. The fourth and fifth transistor 920 . 922 form a current mirror which is designed such that a drain-source current flowing through the fifth transistor 922 flows, has an amount equal to Iref and a drain-source current flowing through the fourth transistor 920 flows, has an amount equal to Iref / m. As discussed below, this configuration ensures that the transistors 914 . 916 . 918 . 920 in their triode range, as required for proper operation.

The gates of the second and fourth transistors 916 . 920 are both with the node 940 coupled, so that the channel resistance R916 of the second transistor 916 is given by: R916 = R920 / m Eq. 7

Accordingly, it can be shown that the voltage at the node 942 is given by: V942 = I908 * R916 = I908 * (R920 / m) Eq. 8th where I908 is the magnitude of the second input current signal 908 is. The ratio of the voltage at the node 942 to the ratio of the voltage at the node 938 is therefore given by: V942 / V938 = I908 * (R920 / m) / [(Iref / m) * R920] = I908 / Iref Eq. 9 By substituting Eq. 9 in Eq. 5 is as follows: I912 = (I904 · I908) / Iref Eq. 10

Eq. 10 shows that the magnitude of the output current signal 912 proportional to the product of (a) the magnitude of the first input current signal 904 and (b) the magnitude of the second input current signal 908 is. Eq. 10 also shows that the output current signal 912 is inversely proportional to the reference current signal Iref.

multipliers 900 can achieve one or more advantages that would not necessarily be realized by conventional multipliers.

For example, both input signals 904 . 908 and output signal 912 respectively current signals and no voltage signals, which in certain applications the connection of multipliers 900 to facilitate external circuits. As another example, some embodiments will operate with a unipolar power supply and ground related signals and therefore will not require a shared power supply or require the signals to refer to a center rail potential. In addition, certain embodiments require multipliers 900 no resistors, as in 9 shown. Forming a circuit without resistors may be particularly advantageous in the implementation of integrated circuits since resistors can occupy significant space on the integrated circuit chip.

Furthermore, the interpretation of the multiplier promotes 900 reliable operation under sub-optimal conditions, such as temperature and / or manufacturing process vertices, by ensuring that the transistors 914 . 916 . 918 . 920 in their linear range or triode range, as required for proper operation. In particular, by the interpretation of the multiplier 900 in a way that a drain-source current of the fourth transistor 920 m times smaller than a drain-source current of the fifth transistor 922 , ensures that the fourth transistor 920 is operated in its triode range and that the voltage at the reference node 938 is relatively low. The low voltage at the reference node 938 also causes the first and third transistors 914 . 198 each operated in their triode range, since amplifiers 926 the voltage at the first transistor 914 forces, equal to the voltage at the reference node 938 to be. The second transistor 916 is again operated in its triode region, as long as its drain-source current is less than m · Iref, since this transistor through the fifth transistor 922 is controlled. The larger the value of the parameter m, the further the transistors work 914 . 916 . 918 . 920 therefore in their triode range. As long as m is greater than two and the magnitude of both the first and second input current signals 904 . 908 is less than Iref become transistors 914 . 916 . 918 . 920 are each operated in their triode range, even at temperature and / or manufacturing process vertices.

As discussed above, the logic and driver circuit are 420 ( 4 ) two signals 422 . 424 out, the switching devices 328 . 330 Taxes. Each of the signals 422 . 424 is typically located in a different power domain because the control and freewheeling devices relate to difference nodes.

For example, shows 10 a possible interpretation of the logic and driver circuit 420 in one embodiment, in the control switching device 328 as an N-channel field effect transistor 1028 is implemented and freewheeling switching device 330 as an N-channel field effect transistor 1030 is implemented. It should be understood, however, that the MPPT controller 302 not on the in 10 shown implementation is limited.

A regulator 1002 generates a "basic mode" power rail (Vcc) from the positive power supply node Vddh. Vcc is referenced to the reference power supply node Vss and Vcc or a Other derived rail is used to control much of the circuit in subsystem 338 , such as PWM comparator 418 to supply electricity.

Signal PWM is located in the Vcc / Vss power supply domain because the PWM comparator 418 from the Vcc busbar, which is referenced to Vss. control logic 1004 the circuit 420 converts signal PWM into a control switching signal 1006 for controlling the transistor 1028 and in a freewheeling signal 1008 for controlling the transistor 1030 around. Both signal 1006 as well 1008 are in the Vcc / Vss power domain. driver circuit 1010 generates a gate control voltage signal Vgs1 in response to the freewheel signal 1008 , Gate control voltage signal Vgs1 drives transistor 1030 or, in other words, controls the gate-source voltage of the transistor 1030 to the switching of the transistor 1030 to control. The source of transistor 1030 is electrically coupled to reference node Vss. Accordingly, the gate control voltage signal Vgs1 is also in the Vcc / Vss gate power supply domain.

control transistor 1028 is referenced to switch node Vx instead of the reference node Vss. A booststrap component of the driver and bootstrap circuit 1012 generates a "bootstrap" voltage rail (Vbst), which is related to switch node Vx, so that circuit 1012 the positive gate of the transistor 1028 with respect to the source of the transistor can drive. An energy storage element, such as a capacitor 1014 , is used to store power for the bootstrap voltage rail. Driver and bootstrap circuit 1012 generates a gate control voltage signal Vgs2 in the Vbst / Vx power supply domain to transistor 1028 to drive.

Signals in the Vcc / Vss domain can not be electrically coupled directly to the Vbst / Vx domain because the two domains have different references. In particular, the reference Vss in the Vcc / Vss domain is substantially at a constant voltage. By contrast, the Vbst / Vx domain is referred to switching node Vx, which has a large voltage swing. For example, shows 11 a graph of the voltage at the switching node Vx over time. Signal PWM is also shown on the graph by dashed lines. As can be observed, the voltage at the switching node Vx changes significantly in response to changes in the signal PWM.

Accordingly, logic and driver circuitry includes 420 a level converter 1016 to control switch signal 1006 from the Vcc / Vss domain to a signal 1018 in the Vbst / Vx domain. Thus level converter couples 1016 control logic 1004 , which is located in the Vcc / Vss domain, with driver and bootstrap circuitry 1012 located in the Vbst / Vx domain. 12 shows a signal level converter 1200 , which is a possible embodiment of the level converter 1016 is. However, it should be recognized that level converter 1016 can also be performed in other ways. In addition, level converter 1200 not on the application in circuit 420 limited.

level converter 1200 receives complementary input signals INP, INN located in the Vcc / Vss power supply domain. An inverter 1202 inverts the signal INP and an inverter 1204 inverts the signal INN before these signals with a transconductance stage 1206 in the Vcc / Vss power supply domain. transconductance 1206 is suitable, complementary current signals 1208 . 1210 in response to the input signals INP, INN.

The output of the inverter 1202 is electrically connected to the gates of the P-channel and N-channel field-effect transistors 1212 . 1214 which are adapted to the voltage at the gate and source terminals of the N-channel field effect transistor 1216 to control. The output of the inverter 1204 is electrically connected to the gates of the P-channel and N-channel field-effect transistors 1218 . 1220 which are adapted to the voltage at the gate and source terminals of the N-channel field effect transistor 1222 to control. When the signal INP is in its high state, there is transistor 1212 in its conducting state and transistor 1214 is in its non-conductive state, allowing the gate-source voltage of the transistor 1216 is essentially zero and the transistor 1216 is in its non-conductive state. On the other hand, when the signal INP is in its low state, the transistor is located 1212 in its non-conductive state and the transistor 1214 is in its conducting state, allowing the gate-source voltage of the transistor 1216 essentially equal to Vcc-Vss and the transistor 1216 is in its conductive state. transistors 1218 . 1220 , and 1222 are operated in an analogous manner in response to the signal INN.

Complementary current signals 1208 . 1210 are electrical with a load circuit 1224 coupled in the Vbst / Vx power supply domain adapted to receive complementary output voltage signals OUTP, OUTN in response to current signals 1208 . 1210 to create. load circuit 1224 includes P channel FETs 1226 . 1228 , transistor 1226 is electrically between Vbst and transistor 1222 coupled and is adapted to be operated in its linear range, whereby the magnitude of the current signal 1208 is limited. Similarly, transistor is 1228 electrically between Vbst and transistor 1216 coupled and is adapted to be operated in its linear range, whereby the magnitude of the current signal 1210 is limited.

load circuit 1224 further includes first and second inverter circuits 1230 . 1232 that are related to the Vbst / Vx power domain. The first inverter circuit 1230 is suitable output signal OUTP from current signal 1208 while the second inverter circuit 1232 is suitable, signal OUTN from current signal 1210 to create. inverter 1230 includes a P-channel field-effect high-side transistor 1234 and an N-channel field effect low-side transistor 1236 , transistor 1234 is electrically connected between a high-side rail S2 of the inverter and an output node 1238 coupled and transistor 1236 is electrically between the output node 1238 and Vx coupled. The gates of the transistors 1234 . 1236 are electrical with drains of transistors 1222 . 1226 coupled to a high-side rail S1 of the inverter circuit 1232 are connected. Similarly, inverter circuit includes 1232 a P-channel field-effect high-side transistor 1240 and an N-channel field effect low-side transistor 1242 , transistor 1240 is electrically connected between the high-side rail S1 of the inverter and an output node 1244 coupled and transistor 1242 is electrically between the output node 1244 and Vx coupled. The gates of the transistors 1240 . 1242 are electrical with the drains of the transistors 1216 . 1228 coupled with the high-side rail S2 of the inverter circuit 1230 are connected.

The high-side rail S2 of the inverter circuit 1230 is through a P-channel field effect transistor 1246 electrically coupled with Vbst and high-side rail S1 of the inverter circuit 1232 is through a P-channel field effect transistor 1248 electrically coupled with Vbst. The transistors 1246 and 1248 are cross-coupled, that is, the gate of the transistor 1246 is electrically connected to the drain of the transistor 1248 coupled and the gate of the transistor 1248 is electrically connected to the drain of the transistor 1246 coupled. The gate of the transistor 1246 is electrically connected to the high-side rail S1 of the inverter circuit 1232 coupled and the gate of the transistor 1248 is electrically connected to the high-side rail S2 of the inverter circuit 1230 coupled. Cross-connected transistors 1246 . 1248 achieve a positive feedback, whereby a fast switching of high-side rails S1, S2 and a correspondingly fast operation of the level converter 1200 is encouraged.

Inverter circuits 1230 are 1232 are asymmetrical in the sense that high-side transistors 1234 . 1240 "stronger" than low-side transistors 1236 . 1242 are. More specifically, high-transistor 1234 be operated so that he output node 1238 At least fifty percent of the electrical potential on the high-side rail S2 pulls up when low-side transistor 1236 is in its conductive state. Similarly, high-side transistor 1240 be operated so that he output node 1244 At least fifty percent of the electrical potential on the high-side rail S1 pulls up when low-side transistor 1242 is in its conductive state. Such asymmetry of the inverter circuits 1230 . 1232 is required to achieve proper operation in certain situations.

For example, consider the situation where INP is activated. transistor 1222 will be in its conducting state and transistor 1216 will be in its non-conductive state so that high-side rail S1 is pulled down near Vss and high-side rail S2 is pulled up near Vbst. This will be high-side transistor 1234 operated in its conducting state and low-side transistor 1236 is operated in its non-conductive state, so that output signal OUTP is high. On the other hand will be high-side transistor 1240 operated in its non-conductive state and low-side transistor 1242 is operated in its conductive state, so that output signal OUTP is at low level. However, when the electrical potential of switching node Vx falls below the electrical potential of the reference current node Vss, for example due to the freewheeling action of the freewheeling switching device 330 , it will not be possible low-side transistor 1236 turn off because its gate-source voltage will be positive. Thus, inverter circuit 1230 asymmetric, so that high-side transistor 1234 output node 1238 can pull up, even if there is low-side transistor 1236 is in its conducting state to inverter circuit 1230 to allow it to change its output state from low to high when Vx is at a negative electrical potential relative to Vss. Inverter circuit 1232 is asymmetric for similar reasons, ie to allow the inverter to change its output state from low to high when Vx is at a negative electrical potential with respect to Vss.

load circuit 1224 also includes diodes 1250 . 1252 , The anode of the diode 1250 is electrically coupled to Vx and the cathode of the diode 1250 is electrically coupled to high-side rail S1. The anode of diode 1252 is electrically coupled to Vx and the cathode of the diode 1252 is electrically coupled to high-side rail S2. diodes 1250 . 1252 limit any voltage swing across the transistors 1226 . 1228 and thus help to protect these transistors from overvoltage strokes.

transistors 1222 . 1216 also contribute to the switching of the level converter under certain circumstances 1200 to accelerate. For example, consider again the scenario where signal INP is high and signal INN is low. As discussed above, the transistors are located 1222 . 1234 and 1242 in their conducting states and the transistors 1216 . 1236 and 1240 are in their non-conductive states, so that the OUTP signal is high and the OUTN signal is low. In some cases, Vx will be at a negative electrical potential with respect to Vss, resulting in Vbst being at a negative electrical potential with respect to Vcc. Accordingly, there is the drain of the transistor 1216 at a lower electrical potential than the gate, resulting in the conditional switching of the transistor 1216 from its non-conducting state to its conducting state when its gate-drain voltage exceeds a threshold Vth, which is typically about 0.4 volts. This conduction of the transistor 1216 causes current from Vcc through the transistors 1212 . 1216 to rail S2, whereby rail S2 is pulled up by the difference between a diode voltage and Vth above Vbst, which causes switching of the inverter circuit 1230 accelerated. High-side rail S2 can not be pulled higher than about a diode voltage (about 0.7 volts) above Vbst because of a drain-source body diode (not shown) of the transistor 1246 Rail S2 is stuck on Vbst. Conducting the transistor 1222 accelerates the switching of the inverter circuit 1232 in a similar way, if Vx is negative. level converter 1200 can achieve one or more advantages that may not be realized by conventional level converters. For example, certain embodiments of the level converter 1200 fast or, in other words, introduce a minimum propagation delay in the conversion of the complementary input signals INP, INN into the complementary output signals OUTP, OUTN. For example, in certain embodiments, the propagation delay is less than 7 nanoseconds, even in situations where the electrical potential Vx is below the potential of Vss. This relatively high speed of level converter 1200 is partially due to the inclusion of cross-coupled transistors 1246 . 1248 scored as well by the fact that the transistors 1216 . 1222 Promote fast switching when Vx is negative with respect to Vss, as discussed above. Fast operation is important to, for example, simultaneously routing the control and freewheeling switching devices 328 . 300 due to delays in the switching of the control switching device 328 which is sometimes referred to as "shoot through".

As another example, certain embodiments of the level converter 1200 when both Vcc-Vss and Vbst-Vx are only one volt, potentially allowing operation at low input voltages. The fact that level converter 1200 Difference signals used, such as complementary current signals 1208 . 1210 , also helps to suppress common mode noise between the Vcc / Vss and Vbst / Vx domains.

Multiple instances of MPPT controller 302 can be electrically coupled together. 13 Illustrates, for example, an electrical power system 1300 , the N instances of MPPT controllers 302 in a photovoltaic application, where N is an integer greater than one. In this font, certain instances of a unit can be identified by a number in brackets (eg MPPT controller 302 (1) ), while numbers without brackets refer to any such unit (eg MPPT controller 302 ).

The input connection 308 every MPPT controller 302 is electrically connected to a corresponding photovoltaic device 1304 a common photovoltaic module 1305 coupled. Photovoltaic devices 1304 For example, are single photovoltaic cells or groups of electrically interconnected photovoltaic cells. However, the design of photovoltaic devices 1304 be changed without departing from the scope of the invention. For example, in some alternative embodiments, photovoltaic devices 1304 discrete photovoltaic devices and are not part of a common assembly. As another example, in some other embodiments, two or more photovoltaic devices 1304 different interpretations. A respective input capacitor 1324 is also electrically via each input terminal 308 coupled.

output terminals 314 of the MPPT controller 1302 are with a load 1306 electrically connected in series. One or more output capacitors 1334 are electrical about the load 1306 are paired and used by each of the N MPPT controllers 1302 divided. In some alternative embodiments, load includes 1306 however, a significant capacity and capacitors 1334 therefore omitted. In addition, points in some other alternative embodiments of each MPPT controller 302 a corresponding capacitor (not shown) electrically across its output terminal 314 is coupled.

MPPT controller 302 use coupling inductance 1336 an output circuit 1332 , the circuit 326 electrically with load 1306 coupled, as energy storage inductance. Although this coupling inductance is shown symbolically as a single element, it is actually along a loop-forming output circuit 1332 distributed. However, some alternative embodiments include one or more discrete inductors (not shown) coupled to an output circuit 1332 are electrically connected in series. In embodiments where each MPPT controller 302 has a corresponding capacitor electrically via its output terminal 314 coupled, every MPPT controller needs 302 For example, typically have a corresponding discrete inductance with its output terminal 314 electrically connected in series.

Each MPPT controller 302 is operated in much the same way as with single power MPPT controller electrical power systems 302 was discussed. For example, each MPPT controller controls 302 a voltage Vin at its input terminal 308 to get out of its associated photovoltaic device 304 to maximize the extracted current. In some embodiments, MPPT controllers 302 operated with different phases from each other to constructive interference of the transients resulting from the operation of circuit 326 result, to prevent.

MPPT controller 302 can be modified so that the position of its control and freewheeling switching devices are reversed. For example, MPPT controller could 302 be modified so that the switching device 330 a control switching device is and the switching device 328 a freewheel device, whereby the control switching device can be controlled without a bootstrap circuit. As a result of this modification would be output terminal 314 electrically via the switching device 328 instead of the switching device 330 coupled.

Combinations of features

• (A1) Ein Maximum Power Point Tracking-Controller kann einen Eingangsanschluss zur elektrischen Kopplung mit einer elektrischen Stromquelle, einen Ausgangsanschluss zur elektrischen Kopplung mit einer Last, eine Steuerschaltvorrichtung und ein Steuerungsuntersystem umfassen. Die Steuerschaltvorrichtung kann geeignet sein, wiederholt zwischen ihrem leitenden und nicht leitenden Zustand umzuschalten, um Leistung von dem Eingangsanschluss zu dem Ausgangsanschluss zu übertragen. Das Steuerungsuntersystem kann geeignet sein, das Schalten der Steuerschaltvorrichtung zu steuern, um eine Spannung über den Eingangsanschluss zu regeln, wobei die Regelung zumindest teilweise auf einem Signal basiert, das einen Stromfluss aus dem Ausgangsanschluss repräsentiert, um ein Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert.
• (A2) Im mit (A1) bezeichneten Maximum Power Point Tracking-Controller kann das Steuerungsuntersystem ferner geeignet sein, das Schalten der Steuerschaltvorrichtung teilweise auf dem Signal zu basieren, das Strom aus dem Ausgangsanschluss und eine Differenz zwischen der Spannung an dem Eingangsanschluss und einer Referenzspannung repräsentiert.
• (A3) Im mit (A2) bezeichneten Maximum Power Point Tracking-Controller kann das Steuerungsuntersystem ferner geeignet sein, einen Betrag der Referenzspannung zu variieren, um das Signal, das Leistung aus dem Ausgangsanschluss repräsentiert, zu maximieren.
• (A4) Im mit (A2) oder A3) bezeichneten Maximum Power Point Tracking-Controller kann das Steuerungsuntersystem weiterhin geeignet sein, das Schalten der Steuerschaltvorrichtung teilweise auf Basis eines Fehlersignals zu steuern, wobei das Fehlersignal durch –Kv·(Vin – Vref) + Ki·Io gegeben ist, wobei Kv ein erster Skalierungsfaktor, Ki ein zweiter Faktor, Vin die Spannung am Eingangsanschluss, Vref die Referenzspannung und Io das Signal ist, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert.
• (A5) Im mit (A2) bis (A4) bezeichneten Maximum Power Point Tracking-Controller kann das Steuerungsuntersystem einen Multiplizierer umfassen, der geeignet ist, das Signal, das Leistung aus dem Ausgangsanschluss repräsentiert, aus einem Produkt eines skalierten Signals, das eine mittlere Spannung an dem Ausgangsanschluss repräsentiert, und eines skalierten Signals, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, zu bestimmen.
• (A6) Im mit (A5) bezeichneten Maximum Power Point Tracking-Controller kann das Steuerungsuntersystem ferner umfassen: (a) ein Spannungsskalierungsuntersystem, das geeignet ist, das skalierte Signal, das die mittlere Spannung an dem Ausgangsanschluss repräsentiert, durch die Skalierung eines Signals zu erzeugen, das repräsentiert, ob die mittlere Spannung an dem Leistungsausgangsanschluss innerhalb eines ersten vorbestimmten Wertebereichs liegt und (b) ein Stromskalierungsuntersystem, das geeignet ist, das skalierte Signal zu erzeugen, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, indem ein Signal skaliert wird, das repräsentiert, ob der mittlere Strom, der aus dem Ausgangsanschluss fließt, innerhalb eines zweiten vorbestimmten Wertebereichs liegt.
• (A7) Im mit (A6) bezeichneten Maximum Power Point Tracking-Controller kann das Stromskalierungsuntersystem ferner geeignet sein zu verhindern, dass ein Betrag des skalierten Signals, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, unterhalb eines minimalen Schwellenwertes fällt.
• (A8) Im mit (A7) bezeichneten Maximum Power Point Tracking-Controller kann das Stromskalierungsuntersystem ferner geeignet sein, dem skalierten Signal, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, einen positive Offset-Wert hinzuzufügen, wenn das Signal, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert, innerhalb eines Wertebereichs liegt.
• (A9) In einem beliebigen der mit (A6) bis (A8) bezeichneten Maximum Power Point Tracking-Controller kann das Steuerungsuntersystem ferner ein Stromfilter-Untersystem umfassen, das geeignet ist, das Signal, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, durch Filtern des Signals, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, zu erzeugen.
• (A10) In einem beliebigen der mit (A6) bis (A10) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner ein Spannungsfilteruntersystem umfassen, das geeignet ist, das die mittlere Spannung am Ausgangsport repräsentierende Signal durch das Filtern eines die Spannung an dem Ausgangsanschluss repräsentierenden Signals zu erzeugen.
• (A11) In einem beliebigen der mit (A2) bis (A10) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein, eine Verringerung in dem Betrag der Bezugsspannung zu verhindern, wenn die Spannung an dem Eingangsanschluss unter einen zweiten Schwellenwert fällt.
• (A12) In einem beliebigen der mit (A2) bis (A10) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein, eine Verringerung in dem Betrag der Bezugsspannung zu verhindern, wenn dies dazu führen würde, dass die Spannung an dem Eingangsanschluss unter einen dritten Schwellenwert fällt.
• (A13) In einem beliebigen der mit (A2) bis (A12) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein, eine Erhöhung in dem Betrag der Bezugsspannung zu verhindern, wenn die Spannung an dem Eingangsanschluss über zweiten Schwellenwert steigt.
• (A14) In einem beliebigen der mit (A2) bis (A13) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein: (a) den Betrag der Referenzspannung um eine erste Schrittgröße zu verändern, um das Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert, wenn ein Befehl, ein Tastverhältnis der Steuerschaltvorrichtung zu steuern, unter einem fünften Schwellenwert liegt und (b) den Betrag der Referenzspannung um eine zweite Schrittgröße zu verändern, um das Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert, wenn ein Befehl, ein Tastverhältnis der Steuerschaltvorrichtung zu steuern, größer oder gleich einem sechsten Schwellenwert ist; wobei die zweite Schrittgröße kleiner ist als die erste Schrittgröße.
• (A15) Im mit (A14) bezeichneten Maximum Power Point Tracking-Controller kann der fünfte Schwellenwert gleich dem sechsten Schwellenwert sein.
• (A16) In einem beliebigen der mit (A2) bis (A15) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein: (a) den Betrag der Referenzspannung um eine dritte Schrittgröße zu verändern, um das Signal, das Leistung aus dem Ausgangsanschluss repräsentiert, zu maximieren, wenn eine Differenz in dem Signal, das Leistung aus dem Ausgangsanschluss repräsentiert, zwischen aufeinanderfolgenden Änderungen in dem Betrag der Referenzspannung unter einem siebten Schwellenwert liegt und (b) den Betrag der Referenzspannung um eine vierte Schrittgröße zu verändern, um das Signal, das Leistung aus dem Ausgangsanschluss repräsentiert, zu maximieren, wenn eine Differenz in dem Signal, das Leistung aus dem Ausgangsanschluss repräsentiert, zwischen aufeinanderfolgenden Änderungen in dem Betrag der Referenzspannung größer oder gleich einem achten Schwellenwert ist; wobei die vierte Schrittgröße größer ist als die dritte Schrittgröße.
• (A17) Im mit (A16) bezeichneten Maximum Power Point Tracking-Controller kann der siebte Schwellenwert gleich dem achten Schwellenwert sein.
• (A18) In einem beliebigen der mit (A2) bis (A17) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein: (a) den Betrag der Referenzspannung mit einer ersten Schrittgeschwindigkeit zu verändern, um das Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert, wenn ein Befehl, ein Tastverhältnis der Steuerschaltvorrichtung zu steuern, in einem ersten Wertebereich liegt und (b) den Betrag der Referenzspannung mit einer zweiten Schrittgeschwindigkeit zu verändern, um das Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert, wenn der Befehl, das Tastverhältnis der Steuerschaltvorrichtung zu steuern, in einem zweiten Wertebereich liegt; wobei die zweite Geschwindigkeit größer ist als die erste Geschwindigkeit.
• (A19) Im mit (A18) bezeichneten Maximum Power Point Tracking-Controller kann der erste Wertebereich einen Befehl repräsentieren, dass das Tastverhältnis der Steuerschaltvorrichtung zwischen null und hundert Prozent liegt, und der zweite Wertebereich kann einen Befehl repräsentieren, dass das Tastverhältnis der Steuerschaltvorrichtung kleiner als Null oder größer als hundert Prozent ist.
• (A20) In einem beliebigen der mit (A2) bis (A19) bezeichneten Maximum Power Point Tracking-Controller kann das Steuerungsuntersystem ferner geeignet sein, den Betrag der Referenzspannung zu erhöhen als Reaktion auf das Fallen des Betrags der Spannung an dem Eingangsanschluss unter einen neunten Schwellenwert.
• (A21) In einem beliebigen der mit (A2) bis (A21) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein, bei der Inbetriebnahme des Schaltkreises einen anfänglichen Betrag der Referenzspannung zumindest teilweise auf Basis eines Anfangswerts der Spannung an dem Eingangsanschluss einzustellen.
• (A22) Im mit (A21) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein, bei der Inbetriebnahme des Schaltkreises den anfänglichen Betrag der Referenzspannung auf eine Bruchteil des Anfangswerts der Spannung an dem Eingangsanschluss einzustellen.
• (A23) In einem beliebigen der mit (A2) bis (A22) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein, den Betrag der Referenzspannung als Reaktion auf das Signal, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, das anzeigt, dass ein Betrag des aus dem Ausgangsanschluss fließenden Stroms unter einem zehnten Schwellenwert gefallen ist, zu reduzieren.
• (A24) Im mit (A23) bezeichneten Maximum Power Point Tracking-Controller kann das Steuersystem ferner geeignet sein, die Steuerschaltvorrichtung bei einem festen Tastverhältnis als Reaktion auf das Signal, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, dass ein Betrag des aus dem Ausgangsanschluss fließenden Stroms unter einen elften Schwellenwert gefallen ist, zu betreiben, wobei der elfte Schwellenwert niedriger als der zehnte Schwellenwert ist.
• (A25) In einem beliebigen der mit (A1) bis (A24) bezeichneten Maximum Power Point Tracking-Controller kann die Steuerschaltvorrichtung elektrisch zwischen einer ersten Klemme des Eingangsanschlusses und einer ersten Klemme des Ausgangsanschlusses gekoppelt sein und kann der Maximum Power Point Tracking-Controller ferner eine Freilaufvorrichtung umfassen, die zwischen der ersten Klemme des Ausgangsanschlusses und einer zweiten Klemme des Ausgangsanschlusses elektrisch gekoppelt ist, wobei die Freilaufvorrichtung geeignet ist, einen Pfad für den Stromfluss zwischen den ersten und zweiten Klemmen des Ausgangsanschlusses zur Verfügung zu stellen, wenn die Steuerschaltvorrichtung sich in ihrem nicht leitenden Zustand befindet.
• (A26) In einem beliebigen der mit (A1) bis (A25) bezeichneten Maximum Power Point Tracking-Controller können die Steuerschaltvorrichtung und das Steuerungsuntersystem Teil einer gemeinsamen integrierten Schaltung sein.
• (A27) In einem beliebigen der mit (A1) bis (A26) bezeichneten Maximum Power Point Tracking-Controller: (a) kann die Steuerschaltvorrichtung einen dynamisch angepassten Feldeffekttransistor umfassen; (b) kann der Maximum Power Point Tracking-Controller ferner ein Strom-Rekonstruktor-Untersystem umfassen, das geeignet ist, das Signal, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, zu erzeugen, wobei das Strom-Rekonstruktor-Untersystem eine Verstärkung hat, die zumindest teilweise abhängig von einer Größe des dynamisch angepassten Feldeffekttransistors ist und (c) kann das Steuerungsuntersystem geeignet sein, eine Größe des dynamisch angepassten Feldeffekttransistors zu verringern, wenn ein Betrag des Signals, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, unter einen zwölften Schwellenwert fällt, und damit die Verstärkung des Strom-Rekonstruktor-Untersystem zu erhöhen.
• (B1) Ein Stromversorgungssystem kann eine elektrische Stromquelle und einen Maximum Power Point Tracking-Controller umfassen. Der Maximum Power Point Tracking-Controller kann einen Eingangsanschluss zur elektrischen Kopplung mit einer elektrischen Stromquelle, einen Ausgangsanschluss zur elektrischen Kopplung mit einer Last, eine Steuerschaltvorrichtung und ein Steuerungsuntersystem umfassen. Die Steuerschaltvorrichtung kann geeignet sein, wiederholt zwischen ihrem leitenden und nicht leitenden Zustand umzuschalten, um Leistung von dem Eingangsanschluss zu dem Ausgangsanschluss zu übertragen. Das Steuerungsuntersystem kann geeignet sein, das Schalten der Steuerschaltvorrichtung zu steuern, um eine Spannung über den Eingangsanschluss zu regeln, wobei die Regelung zumindest teilweise auf einem Signal basiert, das einen Stromfluss aus dem Ausgangsanschluss repräsentiert, um ein Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert.
• (B2) In dem mit (B1) bezeichneten Stromversorgungssystem kann die elektrische Stromquelle eine photovoltaische Vorrichtung umfassen.
• (B3) In dem mit (B2) bezeichneten Stromversorgungssystem kann die photovoltaische Vorrichtung eine Mehrzahl von miteinander verbundenen photovoltaischen Zellen umfassen.
• (B4) In einen der mit (B2) oder (B3) bezeichneten Stromversorgungssysteme kann die photovoltaische Vorrichtung eine Mehrfach-Photovoltaikzelle umfassen.
• (B5) In einem beliebigen der mit (B1) bis (B4) bezeichneten Stromversorgungssysteme kann das Steuerungsuntersystem geeignet sein, das Schalten der Steuerschaltvorrichtung teilweise auf dem Signal zu basieren, das Strom aus dem Ausgangsanschluss und eine Differenz zwischen der Spannung an dem Eingangsanschluss und einer Referenzspannung repräsentiert.
• (B6) In dem mit (B5) bezeichneten Stromversorgungssystem kann das Steuerungsuntersystem ferner geeignet sein, einen Betrag der Referenzspannung zu variieren, um das Signal, das Leistung aus dem Ausgangsanschluss repräsentiert, zu maximieren.
• (B7) Im einem der mit (B5) oder (B6) bezeichneten Stromversorgungssysteme kann das Steuerungsuntersystem ferner geeignet sein, das Schalten der Steuerschaltvorrichtung teilweise auf Basis eines Fehlersignals zu steuern, wobei das Fehlersignal durch –Kv·(Vin – Vref) + Ki·Io gegeben ist, wobei Kv ein erster Skalierungsfaktor, Ki ein zweiter Skalierungsfaktor, Vin die Spannung am Eingangsanschluss, Vref die Referenzspannung und Io das Signal ist, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert.
• (B8) In einem beliebigen der mit (B1) bis (B7) bezeichneten Stromversorgungssysteme kann die Steuerschaltvorrichtung elektrisch zwischen einer ersten Klemme des Eingangsanschlusses und einer ersten Klemme des Ausgangsanschlusses gekoppelt sein, wobei der Maximum Power Point Tracking-Controller ferner eine Freilaufvorrichtung umfasst, die zwischen der ersten Klemme des Ausgangsanschlusses und einer zweiten Klemme des Ausgangsanschlusses elektrisch gekoppelt ist, wobei die Freilaufvorrichtung geeignet ist, einen Pfad für den Stromfluss zwischen den ersten und zweiten Klemmen des Ausgangsanschlusses zur Verfügung zu stellen, wenn die Steuerschaltvorrichtung sich in ihrem nicht leitenden Zustand befindet.
• (B9) In einem beliebigen der mit (B1) bis (B8) bezeichneten Stromversorgungssysteme kann das Steuerungsuntersystem einen Multiplizierer umfassen, der geeignet ist, das Signal, das Leistung aus dem Ausgangsanschluss repräsentiert, aus einem Produkt eines skalierten Signals, das eine mittlere Spannung an dem Ausgangsanschluss repräsentiert, und eines skalierten Signals, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, zu bestimmen.
• (B10) In dem mit (B9) bezeichneten Stromversorgungssystem kann das Steuerungsuntersystem ferner geeignet sein zu verhindern, dass ein Betrag des skalierten Signals, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, unterhalb eines minimalen Schwellenwertes fällt.
• (B11) In einem beliebigen der mit (B1) bis (B10) bezeichneten Stromversorgungssysteme können die Steuerschaltvorrichtung und das Steuerungsuntersystem Teil einer gemeinsamen integrierten Schaltung sein.
• (B12) In dem mit (B11) bezeichneten Stromversorgungssystem können sich die gemeinsame integrierte Schaltung und die photovoltaische Vorrichtung zusammen in einem Gehäuse befinden.
• (B13) Ein beliebiges der mit (B1) bis (B12) bezeichneten Stromversorgungssysteme kann ferner ein oder mehrere zusätzliche Maximum Power Point Tracking-Controller umfassen, die elektrisch mit dem Ausgangsanschluss und der Last in Reihe geschaltet sind, wobei jeder zusätzliche Maximum Power Point Tracking-Controller geeignet ist, Strom von einer entsprechenden zusätzlichen elektrischen Stromquelle an die Last zu übertragen.
• (C1) Verfahren zum Betreiben eines Maximum Power Point Tracking-Controllers, umfassend einen Eingangsanschluss zur elektrischen Kopplung mit einer elektrischen Stromquelle und einen Ausgangsanschluss zur elektrischen Kopplung mit einer Last, das folgenden Schritte umfassen kann: (a) wiederholtes Schalten einer Steuerschaltvorrichtung des Maximum Power Point Tracking-Controllers zwischen ihrem leitenden und nicht leitenden Zustand, um Leistung von dem Eingangsanschluss an den Ausgangsanschluss zu übertragen und (b) Steuern des Schaltens der Steuerschaltvorrichtung zumindest teilweise auf Basis eines Signals, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, um einen Betrag einer Spannung an dem Eingangsanschluss so zu regeln, dass ein Signal, das Leistung aus dem Ausgangsanschluss repräsentiert, maximiert wird.
• (C2) Das mit (C1) bezeichnete Verfahren kann ferner das Steuern des Schaltens der Steuerschaltvorrichtung teilweise auf Basis des Signals umfassen, das den aus dem Ausgangsanschluss fließenden Strom und eine Differenz zwischen dem Betrag der Spannung an dem Eingangsanschluss und einer Referenzspannung repräsentiert.
• (C3) Das mit (C2) bezeichnete Verfahren kann ferner das Variieren eines Betrags der Referenzspannung umfassen, um das die Leistung aus dem Ausgangsanschluss repräsentierende Signal zu maximieren.
• (C4) Eines der mit (C2) oder (C3) bezeichneten Verfahren kann ferner die Steuerung des Schaltens der Steuerschaltvorrichtung teilweise auf Basis eines Fehlersignals umfassen, wobei das Fehlersignal durch –Kv·(Vin – Vref) + Ki·Io gegeben ist, wobei Kv ein erster Skalierungsfaktor, Ki ein zweiter Skalierungsfaktor, Vin die Spannung am Eingangsanschluss, Vref die Referenzspannung und Io das Signal ist, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert.
• (C5) Ein beliebiges der mit (C2) bis (C4) bezeichneten Verfahren kann ferner das Bestimmen des Signals umfassen, das die Leistung aus dem Ausgangsanschluss repräsentiert, durch Multiplikation eines Signals, das die mittlere Spannung an dem Ausgangsanschluss repräsentiert, mit einem Signal, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, unter Verwendung eines Multiplizierers.
• (C6) Das mit (C5) bezeichnete Verfahren kann ferner das Filtern des Signals umfassen, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, um das Signal zu erzeugen, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert.
• (C7) Eines der mit (C5) oder (C6) bezeichneten Verfahren kann ferner das Filtern eines Signals umfassen, das die Spannung an dem Ausgangsanschluss repräsentiert, um das Signal zu erzeugen, das die mittlere an dem Ausgangsanschluss anliegende Spannung repräsentiert.
• (C8) Eines der mit (C5) bis (C7) bezeichneten Verfahren kann ferner das Verhindern umfassen, dass ein Betrag des Signals, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, unter einen minimalen Schwellenwert fällt.
• (C9) Ein beliebiges der mit (C2) bis (C8) bezeichneten Verfahren kann ferner umfassen: (a) Speichern eines ersten Abtastwertes des Signals, das die Leistung aus dem Ausgangsanschluss repräsentiert, wenn ein Tastverhältnis der Steuerschaltvorrichtung hundert Prozent beträgt; (b) Verringern des Betrags der Referenzspannung um einen ersten Betrag; (c) Speichern eines zweiten Abtastwertes des Signals, das die Leistung aus dem Ausgangsanschluss repräsentiert, nach dem Schritt des Verringerns des Betrags der Referenzspannung um den ersten Betrag; (d) Vergleichen eines ersten Abtastwertes des Signals, das die Leistung aus dem Ausgangsanschluss repräsentiert, mit dem zweiten Abtastwert des Signals, das die Leistung aus dem Ausgangsanschluss repräsentiert; (e) Erhöhen des Betrags der Referenzspannung, wenn der erste Abtastwert des Signals, das die Leistung aus dem Ausgangsanschluss repräsentiert, größer ist als der zweite Abtastwert des Signals, das die Leistung aus dem Ausgangsanschluss repräsentiert und (f) Verringern des Betrags der Referenzspannung, wenn der zweite Abtastwert des Signals, das die Leistung aus dem Ausgangsanschluss repräsentiert, größer ist als der erste Abtastwert des Signals, das die Leistung aus dem Ausgangsanschluss repräsentiert.
• (C10) Ein beliebiges der mit (C2) bis (C9) bezeichneten Verfahren kann ferner das Verhindern einer Verringerung des Betrags der Referenzspannung umfassen, wenn die Spannung an dem Eingangsanschluss unter einen zweiten Schwellenwert fällt.
• (C11) Ein beliebiges der mit (C2) bis (C10) bezeichneten Verfahren kann ferner das Verhindern einer Erhöhung des Betrags der Referenzspannung umfassen, wenn die Spannung an dem Eingangsanschluss über einen dritten Schwellenwert steigt.
• (C12) Ein beliebiges der mit (C2) bis (C11) bezeichneten Verfahren kann ferner umfassen: (a) Ändern des Betrags der Referenzspannung um eine erste Schrittgröße, um das Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert, wenn ein Befehl, ein Tastverhältnis der Steuerschaltvorrichtung zu steuern, unter einem vierten Schwellenwert liegt und (b) Ändern des Betrags der Referenzspannung um eine zweite Schrittgröße, um das Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert, wenn ein Befehl, ein Tastverhältnis der Steuerschaltvorrichtung zu steuern, größer oder gleich einem fünften Schwellenwert ist; wobei die zweite Schrittgröße kleiner ist als die erste Schrittgröße.
• (C13) Ein beliebiges der mit (C2) bis (C11) bezeichneten Verfahren kann ferner umfassen: (a) Ändern des Betrags der Referenzspannung mit einer ersten Schrittgeschwindigkeit, um das Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert, wenn ein Befehl, ein Tastverhältnis der Steuerschaltvorrichtung zu steuern, in einem ersten Wertebereich liegt und (b) Ändern des Betrags der Referenzspannung mit einer zweiten Schrittgeschwindigkeit, um das Signal zu maximieren, das Leistung aus dem Ausgangsanschluss repräsentiert, wenn der Befehl, das Tastverhältnis der Steuerschaltvorrichtung zu steuern, in einem zweiten Wertebereich liegt; wobei die zweite Geschwindigkeit größer ist als die erste Geschwindigkeit.
• (C14) In dem mit (C13) bezeichneten Verfahren kann der erste Wertebereich repräsentieren, dass dem Tastverhältnis der Steuerschaltvorrichtung befohlen wird, zwischen null und hundert Prozent zu liegen, und kann der zweite Wertebereich repräsentieren, dass dem Tastverhältnis der Steuerschaltvorrichtung befohlen wird, kleiner als Null oder größer als hundert Prozent zu sein.
• (C15) Ein beliebiges der mit (C2) bis (C14) bezeichneten Verfahren kann ferner eine Erhöhung des Betrags der Referenzspannung umfassen als Reaktion auf das Fallen des Betrags der Spannung an dem Eingangsanschluss unter einen sechsten Schwellenwert.
• (C16) Ein beliebiges der mit (C2) bis (C15) bezeichneten Verfahren kann ferner das Einstellen eines anfänglichen Betrags der Referenzspannung umfassen zumindest teilweise auf Basis eines Anfangswerts der Spannung an dem Eingangsanschluss bei der Inbetriebnahme des Schaltkreises.
• (C17) Das mit (C16) bezeichnete Verfahren kann ferner das Einstellen des anfänglichen Betrags der Referenzspannung auf einen Bruchteil der Spannung an dem Eingangsanschluss bei der Inbetriebnahme des Schaltkreises umfassen.
• (C18) Eines der mit (C2) bis (C17) bezeichneten Verfahren kann ferner das Verringern des Betrags der Referenzspannung umfassen als Reaktion auf das Fallen eines Betrags des Stroms, der aus dem Ausgangsanschluss fließt, unter einen siebten Schwellenwert.
• (C19) Das mit (C18) bezeichnete Verfahren kann ferner das Betreiben der Steuerschaltvorrichtung mit einem festen Tastverhältnis umfassen als Reaktion auf das Fallen eines Betrags des aus dem Ausgangsanschluss fließenden Stroms unter einen achten Schwellenwert, wobei der achte Schwellenwert niedriger als der siebte Schwellenwert ist.
• (C20) Ein beliebiges der mit (C1) bis (C19) bezeichneten Verfahren kann ferner umfassen: (a) Erzeugen des Signals, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, unter Verwendung eines Strom-Rekonstruktor-Untersystems und (b) Verringern einer Größe eines dynamisch angepassten Feldeffekttransistors der Steuerschaltvorrichtung, wenn ein Betrag des Signals, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, unter einen neunten Schwellenwert fällt, und damit eine Erhöhung der Verstärkung des Strom-Rekonstruktor-Untersystems.
• (D1) Ein elektronischer Filter kann umfassen: (a) ein Integrator-Untersystem, das geeignet ist, in einer bipolaren Domäne betrieben zu werden, um eine Wechselstromkomponente eines Eingangssignals zu filtern und (b) eine Transkonduktanz-Schaltung, die geeignet ist, in einer unipolaren Domäne betrieben zu werden, um ein Ausgangsstromsignal zu erzeugen, das proportional zu einem Mittelwert des Eingangsstromsignals ist.
• (D2) In dem mit (D1) bezeichneten elektronischen Filter: kann das Integrator-Untersystem geeignet sein, ein Integratorsignal zu erzeugen, das den Mittelwert des Eingangsstromsignals repräsentiert und (b) kann die Transkonduktanz-Schaltung einen ersten Transkonduktanz-Verstärker umfassen, der geeignet ist, das Ausgangsstromsignal aus dem Integratorsignal zu erzeugen.
• (D3) In dem mit (D2) bezeichneten elektronischen Filter kann die Transkonduktanz-Schaltung ferner einen zweiten Transkonduktanz-Verstärker umfassen, der geeignet ist, aus dem Integratorsignal eine Gleichstromkomponente des Eingangsstromsignals zu erzeugen.
• (D4) In einem beliebigen der mit (D1) bis (D3) bezeichneten elektronischen Filter kann das Integrator-Untersystem umfassen: (a) einen Integrator mit einer invertierenden Eingangsklemme und einer nicht-invertierenden Eingangsklemme und (b) eine Widerstandsvorrichtung, die über die Eingangsklemmen des Integrators elektrisch gekoppelt ist; wobei die nichtinvertierende Eingangsklemme des Integrators mit einem Referenzknoten des elektronischen Filters über eine Spannungsquelle elektrisch gekoppelt ist, die invertierende Eingangsklemme des Integrators mit einem ersten Knoten elektrisch gekoppelt ist und der elektronische Filter so angeordnet ist, dass das Eingangsstromsignal aus dem ersten Knoten fließt.
• (E1) Ein Signal-Skalierungssystem kann umfassen (a) ein Transkonduktanz-Untersystem, das geeignet ist, ein Eingangsspannungssignal in ein Ausgangsstromsignal umzuwandeln, wobei das Transkonduktanz-Untersystem einen programmierbaren Widerstand umfasst, der geeignet ist, eine Verstärkung des Transkonduktanz-Untersystems einzustellen und (b) eine Steuerlogik, die geeignet ist, einen Widerstand des programmierbaren Widerstands einzustellen, um die Verstärkung des Transkonduktanz-Untersystems so einzustellen, dass ein Betrag des Ausgangsstromsignals mindestens so groß wie ein erster Schwellenwert ist.
• (E2) In dem mit (E1) bezeichneten Signal-Skalierungssystem kann das Transkonduktanz-Untersystem ferner umfassen: (a) einen Transistor, der mit dem programmierbaren Widerstand elektrisch gekoppelt ist und (b) einen Verstärker, der geeignet ist, den Transistor zu steuern, um eine Spannung über den programmierbaren Widerstand als Reaktion auf das Eingangsspannungssignal zu steuern.
• (E3) In einem beliebigen der mit (E1) oder (E2) bezeichneten Signalskalierungssysteme kann die Steuerlogik ferner geeignet sein, eine Verstärkung des Transkonduktanz-Untersystems als Reaktion auf ein erstes externes Signal auf einen Mindestwert einzustellen.
• (E4) In einem beliebigen der mit (E1) bis (E3) bezeichneten Signal-Skalierungssysteme kann die Steuerlogik ferner geeignet sein, die Verstärkung des Transkonduktanz-Untersystems als Reaktion auf ein zweites externes Signal zu inkrementieren, bis der Betrag des Ausgangsstromsignals mindestens so groß wie der erste Schwellenwert ist.
• (E5) In einem beliebigen der mit (E1) bis (E4) bezeichneten Signal-Skalierungssysteme kann die Steuerlogik ferner geeignet sein zu erkennen, wenn der Betrag des Ausgangsstromsignals einen zweiten Schwellenwert überschreitet, wobei der zweite Schwellenwert größer als der erste Schwellenwert ist.
• (E6) In dem mit (E5) bezeichneten Signal-Skalierungssystem kann die Steuerlogik ferner geeignet sein, ein Signal zu erzeugen, das anzeigt, dass der Betrag des Ausgangsstromsignals den zweiten Schwellenwert übersteigt.
• (E7) In einem beliebigen der mit (E1) bis (E6) bezeichneten Signalskalierungssysteme kann das Transkonduktanz-System ferner einen Stromspiegel umfassen, der geeignet ist, das Ausgangsstromsignal als Reaktion auf Stromfluss durch den programmierbaren Widerstand zu erzeugen.
• (F1) Ein Signalpegelwandler zum Verschieben komplementärer Eingangsspannungssignale einer ersten Stromversorgungsdomäne in komplementäre Ausgangsspannungssignale einer zweiten Stromversorgungsdomäne kann umfassen: (a) eine Transkonduktanzstufe in der ersten Stromversorgungsdomäne, die geeignet ist, komplementäre Stromsignale als Reaktion auf die komplementäre Eingangsspannungssignale zu erzeugen und (b) eine Lastschaltung in der zweiten Stromversorgungsdomäne, die geeignet ist, die komplementären Ausgangsspannungssignale als Reaktion auf die komplementären Stromsignale zu erzeugen, wobei die Lastschaltung eine erste und eine zweite Inverter-Schaltung umfasst, die geeignet sind, die komplementären Ausgangsspannungssignale als Reaktion auf die komplementären Stromsignale zu erzeugen.
• (F2) In dem mit (F1) bezeichneten Signalpegelwandler: kann eine High-Side-Schiene der ersten Inverter-Schaltung mit einer High-Side-Schiene der zweiten Stromversorgungsdomäne durch einen ersten Transistor elektrisch gekoppelt sein; kann eine High-Side-Schiene der zweiten Inverter-Schaltung mit einer High-Side-Schiene der zweiten Stromversorgungsdomäne durch einen zweiten Transistor elektrisch gekoppelt sein und können der erste und zweite Transistor kreuzgekoppelt sein.
• (F3) In dem mit (F2) bezeichneten Signalpegelwandler kann jede der Inverter-Schaltungen umfassen: (a) einen High-Side-Transistor, der zwischen der High-Side-Schiene der Inverter-Schaltung und einem Ausgangsknoten der Inverter-Schaltung elektrisch gekoppelt ist und (b) einen Low-Side-Transistor, der zwischen dem Ausgangsknoten der Inverter-Schaltung und einer Referenzschiene der zweiten Stromversorgungsdomäne elektrisch gekoppelt ist; wobei der High-Side-Transistor geeignet ist, den Ausgangsknoten der Inverter-Schaltung zu mindestens fünfzig Prozent des elektrisches Potentials der High-Side-Schiene des Inverters in Bezug auf die Referenzschiene der zweiten Stromversorgungsdomäne zu ziehen, wenn der Low-Side-Transistor sich im leitenden Zustand befindet.
• (F4) In einem der mit (F2) oder (F3) bezeichneten Signalpegelwandler kann die Transkonduktanzstufe geeignet sein, Strom in die High-Side-Schiene der ersten und zweiten Inverter-Schaltungen zu treiben, wenn ein elektrisches Potential einer Referenzschiene der zweiten Stromversorgungsdomäne unter einem elektrischen Potential einer Referenzschiene der ersten Stromversorgungsdomäne liegt.
• (G1) Ein System zum Bestimmen eines Signals, das Leistung in einem Maximum Power Point Tracking-Controller (MPPT-Controller) repräsentiert, kann umfassen: (a) ein Spannungsfilter-Untersystem, das geeignet ist, ein Signal zu erzeugen, das die mittlere Spannung an einem Ausgangsanschluss des MPPT-Controllers repräsentiert durch das Filtern eines Signals, das die Spannung an dem Ausgangsanschluss repräsentiert; (b) ein Stromfilter-Untersystem, das geeignet ist, ein Signal zu erzeugen, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert durch das Filtern eines Signals, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert; (c) ein Spannungsskalierungsuntersystem, das geeignet ist, ein skaliertes Signal, das die mittlere Spannung an dem Ausgangsanschluss repräsentiert, durch die Skalierung des Signals zu erzeugen, das repräsentiert, ob die mittlere Spannung an dem Ausgangsanschluss innerhalb eines ersten vorbestimmten Wertebereichs liegt; (d) ein Stromskalierungsuntersystem, das geeignet ist, ein skaliertes Signal zu erzeugen, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, indem das Signal skaliert wird, das repräsentiert, ob der mittlere Strom, der aus dem Ausgangsanschluss fließt, innerhalb eines zweiten vorbestimmten Wertebereichs liegt und (e) einen Multiplizierer, der geeignet ist, das Signal, das Leistung repräsentiert, aus einem Produkt des skalierten Signals, das die mittlere Spannung an dem Ausgangsanschluss repräsentiert, und dem skalierten Signal, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert, zu bestimmen.
• (G2) In dem mit (G1) bezeichneten System kann der Multiplizierer umfassen: (a) einen ersten Eingangsanschluss, der geeignet ist, das skalierte Signal zu empfangen, das die mittlere Spannung an dem Ausgangsanschluss repräsentiert; (b) einen zweiten Eingangsanschluss, der geeignet ist, das skalierte Signal zu empfangen, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert; (c) einen Ausgangsanschluss, der geeignet ist, das Signal vorzusehen, das den Strom repräsentiert; (d) einen ersten Feldeffekttransistor, der mit dem ersten Eingangsanschluss elektrisch in Reihe geschaltet ist; (e) einen zweiten Feldeffekttransistor, der mit dem zweiten Eingangsanschluss elektrisch in Reihe geschaltet ist; (f) einen dritten Feldeffekttransistor, der mit dem Ausgangsanschluss elektrisch in Reihe geschaltet ist und (g) eine Steuerschaltung, die geeignet ist, den ersten, zweiten und dritten Feldeffekttransistor jeweils so zu steuern, dass ein Betrag des Stroms, der in den Ausgangsanschluss fließt, proportional zu einem Produkt von (1) einem Betrag des in den ersten Eingangsanschluss fließenden Stroms und (2) einem Betrag des in den zweiten Eingangsanschluss fließenden Stroms ist.
• (G3) In dem mit (G2) bezeichneten System kann ein Gate des ersten Feldeffekttransistors elektrisch mit einem Gate des dritten Feldeffekttransistors gekoppelt sein.
• (G4) Das mit (G3) bezeichnete System kann ferner umfassen: (a) einen vierten und fünften Feldeffekttransistor, die einen Stromspiegel bilden, der derart ausgelegt ist, dass ein Betrag eines Drain-zu-Source-Stroms, der durch den fünften Feldeffekttransistor fließt, gleich Iref ist, und ein Betrag eines Drainzu-Source-Stroms, der durch den vierten Feldeffekttransistor fließt, gleich Iref/m ist und (b) einen ersten Verstärker, der geeignet ist, das Gate des ersten Feldeffekttransistors so zu steuern, dass eine Spannung an dem ersten Feldeffekttransistor gleich einer Spannung an dem vierten Feldeffekttransistor ist.
• (G5) In dem mit (G4) bezeichneten System kann ein Gate des zweiten Feldeffekttransistors mit einem Gate des vierten Feldeffekttransistors und einem Gate des fünften Feldeffekttransistors elektrisch gekoppelt sein.
• (G6) In einem der mit (G4) oder (G5) bezeichneten Systeme kann der zweite Feldeffekttransistor einen Kanalwiderstand von R/m haben und der vierte und fünfte Feldeffekttransistor jeweils einen Kanalwiderstand von R haben, wenn der zweite, vierte und fünfte Transistor durch eine gemeinsame Gatezu-Source-Spannung getrieben werden.
• (G7) Ein beliebiges der mit (G2) bis (G6) bezeichneten Systeme kann ferner einen zweiten Verstärker und einen sechsten Transistor umfassen, der ausgelegt ist, den Betrag des Stroms, der in den Ausgangsanschluss fließt, so zu steuern, dass eine Spannung an dem zweiten Feldeffekttransistor gleich einer Spannung an dem dritten Feldeffekttransistor ist.
• (G8) In einem beliebigen der mit (G1) bis (G7) bezeichneten Systeme kann das Stromskalierungsuntersystem umfassen: (a) ein Transkonduktanz-Untersystem, das geeignet ist, das Signal, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert, in das skalierte Signal umzuwandeln, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert, wobei das Transkonduktanz-Untersystem einen programmierbaren Widerstand umfasst, der geeignet ist, eine Verstärkung des Transkonduktanz-Untersystem einzustellen und (b) eine Steuerlogik, die geeignet ist, einen Widerstand des programmierbaren Widerstands einzustellen, um die Verstärkung des Transkonduktanz-Untersystems so einzustellen, dass ein Betrag des skalierten Signals, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert, mindestens so groß wie ein erster Schwellenwert ist.
• (G9) In dem mit (G8) bezeichneten System kann das Transkonduktanz-Untersystem ferner umfassen: (a) einen Transistor, der mit dem programmierbaren Widerstand elektrisch gekoppelt ist und (b) einen Verstärker, der geeignet ist, den Transistor zu steuern, um eine Spannung an dem programmierbaren Widerstand als Reaktion auf das Signal, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert, zu steuern.
• (G10) In einem beliebigen der mit (G8) oder (G9) bezeichneten Systeme kann die Steuerlogik ferner geeignet sein, eine Verstärkung des Transkonduktanz-Untersystems als Reaktion auf ein erstes externes Signal auf einen Mindestwert einzustellen.
• (G11) In einem beliebigen der mit (G8) bis (G10) bezeichneten Systeme kann die Steuerlogik ferner geeignet sein, die Verstärkung des Transkonduktanz-Untersystems als Reaktion auf ein zweites externes Signal zu inkrementieren, bis der Betrag des skalierten Signals, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, mindestens so groß wie der erste Schwellenwert ist.
• (G12) In einem beliebigen der mit (G8) bis (G11) bezeichneten Systeme kann das Transkonduktanz-Untersystem ferner einen Stromspiegel umfassen, der geeignet ist, das skalierte Signals, das den aus dem Ausgangsanschluss fließenden mittleren Strom repräsentiert, als Reaktion auf den durch den programmierbaren Widerstand fließenden Strom zu erzeugen.
• (G13) In einem beliebigen der mit (G1) bis (G12) bezeichneten Systeme kann das Stromfilteruntersystem umfassen: (a) ein Integrator-Untersystem, das geeignet ist, in einer bipolaren Domäne betrieben zu werden, um eine Wechselstromkomponente des Signals zu filtern, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert und (b) eine Transkonduktanz-Schaltung, die geeignet ist, in einer unipolaren Domäne betrieben zu werden, um das Signal, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert, aus einem mittleren Wert des Signals zu erzeugen, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert.
• (G14) In dem mit (G13) bezeichneten System: kann das Integrator-Untersystem geeignet sein, ein Integratorsignal zu erzeugen, das den Mittelwert des Signals repräsentiert, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, und kann die Transkonduktanz-Schaltung einen ersten Transkonduktanz-Verstärker umfassen, der geeignet ist, das Signal, das den mittleren aus dem Ausgangsanschluss fließenden Strom repräsentiert, aus dem Integratorsignal zu erzeugen.
• (G15) In dem mit (G14) bezeichneten System kann die Transkonduktanz-Schaltung ferner einen zweiten Transkonduktanz-Verstärker umfassen, der geeignet ist, eine Gleichstromkomponente des Signals, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, aus dem Integratorsignal zu erzeugen.
• (G16) In einem beliebigen der mit (G13) bis (G15) bezeichneten Systeme kann das Integrator-Untersystem umfassen: (a) einen Integrator mit einer invertierenden Eingangsklemme und einer nicht-invertierenden Eingangsklemme; und (b) eine Widerstandsvorrichtung, die über die Eingangsklemmen des Integrators elektrisch gekoppelt ist; wobei die nicht-invertierende Eingangsklemme des Integrators mit einem Referenzknoten über eine Spannungsquelle elektrisch gekoppelt ist, die invertierende Eingangsklemme des Integrators mit einem ersten Knoten elektrisch gekoppelt ist und das Stromfilter-Untersystem so eingerichtet ist, dass das Signal, das den aus dem Ausgangsanschluss fließenden Strom repräsentiert, aus dem ersten Knoten fließt.
• (H1) Ein Multiplizierer kann umfassen: (a) einen ersten und einen zweiten Eingangsanschluss; (b) einen Ausgangsanschluss; (c) einen ersten Feldeffekttransistor, der mit dem ersten Eingangsanschluss elektrisch in Reihe geschaltet ist; (d) einen zweiten Feldeffekttransistor, der mit dem zweiten Eingangsanschluss elektrisch in Reihe geschaltet ist; (e) einen dritten Feldeffekttransistor, der mit dem Ausgangsanschluss elektrisch in Reihe geschaltet ist und (f) eine Steuerschaltung, die geeignet ist, den ersten, zweiten und dritten Feldeffekttransistor jeweils so zu steuern, dass ein Betrag des Stroms, der in den Ausgangsanschluss fließt, proportional zu einem Produkt von (1) einem Betrag des in den ersten Eingangsanschluss fließenden Stroms und (2) einem Betrag des in den zweiten Eingangsanschluss fließenden Stroms ist.
• (H2) In dem mit (H1) bezeichneten Multiplizierer kann ein Gate des ersten Feldeffekttransistors elektrisch mit einem Gate des dritten Feldeffekttransistors gekoppelt sein.
• (H3) Einer der mit (H1) oder (H2) bezeichneten Multiplizierer kann ferner umfassen: (a) einen vierten und fünften Feldeffekttransistor, die einen Stromspiegel bilden, der derart ausgelegt ist, dass ein Betrag eines Drain-zu-Source-Stroms, der durch den fünften Feldeffekttransistor fließt, gleich Iref ist, und ein Betrag eines Drain-zu-Source-Stroms, der durch den vierten Feldeffekttransistor fließt, gleich Iref/m ist und (b) einen ersten Verstärker, der geeignet ist, das Gate des ersten Feldeffekttransistors so zu steuern, dass eine Spannung an dem ersten Feldeffekttransistor gleich einer Spannung an dem vierten Feldeffekttransistor ist.
• (H4) In dem mit (H3) bezeichneten Multiplizierer kann ein Gate des zweiten Feldeffekttransistors mit einem Gate des vierten Feldeffekttransistors und einem Gate des fünften Feldeffekttransistors elektrisch gekoppelt sein.
• (H5) In einem der mit (H3) oder (H4) bezeichneten Multiplizierer kann der zweite Feldeffekttransistor einen Kanalwiderstand von R/m haben und der vierte und fünfte Feldeffekttransistor jeweils einen Kanalwiderstand von R haben, wenn der zweite, vierte und fünfte Transistor durch eine gemeinsame Gate-zu-Source-Spannung getrieben werden.
• (H6) Ein beliebiger der mit (H1) bis (H5) bezeichneten Multiplizierer kann ferner einen zweiten Verstärker und einen sechsten Transistor umfassen, der ausgelegt ist, den Betrag des Stroms, der in den Ausgangsanschluss fließt, so zu steuern, dass eine Spannung an dem zweiten Feldeffekttransistor gleich einer Spannung an dem dritten Feldeffekttransistor ist.

The features described above as well as the features claimed below may be combined in various ways without departing from the scope of the invention. The following examples illustrate some possible combinations:

• (A1) A maximum power point tracking controller may include an input terminal for electrical coupling to an electrical power source, an output terminal for electrical coupling to a load, a control switching device, and a control subsystem. The control switching device may be adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input port to the output port. The control subsystem may be adapted to control the switching of the control switching device to control a voltage across the input terminal, wherein the control is based, at least in part, on a signal representing a current flow from the output terminal to maximize a signal, the power from the Output terminal represents.
• (A2) In the maximum power point tracking controller (A1), the control subsystem may be further adapted to partially base the switching of the control switching device on the signal, the current from the output terminal, and a difference between the voltage at the input terminal and a reference voltage represents.
• (A3) In the maximum power point tracking controller labeled (A2), the control subsystem may further be adapted to vary an amount of the reference voltage to maximize the signal representing power from the output port.
• (A4) In the maximum power point tracking controller designated (A2) or A3), the control subsystem may be further adapted to control the switching of the control switching device partly based on an error signal, the error signal being represented by -Kv * (Vin-Vref) + Ki · Io where Kv is a first scaling factor, Ki is a second factor, Vin is the voltage at the input terminal, Vref is the reference voltage, and Io is the signal representing the current flowing out of the output terminal.
• (A5) In the maximum power point tracking controller labeled (A2) through (A4), the control subsystem may include a multiplier capable of expressing the signal representing power from the output port from a product of a scaled signal having a mean value Voltage at the output terminal, and a scaled signal representing the average current flowing from the output terminal.
• (A6) In the maximum power point tracking controller labeled (A5), the control subsystem may further comprise: (a) a voltage scaling subsystem that is capable of producing the scaled signal the average voltage at the output terminal represents, by the scaling of a signal representing whether the average voltage at the power output terminal is within a first predetermined range of values, and (b) a current scaling subsystem capable of producing the scaled signal represents the average current flowing out of the output terminal by scaling a signal representing whether the average current flowing out of the output terminal is within a second predetermined value range.
• (A7) In the maximum power point tracking controller labeled (A6), the power scaling subsystem may further be adapted to prevent an amount of the scaled signal representing the average current flowing out of the output port from falling below a minimum threshold.
• (A8) In the maximum power point tracking controller labeled (A7), the power scaling subsystem may further be adapted to add a positive offset value to the scaled signal representing the average current flowing out of the output port if the signal representing the middle one represents current flowing from the output terminal is within a range of values.
• (A9) In any one of the maximum power point tracking controllers labeled (A6) through (A8), the control subsystem may further include a current filter subsystem capable of passing the signal representing the average current flowing out of the output port Filtering the signal representing the average current flowing from the output terminal to produce.
• (A10) In any one of the maximum power point tracking controllers labeled (A6) through (A10), the control system may further include a voltage filter subsystem capable of detecting the signal representative of the average voltage at the output port by filtering the voltage across the output port To produce output terminal representing signal.
• (A11) In any one of the maximum power point tracking controllers (A2) through (A10), the control system may further be adapted to prevent a decrease in the amount of the reference voltage when the voltage at the input terminal falls below a second threshold ,
• (A12) In any one of the maximum power point tracking controllers labeled (A2) through (A10), the control system may further be adapted to prevent a decrease in the amount of the reference voltage, if that would cause the voltage on the Input terminal falls below a third threshold.
• (A13) In any of the maximum power point tracking controllers labeled (A2) through (A12), the control system may further be adapted to prevent an increase in the amount of the reference voltage when the voltage at the input terminal rises above the second threshold.
• (A14) In any of the maximum power point tracking controllers labeled (A2) through (A13), the control system may be further configured to: (a) vary the magnitude of the reference voltage by a first step size to maximize the signal Power from the output port represents when a command to control a duty cycle of the control switching device is below a fifth threshold and (b) to change the magnitude of the reference voltage by a second step size to maximize the signal representing power from the output port; when an instruction to control a duty cycle of the control switching device is greater than or equal to a sixth threshold; wherein the second step size is smaller than the first step size.
• (A15) In the maximum power point tracking controller labeled (A14), the fifth threshold may be equal to the sixth threshold.
• (A16) In any one of the Maximum Power Point Tracking Controllers (A2) through (A15), the control system may be further adapted to: (a) vary the magnitude of the reference voltage by a third step size, the signal, the power represents the output terminal, when a difference in the signal representing power from the output terminal is below a seventh threshold between successive changes in the magnitude of the reference voltage and (b) altering the magnitude of the reference voltage by a fourth step size maximizing the signal representing power from the output port when a difference in the signal representing power from the output port between successive changes in the magnitude of the reference voltage is greater than or equal to an eighth threshold; wherein the fourth step size is greater than the third step size.
• (A17) In the maximum power point tracking controller labeled (A16), the seventh threshold may be equal to the eighth threshold.
• (A18) In any of the maximum power point tracking controllers labeled (A2) through (A17), the control system may be further adapted to: (a) alter the magnitude of the reference voltage at a first pacing rate to maximize the signal Power from the output port represents when a command to control a duty cycle of the control switching device is in a first range of values; and (b) changing the magnitude of the reference voltage at a second pace to maximize the signal representing power from the output port; if the command to control the duty cycle of the control switching device is in a second range of values; wherein the second speed is greater than the first speed.
• (A19) In the maximum power point tracking controller (A18), the first range of values may represent a command that the duty ratio of the control switching device is between zero and one hundred percent, and the second value range may represent a command that the duty ratio of the control switching device is smaller is zero or greater than one hundred percent.
• (A20) In any one of the maximum power point tracking controllers (A2) through (A19), the control subsystem may further be adapted to increase the magnitude of the reference voltage in response to the amount of voltage at the input terminal falling below a ninth threshold.
• (A21) In any one of the maximum power point tracking controllers labeled (A2) through (A21), the control system may further be adapted, at power-up of the circuit, for an initial amount of the reference voltage based at least in part on an initial value of the voltage at the input terminal adjust.
• (A22) In the maximum power point tracking controller labeled (A21), the control system may further be adapted to set the initial magnitude of the reference voltage to a fraction of the initial value of the voltage at the input terminal upon start-up of the circuit.
• (A23) In any of the maximum power point tracking controllers labeled (A2) through (A22), the control system may further be adapted to display the magnitude of the reference voltage in response to the signal representing the current flowing out of the output terminal in that an amount of current flowing out of the output terminal has fallen below a tenth threshold.
• (A24) In the maximum power point tracking controller (A23), the control system may further be adapted to, at a fixed duty cycle, responsive to the signal representative of the current flowing out of the output terminal, extracting the amount from the output terminal current below an eleventh threshold, the eleventh threshold being lower than the tenth threshold.
• (A25) In any one of the maximum power point tracking controllers (A1) through (A24), the control switching device may be electrically coupled between a first terminal of the input terminal and a first terminal of the output terminal, and may also be the maximum power point tracking controller a freewheel device electrically coupled between the first terminal of the output terminal and a second terminal of the output terminal, the freewheel device being adapted to provide a path for current flow between the first and second terminals of the output terminal when the control switching device is in its non-conductive state.
• (A26) In any one of the maximum power point tracking controllers (A1) to (A25), the control switching device and the control subsystem may be part of a common integrated circuit.
• (A27) In any one of the maximum power point tracking controllers (A1) to (A26): (a) the control switching device may comprise a dynamically adjusted field effect transistor; (b) the maximum power point tracking controller may further comprise a current reconstructor subsystem adapted to generate the signal representing the current flowing out of the output terminal, the current reconstructor subsystem having a gain, which is at least partially dependent on a size of the dynamically adjusted field effect transistor, and (c) the control subsystem may be adapted to reduce a size of the dynamically adjusted field effect transistor when an amount of the signal representing the current flowing out of the output terminal is below a twelfth threshold falls, thereby increasing the gain of the current-reconstructor subsystem.
• (B1) A power system may include an electrical power source and a maximum power point tracking controller. The maximum power point tracking controller may include an input port for electrical coupling to an electrical power source, an output port for electrical coupling to a load, a control switching device, and a control subsystem. The control switching device may be adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input port to the output port. The control subsystem may be adapted to control the switching of the control switching device to control a voltage across the input terminal, wherein the control is based, at least in part, on a signal representing a current flow from the output terminal to maximize a signal, the power from the Output terminal represents.
• (B2) In the power supply system indicated by (B1), the electric power source may include a photovoltaic device.
• (B3) In the power supply system indicated by (B2), the photovoltaic device may include a plurality of interconnected photovoltaic cells.
• (B4) In one of the power supply systems indicated by (B2) or (B3), the photovoltaic device may comprise a multiple photovoltaic cell.
• (B5) In any one of the power supply systems denoted by (B1) to (B4), the control subsystem may be adapted to partially base the switching of the control switching device on the signal, the current from the output terminal, and a difference between the voltage at the input terminal and a Reference voltage represents.
• (B6) In the power supply system indicated by (B5), the control subsystem may further be adapted to vary an amount of the reference voltage to maximize the signal representing power from the output port.
• (B7) In one of the power supply systems designated (B5) or (B6), the control subsystem may further be adapted to control the switching of the control switching device partly based on an error signal, the error signal being represented by -Kv * (Vin-Vref) + Ki * Io, where Kv is a first scaling factor, Ki is a second scaling factor, Vin is the voltage at the input terminal, Vref is the reference voltage, and Io is the signal representing the current flowing out of the output terminal.
• (B8) In any of the power supply systems labeled (B1) through (B7), the control switching device may be electrically coupled between a first terminal of the input terminal and a first terminal of the output terminal, the maximum power point tracking controller further comprising a free wheeling device is electrically coupled between the first terminal of the output terminal and a second terminal of the output terminal, wherein the free-wheeling device is adapted to provide a path for the flow of current between the first and second terminals of the output terminal when the control switching device is in its non-conductive state ,
• (B9) In any of the power supply systems denoted by (B1) to (B8), the control subsystem may include a multiplier adapted to receive the signal representing power from the output port from a product of a scaled signal indicative of a mean voltage represents the output port and a scaled signal representing the average current flowing out of the output port.
• (B10) In the power supply system labeled (B9), the control subsystem may further be adapted to prevent an amount of the scaled signal representing the average current flowing out of the output terminal from falling below a minimum threshold.
• (B11) In any of the power supply systems labeled (B1) to (B10), the control switching device and the control subsystem may be part of a common integrated circuit.
• (B12) In the power supply system indicated by (B11), the common integrated circuit and the photovoltaic device may be housed together in one package.
• (B13) Any of the power supply systems labeled (B1) to (B12) may further include one or more additional maximum power point tracking controllers electrically coupled in series with the output port and the load, each providing additional maximum power point tracking Controller is adapted to transfer power from a corresponding additional electrical power source to the load.
• (C1) A method of operating a maximum power point tracking controller, comprising an input terminal for electrical coupling to an electrical power source and an output terminal for electrical coupling to a load, comprising the steps of: (a) repetitively switching a maximum power control switching device Point tracking controller between its conductive and non-conductive state to transmit power from the input terminal to the output terminal and (b) controlling the switching of the control switching device at least partially based on a signal representing the current flowing from the output terminal by an amount a voltage at the input terminal so that a signal representing power from the output terminal is maximized.
• (C2) The method (C1) may further include controlling the switching of the control switching device based in part on the signal representing the current flowing out of the output terminal and a difference between the amount of the voltage at the input terminal and a reference voltage.
• (C3) The method indicated by (C2) may further comprise varying an amount of the reference voltage to maximize the signal representing the power from the output terminal.
• (C4) One of the methods (C2) or (C3) may further include controlling the switching of the control switching device based in part on an error signal, the error signal being given by -Kv * (Vin-Vref) + Ki * Io, where Kv is a first scaling factor, Ki is a second scaling factor, Vin is the voltage at the input terminal, Vref is the reference voltage, and Io is the signal representing the current flowing out of the output terminal.
• (C5) Any of the methods (C2) to (C4) may further comprise determining the signal representing power from the output port by multiplying a signal representing the average voltage at the output port by a signal, representing the average current flowing out of the output terminal, using a multiplier.
• (C6) The method (C5) may further comprise filtering the signal representing the current flowing out of the output terminal to produce the signal representing the average current flowing out of the output terminal.
• (C7) One of the methods (C5) or (C6) may further comprise filtering a signal representing the voltage at the output terminal to produce the signal representing the average voltage applied to the output terminal.
• (C8) One of the methods (C5) to (C7) may further include preventing an amount of the signal representing the average current flowing out of the output terminal from falling below a minimum threshold value.
• (C9) Any of the methods (C2) through (C8) may further include: (a) storing a first sample of the signal representing power from the output terminal when a duty cycle of the control switching device is one hundred percent; (b) reducing the magnitude of the reference voltage by a first amount; (c) storing a second sample of the signal representing the power from the output terminal after the step of reducing the magnitude of the reference voltage by the first amount; (d) comparing a first sample of the signal representing power from the output port to the second sample of the signal representing power from the output port; (e) increasing the magnitude of the reference voltage when the first sample of the signal representing power from the output terminal is greater than the second sample of the signal representing power from the output terminal and (f) decreasing the magnitude of the reference voltage, when the second sample of the signal representing the power from the output terminal is greater than the first sample of the signal representing the power from the output terminal.
• (C10) Any of the methods (C2) to (C9) may further include preventing a decrease in the magnitude of the reference voltage when the voltage at the input terminal falls below a second threshold.
• (C11) Any of the methods (C2) to (C10) may further include preventing an increase in the magnitude of the reference voltage when the voltage at the input terminal rises above a third threshold.
• (C12) Any of the methods (C2) through (C11) may further include: (a) changing the magnitude of the reference voltage by a first step size to maximize the signal representing power from the output port when a command, controlling the duty cycle of the control switching device is below a fourth threshold and (b) changing the magnitude of the reference voltage by a second step size to maximize the signal representing power from the output port when a command to control a duty cycle of the control switching device; is greater than or equal to a fifth threshold; wherein the second step size is smaller than the first step size.
• (C13) Any of the methods (C2) through (C11) may further include: (a) changing the magnitude of the reference voltage at a first pacing rate to maximize the signal representing power from the output port when a command, controlling the duty cycle of the control switching device is within a first range of values; and (b) changing the magnitude of the reference voltage at a second step speed to maximize the signal representing power from the output port when the command to control the duty cycle of the control switching device, is in a second range of values; wherein the second speed is greater than the first speed.
• (C14) In the method indicated by (C13), the first range of values may represent commanding the duty ratio of the control switching device to be between zero and one hundred percent, and may represent the second range of values commanding the duty ratio of the control switching device less than To be zero or greater than one hundred percent.
• (C15) Any of the methods indicated by (C2) to (C14) may further comprise increasing the magnitude of the reference voltage in response to the fall of the magnitude of the voltage at the input terminal below a sixth threshold.
• (C16) Any one of the methods (C2) to (C15) may further include adjusting an initial magnitude of the reference voltage based at least in part on an initial value of the voltage at the input terminal at the start-up of the circuit.
• (C17) The method indicated by (C16) may further comprise adjusting the initial magnitude of the reference voltage to a fraction of the voltage at the input terminal upon start-up of the circuit.
• (C18) One of the methods (C2) to (C17) may further include decreasing the magnitude of the reference voltage in response to the fall of an amount of the current flowing out of the output terminal below a seventh threshold value.
• (C19) The method (C18) may further include operating the control switching device at a fixed duty cycle in response to the fall of an amount of current flowing out of the output terminal below an eighth threshold, the eighth threshold being lower than the seventh threshold.
• (C20) Any of the methods (C1) to (C19) may further include: (a) generating the signal representing the current flowing out of the output terminal using a current-reconstructor subsystem, and (b) reducing one Size of a dynamically adjusted field effect transistor of the control switching device when an amount of the signal representing the current flowing out of the output terminal falls below a ninth threshold, and thus an increase in the gain of the current-reconstructor subsystem.
• (D1) An electronic filter may include: (a) an integrator subsystem capable of operating in a bipolar domain to filter an AC component of an input signal, and (b) a transconductance circuit that is suitable for a unipolar domain to produce an output current signal that is proportional to an average of the input current signal.
• (D2) In the electronic filter denoted (D1), the integrator subsystem may be adapted to generate an integrator signal representing the average of the input current signal, and (b) the transconductance circuit may comprise a first transconductance amplifier as appropriate is to generate the output current signal from the integrator signal.
• (D3) In the electronic filter denoted (D2), the transconductance circuit may further comprise a second transconductance amplifier adapted to generate from the integrator signal a DC component of the input current signal.
• (D4) In any of the electronic filters denoted (D1) through (D3), the integrator subsystem may comprise: (a) an integrator having an inverting input terminal and a non-inverting input terminal, and (b) a resistive device passing across the Input terminals of the integrator is electrically coupled; wherein the non-inverting input terminal of the integrator is electrically coupled to a reference node of the electronic filter via a voltage source, the inverting input terminal of the integrator is electrically coupled to a first node, and the electronic filter is arranged such that the input current signal flows out of the first node.
• (E1) A signal scaling system may comprise (a) a transconductance subsystem adapted to convert an input voltage signal into an output current signal, the transconductance subsystem comprising a programmable resistor adapted to adjust a gain of the transconductance subsystem and (b) control logic adapted to adjust a resistance of the programmable resistor to adjust the gain of the transconductance subsystem such that an amount of the output current signal is at least as large as a first threshold.
• (E2) In the signal scaling system labeled (E1), the transconductance subsystem may further comprise: (a) a transistor electrically coupled to the programmable resistor and (b) an amplifier adapted to drive the transistor to control a voltage across the programmable resistor in response to the input voltage signal.
• (E3) In any of the signal scaling systems designated (E1) or (E2), the control logic may further be adapted to set a gain of the transconductance subsystem to a minimum value in response to a first external signal.
• (E4) In any of the signal scaling systems designated (E1) through (E3), the control logic may further be adapted to increment the gain of the transconductance subsystem in response to a second external signal until the magnitude of the output current signal is at least as large as the first threshold.
• (E5) In any of the signal scaling systems labeled (E1) through (E4), the control logic may further be adapted to detect when the magnitude of the output current signal exceeds a second threshold, wherein the second threshold is greater than the first threshold.
• (E6) In the signal scaling system labeled (E5), the control logic may further be adapted to generate a signal indicating that the magnitude of the output current signal exceeds the second threshold.
• (E7) In any of the signal scaling systems designated (E1) through (E6), the transconductance system may further include a current mirror adapted to generate the output current signal in response to current flow through the programmable resistor.
• (F1) A signal level converter for shifting complementary input voltage signals of a first power supply domain into complementary output voltage signals of a second power supply domain may comprise: (a) a transconductance stage in the first power supply domain adapted to generate complementary current signals in response to the complementary input voltage signals; Load circuit in the second power supply domain adapted to generate the complementary output voltage signals in response to the complementary current signals, the load circuit comprising first and second inverter circuits adapted to generate the complementary output voltage signals in response to the complementary current signals ,
• (F2) In the signal level converter (F1), a high-side rail of the first inverter circuit may be electrically coupled to a high-side rail of the second power supply domain through a first transistor; For example, a high side rail of the second inverter circuit may be electrically coupled to a high side rail of the second power supply domain through a second transistor, and the first and second transistors may be cross coupled.
• (F3) In the signal level converter labeled (F2), each of the inverter circuits may include: (a) a high-side transistor electrically coupled between the inverter circuit's high-side rail and an inverter node output node and (b) a low-side transistor electrically coupled between the output node of the inverter circuit and a reference rail of the second power supply domain; wherein the high-side transistor is adapted to pull the output node of the inverter circuit to at least fifty percent of the electrical potential of the high-side rail of the inverter with respect to the reference rail of the second power supply domain when the low-side transistor is in the conductive state.
• (F4) In one of the signal level transducers (F2) or (F3), the transconductance stage may be adapted to drive current into the high side rail of the first and second inverter circuits when an electric potential of a reference rail of the second power supply domain is below an electrical potential of a reference rail of the first power supply domain.
• (G1) A system for determining a signal representing power in a Maximum Power Point Tracking Controller (MPPT) may include: (a) a voltage filter subsystem capable of generating a signal representative of the average power signal Voltage at an output terminal of the MPPT controller represented by filtering a signal representing the voltage at the output terminal; (b) a current filter subsystem adapted to generate a signal representing the average current flowing out of the output terminal by filtering a signal representing the current flowing out of the output terminal; (c) a voltage scaling subsystem adapted to generate a scaled signal representing the average voltage at the output port by scaling the signal representing whether the average voltage at the output port is within a first predetermined range of values; (d) a current scaling subsystem capable of generating a scaled signal representing the average current flowing out of the output port by scaling the signal representing whether the average current flowing out of the output port is within a second predetermined one Range of values and (e) a multiplier capable of representing the signal representing power from a product of the scaled signal representing the average voltage at the output port and the scaled signal representing the average current flowing from the output port to determine.
• (G2) In the system designated (G1), the multiplier may comprise: (a) a first input terminal adapted to receive the scaled signal representing the average voltage at the output terminal; (b) a second input terminal adapted to receive the scaled signal representing the average current flowing out of the output terminal; (c) an output terminal capable of providing the signal representing the current; (d) a first field effect transistor electrically connected in series with the first input terminal; (e) a second field effect transistor electrically connected in series with the second input terminal; (f) a third field effect transistor electrically connected in series with the output terminal; and (g) a control circuit adapted to control the first, second, and third field effect transistors, respectively, such that an amount of the current flowing into the output terminal , is proportional to a product of (1) an amount of current flowing into the first input terminal and (2) an amount of current flowing into the second input terminal.
• (G3) In the system indicated by (G2), a gate of the first field effect transistor may be electrically coupled to a gate of the third field effect transistor.
• (G4) The system denoted by (G3) may further comprise: (a) fourth and fifth field effect transistors forming a current mirror configured such that an amount of drain-to-source Current flowing through the fifth field effect transistor is Iref, and an amount of drain to source current flowing through the fourth field effect transistor is Iref / m, and (b) a first amplifier suitable for the gate of first field effect transistor so that a voltage at the first field effect transistor is equal to a voltage at the fourth field effect transistor.
• (G5) In the system indicated by (G4), a gate of the second field effect transistor may be electrically coupled to a gate of the fourth field effect transistor and a gate of the fifth field effect transistor.
• (G6) In one of the systems denoted by (G4) or (G5), the second field effect transistor may have a channel resistance of R / m and the fourth and fifth field effect transistors each have a channel resistance of R if the second, fourth and fifth transistors have a channel resistance common gate to source voltage to be driven.
• (G7) Any of the systems indicated by (G2) to (G6) may further include a second amplifier and a sixth transistor configured to control the amount of current flowing into the output terminal to supply a voltage the second field effect transistor is equal to a voltage at the third field effect transistor.
• (G8) In any of the systems labeled (G1) through (G7), the power scaling subsystem may include: (a) a transconductance subsystem capable of scaling the signal representative of the average current flowing from the output port Converting the signal representing the average current flowing from the output terminal, the transconductance subsystem comprising a programmable resistor adapted to adjust a gain of the transconductance subsystem; and (b) a control logic suitable for a resistance of the programmable resistor to adjust the gain of the transconductance subsystem such that an amount of the scaled signal representing the average current flowing out of the output terminal is at least as large as a first threshold.
• (G9) In the system designated (G8), the transconductance subsystem may further comprise: (a) a transistor electrically coupled to the programmable resistor and (b) an amplifier adapted to control the transistor controlling a voltage on the programmable resistor in response to the signal representing the average current flowing out of the output terminal.
• (G10) In any of the systems labeled (G8) or (G9), the control logic may further be adapted to set a gain of the transconductance subsystem to a minimum value in response to a first external signal.
• (G11) In any of the systems labeled (G8) through (G10), the control logic may further be adapted to increment the gain of the transconductance subsystem in response to a second external signal until the magnitude of the scaled signal comprising the output signal represents the current flowing through the output terminal, at least as large as the first threshold value.
• In any of the systems denoted by (G8) to (G11), the transconductance subsystem may further comprise a current mirror capable of representing the scaled signal representing the average current flowing out of the output terminal in response to the current signal to generate the current flowing through the programmable resistor.
• (G13) In any of the systems labeled (G1) through (G12), the stream filter subsystem may comprise: (a) an integrator subsystem capable of operating in a bipolar domain to filter an AC component of the signal, which represents the current flowing out of the output terminal and (b) a transconductance circuit capable of being operated in a unipolar domain to obtain the signal representing the average current flowing out of the output terminal from an average value of the signal which represents the current flowing out of the output terminal.
• (G14) In the system designated (G13): the integrator subsystem may be adapted to generate an integrator signal representing the average value of the signal representing the current flowing out of the output terminal, and the transconductance circuit may provide a first transconductance Amplifier, which is adapted to generate the signal representing the average current flowing from the output terminal of the integrator signal.
• (G15) In the system indicated by (G14), the transconductance circuit may further include a second transconductance amplifier capable of generating a DC component of the signal representing the current flowing out of the output terminal from the integrator signal.
• (G16) In any of the systems labeled (G13) through (G15), the integrator subsystem may include: (a) an integrator having an inverting input terminal and a non-inverting input terminal; and (b) a resistance device electrically coupled across the input terminals of the integrator; wherein the non-inverting input terminal of the integrator is electrically coupled to a reference node via a voltage source, the inverting input terminal of the integrator is electrically coupled to a first node, and the current filter subsystem is arranged to receive the signal representing the current flowing out of the output terminal represents, flows from the first node.
• (H1) A multiplier may comprise: (a) first and second input terminals; (b) an output terminal; (c) a first field effect transistor electrically connected in series with the first input terminal; (d) a second field effect transistor electrically connected in series with the second input terminal; (e) a third field effect transistor electrically connected in series with the output terminal; and (f) a control circuit adapted to control the first, second, and third field effect transistors, respectively, such that an amount of the current flowing into the output terminal , is proportional to a product of (1) an amount of current flowing into the first input terminal and (2) an amount of current flowing into the second input terminal.
• (H2) In the multiplier (H1), a gate of the first field effect transistor may be electrically coupled to a gate of the third field effect transistor.
• (H3) One of the multipliers denoted (H1) or (H2) may further comprise: (a) fourth and fifth field effect transistors forming a current mirror configured such that an amount of a drain-to-source current, which flows through the fifth field effect transistor, is equal to Iref, and an amount of drain-to-source current flowing through the fourth field effect transistor is Iref / m, and (b) a first amplifier suitable for the gate of the first field effect transistor so that a voltage at the first field effect transistor is equal to a voltage at the fourth field effect transistor.
• (H4) In the multiplier (H3), a gate of the second field effect transistor may be electrically coupled to a gate of the fourth field effect transistor and a gate of the fifth field effect transistor.
• (H5) In one of the multipliers denoted (H3) or (H4), the second field effect transistor may have a channel resistance of R / m and the fourth and fifth field effect transistors each have a channel resistance of R if the second, fourth and fifth transistors are connected through one common gate-to-source voltage to be driven.
• (H6) Any of the multipliers designated (H1) to (H5) may further include a second amplifier and a sixth transistor configured to control the amount of current flowing in the output terminal to supply a voltage the second field effect transistor is equal to a voltage at the third field effect transistor.

Changes may be made in the above methods and systems without departing from the scope of the invention. For example, N-channel field effect transistors could be replaced by P-channel field effect transistors, or vice versa, with corresponding changes made to the associated circuits. As another example, field effect transistors could be replaced by bipolar transistors, with corresponding changes made to the associated circuits. It should therefore be understood that the contents contained in the above description and shown in the accompanying drawings are to be taken as illustrative and should not be interpreted in a limiting sense. The following claims are intended to cover all general and specific features of the invention described herein, as well as all statements relating to the disclosed methods and systems, which fall within the claims according to the language chosen.

Claims (103)

Maximum Power Point Tracking Controller, comprising: an input terminal for electrical coupling to an electrical power source; an output terminal for electrical coupling to a load; a control switching device adapted to repeatedly switch between its conductive and non-conductive states to transfer power from the input terminal to the output terminal; and a control subsystem adapted to control the switching of the control switching device to control a voltage across the input terminal, wherein the control is based, at least in part, on a signal representing a current flow from the output terminal to maximize a signal, the power represents the output terminal. The maximum power point tracking controller of claim 1, wherein the control subsystem is further adapted to control the switching of the control switching device based in part on the signal representing current from the output terminal and a difference between the voltage at the input terminal and a reference voltage. The maximum power point tracking controller of claim 2, wherein the control subsystem is further adapted to vary an amount of the reference voltage to maximize the signal representing power from the output port. The maximum power point tracking controller of claim 3, wherein the control subsystem is further adapted to control switching of the control switching device based in part on an error signal, the error signal being given by -Kv * (Vin-Vref) + Ki * Io, where Kv a first scaling factor, Ki a second factor, Vin the voltage at the input terminal, Vref the reference voltage, and Io the signal representing the current flowing out of the output terminal. The maximum power point tracking controller of claim 4, wherein the control switching device is electrically coupled between a first terminal of the input terminal and a first terminal of the output terminal, the maximum power point tracking controller further comprising a freewheel device connected between the first terminal of the output terminal and a second terminal of the output terminal is electrically coupled, wherein the free-wheeling device is adapted to provide a path for the flow of current between the first and second terminals of the output terminal when the control switching device is in its non-conductive state. The maximum power point tracking controller of claim 5, wherein the control subsystem comprises a multiplier capable of representing the signal representing power from the output port from a product of a scaled signal representing a mean voltage at the output port and a scaled one Signal, which represents the average current flowing from the output terminal to determine. The maximum power point tracking controller of claim 6, wherein the control subsystem further comprises: a voltage scaling subsystem adapted to generate the scaled signal representing the average voltage at the output port by scaling a signal representing whether the average voltage at the power output port is within a first predetermined range of values; and a power scaling subsystem adapted to generate the scaled signal representing the average current flowing out of the output port by scaling a signal representative of whether the average current flowing out of the output port is within a second predetermined range of values.  The maximum power point tracking controller of claim 7, wherein the power scaling subsystem is further adapted to prevent an amount of the scaled signal representing the average current flowing out of the output port from falling below a minimum threshold.  The maximum power point tracking controller of claim 8, wherein the power scaling subsystem is further adapted to add a positive offset value to the scaled signal representing the average current flowing out of the output port if the signal is the average current flowing out of the output port represents within a first range of values.  The maximum power point tracking controller of claim 7, wherein the control subsystem further comprises a current filter subsystem capable of expressing the signal representing the average current flowing out of the output port by filtering the signal representative of the average current flowing out of the output port represents, to produce.  The maximum power point tracking controller of claim 10, wherein the control subsystem further comprises a voltage filter subsystem adapted to receive the signal representing the average voltage applied to the output port by filtering a signal representative of the voltage applied to the output port , to create. The maximum power point tracking controller of claim 3, wherein the control subsystem is further adapted to prevent a decrease in the magnitude of the reference voltage when the voltage at the input terminal falls below a threshold.  The maximum power point tracking controller of claim 3, wherein the control subsystem is further adapted to prevent a decrease in the magnitude of the reference voltage if that decrease would cause the voltage at the input port to fall below a threshold.  The maximum power point tracking controller of claim 3, wherein the control subsystem is further adapted to prevent an increase in the magnitude of the reference voltage as the voltage at the input terminal rises above a threshold.  The maximum power point tracking controller of claim 3, wherein the control subsystem is further suitable: change the magnitude of the reference voltage by a first step size to maximize the signal representing power from the output port when a command to control a duty cycle of the control switching device is below a first threshold; and change the magnitude of the reference voltage by a second step size to maximize the signal representing power from the output port when a command to control a duty cycle of the control switching device is greater than or equal to a second threshold; wherein the second step size is smaller than the first step size. The maximum power point tracking controller of claim 15, wherein the first threshold is equal to the second threshold. The maximum power point tracking controller of claim 3, wherein the control subsystem is further suitable: to vary the magnitude of the reference voltage by a first step size to maximize the signal representing power from the output port when a difference in the signal representing power from the output port is between successive changes in the magnitude of the reference voltage below a first one Threshold is; and to vary the magnitude of the reference voltage by a second step size to maximize the signal representing power from the output port when a difference in the signal representing power from the output port is greater than or equal to between successive changes in the magnitude of the reference voltage a second threshold; wherein the second step size is greater than the first step size. The maximum power point tracking controller of claim 17, wherein the first threshold is equal to the second threshold. The maximum power point tracking controller of claim 3, wherein the control subsystem is further suitable: change the magnitude of the reference voltage at a first stepping rate to maximize the signal representing power from the output port when a command to control a duty cycle of the control switching device is in a first range of values; and altering the magnitude of the reference voltage at a second pacing rate to maximize the signal representing power from the output port when the command to control the duty cycle of the control switching device is in a second range of values; wherein the second step speed is greater than the first step speed. The maximum power point tracking controller of claim 19, wherein the first range of values represents a command that the duty cycle of the control switching device is between zero and one hundred percent, and the second range of values represents a command that the duty cycle of the control switching device is less than zero or greater than one hundred Percent is. The maximum power point tracking controller of claim 3, wherein the control subsystem is further adapted to increase the magnitude of the reference voltage below a threshold in response to the amount of voltage at the input terminal falling. The maximum power point tracking controller of claim 3, wherein the control subsystem is further adapted to set an initial amount of the reference voltage at least in part based on an initial value of the voltage at the input terminal upon start-up of the circuit. The maximum power point tracking controller of claim 22, wherein the control subsystem is further adapted to set the initial magnitude of the reference voltage to a fraction of the initial value of the voltage at the input terminal upon start-up of the circuit.  The maximum power point tracking controller of claim 3, wherein the control subsystem is further adapted to display the magnitude of the reference voltage in response to the signal representing the current flowing out of the output terminal indicating that an amount of current flowing out of the output terminal is below one first threshold has fallen.  The maximum power point tracking controller of claim 24, wherein the control subsystem is further adapted to, at a fixed duty cycle, responsive to the signal representative of the current flowing out of the output terminal, reducing the amount of current flowing out of the output terminal below a second one Threshold has fallen, with the second threshold being lower than the first threshold.  The maximum power point tracking controller of claim 1, wherein the control switching device and the control subsystem are part of a common integrated circuit.  The maximum power point tracking controller of claim 1, wherein: the control switching device comprises a dynamically adapted field effect transistor; the maximum power point tracking controller further comprises a current reconstructor subsystem adapted to generate the signal representing the current flowing out of the output terminal, the current reconstructor subsystem having a gain that is at least partially dependent is of a size of the dynamically adjusted field effect transistor; and the control subsystem is adapted to reduce a size of the dynamically adjusted field effect transistor when an amount of the signal representing the current flowing out of the output terminal falls below a threshold, thereby increasing the gain of the current reconstructor subsystem. Power supply system comprising: an electrical power source; and a maximum power point tracking controller, comprising: an input terminal electrically coupled to the electrical power source, an output terminal for electrical coupling to a load, a control switching device capable of repeatedly switching between its conductive and non-conductive states to transfer power from the electric power source to the output port, and a control subsystem adapted to control the switching of the control switching device to control a voltage across the input terminal, wherein the control is based, at least in part, on a signal representing a current flow from the output terminal to maximize a signal, the power represents the output terminal.  The power system of claim 28, wherein the power source comprises a photovoltaic device.  The power system of claim 29, wherein the photovoltaic device comprises a plurality of interconnected photovoltaic cells.  The power system of claim 29, wherein the photovoltaic device comprises a multiple photovoltaic cell.  The power system of claim 29, wherein the control subsystem is adapted to control switching of the control switching device based in part on the signal representing current from the output terminal and a difference between the voltage at the input terminal and a reference voltage.  The power system of claim 32, wherein the control subsystem is further adapted to vary an amount of the reference voltage to maximize the signal representing power from the output terminal. The power system of claim 33, wherein the control subsystem is further adapted to control the switching of the control switching device based in part on an error signal, wherein the Where Kv is a first scaling factor, Ki is a second scaling factor, Vin is the voltage at the input terminal, Vref is the reference voltage, and Io is the signal representing the current flowing out of the output terminal represents.  The power system of claim 34, wherein the control switching device is electrically coupled between a first terminal of the input terminal and a first terminal of the output terminal, the maximum power point tracking controller further comprising a free wheeling device connected between the first terminal of the output terminal and a second terminal of the output terminal is electrically coupled, wherein the free-wheeling device is adapted to provide a path for the flow of current between the first and second terminals of the output terminal when the control switching device is in its non-conductive state.  The power system of claim 35, wherein the control subsystem comprises a multiplier capable of representing the signal representing power from the output port, a product of a scaled signal representing a mean voltage at the output port, and a scaled signal representing the represents the average current flowing in the output terminal.  The power system of claim 36, wherein the control subsystem is further adapted to prevent an amount of the scaled signal representing the average current flowing out of the output terminal from falling below a minimum threshold.  The power system of claim 29, wherein the control switching device and the control subsystem are part of a common integrated circuit.  The power system of claim 38, wherein the common integrated circuit and the photovoltaic device are located together in a housing.  The power system of claim 28, wherein the power system further includes one or more additional maximum power point tracking controllers electrically coupled in series with the output terminal and the load, each additional maximum power point tracking controller being capable of providing power from a corresponding one of the power sources additional electrical power source to the load.  A method of operating a maximum power point tracking controller, comprising an input terminal for electrical coupling to an electrical power source and an output terminal for electrical coupling to a load, comprising the steps of: repeatedly switching a control switching device of the maximum power point tracking controller between its conducting and non-conducting states to transfer power from the input port to the output port; and Controlling the switching of the control switching device based at least in part on a signal representing the current flowing out of the output terminal to regulate an amount of voltage at the input terminal such that a signal representing power from the output terminal is maximized.  The method of claim 41, further comprising controlling the switching of the control switching device based in part on the signal representing the current flowing out of the output terminal and a difference between the magnitude of the voltage at the input terminal and a reference voltage.  The method of claim 42, further comprising varying an amount of the reference voltage to maximize the signal representing power from the output terminal.  The method of claim 43 further comprising controlling the switching of the control switching device based in part on an error signal, the error signal being given by -Kv * (Vin-Vref) + Ki * Io, where Kv is a first scaling factor, Ki is a second scaling factor, Vin the voltage at the input terminal, Vref is the reference voltage, and Io is the signal representing the current flowing out of the output terminal. The method of claim 44, further comprising determining the signal representing power from the output port by multiplying a signal indicative of the average voltage at the output port Output terminal, with a signal representing the average current flowing out of the output terminal, using a multiplier.  The method of claim 45, further comprising filtering the signal representing the current flowing out of the output terminal to produce the signal representing the average current flowing out of the output terminal.  The method of claim 46, further comprising filtering a signal representing the voltage at the output terminal to produce the signal representing the average voltage applied to the output terminal.  The method of claim 47, further comprising preventing an amount of the signal representing the average current flowing out of the output terminal from falling below a minimum threshold. The method of claim 43, further comprising: Storing a first sample of the signal representing the power from the output terminal when a duty cycle of the control switching device is one hundred percent; Reducing the magnitude of the reference voltage by a first amount; Storing a second sample of the signal representing the power from the output terminal after the step of decreasing the magnitude of the reference voltage by the first amount; Comparing the first sample of the signal representing the power from the output terminal with the second sample of the signal representing power from the output terminal; Increasing the magnitude of the reference voltage when the first sample of the signal representing power from the output terminal is greater than the second sample of the signal representing power from the output terminal; and Decreasing the magnitude of the reference voltage when the second sample of the signal representing the power from the output terminal is greater than the first sample of the signal representing power from the output terminal.  The method of claim 43, further comprising preventing a decrease in the magnitude of the reference voltage when the voltage at the input terminal falls below a threshold.  The method of claim 43, further comprising preventing an increase in the magnitude of the reference voltage as the voltage at the input terminal increases above a threshold.  The method of claim 43, further comprising: Changing the magnitude of the reference voltage by a first step size to maximize the signal representing power from the output port when a command to control a duty cycle of the control switching device is below a first threshold; and Changing the magnitude of the reference voltage by a second step size to maximize the signal representing power from the output port when a command to control a duty cycle of the control switching device is greater than or equal to a second threshold; wherein the second step size is smaller than the first step size.  The method of claim 43, further comprising: Changing the magnitude of the reference voltage at a first step speed to maximize the signal representing power from the output port when a command to control a duty cycle of the control switching device is in a first range of values; and Changing the magnitude of the reference voltage at a second pacing rate to maximize the signal representing power from the output port when the command to control the duty cycle of the control switching device is in a second range of values; wherein the second step speed is greater than the first step speed.  The method of claim 53, wherein the first range of values represents that the duty cycle of the control switching device is between zero and one hundred percent, and the second range of values represents that the duty cycle of the control switching device is required to be less than zero or greater than one hundred percent. The method of claim 43, further comprising increasing the magnitude of the reference voltage in response to the falling of the magnitude of the voltage applied to the input terminal below a threshold.  The method of claim 43, further comprising adjusting an initial magnitude of the reference voltage based at least in part on an initial value of the voltage at the input terminal upon start-up of the circuit.  The method of claim 56, further comprising adjusting the initial magnitude of the reference voltage to a fraction of the voltage at the input terminal upon start-up of the circuit.  The method of claim 43, further comprising decreasing the magnitude of the reference voltage in response to the fall of an amount of current flowing out of the output terminal below a first threshold.  The method of claim 58, further comprising operating the fixed duty cycle control switching device in response to the fall of an amount of current flowing out of the output terminal below a second threshold, the second threshold being lower than the first threshold.  The method of claim 41, further comprising: Generating the signal representing the current flowing out of the output terminal using a current-reconstructor subsystem; and Decreasing an amount of a dynamically adjusted field effect transistor of the control switching device when an amount of the signal representing the current flowing out of the output terminal falls below a threshold, and thus increasing the gain of the current reconstructor subsystem.  A method of transmitting electrical power between an electrical power source and a load using a maximum power point tracking controller, comprising the step of controlling the switching of a control switching device based at least in part on a signal provided by an energy storage inductance of the maximum power point tracking controller flowing current to regulate a voltage at the electrical power source such that: (a) the voltage at the power source is greater than or equal to a voltage at the load, and (b) a signal representing the power transmitted to the load, is maximized.  The method of claim 61, further comprising controlling the control switching device based in part on the signal representing the current flowing out of the output terminal and a difference between the magnitude of the voltage at the electrical power source and a reference voltage.  The method of claim 62, further comprising varying an amount of the reference voltage to maximize the signal representing power transmitted to the load.  Multiplier, comprising: a first and a second input terminal; an output terminal; a first field effect transistor electrically connected in series with the first input terminal; a second field effect transistor electrically connected in series with the second input terminal; a third field effect transistor electrically connected in series with the output terminal; and a control circuit adapted to control the first, second and third field effect transistors respectively so that an amount of the current flowing in the output terminal is proportional to a product of (a) an amount of the current flowing into the first input terminal and ( b) is an amount of current flowing into the second input terminal.  The multiplier of claim 64, wherein a gate of the first field effect transistor is electrically coupled to a gate of the third field effect transistor. The multiplier of claim 65, further comprising: a fourth and fifth field effect transistor forming a current mirror configured such that an amount of a drain-to-source current flowing through the fifth field effect transistor is Iref and an amount of a drain-to-source current flowing through the fourth field effect transistor, is equal to Iref / m; and a first amplifier adapted to control the gate of the first field effect transistor such that a voltage at the first field effect transistor is equal to a voltage at the fourth field effect transistor.  The multiplier of claim 66, wherein a gate of the second field effect transistor is electrically coupled to a gate of the fourth field effect transistor and a gate of the fifth field effect transistor.  The multiplier of claim 67, wherein the second field effect transistor has a channel resistance of R / m and the fourth and fifth field effect transistors each have a channel resistance of R when the second, fourth and fifth transistors are driven by a common gate to source voltage.  The multiplier of claim 68, further comprising a second amplifier and a sixth transistor configured to control the amount of current flowing into the output terminal such that a voltage at the second field effect transistor is equal to a voltage at the third field effect transistor.  Electronic filter comprising: an integrator subsystem adapted to operate in a bipolar domain to filter an AC component of an input signal; and a transconductance circuit capable of operating in a unipolar domain to produce an output current signal that is proportional to an average of the input current signal.  An electronic filter according to claim 70, wherein: the integrator subsystem is adapted to generate an integrator signal representing the mean value of the input current signal; and the transconductance circuit comprises a first transconductance amplifier adapted to generate the output current signal from the integrator signal.  The electronic filter of claim 70, wherein the integrator subsystem comprises: an integrator having an inverting input terminal and a non-inverting input terminal; and a resistance device electrically coupled via the input terminals of the integrator; wherein the non-inverting input terminal of the integrator is electrically coupled to a reference node of the electronic filter via a voltage source, the inverting input terminal of the integrator is electrically coupled to a first node and the electronic filter is arranged so that the input current signal flows out of the first node.  The electronic filter of claim 72, wherein the transconductance circuit further comprises a second transconductance amplifier adapted to generate from the integrator signal a DC component of the input current signal.  A method of filtering an input signal, comprising: Filtering an AC component of the input signal in a bipolar domain; and Generating a DC component of the input signal in a unipolar domain.  The method of claim 74, further comprising mirroring the DC component of the input signal in the unipolar domain to produce an output signal representing an average value of the input signal.  Signal scaling system comprising: a transconductance subsystem adapted to convert an input voltage signal to an output current signal, the transconductance subsystem comprising a programmable resistor adapted to adjust a gain of the transconductance subsystem; and control logic adapted to adjust a resistance of the programmable resistor to adjust the gain of the transconductance subsystem such that an amount of the output current signal is at least as large as a first threshold. The signal scaling system of claim 76, wherein the transconductance subsystem further comprises: a transistor electrically coupled to the programmable resistor; and an amplifier adapted to control the transistor to control a voltage across the programmable resistor in response to the input voltage signal.  The signal scaling system of claim 77, wherein the control logic is further adapted to set a gain of the transconductance subsystem to a minimum value in response to a first external signal.  The signal scaling system of claim 78, wherein the control logic is further adapted to increment the gain of the transconductance subsystem in response to a second external signal until the magnitude of the output current signal is at least as large as the first threshold.  The signal scaling system of claim 79, wherein the control logic is further adapted to detect when the magnitude of the output current signal exceeds a second threshold, wherein the second threshold is greater than the first threshold.  The signal scaling system of claim 80, wherein the control logic is further adapted to generate a signal indicating that the magnitude of the output current signal exceeds the second threshold.  The signal scaling system of claim 81, wherein the transconductance system further comprises a current mirror adapted to generate the output current signal in response to the current flowing through the programmable resistor.  A signal level converter for shifting complementary input voltage signals of a first power supply domain into complementary output voltage signals of a second power supply domain, comprising: a transconductance stage in the first power supply domain adapted to generate complementary current signals in response to the complementary input voltage signals; and a load circuit in the second power supply domain adapted to generate the complementary output voltage signals in response to the complementary current signals, the load circuit including first and second inverter circuits adapted to supply the complementary output voltage signals in response to the complementary current signals produce.  Signal level converter according to claim 83, wherein: a high side rail of the first inverter circuit is electrically coupled to a high side rail of the second power supply domain through a first transistor; a high side rail of the second inverter circuit is electrically coupled to a high side rail of the second power supply domain through a second transistor; and the first and second transistors are cross-coupled.  The signal level converter of claim 84, wherein each of the inverter circuits comprises: a high side transistor electrically coupled between the high side rail of the inverter circuit and an output node of the inverter circuit; and a low-side transistor electrically coupled between the output node of the inverter circuit and a reference rail of the second power supply domain; wherein the high side transistor is capable of pulling the output node of the inverter circuit up to at least fifty percent of an electrical potential of the high side rail of the inverter with respect to the reference rail of the second power supply domain when the low side transistor is in a conductive state.  The signal level converter of claim 85, wherein the transconductance stage is capable of driving current into the high side rail of the first and second inverter circuits when an electrical potential of a reference rail of the second power supply domain is below an electrical potential of a reference rail of the first power supply domain. A system for determining a signal representing power in a Maximum Power Point Tracking Controller (MPPT), comprising: a voltage filter subsystem adapted to generate a signal representative of the average voltage at an output port of the MPPT controller represented by filtering a signal representing the voltage at the output terminal; a current filter subsystem adapted to generate a signal representing the average current flowing out of the output terminal by filtering a signal representing the current flowing out of the output terminal; a voltage scaling subsystem adapted to generate a scaled signal representing the average voltage at the output port by scaling the signal representing whether the average voltage at the output port is within a first predetermined range of values; a current scaling subsystem adapted to generate a scaled signal representative of the average current flowing out of the output port by scaling the signal representing whether the average current flowing out of the output port is within a second predetermined range of values; and a multiplier adapted to determine the signal representing power from a product of the scaled signal representing the average voltage at the output port and the scaled signal representing the average current flowing from the output port.  The system of claim 87, wherein the multiplier comprises: a first input terminal adapted to receive the scaled signal representing the average voltage at the output terminal; a second input terminal adapted to receive the scaled signal representing the average current flowing out of the output terminal; an output terminal capable of providing the signal representing the current; a first field effect transistor electrically connected in series with the first input terminal; a second field effect transistor electrically connected in series with the second input terminal; a third field effect transistor electrically connected in series with the output terminal; and a control circuit adapted to control the first, second and third field effect transistors respectively so that an amount of the current flowing into the output terminal is proportional to a product of (a) an amount of the current flowing into the first input terminal and ( b) is an amount of current flowing into the second input terminal.  The system of claim 88, wherein a gate of the first field effect transistor is electrically coupled to a gate of the third field effect transistor.  The system of claim 89, further comprising: a fourth and fifth field effect transistor forming a current mirror configured such that an amount of a drain-to-source current flowing through the fifth field effect transistor is Iref and an amount of a drain-to-source current flowing through the fourth field effect transistor, is equal to Iref / m; and a first amplifier adapted to control the gate of the first field effect transistor such that a voltage at the first field effect transistor is equal to a voltage at the fourth field effect transistor.  The system of claim 90, wherein a gate of the second field effect transistor is electrically coupled to a gate of the fourth field effect transistor and a gate of the fifth field effect transistor.  The system of claim 91, wherein the second field effect transistor has a channel resistance of R / m and the fourth and fifth field effect transistors each have a channel resistance of R when the second, fourth and fifth transistors are driven by a common gate to source voltage.  The system of claim 92, further comprising a second amplifier and a sixth transistor configured to control the amount of current flowing into the output terminal such that a voltage at the second field effect transistor is equal to a voltage at the third field effect transistor.  The system of claim 88, wherein the stream scaling subsystem comprises: a transconductance subsystem adapted to convert the signal representing the average current flowing from the output terminal into the scaled signal representing the average current flowing out of the output terminal, the transconductance subsystem comprising a programmable resistor as appropriate is to set a gain of the transconductance subsystem; and control logic adapted to adjust a resistance of the programmable resistor to adjust the gain of the transconductance subsystem such that an amount of the scaled signal representing the average current flowing out of the output terminal is at least as large as a first threshold. The system of claim 94, wherein the transconductance subsystem further comprises: a transistor electrically coupled to the programmable resistor; and an amplifier adapted to control the transistor to control a voltage on the programmable resistor in response to the signal representing the average current flowing out of the output terminal.  The system of claim 95, wherein the control logic is further adapted to set a gain of the transconductance subsystem to a minimum value in response to a first external signal.  The system of claim 96, wherein the control logic is further adapted to increment the gain of the transconductance subsystem in response to a second external signal until the magnitude of the scaled signal representing the current flowing out of the output terminal is at least as large as the first one Threshold is.  The system of claim 97, wherein the transconductance system further comprises a current mirror adapted to generate the scaled signal representing the average current flowing out of the output terminal in response to the current flowing through the programmable resistor.  The system of claim 94, wherein the stream filter subsystem comprises: an integrator subsystem adapted to operate in a bipolar domain to filter an AC component of the signal representing the current flowing out of the output terminal; and a transconductance circuit capable of operating in a unipolar domain to generate the signal representing the average current flowing out of the output terminal from an average value of the signal representing the current flowing out of the output terminal.  The system of claim 99, wherein: the integrator subsystem is adapted to generate an integrator signal representative of the mean value of the signal representing the current flowing out of the output terminal; and the transconductance circuit comprises a first transconductance amplifier adapted to generate the signal representing the average current flowing out of the output terminal from the integrator signal. The system of claim 100, wherein the integrator subsystem comprises: an integrator having an inverting input terminal and a non-inverting input terminal; and a resistance device electrically coupled via the input terminals of the integrator; wherein the non-inverting input terminal of the integrator is electrically coupled to a reference node via a voltage source, the inverting input terminal of the integrator is electrically coupled to a first node and the current filter subsystem is arranged so that the signal representing the current flowing out of the output terminal flows out of the first node. The system of claim 101, wherein the transconductance circuit further comprises a second transconductance amplifier adapted to generate a DC component of the signal representing the current flowing out of the output terminal from the integrator signal. A method for determining a signal representing power in a Maximum Power Point Tracking Controller (MPPT), comprising the steps of: filtering a signal representative of the current flowing out of the output port of the MPPT controller to obtain a signal, representing the average current flowing from the output terminal; Filtering a signal representing the voltage at the output terminal to obtain a signal representing the average voltage at the output terminal; Scaling the signal representing the average current flowing out of the output terminal to obtain a scaled signal representing the average current flowing out of the output terminal; Scaling the signal representing the average voltage at the output port to obtain a scaled signal representing the average voltage at the output port; and Multiplying the scaled signal representing the average current flowing from the output terminal with the scaled signal representing the average voltage at the output terminal to obtain the signal representing the power.

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