DE10358299A1 - Capacitor component for integrated circuits has trench in a substrate containing alternating conductive and dielectric layers - Google Patents

Abstract

A capacitor component for integrated circuits comprises a trench (12) in a substrate (10) having at least three conductive layers (14,18,20) alternating with at least two dielectric layers in the trench. Preferably there is a highly doped region at a trench wall with one of the conductive layers being built through this region. An independent claim is also included for a production process for the above.

Description

The The present invention relates to an electronic capacitor device and in particular to an electronic capacitor device below Use of a trench capacitance. Further The present invention relates to a method of manufacturing a capacitor device.

For the integration of passive devices on ICs with silicon substrates is the Chip area decisive criterion for Integration density. Hereby play beside application-specific Topics the chip costs a crucial role. To the chip costs preferably Therefore, attempts are usually made to keep one for a semiconductor circuit necessary chip area preferably to keep low. For electronic Circuits that are very big capacities need, Therefore, in addition to usual Plate capacitors (MIS and / or MIM capacities; MIS = metal-insulator-semiconductor = Metal-insulator-semiconductor; MIM = metal-insulator-metal-capacitances) too so-called trench capacities uses. These are deep trenches produced in silicon (up to depths of 20 μm). These silicon trenches turn are filled with a dielectric and a conductive layer to size To achieve area capacities. By this method it is possible by a factor of 10 to 20 higher To produce area capacities, which is limited by the thickness of the dielectric. The restrictions in the thickness of the dielectric is determined by the respective requirements the circuit determined. An important criterion here is breakthrough resistance and thus sensitivity of the circuit to high voltage spikes, for example in the ESD case (ESD = Electrostatic Discharge) may occur. Another disadvantage of such a structure is to be seen in that for some electrical circuit applications a further He increase the on a chip surface provided capacity necessary is.

outgoing from this prior art, the present invention is the Task based, an increase the per chip area feasible capacities to enable and thus to a cost reduction in the production of integrated electronic To contribute to circuits with integrated capacities. Further lies The object of the present invention is to provide a method by the one increase the per chip area feasible capacities possible is.

These The object is achieved by a capacitor component according to claim 1 and a method for Producing a capacitor device according to claim 8 solved.

The present invention provides a capacitor device with
a substrate;
a trench formed in the substrate;
at least three conductive layers, and
at least two dielectric layers,
wherein the conductive layers and the dielectric layers are alternately disposed in the trench.

• a) Bereitstellen eines Substrats, wobei in dem Substrat ein Graben gebildet ist;
• b) Ausbilden einer ersten leitfähigen Schicht in dem Graben;
• c) Ausbilden einer ersten dielektrischen Schicht in dem Graben, die an die erste leitfähige Schicht angrenzt;
• d) Ausbilden einer zweiten leitfähigen Schicht in dem Graben, die an die erste dielektrische Schicht angrenzt und von der ersten leitfähigen Schicht elektrisch getrennt ist;
• e) Ausbilden einer zweiten dielektrischen Schicht in dem Graben, die an die zweite leitfähige Schicht angrenzt; und
• f) Ausbilden einer dritten leitfähigen Schicht in dem Graben, die an die zweite dielektrische Schicht angrenzt und von der zweiten leitfähigen Schicht elektrisch getrennt ist.

Furthermore, the present invention provides a method for manufacturing a capacitor device comprising the following steps:

• a) providing a substrate, wherein in the substrate a trench is formed;
• b) forming a first conductive layer in the trench;
• c) forming a first dielectric layer in the trench adjacent to the first conductive layer;
• d) forming a second conductive layer in the trench adjacent to the first dielectric layer and electrically isolated from the first conductive layer;
• e) forming a second dielectric layer in the trench adjacent to the second conductive layer; and
• f) forming a third conductive layer in the trench adjacent to the second dielectric layer and electrically isolated from the second conductive layer.

According to the invention, the approach described above is abandoned, in which deep trenches are produced in a silicon and these trenches are filled up only with a dielectric and a conductive layer. According to the invention, a further increase in the realizable capacitance per chip area can be produced by two or more superpositions of dielectric and conductive layers. An advantage of the approach according to the invention is that this "sandwich" allows a significant increase in the realizable capacities per chip area (ie, a significantly increased area capacity) Furthermore, by two or more layers of dielectric and conductive layers, a plurality of initially independent Capacities can be realized on the limited available chip area, which results in additional degrees of freedom in the circuit design.Through the two or more layers of dielectric and conductive layers, significantly larger capacities (ie higher capacitance values) can be achieved with a small space requirement or with small chip areas With the present invention it is therefore possible to provide the necessary chip area for components that require large capacities to reduce significantly. Possible fields of application of the approach according to the invention are, in addition to the high-frequency applications in BiPOLAR and BiCMOS technology, also logic applications in CMOS technology.

According to one preferred embodiment According to the present invention, the capacitor device comprises a compared to the substrate high-doped portion of a wall the trench, wherein one of the at least three conductive layers through the highly doped Part area is formed. This makes it possible by the use of the heavily doped portion of the substrate serving as a conductive layer serves a separate conductive Layer adjacent to the substrate to avoid and thus the Space requirement of the capacitor component to keep low.

Preferably the capacitor component comprises a first contact connection and a second contact terminal, wherein the second contact terminal is electrically isolated from the first contact terminal and wherein the conductive ones Layers alternating with the first contact terminal or the second contact terminal are connected. By such a capacitor device is thus a parallel connection of the alternating in the Trench arranged conductive and dielectric layers formed independent capacity possible. hereby let yourself form a single capacitor with a much higher capacity as the individual capacities representing separate capacitors separated by two adjacent ones conductive Layers and an intermediate dielectric layer formed are.

According to one another preferred embodiment The present invention extends in the Kondensatorbauele element at least one conductive Layer on a surface of the substrate disposed in one on the surface of the substrate Contact area is contactable.

Preferably the trench has a circular symmetrical shape, whereby the Forming the trench in the substrate can be simplified.

According to one preferred embodiment According to the present invention, the capacitor device comprises at least four conductive layers and at least three dielectric layers, wherein at least two conductive Layers on a surface extend the substrate and in each case in the on the surface of the Substrate arranged contact area are contactable and wherein the two contact areas are essentially the same Dimension on the surface extend the substrate and are offset from each other. Such an arrangement of the contact areas allows advantageously contacting the different conductive layers on a narrow Space around the capacitor device.

According to one another preferred embodiment The present invention is a cover layer on the substrate and the stuffed Trench formed having at least one opening through which one of the conductive Layers is contactable. Such a configuration of the capacitor component allows Advantageously, protection of the capacitor component from mechanical or chemical influences such as oxidation of conductive layers.

According to one preferred embodiment the method according to the invention in manufacturing a capacitor device, the step comprises forming a first conductive one Layer in the trench the diffusion of dopant atoms into the substrate in the area of a trench wall.

hereby can be the advantages already mentioned in relation to a Reduction of the space required in the manufacture of the capacitor device realize.

According to one another preferred embodiment includes the method according to the invention further forming a first contact terminal and one of the first contact terminal electrically separated second contact terminal, being the conductive one Layers alternating with the first contact terminal or the second contact connection are connected. Such a procedure allows forming a single capacitor from the different ones Partial capacitors of the capacitor component as already described above has been.

Preferably includes the method according to the invention further forming a capping layer on the substrate and the trench and forming at least one opening in the cover layer, through which one of the conductive Layers is contactable.

preferred embodiments The present invention will be described below with reference to the accompanying Drawings closer explained. Show it:

1A a cross-sectional view of a first preferred embodiment of the invention capacitor device according to the invention with a double multistack structure;

1B a plan view of the capacitor device from 1A ;

1C an electrical circuit diagram of the capacitor device from 1A ;

2A a cross-sectional view of a second preferred embodiment of the capacitor device according to the invention with a multiple multi-stack construction;

2 B a plan view of the capacitor device from 2A ;

2C an electronic circuit diagram of the capacitor component 2A ;

3A a schematic representation of a simple stack structure with a dielectric layer;

3B a schematic representation of a multi-stack construction with three dielectric layers; and

3C an illustration of a simulation result in which a capacitor device is compared with a simple stack structure with a capacitor element with a multi-stack structure.

In the following description of the preferred embodiments of the present invention are for those in the various Drawings shown and similar acting elements the same reference numerals used.

1A shows a substrate 10 with a ditch 12 formed in the substrate. This ditch 12 For example, it can be used to produce capacitances with high surface capacitances in the substrate 10 (which includes, for example, silicon) etched. The depth of the trench can be up to more than 20 microns. To produce a bottom electrode, a dopant (for example phosphorus) is preferably introduced into the substrate by means of a doped oxide 10 driven in the area of a trench wall. For this purpose, the doped oxide is preferably applied to a surface 13 of the substrate 10 and the ditch wall of the ditch ( 12 ) applied. By thus driving in dopant, at least on the trench wall, a partial area can be achieved 14 of the substrate 10 generate a higher conductivity than the substrate 10 and thus at the trench wall a conductive layer (first conductive layer 14 ). Subsequently, the doped oxide, which is the dopant for driving into the substrate 10 has provided, for example wet-chemically, again from the surface 13 of the substrate 10 and the trench wall removed. For a construction according to the invention of the capacitor component, two dielectric layers (for example an oxide, a silicon nitride, a nitride or a combination of oxide and nitride ONO) and conductive layers (for example consisting of a heavily doped polysilicon, silicide or WSi _x ) are subsequently alternately formed the ditch 12 deposited.

The illustrated conductive and dielectric layers are subsequently patterned by means of phototechnology and etching technology, so that the details explained below and in FIG 1B structure shown results. After structuring, for example, a covering layer is deposited 22 (eg, an interlayer oxide) on the first dielectric layer 16 , the second conductive layer 18 , the second dielectric layer 19 and the third conductive layer 20 , Following this are in the cover layer 22 openings 30 etched, so through each one opening 30 a portion of the first conductive layer 14 , the second conductive layer 18 and the third conductive layer 20 exposed. Following this are the openings 30 preferably filled with metal (for example tungsten), so that the first conductive layer 14 , the second conductive layer 18 and the third conductive layer 20 from a surface 32 the cover layer 22 are contactable. Following this are at those points of the surface 32 the cover layer 22 to which the first conductive layer 14 , the second conductive layer 18 and the third conductive layer 20 are electrically contactable, contact points 341 . 342 . 343 educated. The contact points 341 . 342 . 343 are formed, for example, with a conductive metal layer, which is patterned by means of photographic technology. Through the contact points 341 . 342 . 343 are the third conductive layer 20 through a first external connection 1 , the second conductive layer 18 through a second external connection 2 and the first conductive layer 14 through a first external connection 3 electrically contactable.

Further, the first conductive layer 14 , the first dielectric layer 16 , the second conductive layer 18 , the second dielectric layer 19 and the third dielectric layer 20 in a step shape on the substrate surface 13 arranged. As a result, a structure forms in which a partial region of the first dielectric layer 16 through the second conductive layer 18 is covered and a portion of the second dielectric layer 19 through the third conductive layer 20 is covered, as it is in the 1A is shown. The resulting structure thus has portions of the second dielectric layer 19 and the second conductive layer disposed thereunder 18 on the side over the third conductive layer 20 stand out and thus a good possibility of contacting the second conductive layer 18 from the surface 32 the cover layer 22 Offer. Furthermore, the structure according to 1A Portions of the first dielectric layer 16 and the first conductive layer 14 on the side over the second conductive layer 18 protrude and thus again a good possibility of contacting the first conductive layer 14 from the surface 32 the cover layer 22 offers. Except for the in 1B closer described contact region of the second conductive layer 18 the one over the third conductive layer 20 protruding portion of the second dielectric layer 19 a constant step width, ie a constant width of the third conductive layer 20 protruding portion of the second dielectric layer 19 on.

This results in the in 1A shown layer structure consisting of the substrate 10 with the ditch 12 , the first conductive layer 14 , the first dielectric layer 16 , the second conductive layer 18 , the second dielectric layer 19 and the third conductive layer 20 , the cover layer 22 , preferably filled with metal openings 30 , the contact points 341 . 342 . 343 and the external connections 1 . 2 and 3 ,

For applying the in 1A shown conductive and dielectric layers are preferably used CVD deposition process (CVD = Chemical Vapor Deposition = gas phase deposition), which ensure a conformal and homogeneous deposition.

It It should be noted that the illustrations in this description of the present invention only for explaining the principle of action serve; a true to scale Arrangement of individual components of the present invention can be made out not derive the figures.

1B shows a plan view of the in 1A shown capacitor component. It can be seen here that the second conductive layer is patterned, for example by means of phototechnology and etching technology, in such a way that a lateral contact area is formed 50 results, like in 1B is shown on the right edge of the capacitor device through the third conductive layer 20 covered area of the second dielectric layer 19 protrudes and thus breaks the otherwise circularly symmetrical arrangement of the capacitor device according to the invention. Alternatively, the capacitor device according to the invention may also have other than the circularly symmetrical arrangement, such as a square, rectangular, oval to order or an arrangement consisting of circumferential trenches. By the in 1B illustrated arrangement of the contact area 50 It is thus possible, in a space-saving manner, the second conductive layer 18 be able to contact and thus to be able to dispense with an annular area around the third conductive layer surrounding contact area for contacting the second conductive layer. Further shows 1B the first conductive layer formed in the trench wall 14 underlying the first dielectric layer 16 is arranged and therefore indicated by a dashed line. Furthermore, it is off 1B the arrangement of the third conductive layer 20 in the middle of the illustrated capacitor component as well as the third conductive layer 20 protruding portion of the second dielectric layer 19 with the exception of the contact area 50 constant step width. Further shows 1B the arrangement of the first contact point 341 for contacting the third conductive layer 20 , the second contact point 342 for contacting the second conductive layer 18 and the third contact point 343 for contacting the first conductive layer 14 , by which a surface-saving contacting possibility of the capacitor component is made possible.

1C shows the electrical diagram of the capacitor device 1A , As in 1C is shown, the electrical circuit diagram by a series circuit of a first capacitor 60 and a second capacitor 62 wherein the third conductive layer in communication with the second dielectric layer and the second conductive layer is the first capacitor 60 and the second conductive layer in communication with the first dielectric layer 16 and the first conductive layer 14 the second capacitor 62 form. This results in the in 1C shown interconnection of the first capacitor 60 with the second capacitor 62 , wherein the first capacitor 60 between the first external connection 1 and the second external connection 2 is switched and the second capaci tor 62 between the second external connection 2 and the third external connection 3 is switched. Preferably, the individual conductive layers (ie, the electrodes) of the first capacitor 60 and the second capacitor 62 by means of the first external connection 1 , the second external connection 2 as well as the third external connection 3 (ie, the terminal contacts) are electrically connected in parallel. In particular, the electrically conductive connection of the first external terminal 1 with the third external connection 3 leads to a parallel connection of the first capacitor 60 with the second capacitor 62 , By a layout-technical stringing together by such a layer sequence of conductive and dielectric layers, capacities (trench capacitances) with very large capacitance values can be realized in a space-saving manner thus realize an increase in the area capacity many times over. This opens up a meaningful integration into silicon substrates based on ICs for applications with very high capacitance values.

2A shows a second preferred embodiment of the capacitor device according to the invention. Unlike the in 1A Embodiment shown here are still a third dielectric layer 80 like that in the ditch 12 arranged it to the third conductive layer 20 adjacent and further is a fourth conductive layer 82 like that in the ditch 12 arranged to contact the third dielectric layer 80 borders. Further, the fourth conductive layer 82 again via an opening 30 in the cover layer 22 contactable, the opening 30 for contacting the fourth conductive layer 82 in turn may be filled with metal (eg tungsten) and being on the surface 24 the cover layer 22 at a location where the fourth conductive layer 82 over the filled opening 30 is contactable, a fourth contact point 344 imprinted with an external connector 4 for contacting the fourth conductive layer 82 connected is.

2A again shows a step-shaped structure wherein, in contrast to the illustration in 1A now the third dielectric layer 80 on the third conductive layer 20 is arranged, wherein a portion of the third dielectric layer 80 through the fourth conductive layer 82 is covered. This results analogously to the representation in FIG 1A again a stepped structure in which through the fourth conductive layer 82 a portion of the third dielectric layer 80 is covered by the third conductive layer 20 a portion of the second dielectric layer 19 is covered and through the second conductive layer 18 a portion of the first dielectric layer 16 is covered, as in 2A is shown.

2 B shows a plan view of the capacitor device 2A , Analogous to the comments in relation to 1B is in the second preferred embodiment, in turn, a contact area 50 for contacting the in 2A illustrated second conductive layer 18 out. It is also in 2 B again below the first dielectric layer 16 arranged first conductive layer 14 represented by the dashed line.

Furthermore, it is off 2 B it can be seen that for contacting the third conductive layer 20 another contact area 90 is formed, which is also analogous to the contact area 50 protrudes beyond the otherwise circularly symmetrical shape of the capacitor component. Because of that, the wider contact area 90 in relation to one with the contact area 50 common axis of rotation 92 at a predetermined angle 94 is arranged rotated, a space-saving contacting possibility of the second and third conductive layer of the capacitor device can be realized. Preferably, the contact area 50 and the further contact area 90 essentially the same dimensions. Furthermore, it is off 2 B again the arrangement of the first contact point 341 for contacting the third conductive layer 20 , the second contact point 342 for contacting the second conductive layer 18 , the third contact point 343 for contacting the first conductive layer 14 and the fourth contact point 344 for contacting the fourth conductive layer 82 recognizable, which in turn offer a space-saving possibility of contacting the capacitor device. In addition, the 2 B be taken that, analogous to the in 1B shown structure, a portion of the third dielectric layer 80 over the fourth conductive layer 82 (with the exception of the further contact area 90 ) at a constant distance from the fourth conductive layer 82 beyond that, ie, a constant step depth of one step from the third dielectric layer 80 to the fourth conductive layer 82 is realized. In addition, a portion of the second dielectric layer is 19 over the fourth conductive layer 82 beyond the contact area 50 to build.

2C shows the electrical diagram of the capacitor device 2A , Opposite the in 1C shown electrical circuit diagram is now a third capacitor 96 to recognize that between the first external connection 1 as well as the fourth external connection 4 is switched. The third capacitor 96 is formed by the fourth conductive layer in conjunction with the third dielectric layer and the third conductive layer. Now turn the first external connection 1 with the third external connection 3 as well as the fourth external connection 4 with the second external connection 2 electrically connected, resulting in a parallel connection of the first capacitor 60 , second capacitor 62 and third capacitor 96 , which results in a further increase in the resulting capacitance over a capacitance, such as from an electrically conductive connection of the external terminals 1 and 3 the in 1C shown capacity results.

The Area capacity (i.e. the capacity per chip area) let yourself by further stacking of dielectric layers and conductive Increase layers further. This requires a repetition of the deposition processes as well as a Adaptation of the structuring of the multiple layer structure.

A comparison of simulation values of single and multiple dielectric layers in a capacitor device confirms that the capacitance for z. B. three deposited dielectric layers by a factor 3 can be increased. For this purpose can 3A the schematic structure of a simple stack structure with two conductive layers and a dielectric layer are removed. As from the schematic structure in 3A 1, a first conductive layer PO1 is separated from a second conductive layer PO2 by a dielectric layer OX1. In contrast, the in 3B illustrated schematic structure of a multi-stack structure with four conductive layers and three dielectric layers. In this multi-stack structure, the first conductive layer PO1 is separated from the second conductive layer PO2 by the first dielectric layer OX1, which in turn is separated from a third conductive layer PO3 by a second dielectric layer OX2. The third conductive layer PO3 is separated from a fourth conductive layer PO4 by a third dielectric layer OX3.

3C shows a diagram of a simulation result of a 2D simulation of the in 3A and 3B illustrated structures of capacitor devices. In this case, the abscissa represents the frequency in hertz (Hz), while the ordinate represents the capacitance C in the unit femto-farad per μm [fF / μm]. This in 3C shown simulation result shows that a simple stack construction, as in 3A an exemplary specific capacitance C _spec = 17.3 fF / μm for a dielectric thickness d of 20 nm, an ε of 3.9 and a trench depth of 10 μm in a frequency range from one kilohertz to one gigahertz. As an indication, it should be noted that the width of the capacitor component represents the third dimension. Taking into account the width L, one must start from a specific capacitance C 'which satisfies the equation C' = ε ₀ × μ L / d. The simulation result for the simple stack construction is indicated by a dashed line 100 in the diagram in 3C shown. In contrast, a multistack construction with three dielectric layers, as it is known in US Pat 3B is shown, a specific capacity C _spec = 52 fF / μm over said frequency range, which in the diagram in 3C leads to a simulation result by a solid line 102 is shown. It can be seen here that the specific capacitance C _spec for three deposited dielectric layers is approximately one factor 3 can be increased. The illustrations in 3A and 3B However, only give the schematic structure of the components again, a true to scale reproduction of reality is also not apparent from the representations.

Even though above preferred embodiments closer to the present invention have been explained, It is obvious that the present invention is not limited to these embodiments limited is. In particular, the present invention also applies on capacitor components that have a different arrangement of contact areas as well as more than four conductive layers and three dielectric layers Have layers.

1

first external connection

2

second external connection

3

third external connection

4

fourth external connection

10

substratum

12

dig

13

Surface of the substrate 10

14

First conductive layer

16

First dielectric layer

18

Second conductive layer

19

Second dielectric layer

20

third conductive layer

22

covering

30

Openings of the cover layer 22

32

Surface of the covering

341

first contact point

342

second contact point

343

third contact point

344

fourth contact point

50

contact area

60

first capacitor

62

second capacitor

80

third dielectric layer

82

Fourth conductive layer

90

Another contact area

92

Common axis of rotation of the contact area 50 with the

further contact area 90

94

predefined angle

96

third capacitor

PO1

First conductive layer

OX1

First dielectric layer

PO2

Second conductive layer

OX2

Second dielectric layer

PO3

third conductive layer

OX3

third dielectric layer

PO4

Fourth conductive layer

100

dashed Line of the simulation result for a simple stack structure of the capacitor device

102

solid Line of the simulation result for a multistack structure of the capacitor device

Claims (11)

Capacitor component with the following features: a substrate ( 10 ); a ditch ( 12 ) contained in the substrate ( 10 ) is formed; at least three conductive layers ( 14 . 18 . 20 ) and at least two dielectric layers ( 16 . 19 ), the conductive layers ( 14 . 18 . 20 ) and the dielectric layers ( 16 . 19 ) alternating in the trench ( 12 ) are arranged. Capacitor device according to Claim 1, in which the substrate ( 10 ) a highly-doped subregion ( 14 ) on a wall of the trench, wherein one of the at least three conductive layers ( 14 . 18 . 20 ) through the heavily doped subregion ( 14 ) is formed. A capacitor device according to claim 1 or 2, comprising a first contact terminal and a second contact terminal, wherein the first contact terminal is electrically isolated from the second contact terminal, and wherein the conductive layers (14). 14 . 18 . 20 ) are alternately connected to the first contact terminal or the second contact terminal. Capacitor component according to one of Claims 1 to 3, in which at least one conductive layer ( 18 ) on a surface ( 13 ) of the substrate ( 10 ) and in one on the surface ( 13 ) of the substrate ( 10 ) arranged contact area ( 50 ) is contactable. Capacitor component according to one of Claims 1 to 4, in which the trench ( 12 ) has a circular symmetrical, square, rectangular or oval shape. Capacitor component according to one of Claims 1 to 5, comprising at least four conductive layers ( 14 . 18 . 20 . 82 ) and at least three dielectric layers ( 16 . 19 . 80 ), wherein at least two conductive layers ( 16 . 20 ) on a surface ( 13 ) of the substrate ( 10 ) and in each case on the surface ( 13 ) of the substrate ( 10 ) arranged contact area ( 50 . 90 ) are contactable and wherein the contact areas ( 50 . 90 ) of substantially the same size on the surface ( 13 ) of the substrate ( 10 ) and offset from one another. Capacitor component according to one of Claims 1 to 6, in which a covering layer ( 22 ) is formed on the substrate and the filled trench, the at least one opening ( 30 ), through which one of the conductive layers ( 82 ) is contactable. A method of manufacturing a capacitor device comprising the steps of: a) providing a substrate ( 10 ), wherein in the substrate ( 10 ) a ditch ( 12 b) forming a first conductive layer ( 14 ) in the trench ( 12 ); c) forming a first dielectric layer ( 16 ) in the trench ( 12 ) connected to the first conductive layer ( 14 ) adjoins; d) forming a second conductive layer ( 18 ) in the trench ( 12 ) attached to the first dielectric layer ( 16 ) and from the first conductive layer ( 14 ) is electrically isolated; e) forming a second dielectric layer ( 19 ) in the trench ( 12 ) connected to the second conductive layer ( 18 ) adjoins; and f) forming a third conductive layer ( 20 ) in the trench ( 12 ) connected to the second dielectric layer ( 19 ) and of the second conductive layer ( 18 ) is electrically isolated. Method according to claim 8, wherein step (b) involves diffusing dopant atoms into the substrate comprises in the region of a trench wall. The method of claim 8 or 9, further comprising the step of: forming a first contact terminal and a second contact terminal electrically isolated from the first contact terminal, the conductive layers 14 . 18 . 20 ) are alternately connected to the first contact terminal or the second contact terminal. Method according to one of claims 8 to 10, further comprising the steps of: forming a cover layer ( 22 ) on the substrate ( 10 ) and the ditch ( 12 ); and forming at least one opening ( 30 ) in the cover layer ( 22 ) through which one of the conductive layers ( 82 ) is contactable.