DE102021201103A1 - DC VOLTAGE CONVERTER - Google Patents

Abstract

A DC-DC converter according to the invention comprises at least one stage. Each stage comprises a parallel circuit made up of an input capacitor (C _In ) and a series circuit which has at least one inductance (L) and at least one switch (S ₁ ). The parallel connection of the stage includes a first connection and a second connection. The first terminal is connected to the input capacitor (C _In ) and the inductor (L) of the stage, and the second terminal of the parallel circuit is connected to the input capacitor (C _In ) and the switch (S ₁ ) of the primary stage. At least one of the stages includes a clamp circuit. The clamp circuit includes an energy buffer (C _sn ) having a first terminal connected to a node between the inductor (L) and the switch (S ₁ ) of the stage and a second terminal. The clamping circuit is designed to connect the second terminal of the energy buffer (C _sn )
• during at least part of a blocking state of the switch (S ₁ ) of the stages to connect to the first terminal of the parallel circuit of one of the stages, and
• to connect during at least part of a conducting state of the switch (S ₁ ) of the stages to the second connection of the parallel circuit of one of the stages via a separate path from the switch of the stage.

Description

field of invention

The present invention relates to the field of DC-DC converters, in particular to single- or multi-stage converter topologies, e.g. flyback converters, forward converters or push-pull converters, without galvanic isolation, which use inductive components, e.g Use components, e.g. transformers, as energy-transmitting components.

Background of the Invention

A well-known topology of a DC-DC converter in the form of a flyback converter with galvanic isolation is described, for example, by U. Tietze and C. Schenk in semiconductor circuit technology, Springer-Verlag, 12th edition, year 2002, chapter 16.7.1 single-ended converter, pages 952-954 , ISBN3540428496 and is described in 1 shown. The flyback converter includes an input 100 having input terminals 100a and 100b between which an input capacitor C _In is connected, and an output 102 having output terminals 102a and 102b between which an output capacitor C _Out is connected. Furthermore, the flyback converter includes a transformer Tr ₁ , which includes a first or primary-side coil or inductor L _Wp1 and a second or secondary-side coil or inductor L _Wp2 , which are electrically or magnetically coupled to one another, for example. A series circuit on the primary side comprising the coil L _{Wp1 on} the primary side and a switch S ₁ is connected between the input terminals 100a, 100b or is connected in parallel with the input capacitor C _In . A first terminal of primary side coil L _Wp is connected to input terminal 100a, a second terminal of primary side coil L _Ws is connected to a first terminal of switch S ₁ , and a second terminal of switch S ₁ is connected to input terminal 100b. A secondary-side series circuit comprising the secondary-side coil Lws and a diode D ₁ is connected between the output terminals 102a, 102b or is connected in parallel with the output capacitor Cout. A first terminal of the secondary side coil Lws is connected to the anode terminal of the diode D ₁ , the cathode terminal of the diode D ₁ is connected to the output terminal 102a, and a second terminal of the secondary side coil _Lws is connected to the output terminal 102b.

the inside 1 The flyback converter shown is used, for example, in large numbers as a DC voltage converter, DC/DC converter, in the power range up to a few 100 watts, if galvanic isolation between the input and output side is required, see above. E.g. in power supply units of PCs or chargers for portable devices. At the in 1 In the circuit shown, an input voltage U _In is buffered with the input capacitor C _In and applied to the primary winding L _Wp of the transformer Tr ₁ via the clocked switch S ₁ . The switching frequency is typically in the range of several kilohertz to megahertz. When the switch S ₁ is conductive, a current builds up in the primary winding L _Wp and energy is stored in the magnetic circuit of the transformer Tr ₁ . The secondary-side diode D ₁ is in the blocking state in this first section of the switching period, since it is operated in the reverse direction due to the winding sense of the transformer Tr ₁ . In the second section of the switching period, the switch S ₁ goes into the blocking state and due to the self-induction both the voltage of the primary winding L _Wp and the secondary winding L _Ws reverse. The diode D ₁ is then forward-biased and the energy previously stored in the magnetic circuit is, depending on the operating mode, wholly or partly transferred to the output capacitor Cout. The output capacitor Cout buffers the output voltage Uout so that a stable output voltage Uout is available despite the discontinuous energy transfer. The ratio of the input voltage U _In and the output voltage U _Out can be specified by the choice of the transformation ratio ü of the transformer Tr ₁ . The output voltage Uout is regulated by varying the duration of the conductive state or the on time of the switch S ₁ in relation to the duration of its switching period, the so-called duty cycle.

When using the 1 In the flyback converter topology described, the core material is used inefficiently due to the one-sided, magnetic modulation of the transformer core, so that economic use is limited to low outputs in the range of less than 1 kW. With greater power, the costs for control and the switches, which are very low in a flyback converter, play an increasingly smaller role. On the other hand, the cost of the transformer with its copper windings and magnetic core plays an increasingly important role, and the poor utilization of this component in the flyback converter makes the topology for higher powers increasingly unattractive.
Another limiting factor for using the flyback converter at higher power levels is its relatively low transfer efficiency, which increases the effort required to dissipate the heat loss. One reason for the limited efficiency of the topology is described below.

In a real transformer, the primary and secondary windings are not ideally coupled. Some of the energy is therefore not transferred to the secondary side of the transformer but is stored in the leakage inductances. Together with parasitic capacitances, such as the capacitance of the primary-side switch or the winding capacitance of the transformer, the stray inductances form an oscillating circuit.

When the switch on the primary side is switched off or when it changes to the blocking state, oscillations occur within this oscillating circuit and thus also across the switch. The amplitude of the oscillations can be significant and the frequency of the oscillation is often more than a decade above the switching frequency of the converter. Without suitable measures to dampen the vibration or limit the magnitude of the switch voltage, the switch can fail or become defective.

A countermeasure known from the prior art for damping the oscillation is the so-called snubber circuit, which absorbs the energy from the leakage inductance, thereby limiting the magnitude of the voltage overshoot and at the same time reducing the duration of the oscillation. A variety of snubber circuits are known. Some convert 100% of the energy from the leakage inductances to heat, thereby increasing the converter's losses. Many snubber circuits react inflexibly to voltage changes at the input of the converter, and their dampening effect cannot therefore be limited to the undesired oscillation alone in all work areas. A part of the primarily available energy is therefore immediately converted into heat without being stored in the leakage inductance beforehand. With low-loss snubbers, also referred to as lossless or regenerative snubbers, it is possible to recover part of the electrical energy from the leakage inductances for the circuit, but this is associated with considerable additional effort and additional costs.

Exemplary snubber circuits are, for example, in U.S. 10,135,344 B2 , the DE 36 34 990 A1 , the U.S. 5,734,563 A , the U.S.A. 4,959,764 or the DE 10 2016 117 936 A1 described.

For single-stage converters, the U.S.A. 4,959,764 considered, from which the in 2 shown flyback converter topology with galvanic isolation. The flyback converter topology according to 2 essentially corresponds to the in 1 illustrated topology. Unlike in 1 For example, the first terminal of switch S ₁ is connected to input terminal 100a, the second terminal of switch S ₁ is connected to the first terminal of primary side inductor L _Wp , and the second terminal of primary side inductor L _Wp is connected to input terminal 100b.

Furthermore, the topology includes, on the primary side, a further series circuit comprising a snubber capacitor C _sn and a snubber switch S _sn , which is connected up in parallel with the coil L _Wp on the primary side. A first terminal of the snubber capacitor C _sn is connected to the first terminal of the primary side coil L _Wp , a second terminal of the snubber capacitor C _sn is connected to a first terminal of the snubber switch S _sn , and a second terminal of the snubber Switch S _sn is connected to the second terminal of the primary-side coil L _Wp . A further diode D ₂ and a further coil or inductance L ₁ are provided on the secondary side. The cathode of the further diode D ₂ is connected to the cathode of the diode D ₁ or the first output connection 102a. The anode of the further diode D ₂ is connected to the second terminal of the coil L _Ws on the secondary side. Furthermore, the anode of the further diode D ₂ or the second terminal of the secondary-side coil Lws is connected to the second output terminal 102b via the further coil L1.

In 2 the switches are shown as metal-oxide-semiconductor field-effect transistors, MOSFETs, with an anti-parallel body diode. In 2 also shows the parasitic capacitance of the MOSFET.

The switches mentioned in the present description enable a bidirectional current flow in the conducting state. A diode is therefore connected in parallel with switches that cannot manage this bidirectional current flow themselves. In the present description, the switches used are also shown in simplified form, e.g. by the in 3(a) shown simplified representation of a switch, which can be implemented in practice by a semiconductor switch, eg by a MOSFET with body diode, see 2 and 3(b) , by an insulated-gate bipolar transistor (IGB-T), with external anti-parallel diode, see 3(c) , or by a bipolar transistor (English bipolar junction transistor), BJT, with external, anti-parallel diode, see 3(d) .

The DC/DC converter according to 2 uses an additional switch, S _s , on the primary side. The circuit allows high efficiency in recovering the energy from the leakage inductance. In addition, the body diode of the Switch S _sn in conjunction with the capacitor C _sn as a reliable voltage limitation for the switch S ₁ . Furthermore, a zero-voltage switching for the main switch S ₁ can be achieved by suitable control of the switch S _sn . In order for the capacitor C _sn to expand due to the energy absorption from the in 2 If the leakage inductance (not shown) of the transformer winding L _Wp does not continue to charge, the switch S _sn is activated in the blocking phase of S ₁ and thereby allows a reversal of the current direction in the capacitor C _sn and in the magnetizing inductance L _Wp of the transformer, which also causes the zero Voltage switching can be achieved.

Similar circuits are for example in the U.S. 4,975,821A , the U.S. 5,126,931A , the U.S. 5,173,846 A , the U.S. 5,303,138 A , the U.S. 5,528,482 A or the U.S. 5,734,563 A described.

For multi-stage converter is an example DE 10 2016 117 936 A1 considered, from which the in 4 illustrated multi-stage flyback converter topology with galvanic isolation can be removed. 4 shows a topology with four stages 104 ₁ -104 ₄ connected in series on the primary side. The secondary is in 4 not shown. Each stage 104 ₁ -104 ₄ comprises a parallel circuit made up of the input capacitor C _In1 -C _In4 and a series circuit which has the primary-side inductance L _{Wp1 -} L _Wp4 and the switch S ₁ -S ₄ . The input capacitors C _In1 -C _In4 are connected in series between the input terminals 100a, 100b of the input 100. The parallel circuit of each stage 104 ₁ -104 ₄ includes a first port 104a ₁ -104a ₄ and a second port 104b ₁ -104b ₄ . The first connection 106an (n=1, 2, 3, 4, . . . N) of the primary-side inductance L _Wpn of a stage 104 _n is connected to the first connection 104an or to the first connection of the input capacitor C _Inn , the second connection 106b _n of the primary side inductance L _Wpn of a stage 104 _n is connected to the first terminal 108an of the switch S _n and the second terminal 108b _n of the switch S _n is connected to the second terminal 104b _n of the stage and to the second terminal of the input capacitor, respectively Connected to C _Inn .

Furthermore, the in 4 illustrated multi-stage flyback converter topology, the capacitors C _c1 -C _c3 , referred to there as synchronization capacitors, which are each connected between the terminals 106b and 108a of adjacent stages, i.e. between the second terminals 106b of the primary-side inductance L _Wp1 -L _Wp4 or between the first terminals 108a of switches S ₁ -S ₄ . In addition, the circuit includes the diode D _Clamp , referred to there as a clamping diode, whose anode is connected to the second connection 106b ₂ of the primary-side inductance L _Wp2 or the first connection 108a ₂ of the switch S ₂ of the second stage 104 ₂ , and whose cathode is connected to the first port 104a ₃ of the third stage 104 ₃ and the second port 104b ₄ of the fourth stage 104 ₄ .

in the in 4 In the circuit shown, the stages or primary stages 104 _n are connected in series and there is a capacitor C _cn from each first terminal 108an of the switch S _n to the next, thereby resisting a voltage change across the same within a switching period, and therefore in connection with the one can also speak of a rectification of the switch voltage over a period of stable voltage of the input capacitors. The logic signal of the switches S ₁ -S ₄ is the same for all switches, so that all switches conduct and block at the same time. When the switches go into the off state, the diode D _Clamp provides the limit on the switch voltage. In this case, part of the energy from the leakage inductances of the primary windings L _Wpn is absorbed in the capacitors Ccn, while another part flows directly back into the input capacitors C _Inn via the diode D _Clamp .

When the switches turn conductive together, each capacitor C _cn is connected in parallel with one of the input capacitors C _Inn , equalizing the voltage of the capacitors and dissipating the energy absorbed by the capacitors C _cn by a charge pumping process across the conductive switches S _n is transferred to the input capacitors C _Inn . The latter prevents overcharging of the capacitors C _cn and also ensures a stable clamping voltage.

The voltages at the input capacitors C _Inn are balanced in two ways. On the one hand, the magnetic coupling of the windings L _Wpn ensures that the voltages are equalized during the conducting phase of the switches S _n . Due to the magnetic coupling, the same voltage is applied to each winding L _Wpn , differences are only possible due to the presence of a leakage inductance between the windings and result in a current flow. This current flow ensures a charge exchange between the input capacitors C _Inn and thus the balancing of the voltages across the input capacitors C _Inn .

On the other hand, the charge pump process also ensures that the voltages at the input capacitors C _Inn are balanced. For example, a lower voltage across one of the input capacitors C _Inn would cause the charge pump pen process during the conducting phase of the switches S _n also lead to a lower voltage across the associated capacitor C _cn . This would in turn mean that less voltage can build up across the leakage inductance of the associated winding L _Wpn during the blocking phase of the switch S _n , so it will take more time to release the energy from this leakage inductance. As a result, a current flows longer through the associated capacitor C _cn , so that it absorbs more charge. During the next conducting phase of the switches S _n , this charge is passed on to the associated input capacitor C _Inn via the charge pump process. Since the associated input capacitor C _Inn receives more charge than that of the other primary stages, its voltage swing is also larger during this charge pumping process, which promotes the balancing of the voltages across the input capacitors.

Furthermore, be on the DE 44 22 409 A1 referred, which describes a method and a device for charge exchange between a plurality of series-connected energy storage devices or energy converters. Also from the DE 44 22 409 A1 it is known to provide capacitors between the series-connected energy stores, which absorb the energy stored in the leakage inductances and return it without loss, so that the circuit can reliably prevent voltage peaks from occurring across the switches.

Proceeding from the prior art described above, the object of the present invention is to provide a DC-DC converter and a method to avoid the disadvantages identified in the above-described, known DC-DC converters with capacitors connected between the stages and described below.

This object is achieved by a DC-DC converter according to claim 1 and by a method according to claim 15.

character list

• 1 eine bekannte Sperrwandler-Topologie mit galvanischer Trennung,
• 2 eine Sperrwandler-Topologie mit galvanischer Trennung entsprechend der US 4 959 764 A ,
• 3 die in dieser Beschreibung verwendete, vereinfachte Darstellung eines Schalters, siehe 3(a) und Beispiele von Halbleiter-Schaltern, welche in der Praxis eingesetzt werden können, siehe 3(b), 3(c) und 3(d),
• 4 eine Sperrwandler-Topologie mit galvanischer Trennung entsprechend der DE 10 2016 117 936 A1 ,
• 5 die Strompfade in der Schaltung nach 4, wenn nach einer leitenden Phase aller Schalter ein Schalter als letzter in den sperrenden Zustand übergeht,
• 6 ein erstes Ausführungsbeispiel der vorliegenden Erfindung, gemäß dem die erfindungsgemäße Klemmschaltung in einer einstufigen Gleichspannungswandlerschaltung realisiert ist,
• 7 ein Ausführungsbeispiel der vorliegenden Erfindung, gemäß dem die erfindungsgemäße Klemmschaltung in einer mehrstufigen Gleichspannungswandlertopologie eingesetzt wird,
• 8 ein Ausführungsbeispiel der erfindungsgemäßen Klemmschaltung,
• 9 ein weiteres Ausführungsbeispiel der erfindungsgemäßen Klemmschaltung,
• 10 verschiedene Ausführungsbeispiele der Schaltungsanordnung der Klemmschaltung gemäß 8 oder 9,
• 11 ein Ausführungsbeispiel eines einstufigen Gleichspannungswandlers, welcher die erfindungsgemäße Klemmschaltung gemäß 9 aufweist, bei welcher die Schaltungsanordnung einen Aufbau gemäß 10(a) hat,
• 12 ein Ausführungsbeispiel eines Gleichspannungswandlers mit zwei Stufen, bei dem die zweite Stufe eine Klemmschaltung aufweist, welche gemäß 8 in Verbindung mit 10(a) aufgebaut ist,
• 13 ein weiteres Ausführungsbeispiel eines mehrstufigen Gleichspannungswandlers gemäß der vorliegenden Erfindung,
• 14 ein wiederum weiteres Ausführungsbeispiel eines erfindungsgemäßen Gleichspannungswandlers mit mehreren Stufen, bei dem in mehreren der Stufen eine Klemmschaltung vorgesehen ist,
• 15 die Strompfade der Schaltung gemäß 13, wenn beim Übergang von der leitenden Phase aller Schalter in die sperrende Phase ein Schalter kurzzeitig im leitenden Zustand verbleibt;
• 16 die Schaltung gemäß 13, bei der nur ein Schalter leitet,
• 17 ein Ausführungsbeispiel eines Gleichspannungswandlers, bei dem N, N≥2, Stufen in Reihe geschaltet sind,
• 18 ein weiteres Ausführungsbeispiel eines Gleichspannungswandlers mit drei Stufen, ähnlich der Ausführungsform gemäß 14, bei der anstelle der in 14 beschriebenen Klemmschaltungen die zweite und dritte Stufe jeweils eine Klemmschaltung umfassen, welche gemäß 9 in Verbindung mit 10(a) aufgebaut ist,
• 19 ein Ausführungsbeispiel eines erfindungsgemäßen Gleichspannungswandlers mit zwei in Reihe geschalteten Primärstufen, welche jeweils eine Klemmschaltung gemäß den Lehren der vorliegenden Erfindung umfassen,
• 20 einen dreistufigen Gleichspannungswandler mit den Klemmschaltungen, welche gemäß 8 und 10(a) bzw. gemäß 9 und 10(a) aufgebaut sind,
• 21 ein Ausführungsbeispiel für die Symmetrierung der Spannungen an den Eingangskondensatoren durch eine magnetische Kopplung der primärseitigen Wicklungen von mehrstufigen Gleichspannungswandlern,
• 22 ein Ausführungsbeispiel für die Symmetrierung der Spannungen an den Eingangskondensatoren durch eine elektrische Kopplung der Sekundärwicklungen von mehrstufigen Gleichspannungswandlern,
• 23 ein Ausführungsbeispiel der vorliegenden Erfindung zur Symmetrierung der Spannungen an den Eingangskondensatoren durch Parallelschaltung der DC-Ausgänge der Sekundärstufen,
• 24 ein Ausführungsbeispiel zur Symmetrierung der Spannungen an den Eingangskondensatoren durch Regelung der Leistung jeder Stufe, und
• 25 ein weiteres Ausführungsbeispiel zur Symmetrierung der Spannungen an den Eingangskondensatoren durch Regelung der Leistung jeder Stufe, Ausführungsbeispiele der vorliegenden Erfindung werden unter Bezugnahme auf die beigefügten Zeichnungen, in denen gleichen oder ähnlichen Elementen die gleichen Bezugszeichen zugeordnet sind, näher beschrieben.

Embodiments of the present invention will now be explained in more detail with reference to the accompanying drawings. Show it:

• 1 a known flyback converter topology with galvanic isolation,
• 2 a flyback converter topology with galvanic isolation according to the U.S.A. 4,959,764 ,
• 3 the simplified representation of a switch used in this description, see 3(a) and examples of semiconductor switches which can be used in practice, see 3(b) , 3(c) and 3(d) ,
• 4 a flyback converter topology with galvanic isolation according to the DE 10 2016 117 936 A1 ,
• 5 the current paths in the circuit 4 , if, after a conducting phase of all switches, one switch is the last to switch to the blocking state,
• 6 a first exemplary embodiment of the present invention, according to which the clamping circuit according to the invention is implemented in a single-stage DC-DC converter circuit,
• 7 an embodiment of the present invention, according to which the clamping circuit according to the invention is used in a multi-stage DC-DC converter topology,
• 8th an embodiment of the clamping circuit according to the invention,
• 9 another embodiment of the clamp circuit according to the invention,
• 10 various exemplary embodiments of the circuit arrangement of the clamping circuit according to FIG 8th or 9 ,
• 11 an embodiment of a single-stage DC-DC converter, which according to the clamp circuit of the invention 9 has, in which the circuit arrangement has a structure according to 10(a) Has,
• 12 an embodiment of a DC-DC converter with two stages, in which the second stage has a clamp circuit, which according to 8th combined with 10(a) is constructed,
• 13 a further embodiment of a multi-stage DC-DC converter according to the present invention,
• 14 yet another exemplary embodiment of a DC/DC converter according to the invention with a plurality of stages, in which a clamping circuit is provided in a number of the stages,
• 15 the current paths of the circuit according to 13 , if during the transition from the conducting phase of all switches to the blocking phase one switch briefly remains in the conducting state;
• 16 the circuit according to 13 , where only one switch conducts,
• 17 an embodiment of a DC-DC converter in which N, N≥2, stages are connected in series,
• 18 another embodiment of a DC-DC converter with three levels, similar to the embodiment according to FIG 14 , at which instead of in 14 described clamping circuits, the second and third stages each comprise a clamping circuit, which according to 9 is constructed in connection with 10(a),
• 19 an embodiment of a DC-DC converter according to the invention with two series-connected primary stages, each of which comprises a clamping circuit according to the teachings of the present invention,
• 20 a three-stage DC-DC converter with the clamping circuits, which according to 8th and 10(a) or according to 9 and 10(a) are built up
• 21 an embodiment for balancing the voltages at the input capacitors by magnetic coupling of the primary-side windings of multi-stage DC-DC converters,
• 22 an embodiment for balancing the voltages at the input capacitors by electrically coupling the secondary windings of multi-stage DC voltage converters,
• 23 an embodiment of the present invention for balancing the voltages at the input capacitors by parallel connection of the DC outputs of the secondary stages,
• 24 an embodiment for balancing the voltages on the input capacitors by controlling the power of each stage, and
• 25 another embodiment for balancing the voltages on the input capacitors by controlling the power of each stage. Embodiments of the present invention will be described in more detail with reference to the accompanying drawings, in which the same reference numerals are assigned to the same or similar elements.

Disadvantages of circuits known from the prior art

The inventors of the present invention have examined the known rectifier circuits described above and found disadvantages which are eliminated according to the invention.

Disadvantages of the U.S.A. 4,959,764 known circuit according to 2 are primarily in the complexity of driving the switch S ₁ , because this is a high-side switch. If a MOSFET is used for this switch, then the reference point of the control, the source connection of the MOSFET, has a potential that changes with each switching state. This results in the need for a gate driver supply and a gate driver input signal that function correctly despite constant potential changes. The resulting circuit complexity increases the cost of the converter. The generation of the control signal for the two switches is also complex, because on the one hand the control signal for both switches is not the same or simply inverted, and on the other hand the control also requires measurement technology effort, depending on the circuit implementation, in order to achieve zero-voltage switching enable.

The ones from the DE 10 2016 117 936 A1 or from the DE 44 22 409 A1 Known direct coupling of the switch voltages via the capacitors C _cn , which is very effective particularly for rapid changes, has disadvantages since differences in the actuation or in the component tolerances of the switches result in the switching times of the switches S _n deviating slightly from one another or not exactly are the same. In fact, a small shift in the switching times of the switches S _n can never be completely prevented.

An example is considered below in which all switches of the primary stages were initially conductive and a current built up in the magnetizing inductance. The switches then go into the blocking state, but one switch is delayed. 5 shows the current paths in the circuit 4 , if, after a conducting phase of all switches, switch S ₁ is the last to switch to the blocking state. With each switch S _n which goes into the blocking state, the winding current commutates from the switch to the capacitor C _cn . Depending on the position of the switch, this current flows via additional capacitors to the still conducting switch S ₁ . Ultimately, in this example, switch S ₁ takes over the currents of all primary stages. Since there is only a very brief moment in which all currents are concentrated on a switch, this generally does not pose a direct problem for this switch. However, the switching losses of this switch will be correspondingly higher.

Depending on the choice of switching frequency or the ratio of switching time to clock period, the switching losses can be the dominant losses of the switches and thus have a significant influence on their heating. If such a resulting asymmetry of the switching losses when developing the If the cooling concept was not taken into account, this can lead to overheating of individual switches. This can be amplified, for example, when using MOSFETs as switches due to the thermal dependence of their threshold voltage. A higher chip temperature MOSFET will generally switch state at a lower threshold voltage, causing it to turn on earlier and turn off later than a lower chip temperature switch. This can lead to positive feedback on the switching losses and ultimately thermal runaway for the switch.

Another disadvantage of direct coupling of all switch voltages is that driving the transformer windings individually is not possible, but this can be desirable, especially in cases of low output power in relation to the rated power of the overall converter, in order to build up a lower current in the magnetizing inductance. At low output powers, depending on the topology on the secondary side, a very short on-time of the switches may be necessary. This is problematic for controlling the switches in several respects. The reason for this is that, depending on the control circuit, minimum switch-on times are required and pulses that are too short are not passed on to the switch at all. In any case, the driver needs a certain amount of time to turn on the switch completely, so too short an on-time leads to operation of the switches in which they do not reach their full capacity, making the transfer of power to the secondary side more inefficient.

If, on the other hand, the windings of the individual primary stages could be operated independently of one another, it would be possible with low output power to control the windings not simultaneously but cyclically or periodically one after the other, e.g. by activating only one switch of a primary stage within a switching period. Thus, the on-time of that one switch could be lengthened accordingly.

Another disadvantage of using capacitors C _cn for direct coupling of all switch voltages is that they, in conjunction with the magnetic coupling of the windings, result in a parallel connection of leakage inductances and capacitors C _cn . The resulting parallel resonant circuit, which depending on the state of the switch also includes other components, can in turn be the starting point for new unwanted oscillations in the system. This oscillating circuit is again excited by the previously described slight time offset in the state change of the switches, which in practice can never be completely ruled out.

Solution according to the invention

The aforementioned disadvantages of conventional direct-current converters are solved according to the present invention in that an energy buffer, e.g. a capacitor, is no longer permanently connected, but instead is switched according to the invention between different nodes, depending on the state of the switch of a stage, so that the winding or the switch of each stage is provided with its own commutation path for the current, which is active until the energy in the respective leakage inductance has been dissipated.

Embodiments of the present invention provide a clamp circuit that includes at least the energy buffer. A first connection of the energy buffer is connected to the node between the inductance and the switch of a stage. A second terminal of the energy buffer is optionally connected to a parallel circuit of an input capacitor and a series circuit comprising an inductor and a switch of any stage, e.g. to a first terminal or a second terminal of a parallel circuit of the stage, or, in the case of multi-stage embodiments , connected to a first terminal or a second terminal of parallel circuits of any stages.

According to the teachings of the present invention, this ensures that during the conducting state of the switch of a stage, which is equipped with the clamping circuit, the energy buffer at its second terminal with an input terminal of the stage or, in multi-stage configurations of the circuit, with an input terminal of a any of the stages can be connected. In this case, a current path is provided for the second connection of the energy buffer, which does not run via the switch or switches of the stages, so that a separate path is provided by the switch or switches to discharge the charges which the energy buffer carries out during the blocking phase of the stage switch through the current flowing through it, to allow the input capacitor or the input capacitors.

During the blocking phase of the stage switch equipped with the clamp circuit, the clamp circuit is able to take over the current flow from the stage switch, thereby avoiding voltage spikes at the switch, as well as dampening oscillations.

Since the clamp circuit is only active when current is commutated to it from the switch or charge is transferred to the input capacitor, it achieves its goal of limiting the switch voltage and damping the oscillation without permanently balancing all the switch voltages and without building up another, continuous oscillating circuit. This results in the advantages mentioned above, the possibility of separate control of the windings, avoiding the construction of a parallel circuit with the leakage inductance that is capable of oscillating, and at different switching times of the primary switches, preventing the commutation of the currents from stages with switches that are already blocking to stages with switches that are still conductive switches. The latter is ensured by the energy in the leakage inductances, because as long as this maintains the flow of current via the clamping circuit in the blocking phase of a switch of a stage, this proportion of the magnetizing current does not flow via the switches that are still in the conducting state.

According to exemplary embodiments, the clamp circuit according to the invention is used in single-stage converter topologies or in multi-stage converter topologies, it being possible for multi-stage converter topologies to have one or more of the stages with the clamp circuit according to the invention.

According to exemplary embodiments, the clamping circuit according to the invention can be used in single-stage or multi-stage converter topologies without electrical isolation, in which case the stage or stages have an inductance, e.g. B. in the form of a coil or storage choke. According to other exemplary embodiments, the clamping circuit according to the invention is used in a single-stage or multi-stage DC/DC converter with galvanic isolation, so that the circuit comprises one or more primary stages connected in series and one or more secondary stages. In such exemplary embodiments, the secondary stage or stages includes respective inductances, which form a transformer in the case of a single-stage topology. In the case of a multi-stage topology, the primary-side and secondary-side inductances form the windings of one or more transformers, for example depending on whether two or more of the inductances or windings of the stages are magnetically coupled on the primary side or not.

Single-stage DC-DC converter circuit

6 shows a first exemplary embodiment of the present invention, according to which the clamping circuit according to the invention is implemented in a single-stage DC-DC converter circuit. The basic structure of the in 6 shown circuit, more precisely the one in 6 illustrated, single stage of the circuit corresponds to the basis of 1 previously described structure. In the 6 The stage 104 shown comprises an input 100 with the input terminals 100a and 100b, as well as the parallel circuit comprising the input capacitor C _In and the series circuit comprising the inductance L and the switch S ₁ . At the in 6 In the single-stage embodiment shown, the terminals 104a, 104b of the stage 104 correspond to the input terminals 100a, 100b of the DC/DC converter. The first terminal 106a of the inductance L is connected to the terminal 104a of the stage and the second terminal 106b of the inductance L is connected to a first terminal 108a of the switch S ₁ . The second terminal 108b of switch S ₁ is connected to the second terminal 104b of stage 104 .

6 further illustrates a clamp circuit 200 comprising at least one energy buffer C _sn , e.g. B. in the form of one or more capacitors C _sn . The clamp circuit 200 includes a first terminal 200a, a second terminal 200b and a third terminal 200c. The energy buffer C _sn includes, as in 6 1, a first terminal 202a and a second terminal 202b, the first terminal 202a of the energy buffer C _sn being connected to a node or terminal K3 between the second terminal 106b of the inductance L and the first terminal 108a of the switch S ₁ . The clamp circuit 200 is configured to selectively connect the second terminal 202b of the energy buffer C _sn to a node K1 between the first terminal 106a of the inductance L and the first terminal 104a of the stage or a node K2 between the second terminal 108b of the switch and the second terminal 104b of the stage to connect. In other words, the node K1 is the first terminal of the aforesaid parallel circuit of the stage and the node K2 is the second terminal of the aforesaid parallel circuit of the stage.

When the switch S ₁ is off, which is also referred to as the open switch state or off-time of the switch, the clamping circuit 200 causes the connection of the second connection 202b of the energy buffer C _sn to the connection K1, so the second connection 202b of the energy buffer C _sn is connected connected to port 104a of stage 104. When the switch S ₁ is off, the clamp circuit 200 causes a current to flow from the switch S ₁ to the energy buffer C _sn and is thus able to avoid voltage spikes at the switch S ₁ .

With switch S ₁ conducting, also referred to as the closed switch state or switch on-time, the clamp circuit 200 causes the second terminal 202b of the energy buffer C _sn to be connected to terminal K2, i.e. the second terminal 202b of the energy buffer C _sn is connected to the second port 104b of the level connected. When the switch S ₁ is conducting, the energy buffer C _sn is connected between the terminals K2 and K3, causing a charge drain from the energy buffer C _sn to the input capacitor C _In if the voltage across the energy buffer C _sn is higher than the voltage across the capacitor C _In . How out 6 can be seen, the charge equalization in this situation takes place via a path from the energy buffer C _sn via the connection K2 to the input capacitor C _In , i.e. not via the switch S ₁ but via a path separate from the switch, which means that the disadvantages described above in connection with occurring Vibrations are avoided or reduced.

At this point it is pointed out that the connection of the respective components described herein can either be directly to one another or that one or more additional components are provided in the connection paths between the respective components. For example, it can be provided according to exemplary embodiments to connect the energy buffer C _sn directly, ie without the interposition of further components, to the node K3, whereas in other exemplary embodiments one or more additional components, e.g. in the form of a diode or other switching element, can be connected between the first terminal 202a of the energy buffer C _sn and the third terminal 200c of the clamping circuit 200 .

At the in 6 illustrated embodiment is a single-stage DC-DC converter, which can be constructed with or without galvanic isolation. In the case of an embodiment without galvanic isolation, the inductance L is in the form of a coil or storage inductor, for example, and there is no secondary side. In the case of a design with galvanic isolation, the inductance L forms a primary winding of a transformer or autotransformer and the in 6 Stage 104 shown can also be referred to as the primary stage. In this case, similar to using the 1 has been described, a secondary side can be provided with a corresponding winding. Exemplary embodiments for the configuration of secondary sides in DC voltage converter topologies with galvanic isolation will be described in detail later.

Multi-stage DC voltage converter circuit

7 shows an embodiment of the present invention, according to which the clamp circuit according to the invention is used in a multi-level DC-DC converter topology. 7 shows a schematic representation of a DC-DC converter topology with N stages, with N ≥ 2. 7 Figure 10 illustrates stages 104 ₁ , 104 ₂ , 104 _n , 104 _N-1 and 104 _N . At least one of the stages mentioned comprises the clamping circuit 200 according to the invention, e.g. B. the stage 104 _n in 7 . The affiliation of a clamping circuit to a specific stage is determined depending on which node K3 the first connection 202a of the energy buffer C _sn of the clamping circuit 200 or the third connection 200c of the clamping circuit 200 is connected to. At the in 7 In the embodiment shown, the first connection 202a of the energy buffer C _sn is connected to the node K3 _n via the third connection 200c of the clamping circuit 200, so that the clamping circuit 200 is part of the stage 104 _n . According to embodiments of the present invention, the first and second terminals 200a and 200b of the clamp circuit 200 are connected to arbitrary terminals K1 and K2 of the other stages, respectively. For example, port 200a may be connected to port K1 _n and port 200b may be connected to port K2 ₁ . However, the present invention is not limited to such embodiments, rather, as just mentioned, each of the terminals 200a and 200b of the clamping circuit 200 with one of the terminals K1 and K2 of the parallel circuits of any of the stages, including the terminals K1 and K2 of Level 104 _n be connected.

According to further exemplary embodiments, in the case of a multi-stage configuration of the DC-DC converter according to FIG 7 at least one or more further stages identify a clamping circuit. In this case, the third connection 200c of the respective clamping circuit is connected to the corresponding node K3 of the respective stage. The respective terminals 200a and 200b of the clamping circuit can be connected to any terminals K1 or K2 of the stages, it being possible for the multiple clamping circuits to be connected to the terminals K1 and/or K2 of the parallel circuits of the same or different stages.

According to exemplary embodiments, it can be provided that, in the case of a multi-stage configuration of the DC-DC converter, those stages which do not have a clamping circuit have a diode (see e.g 12 ). Such a diode is provided such that its anode is connected to the node K3 of the stage which has no clamping circuit, and the cathode of the diode is connected to a first terminal K1 of a parallel circuit of any of the higher stages.

As already mentioned above, the clamping circuit 200 is designed or capable of selectively connecting the second connection of the energy buffer C _sn with a connection K1 or a connection K2 of the stage in which the clamping circuit is arranged, or, in the case of a multi-stage configuration according to 7 to connect the corresponding node of any other stage.

First embodiment of the clamping circuit - Variant A

8th illustrates an embodiment of the clamp circuit according to the invention. The clamping circuit 200 comprises the terminals 200a, 200b and 200c, which have already been explained above, and the energy buffer, which according to the illustrated embodiment is implemented by at least one capacitor C _sn , the first terminal 202a of which is connected to the third terminal 200c of the clamping circuit 200 . The second connection 202b of the capacitor C _sn is connected to a circuit arrangement 204 . The circuit arrangement 204 comprises a first connection 204a, which is connected to the first connection 200a of the clamping circuit 200, a second connection 204b, which is connected to the second connection 200b of the clamping circuit 200, and a third connection 204c, which is connected to the second connection 202b Capacitor C _sn of the clamp circuit 200 is connected. The circuit arrangement 204 is configured or able to connect the second connection 202b of the capacitor C _sn to the first connection 200a or to the second connection 200b depending on the state of the switch S of the stage in which the clamping circuit 200 is arranged.

At this point it should be noted that the energy buffer or capacitor C _sn is also referred to as a voltage-limiting capacitor or snubber capacitor.

Second embodiment of the clamping circuit - variant B

9 shows a further embodiment of the design of the clamping circuit 200, according to the addition to the basis of 8th described elements, the diode D _sn and the switch S _sn are provided. The diode D _sn is connected in such a way that its anode is connected to the third connection 200c of the clamping circuit 200 and thus to the node K3 of that stage which contains the clamping circuit. The cathode of the diode D _sn is connected to the first terminal 202a of the capacitor and its second terminal 202b, as also in FIG 8th , connected to the third connection 204c of the circuit arrangement 204 . The switch S _sn is connected between the first terminal 200a of the clamp circuit 200 and the first terminal 202a of the capacitor C _sn such that a first terminal of the switch S _sn is connected to the terminal 202a of the capacitor C _sn and the second terminal of the switch S _sn to the first connection 200a of the clamping circuit 200. According to embodiments, the switch S _sn can be implemented by an N-Ch MOSFET (N-channel MOSFET). In such embodiments, the source terminal of the MOSFET corresponds to the second terminal of the switch S _sn and is thus connected to terminal 200a of the clamp circuit. Since there is a stable voltage potential at connection 200a, driving such a MOSFET is just as easy as with the switches S _n of the primary stages; the drive circuit only has to equalize a DC voltage between the control signal and the MOSFET.

The embodiments of the clamping circuit according to 9 include in addition to the circuitry 8th the diode D _sn and the switch S _sn . However, the present invention is not in accordance with the configuration of the clamp circuit 9 limited, rather, instead of the diode or instead of the switch, other suitable switching elements can be provided, for example a diode instead of the switch S _sn and a switch instead of the diode D _sn .

The clamping circuit according to 8th does not require an additional active switch to limit the switch voltage, so the cost is lower than that of the clamp circuit shown in FIG 9 .

An advantage of the clamp circuit according to 9 is that it can be used to clamp to a higher voltage. It is therefore also possible with it to clamp twice the voltage U _{In in} the stage or the voltage across the input capacitor C _In with only one primary stage, so that the circuit can also be used when only one primary stage is used. The additionally required switch S _sn has, like the main switch S, a fixed reference potential even when several primary stages are connected in series. The control of this switch can therefore be implemented with little effort. In addition, this switch, as well as the diodes D _cl1n and D _c12n , look at the clamping circuit according to FIG 9 only part of the clamping voltage and can therefore be designed more cheaply.

The functions of the clamping circuits according to 8th and 9 are explained in more detail later with reference to further exemplary embodiments of the DC-DC converter circuit according to the invention.

Embodiments of the circuit arrangement of the clamping circuit

The circuit arrangement 204 according to the 8th and 9 operates to selectively connect the second terminal 202b of the capacitor C _sn to terminal 200a and terminal 200b of the clamp circuit 200, respectively, depending on the state of the switch of the stage to which the clamp circuit is associated, as previously mentioned. The clamp circuit is associated with that stage which includes the node K3 to which the third terminal 200c of the clamp circuit is connected. When the switch or switches are conductive in the stage or stages, the circuit arrangement 204 is able to connect the second terminal 202b of the capacitor C _sn to the second terminal 200b of the clamping circuit 200 at least temporarily, i.e. during part or all of conducting phase, which in turn, as previously mentioned, is connected to a terminal K2 of the parallel circuit of any stage. When the switch or switches are blocking, the circuit arrangement 204 is able to connect the second terminal 202b of the capacitor C _sn at least temporarily, i.e. during part of or during the entire blocking phase, to the first terminal 200a of the clamping circuit 200, which in turn is connected to connected to a terminal K1 of a parallel circuit of any one of the stages.

The circuit arrangement 204 can be implemented, for example, by using diodes or switches. 10 shows various exemplary embodiments of the circuit arrangement 204. 10(a) 12 shows an exemplary embodiment of the circuit arrangement 204, which includes a series circuit made up of the diodes D _cl1 and D _cl2 , which can also be referred to as clamping or voltage-limiting diodes. The diodes are connected between the terminals 200a and 200b of the clamp circuit 200 such that the cathode of the first diode D _{cl1 is} connected to the first terminal 200a of the clamp circuit 200 and that the anode of the second diode D _{cl2 is} connected to the second terminal 200b of the clamp circuit is connected. The anode of the first diode D _cl1 and the cathode of the second diode D _cl2 are connected to the node 206 of the circuit arrangement 204 and the second connection 202b of the capacitor C _sn is also connected to the node 206 . This in 10(a) The exemplary embodiment shown comprises the series connection of two diodes, but the present invention is not limited to such a configuration; rather, more than two diodes connected in series can also be provided.

10(b) shows a further exemplary embodiment of the circuit arrangement 204, which essentially consists of the arrangement 10(a) corresponds to, except that the diodes D _cl1 and D _cl2 are replaced by switches S _cl1 and S _cl2 .

10(c) 1 shows yet another exemplary embodiment of the circuit arrangement 204, in which instead of using two or more switching elements between the connections 200a and 200b, a single switch S _cl is provided which connects the node 206 which is connected to the second connection 202b of the capacitor C _sn is connected, optionally depending on the state of the switch of the stage in which the clamping circuit is arranged, to the terminal 200a or the terminal 200b of the clamping circuit.

Further exemplary embodiments of the DC-DC converter according to the invention, which includes one or more clamping circuits, are described below.

Exemplary embodiment of a single-stage DC voltage converter with a clamping circuit according to variant B

Based on 11 an embodiment of a single-stage DC-DC converter is explained below, which according to the clamping circuit according to the invention 9 has, in which the circuit arrangement has a structure according to 10(a) has, with the related to the 6 and 7 mentioned inductances in 11 is denoted as inductance L _Wp . The electrical input of the DC-DC converter 100, comprising the two input terminals 100a and 100b, is at the in 11 illustrated embodiment formed by the first terminal 104a of the stage 104 and by the second terminal 104b of the stage 104.

with the inside 11 The circuit shown can be used to build forward or flyback converters, for example. In these cases, the inductance L _Wp would represent a primary winding of a transformer.

When the main switch S goes into the blocking phase, the capacitor C _sn charges with the help of the energy from the leakage inductance of the transformer and the energy from the magnetizing inductance L _Wp . This charging process takes place, for example, in the first switching cycles after the circuit has been put into operation. The current flows through the series circuit consisting of D _sn , C _sn and D _cl1 . At the same time, the voltage across the switch S is limited by this series connection.

By turning on the switch S _sn occasionally or regularly during the conducting phase of S, the voltage of the capacitor C _sn is limited to the voltage across the input capacitor C _In , here the series connection of S _sn , C _sn , D _cl2 and C _In is active. According to embodiments, the switches S and S _sn are driven with the same logic signal. According to other exemplary embodiments, however, pulses can also be omitted when driving the switch S _sn in order to save on switching losses.

An asynchronous activation of the switch S _sn , ie for example the switching on of S _sn during the blocking phase of the switch S, is permissible. Depending on the case, energy can be fed back from the magnetizing inductance L _Wp into the input capacitor C _In , which means that, for example, the output voltage of the converter can be reduced at low output powers or low output currents without the on-time of the switch S must be reduced. This mode of operation can be useful in keeping the on-time of the switch S above a fixed minimum that is required in practice for driving the switches.

By limiting the voltage across C _sn to the level of the input voltage, the switch voltage across S is simultaneously limited to twice the input voltage. At the same time, the voltage across the switch S _sn is limited to the single input voltage by the series connection of D _cl1 and C _sn .

Opposite the one from the U.S.A. 4,959,764 known circuit has the circuit according to 6 or. 11 the following advantages. Just like with the circuit according to the U.S.A. 4,959,764 the voltage across the switches is clamped and the energy from the leakage inductance of the transformer winding is recovered. In the circuit according to the invention, however, these goals are achieved without a switch in which the reference potential changes with each switching operation. According to the invention, the reference potential of both switches S and S _sn is permanently connected to the input capacitor C _In .

The input capacitor C _In is preferably designed in such a way that the voltage change across it during a switching period can be neglected. The control of both switches is thus very simple, and a complex power supply for the switch control is not necessary.

Exemplary embodiments of multi-level DC/DC converters are described below which, in accordance with the teachings of the present invention, comprise one or more clamping circuits according to the invention, e.g. B. one or more clamping circuits, which have a structure corresponding to the basis of 8th until 10 have described embodiments. At this point it should be noted that that stage which is connected with its first termination K1 or 104a of the parallel circuit to the first input terminal 100a, e.g. the positive pole, of the input 100 is also referred to as the uppermost or upper stage of the multi-stage DC/DC converter. That stage which is connected with its second termination K2 or 104b of the parallel circuit to the second input terminal 100b, eg the negative pole, of the input 100 is also referred to as the lowest or lower stage of the multi-stage DC/DC converter.

Exemplary embodiment of a two-stage DC voltage converter with a clamping circuit according to variant A

12 FIG. 1 shows an embodiment of a DC-DC converter with two stages 104 ₁ and 104 ₂ , in which the second or top stage 104 ₂ has a clamping circuit, which in the illustrated embodiment has a structure according to FIG 8th combined with 10(a) having. The third terminal 200c of the clamp circuit 200 is connected to the node K3 ₂ which is located between the lower or second terminal 106b ₂ of the inductor L _WP2 and the first terminal 108a ₂ of the switch S ₂ . Thus, the clamp circuit 200 is associated with the second stage 104 ₂ . The first terminal 200a of the clamping circuit 200 is connected to the first terminal K1 ₂ of the parallel circuit of the second stage in the illustrated embodiment, and thus to the first terminal 104a ₂ of the second stage and the first terminal 106a ₂ of the inductor L _WP2 . The second connection 200b of the clamping circuit 200 is connected to the connection K2 ₁ , namely the second connection of the parallel circuit in the first stage 104 ₁ , i.e. to the second connection 104b _n of the first stage 104 ₁ and the second connection 108b ₁ of the switch S ₁ the first stage 104 ₁ . The first stage node K3 ₁ , which is between the second terminal 106b ₁ of the inductance L _Wp1 and the first terminal 108a ₁ of the switch S ₁ , is connected to the second stage terminal K1 ₂ 104 ₂ via the diode D _sn1 .

The electrical input of the DC-DC converter, comprising the two input terminals 100a and 100b, is 12 illustrated embodiment through the first connection 104a ₂ of the second stage 104 ₂ and through the second terminal 104b _n of the first stage 104 ₁ is formed.

with the inside 12 The circuit shown can, for example, be used as a forward or flyback converter, and in this case the inductances L _Wp1 and L _{Wp2 would} each represent a primary winding of a transformer or of several transformers. In this case, similar to using the 1 has been described, a secondary side can be provided with corresponding windings.

For the following consideration it is assumed that all switches S _n change their switching state at the same time, the primary stages are used in a flyback converter and the windings L _Wpn are accommodated on a common magnetic core of a transformer.

When the switches are conducting, a current builds up in the common magnetizing inductance of the transformer, but also in the leakage inductances of each winding. When the switch changes to the blocking state, the commutation of the current of the magnetizing inductance to the flyback converter diode on the secondary side begins. However, due to the stray inductances of the primary windings, current still flows at first on the primary side. Since the switches are off, the current in the lower winding L _{Wp1 flows} via the diode D _sn1 and the input capacitor C _In2 , the current in the upper winding L _Wp2 via the capacitor C _sn1 , the diode D _cl1 and the capacitor C _In2 . The switching voltage of the lower switch S ₁ is clamped by the mesh shown to the sum voltage of the two input capacitors C _In1 and C _In2 , that of the upper switch S ₂ to the sum of the voltages of C _sn1 and C _In2 . The leakage inductances act as current sources and thereby reduce their stored energy. The energy is transferred into the input capacitors C _In1 , C _In2 and the capacitor C _sn1 .

When the voltage across capacitor C _sn1 has built up to be higher than that across capacitor C _In1 , in the next switching period when switches S ₁ and S ₂ become conductive again, diode D _{cl2 becomes} conductive, causing the two capacitors C _In1 and C _sn1 are in parallel and charge flows from the capacitor C _sn1 into the input capacitor C _In1 . In continuous operation, this means that the same voltage is present at the capacitor C _sn1 and at the input capacitor C _In1 . It follows that the voltage of both switches is limited to twice the voltage of an input capacitor C _Inn .

The circuit according to 12 can be used to connect any number of primary stages in series, but at least two, with the top or Nth primary stage preferably having a clamping circuit 200, so that the voltage at the switch S _N is limited and the energy from the leakage inductance of the top transformer winding L _WpN can be traced back. For all other _{primary stages} 1, . ...N) is connected. According to other exemplary embodiments, there is also the possibility of one, several or all of the lower primary stages 1, . . . , N-1 having a clamping circuit in accordance with the 8th until 10 equip described embodiments. The voltage level across the input capacitors C _Inn can be kept symmetrical in various ways, which will be described in detail later.

Example of an N-stage DC-DC converter with a clamping circuit according to variant A

13 12 shows another embodiment of a multi-level DC/DC converter according to the present invention. The structure of the circuit according to 13 is similar to the structure of in 12 circuit shown, except that a series connection of N stages 104 ₁ to 104 _N is assumed. In other words, between the second stage 104 ₂ and the uppermost or last stage 104 _N there can be no or any number of further stages, which can be designed either without a clamping circuit or with a clamping circuit. As with the based on the 12 described circuit is also in the embodiment according to 13 the clamp circuit 200 in the top stage 104 _N and thus the capacitor C _snN has its first terminal 202a connected to the node K3 _N . As previously mentioned, terminals 200a and 200b of the clamp circuit can be connected to any terminals of the parallel circuit of any stage and in the case of the in 13 In the exemplary embodiment shown, the connection 200b of the clamping circuit 200 is connected to the second connection K2 ₂ of the parallel circuit of the second stage 104 ₂ .

Similar to the 12 has been described, those stages which do not have a clamping circuit include the diode D _{snn connected} between the respective node K3 _n and the node K1 _n of any of the higher stages. At the in 13 In the illustrated embodiment, diode D _sn1 is connected between node K3 ₁ and the first terminal K1 ₂ of the parallel circuit of stage 104 ₂ and diode D _sn2 is connected between node K3 ₂ of the second Stage and the first terminal K1 _N of the parallel circuit of the stage 104 _N connected.

The circuit according to 13 is an example of how N primary stages can be connected in series. In the example shown, only the top primary stage N is provided with the clamp circuit 8th and 10(a) , consisting of the two diodes D _cl1N and D _cl2N , and the capacitor C _snN . In the remaining _{primary stages 1} , 2, is.

Embodiment of a three-stage DC-DC converter with two clamping circuits according to variant A for clamping to three times the voltage of an input capacitor

14 14 shows yet another exemplary embodiment of a multi-stage DC/DC converter according to the invention, in which a clamping circuit is provided in several of the stages. 14 10 shows a three-stage DC/DC converter comprising stages 104 ₁ , 104 ₂ and 104 ₃ . The second stage 104 ₂ includes a clamp circuit 200 ₂ which, in the illustrated embodiment, is shown in accordance with FIG 8th combined with 10(a) is constructed. Furthermore, the third, uppermost stage comprises the clamping circuit 200 ₃ , which, like the clamping circuit 200 ₂ according to the exemplary embodiment according to FIG 8th combined with 10(a) is constructed. When building the circuit according to 14 the first terminals 200a ₂ and 200a ₃ of the clamp circuits 200 ₂ and 200 ₃ are connected to the terminal K1 ₃ of the parallel circuit of the third stage 104 ₃ and the second terminals 200b ₂ and 200b ₃ are connected to the second terminal K2 ₁ of the parallel circuit of the first level switched. The first stage 104 ₁ includes the diode D _sn1 in the illustrated embodiment, which is connected between the node K3 ₁ and the terminal K1 ₃ of the third stage.

By connecting the diodes D _cl13 and D _cl23 in parallel with the three input capacitors C _Inn connected in series, the clamping voltage is increased to three times the voltage of an input capacitor. On the one hand, this increases the usable range of the output voltage and, on the other hand, the energy in the leakage inductances can be dissipated more quickly when the switch Sn _changes to the blocking state, which in turn means that less energy is retrieved from the magnetizing inductance to the primary side.

In the lowest primary stage 104 ₁ , a diode D _sn1 is again used to clamp the switch voltage by being connected between the first connection 108a ₁ of the switch S ₁ and the first connection 104a ₃ of the stage 104 ₃ .

Opposite the one from the DE 10 2016 117 936 A1 known circuit have the circuits according to 6 or. 12 until 14 the following advantages. The switch voltages or the voltages on the primary windings are not switched in the same way. This results in a higher tolerance for variations in the switching times of the individual primary stages. The following assumes the use of a common transformer core for the windings L _Wpn . If one switch turns off before the others, the current of the associated transformer winding does not commutate directly to the switches that remain in the conducting state. Since each switch has its own freewheeling path, it initially takes over the current with the help of the leakage inductance of each transformer winding. From this point onwards, the current in the leakage inductances is reduced, which means that the remaining switches have to accept more current from the magnetizing inductance.

15 shows the current paths 11, 12, 13 of the circuit according to 13 with three stages if, during the transition from the conducting phase of all switches S ₁ -S ₃ to the blocking phase, switch S ₁ remains briefly the only switch in the conducting state, for example due to component tolerances. In 15 is also shown an output stage or secondary stage with a structure which is based on the 1 was explained. In comparison to the direct capacitive coupling according to the previously described conventional approaches, however, the magnetizing current is not immediately and completely taken over by the switch that remains in the conducting state. The circuit can therefore handle small differences in the switching times, such as those caused in practice by component tolerances, and the risk of switching losses being concentrated on individual switches is significantly reduced.

According to the illustrated exemplary embodiments, the fact that the switch or winding voltages do not have to be switched in the same way is advantageously used as follows. Since the windings of the individual primary stages can be operated independently of one another, it is possible at low output powers to control the windings not simultaneously but cyclically or periodically one after the other, for example by activating only one switch of a primary stage within a switching period, as is shown by the 16 is shown, which the circuit according to 13 with three stages shows, in which only one switch conducts and thus less current is built up in the magnetizing inductance or the current is built up more slowly. Also 16 shows the output stage or secondary stage of the converter with the structure, which is based on the 1 was explained. If the switches are brought into the conducting state one after the other in this way when running through the switching periods and thus not all at the same time, the on-time of the switches S ₁ -S _N can be lengthened accordingly. This embodiment is used, for example, in cases of low output power with respect to the rated power of the overall converter. If this operating mode is not used, a very short conducting phase of the switches may be necessary at low output powers, depending on the secondary-side topology. This can be problematic for controlling the switches in a number of ways. The reason for this is that, depending on the control circuit, minimum switch-on times may be required and pulses that are too short are not passed on to the switch at all. In any case, the driver needs a certain amount of time to turn on the switch completely, too short an on-time therefore leads to operation of the switches in which they do not reach their full capacity, making the transfer of power to the secondary side more inefficient. The exemplary embodiment avoids these problems and the associated disadvantages in that the switches are controlled individually and optionally switched differently and independently of one another.

Based on 12 until 16 exemplary embodiments have been described in which the clamping circuit has a structure according to 8th combined with 10(a) having. The present invention is not limited to such configurations of the clamping circuit, rather the clamping circuit, such as based on the 11 was explained, also according to a structure 9 combined with 10(b) comprising the additional diode D _sn and the additional switch S _sn .

Exemplary embodiment of an N-stage DC-DC converter with a clamping circuit according to variant B

17 Fig. 12 shows an embodiment of a DC-DC converter in which N, N≥2, stages are connected in series. The basic structure according to the embodiment in 17 corresponds to the structure in 13 , except that the clamp circuit according to 9 combined with 10(a) is trained.

The circuit according to the embodiment in 17 thus includes, like the circuit according to the exemplary embodiment in FIG 13 several primary stages N, which are connected in series. The top primary stage N of the series connection includes a clamp circuit 200 according to FIG 9 and 10(a) , so that the voltage across the switch S _N is limited and the energy from the leakage inductance of the top transformer winding L _WpN can be fed back. As with the circuit according to 14 Here too, according to exemplary embodiments, for all other primary stages 1,...,N-1 the voltage can be clamped and the energy recovered, as shown, with a diode D _snn which is connected to the connection K1 _n of a higher primary stage ( n+1,...N) is connected. According to other exemplary embodiments, there is also the possibility of one, several or all of the lower primary stages 1, . . . , N-1 having a clamping circuit in accordance with the 8th until 10 equip described embodiments.

Embodiment of a three-stage DC voltage converter with two clamping circuits according to variant B for clamping to three times the voltage of an input capacitor

18 FIG. 12 shows another embodiment of a three-level DC/DC converter, similar to the embodiment according to FIG 14 , at which instead of in 14 described clamping circuits, the second and third stages each comprise a clamping circuit, which according to 9 in connection with 10(a). Unlike in 14 are in accordance with the embodiment 18 the respective first terminals 200a ₂ and 200a ₃ and the respective second terminals 200b ₂ and 200b ₃ of the clamping circuits 200 ₂ and 200 ₃ are connected to different terminals of the parallel circuits in the three stages. More specifically, the first terminal 200a ₁ of the clamp circuit 200 ₁ is connected to the terminal K1 ₂ of the second stage 104 ₂ and the second terminal 200b ₁ is connected to the terminal K2 ₁ of the first stage parallel circuit 104 ₁ . The clamping circuit 200 ₃ of the third stage 104 ₃ is connected in such a way that its first connection 200a ₃ is connected to the connection K1 ₃ of the parallel circuit of the third stage 104 ₃ and that the second connection 200b ₃ is connected to the connection K2 ₂ or the connection K1 ₁ of the second or first stage is connected.

By using more than one primary stage, more than twice the voltage of an input capacitor C _Inn can be clamped. This can be used with a flyback converter topology, for example, to be able to cover a larger output voltage range. At the in 18 The exemplary embodiment shown is clamped to three times the voltage of an input capacitor C _Inn by the primary stages 104 ₂ , 104 ₃ each having a clamping circuit 200 ₂ , 200 ₃ according to FIG 9 and 10(a) include. In contrast, the clamping of the switch voltage at the lowest primary stage 104 ₁ takes place again with the diode D _sn1 , which is connected to the positive pole of the input capacitor C _In3 .

Embodiment of a two-stage DC-DC converter with two clamping circuits according to variant B for clamping to three times the voltage of an input capacitor

In the case of the in 18 In the embodiment described, the clamping of the switch voltage to more than twice the voltage of an input capacitor C _Inn was realized by using more than one clamping circuit 200 for a three-level DC-DC converter. In further embodiments, the clamping of the switch voltage to a higher voltage, for example to three times the voltage of an input capacitor, can be implemented using only two stages. 19 shows an embodiment of a DC-DC converter according to the invention with two series-connected primary stages, which each comprise a clamping circuit according to the teachings of the present invention. At the in 19 illustrated embodiment is the clamping circuit according to 9 combined with 10(a) built up. The clamp circuits 200 ₁ and 200 ₂ are associated with the stages 104 ₁ and 104 ₂ and the first terminals 202a ₁ and 202a ₂ of the capacitors C _sn1 and C _sn2 are connected via the diodes D _sn1 and D _sn2 to the respective nodes K3 ₁ and .K3 ₂ of the two primary stages connected. The clamping circuits are connected in such a way that the first connection 200a ₃ of the first clamping circuit 200 ₁ is connected to the connection K1 ₂ of the parallel circuit of the second stage 104 ₂ , which in the illustrated embodiment forms the first input connection 100a of the DC/DC converter. The second terminal 200b ₁ of the clamp circuit 200 ₁ is connected to the second terminal K2 ₂ of the second stage parallel circuit and the first terminal K1 ₁ of the first stage parallel circuit, respectively. The clamping circuit 200 ₂ of the second stage is connected in such a way that its first connection 200a ₃ is also connected to the connection K1 ₂ and the second connection 200b ₂ is connected to a second connection K2 ₁ of the parallel connection of the first circuit and thus to the second input connection 100b of the DC-DC converter connected.

In the exemplary embodiments described so far, the DC-DC converter comprises one or more clamping circuits, with the exemplary embodiments described so far comprising a series connection of a plurality of stages with at least two clamping circuits each using clamping circuits which have the same structure, i.e. either a structure according to 8th or according to 9 combined with 10(a) . At this point it should be pointed out that the present invention is not limited to such configurations; rather, the clamping circuits can have circuit configurations which, instead of the configuration according to FIG 10(a) according to the embodiments according to 10(b) or according to 10(c) are trained.

In the embodiment according to 19 becomes as in the embodiment according to 18 the switching voltage of switches S _n is clamped to three times the voltage of an input capacitor C _Inn . This is achieved even though the number of primary stages is only two.

When using a clamp circuit according to 9 and 10(a) there are two variants to increase the clamping voltage. In the first variant, the number of input capacitors C _Inn is increased, which are in parallel with the two diodes D _cl1n and D _cl2n , as shown in 19 is the case with the upper primary stage 104 ₂ .
In the second variant, which in 19 As can be seen in the lower primary stage, the two diodes D _cl1n and D _cl2n are only parallel to an input capacitor C _Inn , but the upper diode D _cl1n is connected to the node K1 _n of the upper primary stage, i.e. the node of the next higher stage tied together.

Embodiment of a three-stage DC voltage converter with a clamping circuit according to variant A and a clamping circuit according to variant B for clamping to three times the voltage of an input capacitor

Furthermore, the present invention is not limited to embodiments in which, in the case of multi-stage DC-DC converters, the clamping circuits have the same structure, ie either according to 8th or according to 9 are trained. According to further exemplary embodiments, the clamping circuits according to FIG 8th and according to 9 be combined. 20 shows a three-stage DC-DC converter with the clamp circuits 200 ₂ and 200 ₃ , the clamp circuit 200 ₂ of the stage 104 ₂ according to 8th and 10(a) is constructed, and the clamp circuit 200 ₃ of the step 104 ₃ according to 9 and 10(a) is constructed. The clamp circuit 200 ₂ has its first and second terminals 200a ₂ and 200b ₂ between the inputs 100a and 100b of the FIG 20 shown DC-DC converter circuit connected. In other words, the terminals 200a are ₂ and 200b ₂ is connected to the first connection K1 ₃ of the parallel circuit of the stage 104 ₃ or to the second connection K2 ₁ of the parallel circuit of the first stage 104 ₁ . The terminals 200a ₃ and 200b ₃ of the clamp circuit 200 ₃ of the third stage 104 ₃ correspond to the input terminal 100a of the DC/DC converter 20 or connected to the second connection K2 ₂ of the parallel circuit of the second stage 104 ₂ or to the first connection K1 ₁ of the parallel circuit of the first stage 104 ₁ .

At the in 20 The embodiment shown uses the shown DC-DC converter on the one hand, the clamping circuit 200 ₂ according to 8th as well as the clamp circuit 200 according to _FIG 9 . Here, too, the voltage of the switches S _n is limited to three times the voltage of an input capacitor C _Inn .

As in the embodiments described so far can also 20 that stage which does not comprise a clamping circuit according to the invention, in the illustrated exemplary embodiment the first or lowest primary stage 104 ₁ , having the diode D _sn1 in order to limit the switching voltage of the switch S ₁ .

At this point it should be pointed out that in the description of the above exemplary embodiments, all stages which do not have a clamping circuit according to the invention have the diode just mentioned for limiting the switch voltage. According to other embodiments, this diode can also be omitted, i. That is, the stages without clamping circuits according to the invention, according to further exemplary embodiments, have no additional diodes for clamping the switch voltage, or have other clamping circuits known from the prior art, such as RLC snubbers.

Embodiments for balancing the voltage at the input capacitors of the DC-DC converter circuit

Exemplary embodiments of the present invention are described below, which enable the balancing of the voltages at the input capacitors C _In of the DC-DC converter circuit. The following exemplary embodiments enable the balancing of the voltages at the input capacitors of a DC/DC converter with galvanic isolation, that is to say with a secondary side, if a plurality of primary sides or primary stages are used.

Magnetic coupling of the inductances or windings on the primary side

According to exemplary embodiments, the primary-side inductances or windings of the exemplary embodiments described above can be primary windings of one or more transformers, and, according to exemplary embodiments, a magnetic coupling of the primary-side windings can be provided for balancing. 21 shows an exemplary embodiment for balancing the voltages at the input capacitors by magnetic coupling of the primary-side windings of multi-stage DC voltage converters, namely the magnetic coupling of the inductances L _Wp1 to L _WpN .

At the in 21 In the illustrated embodiment, a common magnetic core K is used for all windings L _Wpn of the multiple primary stages. Each of the primary windings L _Wpn has the same number of turns, so the magnetic coupling ensures that each winding L _{Wpn has} the same voltage. Differences in the voltages on the windings are only possible due to the presence of the leakage inductance of each winding and result in a current flow.

If the switches S _n of the primary stages are conductive at the same time, the voltage of the input capacitor C _Inn of the respective primary stage is applied to each primary winding. Should the input capacitors have different voltages, a transient current forms across the magnetically coupled windings, which promotes balancing of the voltages. The compensating current only flows in the primary windings, which is why the secondary windings are shown in Fig 21 was waived.

In the case of converters with several transformers, i.e. without magnetic coupling of the windings, a different number of turns in the primary stages is possible in principle, since the transformation ratio is also decisive in this case. With different transformation ratios of the transformers of different stages, you can therefore compensate for different numbers of turns in the primary stages and still achieve a symmetrical distribution of the converter input voltage to the individual stages.

In principle, the clamp circuit according to the invention also enables the use of different numbers of turns, which results in a distribution of the converter input voltage to the individual stages that is proportional to the ratio of the number of turns.

Electrical coupling of the inductances or windings on the secondary side

According to further exemplary embodiments of the present invention, the balancing of the voltages at the input capacitors can be achieved by direct electrical coupling of the secondary windings in the form of a parallel circuit. 22 shows an embodiment of the electrical coupling of the secondary windings by connecting them in parallel. Similar to in 21 are in 22 the primary-side inductances L _Wpn shown, as well as the associated secondary-side inductances or turns L _Wsn . At the in 22 illustrated embodiment, the primary windings are not magnetically coupled, rather the secondary windings are connected in parallel. The parallel connection of the secondary windings can then be connected to the output 102 of the DC voltage converter, for example via a rectifier circuit 110 .

As in 22 is shown, the balancing of the voltages at the input capacitors can also be achieved with a parallel connection of the secondary windings L _Wsn . In this exemplary embodiment, a number of magnetic cores or a number of transformers are used, which can be advantageous, for example, in the case of very high voltages, since the insulation of the primary windings is simpler. Each transformer has the same transformation ratio, the number of turns can be different. As with the magnetic coupling, the same voltage is applied to each primary winding due to the parallel connection. Differences in voltages across the windings are only possible due to the presence of the leakage inductance of each winding and result in current flow. In this embodiment, not only does the leakage inductance between the primary windings have an effect, but also the leakage inductance to and between the secondary windings, since the compensating current must also flow through them.

If the switches S _n of the primary branches are conductive at the same time, the voltage of the input capacitor C _Inn of the respective primary stage is applied to each primary winding. If the input capacitors have different voltages, a compensating current will form via the electrically coupled secondary windings, as a result of which a compensating current will also form on the primary side and the voltages will thus be balanced.

According to yet another exemplary embodiment of the present invention, the voltages at the input capacitors are balanced by connecting the DC outputs of the secondary stages in parallel. Similar to 22 also shows 23 schematically the primary stages with the primary windings L _Wpn , each primary stage, similar to that in 22 , a secondary stage L _Wsn is assigned. Furthermore, each secondary winding is assigned a rectifier circuit 110 _n and the corresponding DC voltage outputs 112 _n of the rectifier circuits 110 _n are connected in parallel and connected to the output 102 of the circuit.

By connecting the DC outputs 112 ₁ , ... 112 _N of the converter output stages in parallel, the voltages across the input capacitors can be balanced or stabilized, although the functional principle differs from that of magnetic coupling or parallel connection of the secondary windings . According to this exemplary embodiment, balancing takes place via the power consumption of the primary stages from their respective input capacitors. Assuming the same transformation ratios for all transformers, a higher voltage of an input capacitor for this primary stage leads to the takeover of a larger proportion of the output current, which also increases the current consumption of this stage on the primary side. Since the series connection of the primary stages means that only a common current can be drawn from the source, the current difference in this scenario must be taken over by the input capacitors, which means that they are recharged and their voltages are adjusted.

According to further exemplary embodiments, the balancing of the voltages at the individual primary stages can take place by independently adjusting the input power of each primary stage.

24 12 shows an embodiment for balancing the voltages on the input capacitors by controlling the power of each stage. According to the embodiment in 24 the primary-side windings L _Wpn are coupled to respective secondary-side windings L _Wsn without magnetic coupling of the primary-side windings. The windings L _Wsn on the secondary side are connected in series and the terminals of the series circuit are connected via the rectifier circuit 110 to the output 102 of the DC-DC converter.

25 FIG. 12 shows another embodiment for balancing the voltages on the input capacitors by controlling the power of each stage independently, but in a different way than the starting example according to FIG 24 separate outputs for the secondary side steps are provided. Unlike in 24 the secondary-side windings Lwsn are separated from one another and connected to separate outputs 102 ₁ to 102 _N , respectively. A rectifier circuit 110 ₁ to 110 _N is provided between the secondary windings and the respective outputs.

According to the 24 and in 25 In the exemplary embodiments illustrated, the voltages across the input capacitors are balanced by controlling the transmission power of the individual primary stages. The aim is for each primary stage to consume the same power on average, which ensures the symmetrical distribution of the source voltage to the individual input capacitors connected in series. Various circuit variants are possible for this operating mode, e.g. the one in 24 series connection of the secondary windings shown, or the in 25 illustrated complete separation of the secondary sides.

More examples

The present invention, as described above with reference to the exemplary embodiments, provides a DC/DC converter that clamps the switch voltage(s) and recovers energy from the leakage inductance(s) using the clamping circuits of FIG 8th or 9 allows.

• - kann die Gesamtschaltung aus einer oder mehreren Primärstufen bestehen,
• - wird beim Klemmen der Schalterspannung auf das n-fache der Eingangsspannung U_Inn einer Stufe, n*U_Inn, nur bei n-1 Primärstufen eine Klemmschaltung gemäß 8 oder 9 benötigt,
• - können alle anderen Primärstufen mit einer Diode vom ersten Anschluss 108an des Schalters S_n auf einen der Eingangskondensatoren einer höheren Primärstufe geklemmt werden, wobei beim Klemmen der Schalterspannung auf das n-fache der Eingangsspannung U_Inn einer Stufe, n*U_In, auf den Pluspol des Eingangskondensators C_Inn einer Stufe geklemmt wird, welcher n-1 Primärstufen höher liegt,
• - kann je nach Anzahl der Primärstufen nicht nur auf das doppelte der Eingangsspannung U_Inn einer Stufe geklemmt werden, mit der Klemmschaltung gemäß 8 kann bei n Stufen auf bis zu n*U_In geklemmt werden, mit der Klemmschaltung gemäß 9 auf bis zu (n+1)*U_In, wobei
  • o bei der Klemmschaltung gemäß 8 die Reihenschaltung der beiden Dioden D_cl1n und D_cl2n beim Klemmen auf n*U_In jeweils zwischen n Eingangskondensatoren geschaltet ist,
  • o bei der Ausgestaltung der Klemmschaltung gemäß 9 nicht nur die Anzahl der Eingangskondensatoren, welche parallel zu ihrem ersten und zweiten Anschluss 200a und 200b in Reihe liegen, eine Rolle spielen, sondern auch, wie viele Stufen höher die Verbindung des ersten Anschlusses 200a im Vergleich zum dritten Anschluss 200c der Klemmschaltung gemäß 9 erfolgt (siehe z.B. die Ausführungsform gemäß 19), wobei die Summe C aus der Anzahl A von Eingangskondensatoren und der Anzahl B von Eingangskondensatoren dem Faktor entspricht, um welchen die Klemmspannung höher als die Spannung eines Eingangskondensators einer Stufe liegt, wobei
    • • die Anzahl A von Eingangskondensatoren diejenigen Eingangskondensatoren umfasst, welche parallel zum ersten und zweiten Anschluss 200a und 200b der Klemmschaltung gemäß 9 in Reihe liegen, und
    • • die Anzahl B von Eingangskondensatoren diejenigen Eingangskondensatoren umfasst, welche zwischen dem ersten Anschluss K1_n einer Parallelschaltung der Stufe, mit welchem der erste Anschluss 200a der Klemmschaltung verbunden ist, und dem zweiten Anschluss K2_n einer Parallelschaltungen der Stufe, deren Knotenpunkt K3_n mit dem dritten Anschluss 200c der Klemmschaltung gemäß 9 verbunden ist, liegt, und
• - kann die Symmetrierung der Spannungen über den Eingangskondensatoren auf verschiedene Weise erfolgen, z.B. durch
  • o eine magnetische Kopplung der Wicklungen,
  • o eine elektrische. Kopplung der Sekundärwicklungen,
  • o eine elektrische. Kopplung auf der Sekundärseite nach der Gleichrichtung,
  • o im Mittel gleiche Leistungsaufnahme der einzelnen Primärstufen,
• - können die Klemmschaltungen gemäß 8 und 9 kombiniert werden.

According to exemplary embodiments

• - the overall circuit can consist of one or more primary stages,
• - When the switch voltage is clamped to the n-fold of the input voltage U _Inn of a stage, n*U _Inn , a clamping circuit is only used in accordance with n-1 primary stages 8th or 9 needed,
• - All other primary stages can be clamped with a diode from the first terminal 108an of the switch S _n to one of the input capacitors of a higher primary stage, with clamping of the switch voltage to n times the input voltage U _Inn of a stage, n*U _In , to the positive pole of the input capacitor C _Inn of a stage is clamped, which is n-1 primary stages higher,
• - Depending on the number of primary stages, it can not only be clamped to twice the input voltage U _Inn of a stage, with the clamping circuit according to 8th can be clamped at n levels up to n*U _In , with the clamping circuit according to 9 up to (n+1)*U _In , where
  • o according to the clamping circuit 8th the series connection of the two diodes D _cl1n and D _cl2n is connected between n input capacitors when clamped to n*U _In ,
  • o according to the design of the clamping circuit 9 not only the number of input capacitors connected in series parallel to their first and second terminals 200a and 200b play a role, but also how many levels higher the connection of the first terminal 200a compared to the third terminal 200c of the clamp circuit according to 9 takes place (see, for example, the embodiment according to 19 ), where the sum C of the number A of input capacitors and the number B of input capacitors corresponds to the factor by which the clamping voltage is higher than the voltage of an input capacitor of a stage, where
    • • the number A of input capacitors includes those input capacitors which are connected in parallel to the first and second terminals 200a and 200b of the clamping circuit according to FIG 9 line up, and
    • • the number B of input capacitors includes those input capacitors which are connected between the first terminal K1 _n of a parallel circuit of the stage to which the first terminal 200a of the clamping circuit is connected and the second terminal K2 _n of a parallel circuit of the stage whose node K3 _n is connected to the third terminal 200c of the clamp circuit according to 9 connected, lies, and
• - the balancing of the voltages across the input capacitors can be done in different ways, eg by
  • o a magnetic coupling of the windings,
  • o an electric one. coupling of the secondary windings,
  • o an electric one. coupling on the secondary side after rectification,
  • o the same average power consumption of the individual primary stages,
• - can the clamping circuits according to 8th and 9 be combined.

In the exemplary embodiments described above, the inductor L _n or L _Wpn and the switch S _n of a stage are connected in series in such a way that the switch S _n of a stage is connected between the second terminal 104b _n of the stage 104 _n and the inductor L _n or L _Wpn is switched. Such a structure is chosen, for example, when the switch S _n is implemented by an N-Ch MOSFET.

According to further exemplary embodiments, the inductor L _n or L _Wpn and the switch S _n of a stage are connected in series such that the switch S _n of a stage is connected between the first terminal 104 on the stage 104 _n and the inductor L _n or L _Wpn is. Such a structure is chosen, for example, when the switch S _n is realized by a P-Ch MOSFET.

According to further exemplary embodiments, a DC-DC converter according to the invention includes a controller which is connected to control terminals of the actively controllable switching elements in order to apply suitable signals for switching the same to the conducting or blocking state. The controller can be designed, for example, in the form of a microcontroller.

Although some aspects of the concept described have been described in the context of a device, it is clear that these aspects also represent a description of the corresponding method, where a block or a device corresponds to a method step or a feature of a method step. Analogously, aspects that have been described in connection with a method step also represent a description of a corresponding block or a device or a feature of a corresponding device.

The embodiments described above are merely illustrative of the principles of the present invention. It is understood that modifications and variations to the arrangements and details described herein will be apparent to those skilled in the art. The invention is therefore only to be limited by the scope of the patent claims below, not by the specific details in the above description and explanation of the exemplary embodiments.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

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• DE 3634990 A1 [0008]
• US 5734563 A [0008, 0014]
• US4959764A [0008, 0009, 0024, 0026, 0068]
• DE 102016117936 A1 [0008, 0015, 0024, 0027, 0084]
• US4975821A [0014]
• US5126931A [0014]
• US5173846A [0014]
• US5303138A [0014]
• US5528482A [0014]
• DE 4422409 A1 [0021, 0027]

Claims (20)

DC-DC converter, with: at least one stage, each stage comprising a parallel circuit made up of an input capacitor (C _In ) and a series circuit which has at least one inductor (L _Wp ) and at least one switch (S _n ), the parallel circuit of the stage comprising a first terminal and a second terminal, the first terminal being connected to the input capacitor (C _In ) and the inductor (L _Wp ) of the stage, and the second terminal of the parallel circuit being connected to the input capacitor (C _In ) and the switch (S _n ) connected to the primary stage; wherein at least one of the stages comprises a clamp circuit, the clamp circuit comprising an energy buffer (C _sn ) having a first terminal connected to a node between the inductance (L _Wp ) and the switch (S _n ) of the stage, and a having a second connection, and wherein the clamping circuit is designed to connect the second connection of the energy buffer (C _sn ) • during at least part of a blocking state of the switch (S _n ) of the stages to the first connection of the parallel circuit of one of the stages, and • during at least part of a conducting state of the switch (S _n ) of the stages to the second terminal of the parallel circuit of one of the stages via a separate path from the switch of the stage. DC converter according to claim 1 , with only one stage, which comprises the clamping circuit, wherein the clamping circuit is designed to connect the second terminal of the energy buffer • during at least part of a blocking state of the switch (S _n ) of the stage to the first terminal of the parallel circuit of the stage, and • to connect during at least part of a conducting state of the stage switch via a separate path from the stage switch (S _n ) to the second terminal of the parallel circuit of the stage. DC converter according to claim 1 , with at least N stages connected in series, with N ≥ 2, with at least one nth stage comprising the clamp circuit, with n = 1, ..., N, with the first terminal of the energy buffer (C _snn ) of the clamp circuit having a node is connected between the inductance (L _Wpn ) and the switch (S _n ) of the nth stage, and wherein the clamping circuit is designed to clamp the second terminal of the energy buffer (Csnn) • during a blocking state of the switches (S ₁ .. . S _N ) of the N stages to the first terminal of the parallel circuit of the nth stage or to the first terminal of the parallel circuit of any of the series connected stages, and • during a conducting state of the switches (S ₁ ... S _N ) of the N stages via a separate path from the switches (S _n ) to the second terminal of the parallel circuit of the nth stage or to the second terminal of the parallel circuit of any of the series connected stages. DC converter according to claim 3 , in which at least two of the N stages each comprise a clamping circuit, the clamping circuits being formed, the second terminals of the energy buffers (C _sn1 ... C _snn ) • during a blocking state of the switches (S ₁ ... S _N ) of the to connect N stages to the first connection of the parallel connection of the same or different stages, and • during a conducting state of the switches (S ₁ ... S _N ) of the N stages via a path separate from the switches (S _n ) to the second connection the parallel connection of the same or different stages. DC converter according to claim 4 , in which the clamping circuits have the same or different construction. DC-DC converter according to one of the preceding claims, in which the clamping circuit comprises the following features: a first terminal which is connected to the first terminal of the parallel circuit of one of the stages, a second terminal which is connected to the second terminal of the parallel circuit of one of the stages, a third terminal connected to the node between the inductance and the switch of the stage, and circuitry configured to the second terminal of the energy buffer (C _sn ) when the switch (S _n ) in the stages is off with the first terminal of the clamping circuit, and with the conducting switch (S _n ) in the stages to connect to the second terminal of the clamping circuit. DC converter according to claim 6 , in which the circuit arrangement of the clamping circuit comprises the following features: a series circuit which has at least a first diode (D _cl1 ) and a second diode (D _cl2 ), the series circuit being connected between the first terminal of the clamping circuit and the second terminal of the clamping circuit , where the second terminal of the energy buffer (C _sn ) is connected to a node between the first diode (D _cl1 ) and the second diode (D _cl2 ), or a series circuit comprising at least a first switch and a second switch, the series circuit being connected between the first terminal of the clamp circuit and the second terminal of the clamp circuit is switched, the second terminal of the energy buffer (C _sn ) being connected to a node between the first switch and the second switch, or a switch to selectively connect the second terminal of the energy buffer (C _In ) to the to connect the first connection of the clamping circuit or to the second connection of the clamping circuit. DC converter according to claim 7 , in which the clamping circuit further comprises the following features: a first circuit element (D _sn ), for example in the form of at least one switch or at least one diode, which is connected between the first connection of the energy buffer (C _sn ) and the third connection of the clamping circuit; and a second circuit element (S _sn ), eg in the form of at least one switch, which is connected between the first connection of the energy buffer (C _sn ) and the first connection of the clamping circuit. DC-DC converter according to one of the preceding claims, in which the at least one stage is a primary stage of the DC-DC converter, the inductance of which is a primary winding of a transformer or at least one primary winding of one of the plurality of transformers, and the DC-DC converter comprises at least one secondary stage which comprises at least one inductance which is at least one secondary winding of the one or more transformers. DC converter according to claim 9 , With at least one electrical output, the secondary stages being connected in parallel or in series with the electrical output. DC converter according to claim 9 , in which each of the secondary stages comprises an electrical output. DC-DC converter according to one of claims 9 until 11 , with one or more rectifier circuits on the secondary side. A DC/DC converter as claimed in any preceding claim, in which the inductances of series connected stages are magnetically coupled, for example by a common magnetic core. DC converter according to Claim 13 , in which the inductances of stages connected in series have the same number of turns. DC converter according to Claim 13 , in which the inductances of stages connected in series have different numbers of turns. DC-DC converter according to one of claims 9 until 12 , in which the inductances of stages connected in series are not magnetically coupled. DC converter according to Claim 16 , in which the inductances of the plurality of transformers have a different number of turns, and the transformation ratios of the respective transformers are selected in order to compensate for the different numbers of turns in the primary stages. DC converter according to Claim 16 , where the inductances of the multiple transformers have the same number of turns. Method for operating a DC-DC converter, which comprises at least one stage and at least one clamping circuit with an energy buffer (C _sn ), each stage being a parallel circuit composed of an input capacitor (C _In ) and a series circuit comprising at least one inductance (L _Wp ) and at least one switch (S _n ), wherein the parallel circuit of the stage comprises a first terminal and a second terminal, the first terminal being connected to the input capacitor (C _In ) and the inductance (L _Wp ) of the stage, and the second Terminal of the parallel circuit is connected to the input capacitor (C _In ) and the switch (S _n ) of the primary stage, the clamping circuit having a first terminal connected to the first terminal of the parallel circuit of one of the stages, a second terminal connected via one of the switches of the steps separate path with the second connection of the parallel connection of a de r stages, and comprising a third terminal connected to the node between the inductance and the switch of the stage, and wherein a first terminal of the energy buffer (C _sn ) is connected to the third terminal of the clamp circuit, and wherein the Method includes the following steps: repeated, e.g. cyclic or periodic, switching the switch (S _n ) of the stages between a blocking state and a conducting state; during at least part of a blocking state of the switch (S _n ) of the stages, connecting the second terminal of the energy buffer (C _sn ) to the first terminal of the clamping circuit, and during at least part of a conducting state of the switch (S _n ) of the stages, connecting the second terminal of the energy buffer (C _sn ) to the second terminal of the clamp circuit. procedure according to claim 19 , in which the first connection of the energy buffer (C _sn ) is connected directly or via a switching element, eg a switch or a diode, to the third connection of the clamping circuit.

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