DE102017200456A1 - Arithmetic unit and operating method for this - Google Patents

Abstract

The invention relates to a computing unit (100; 100a; 100b; 100c; 100d; 100e; 100f; 100g) having at least one arithmetic core (110a, 110b, 110c), a primary memory device (120), and at least one main connection unit (130) Connecting the at least one arithmetic core (110a, 110b, 110c) to the primary memory device (120), wherein the arithmetic unit (100) has at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e 1400f, 1400g), at least one first functional unit (140a) of the at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g) being adapted to a ) receive first data from at least one further functional unit (140, 140b) of the at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g) and / or second data to at least one further functional unit (140, 140b) of the at least two functional elements units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400F; 1400g).

Description

State of the art

The invention relates to a computing unit having at least one arithmetic core, a primary memory device, and at least one main connection unit for connecting the at least one arithmetic core to the primary memory device.

The invention further relates to an operating method for such a computing unit.

Such computing units are known and commercially available, for example in the form of microcontrollers.

It is an object of the present invention to improve a computing unit of the type mentioned in that it has increased flexibility and increased utility.

Disclosure of the invention

This object is achieved in the arithmetic unit of the aforementioned type according to the invention that the arithmetic unit has at least two functional units, wherein at least a first functional unit of the at least two functional units is adapted to a) receive first data from at least one further functional unit of the at least two functional units and / or b) to send second data to at least one further functional unit of the at least two functional units.

The functional units according to the invention advantageously offer the possibility of expanding a computing power and / or the functionality of the computing unit. In particular, the possibility of direct data exchange between the functional units according to the invention makes possible a data flow which does not include the further components of the arithmetic unit, such as, for example, their computing cores or the primary memory device. In this way, the calculation cores or the primary memory device or the main connection unit can be relieved, while at the same time one or more functional units according to the invention perform their intended calculation tasks or other tasks.

Particularly preferably, the arithmetic unit according to the invention can be used in a control unit for a target system, for example in a control unit for an internal combustion engine of a motor vehicle or for a radar-based distance measuring system or the like. In contrast to conventional arithmetic units such as conventional microcontrollers, the arithmetic unit according to the invention is advantageously extended by the functionality provided by the functional units and described in more detail below, and can thus also be regarded as a microcontroller with the additional functionality enabled according to the invention. In general, the computing unit according to the invention can be used wherever conventional computing units such as microcontrollers or microprocessors or digital signal processors or the like are used, and where additional functionality and / or higher performance as provided by the functional units according to the invention is desirable. It is also possible to replace conventional computing units existing in existing systems by the computing unit according to the invention, in order to enable a more efficient processing of calculation and other tasks which have been performed by the conventional computing units since then. According to some embodiments, the use of the computing unit according to the invention is also particularly advantageously conceivable in the field of processing security-relevant data or for processing cryptographic algorithms.

In an advantageous embodiment it is provided that at least one primary connection unit is provided, which is designed to produce, at least temporarily, a, in particular direct, data connection between the first functional unit and at least one further functional unit of the at least two functional units. This advantageously makes it possible to control a data exchange or data flow between different functional units, so that a configuration or reconfiguration of the data connection (s) between the respective functional units is also possible during operation of the arithmetic unit, whereby an increased flexibility is achieved.

In a preferred embodiment, the primary connection unit has at least one coupling network. Particularly preferably, the coupling network is designed as a blocking-free switching network. In this case, the switching network at any time allows the production of data connections between all connected to the switching network function units and possibly other connected to the switching network units such as components of the arithmetic unit.

In another embodiment, it is also conceivable to design the primary connection unit as a coupling network, but not to design the coupling network without blocking.

In further embodiments, the primary connection unit may also comprise other structures, for example at least one bus system which establishes a data connection between the functional units connected to the bus system.

In further embodiments, the primary connection unit may also have at least one direct data connection between at least two functional units. Furthermore, in other embodiments, direct data connections between more than two functional units are conceivable.

In a further embodiment, it can be provided that the at least one primary connection unit has a plurality of the above-mentioned connection mechanisms, that is, for example, a coupling network for connecting some functional units or all functional units to one another and, for example, a bus system which connects several or all functional units and, for example, direct data connections between several or all functional units.

In a further advantageous embodiment, it is provided that a plurality of groups of functional units are provided, wherein each of the plurality of groups is assigned at least one primary connection unit, which is designed to at least temporarily establish a, in particular direct, data connection between functional units of the group concerned. As a result, it is possible to provide a plurality of clusters of functional units which can each carry out similar or different calculations or other tasks.

In a further embodiment it is provided that a primary connection unit, which is assigned to a group of functional units, is designed to establish a data connection between functional units of different groups.

In further embodiments, the primary connection units associated with the respective groups may in turn comprise at least one of the following components: a switching network, a bus system, at least one direct data connection.

In a further embodiment, at least one secondary connection unit is provided which is designed to establish a data connection between the main connection unit and at least one functional unit and / or a data connection between the main connection unit and at least one primary connection unit, thereby providing a powerful connection for data transmission between the respective functional units and the main connection unit. The main connection unit can be designed, for example, as a so-called "core interconnect", ie represent a central connection unit for the high-performance connection (in particular with high data rates and / or low latencies) of the components of the computing unit according to the invention. In a preferred embodiment, the main connection unit may preferably also be designed as a coupling network, in particular as a blocking-free coupling network.

In a further preferred embodiment, at least one secondary storage device is provided, wherein there is a direct data connection between the at least one secondary storage device and at least one functional unit. In the present context, a direct data connection between the secondary storage device and the at least one functional unit is to be understood as meaning a data connection which allows a data exchange between the secondary storage device and the at least one functional unit without using the main connection unit for this purpose. In other words, in the present embodiment, data exchange may occur directly between one or more of the functional units and the secondary storage device, thereby not burdening the main interconnect unit, so that it may be otherwise used, for example for data exchange between the cores and the primary storage device and the like ,

In a further advantageous embodiment, the at least one secondary memory device has a plurality of memory banks, wherein, in particular, the at least one secondary memory device is designed to enable parallel data access to at least two of the plurality of memory banks. This advantageously allows a high bandwidth for accesses to or from the secondary memory device or its banks, and in particular also non-contiguous data blocks can be transmitted in parallel or simultaneously between the functional units involved and the secondary memory device or its memory banks.

In a further preferred embodiment, at least one of the functional units is embodied as a hardware circuit, in particular completely as a hardware circuit. This can be advantageous calculations, logic operations and other of the functional unit in question provided functions are executed particularly quickly and efficiently.

In a further advantageous embodiment, it is provided that at least one of the functional units has at least one of the following elements: a microcontroller, a digital signal processor (DSP), a programmable logic circuit (for example an FPGA, field programmable gate array), an application-specific integrated circuit (ASIC) , application specific integrated circuit).

In one embodiment, it is provided that all functional units are designed as a hardware circuit, in particular completely as a hardware circuit. In other embodiments, it is possible for one or more functional units to be designed as a hardware circuit, in particular completely as a hardware circuit, and for at least one component or another component not completely formed as a hardware circuit to be provided in the form of at least one further functional unit.

For example, in a particularly preferred embodiment, a first number of functional units may be provided which are designed completely as a hardware circuit, and a further functional unit may comprise, for example, a microcontroller or a programmable logic module or a programmable logic circuit.

In a further advantageous embodiment it is provided that at least one of the functional units has at least one of the following components: adder, multiplier, divider, shift register, barrel shifter, comparator, multiplication accumulator (MAC), arithmetic logic unit (ALU), memory unit, registers , Multiplexer, demultiplexer, interface, unit for evaluation of exponential functions, unit for evaluation of trigonometric functions.

In a further preferred embodiment, at least one of the functional units has at least one coarse-granular hardware element. Alternatively or additionally, at least one of the functional units may be formed as coarse-granular the hardware element.

The term "coarse granular" in this case means that the relevant hardware element has more than one logical gate or is formed from more than one logical gate. The gates are in one embodiment, according to function and / or connection with each other unchangeable.

In general, granularity is understood to what extent a system is composed of distinct individual units. A coarse-granular system is composed of comparatively few coarsely granular elements of comparatively large size, whereas a finely granular system is composed of comparatively many comparatively small fine granular elements.

In particular, granularity in the area of computer architectures can be described by the number of logical gates and, concomitantly, in particular by a relationship between arithmetic operations or execution times and communication or data exchange. In finely granular hardware elements (one logical gate each), simple logical operations can be performed quickly in comparatively short processing time, but data is often exchanged between individual elements. In contrast, in coarse-grained hardware elements (in each case a plurality of logic gates), in particular complex operations are carried out in each case with comparatively long execution times, and data is less frequently exchanged between individual elements.

By coarse granular hardware elements are thus to be understood in particular elements which can each automatically perform complex arithmetic operations, in particular without frequently exchanging data with each other. For example, the individual coarse granular hardware elements are each formed as one of the following: more complex elements such as arithmetic logic unit (ALU), memory access unit, communication interface and / or less complex units such as comparator, adder, multiplier, divider, shift register, barrel shifter, multiplication adder ("Multiply-Accumulate", (MAC)), register or register block, memory unit (eg RAM, Flash etc.), multiplexer (eg 2: 1-MUX, M: N-MUX), demultiplexer.

An ALU calculates in particular arithmetic and logical functions. For example, it can perform at least one addition (ADD) as an arithmetic function and at least one negation (NOT) and a conjunction (AND, AND) as a logical function. As arithmetic function, it may also preferably include a subtraction (SUB) and / or a comparison (compare, CMP) and / or a multiplication (MUL) and / or a division and / or a decimal adjustment after addition (decimal adjustment after addition). carry out. As a logical function, it may also have a disjunction (OR, OR) and / or a contravalence (XOR, EOR) and / or a shift to the right and to the left (Right-, left-shift, ASR - arithmetic shift right, ASL - arithmetic shift left, LSR - logical shift to the right, LSL - logical shift to the left) and / or a left and right rotation (ROL, ROR) and / or register- Manipulations and / or bit changes (set bits, clear and test) and / or resort to bits and bytes and / or perform AES commands and / or CRC commands.

In particularly preferred embodiments, multiple interconnected components, e.g. Adder, multiplier, divider, shift register, barrel shifter, comparator, multiplication accumulator, arithmetic logic unit, memory unit, registers, multiplexer, interface or general coarse granular hardware elements that may constitute the functional unit (s) or components thereof, a comparatively complex calculator provided, according to the invention advantageously at least one first functional unit is adapted to receive first data from at least one further functional unit and / or to send second data to at least one further functional unit, as has already been described above. As a result, a data flow can be defined which, inter alia, also makes it possible to carry out comparatively complex calculations, which use, for example, a large number of the abovementioned components or coarse-grained hardware elements, for example in a specifiable sequence according to an algorithm to be evaluated or another calculation rule.

According to a further aspect of the present invention, this data flow can be particularly advantageously also dynamically, that is to say influenced or changed during a running time of the inventive computing unit, ie reconfigured or reconfigured. In a preferred embodiment, this can be accomplished, for example, by appropriate control of the primary connection unit.

According to a further advantageous embodiment, it is provided that the arithmetic unit is designed to modify a configuration of at least one functional unit (or of one or more coarse-grained elements contained therein) and / or to check a state or the configuration of at least one functional unit. As a result, the flexibility and the utility of the computing unit according to the invention is further increased. For example, it can be provided in one embodiment that at least one functional unit has configuration registers which can be arranged, for example, locally in the functional unit. By writing accesses of the arithmetic unit, for example, by virtue of one of its computing cores, the arithmetic unit can thus change the configuration of the functional unit in question.

In other words, in some embodiments, for example, a computing core of the computing unit may be designed to change a configuration of at least one functional unit and / or to check a state or the configuration of at least one functional unit.

In further embodiments, it is conceivable that at least one functional unit is configured to change a configuration of at least one (other) functional unit and / or to check a state or the configuration of at least one functional unit. Furthermore, it is conceivable that in further embodiments a functional unit is designed to change and / or to check its own configuration.

In further embodiments, it is conceivable that at least one peripheral unit of the arithmetic unit is designed to change a configuration of at least one functional unit and / or to check a state or the configuration of at least one functional unit.

For example, the peripheral unit may be a DMA controller. This advantageously makes it possible for the DMA control device to essentially autonomously read, for example, configuration information for a specific functional unit from a first memory area of the arithmetic unit and to write the read-out configuration information into corresponding configuration registers of the relevant functional unit.

In a further embodiment, it is provided that at least one of the functional units is configured to change a configuration of the primary connection unit and / or at least one secondary connection unit and / or a state or the configuration of at least the primary connection unit and / or at least one secondary connection unit to check.

According to a further embodiment, the configuration of the coarse-grained hardware elements is to be understood as a concretization of the function of the coarse-grained hardware elements from the available possibilities and in particular also the connection structure of the individual elements (eg the primary connection unit). By changing the configuration, the arithmetic unit or a functional unit can thus at the hardware level (re) configure the function of the elements and connect (re) the elements in different ways with each other, thereby enabling the adaptation of the arithmetic unit to various hardware-level algorithms. In a particularly preferred embodiment, the configuration or connection of different functional units with each other by the specification of corresponding destination addresses for between the functional units, for example in the form of data packets exchanged data.

In a further advantageous embodiment, it is provided that at least one of the functional units has at least one, in particular direct, data connection to an interrupt request distribution device (English: interrupt router) of the arithmetic unit, and / or at least one, in particular indirectly via a preliminary stage running, data connection an interrupt request distribution means of the arithmetic unit. This advantageously provides the possibility that the functional unit in question may act directly or at least indirectly on the processing of interrupt requests within the arithmetic unit, for example to generate interrupt requests, and / or to delay interrupt requests generated by other units or in any other way influence (for example, to mask). Furthermore, in other embodiments it is advantageously possible to send interrupt requests to the functional unit in order to influence its operation or to change its configuration.

In a further advantageous embodiment, it is provided that at least one of the functional units has a, in particular direct, data connection to an input interface and / or output interface (or a combined input and output interface, English: I / O port) of the arithmetic unit. This advantageously provides the possibility that a functional unit sends input signals to the input interface of the arithmetic unit or outputs output signals via the output interface of the arithmetic unit, for example to units arranged externally to the arithmetic unit.

In a further advantageous embodiment, it is provided that at least one of the functional units has a, in particular direct, data connection to a timer module of the arithmetic unit and / or to an analog / digital converter and / or to at least one further optional component of the arithmetic unit for example, a hardware accelerator unit or the like. This advantageously provides the possibility that the at least one functional unit can act directly on the timer module or can query data such as a counter reading of a timer without having to use the main connection unit of the arithmetic unit. Similar advantages apply to the aspects of the invention, which comprise a direct data connection between at least one functional unit and the analog / digital converter or to an optional hardware accelerator unit.

In a further advantageous embodiment it is provided that at least one of the functional units is designed to change its own configuration. Alternatively or additionally, the functional unit can be designed to change a configuration of at least one further functional unit. In a preferred embodiment, this can be done, for example, by a first functional unit writing corresponding configuration data directly into a configuration register of a second functional unit. The data connection required for this purpose from the first functional unit to the configuration registers of this second functional unit can be implemented as described above several times, for example by the primary connection unit.

In a further advantageous embodiment, it is provided that for the configuration or configuration of one or more functional units corresponding configuration information from a source, such as a configuration memory, are read out and this configuration information is written into the corresponding configuration register of the functional unit concerned. The configuration memory may be arranged, for example, in the secondary storage device. Alternatively or additionally, the configuration memory can also be arranged in the primary memory device. In a further embodiment, it is also conceivable to provide the configuration information by means of external components to the computing unit, for example in the form of (serial) flash memories, which are connected, for example, to corresponding interfaces of the computing unit.

In general, in one embodiment, the primary memory device of the arithmetic unit can advantageously have both a main memory (random access memory, RAM, random access memory) and at least one flash memory, that is to say a nonvolatile memory.

In further embodiments, the secondary memory device is preferably designed as a RAM memory, in particular as a static RAM memory (SRAM).

In a further advantageous embodiment, it is provided that at least one of the functional units has an input interface for receiving the first data and / or a Output interface for outputting the second data. This input or output interface (s) can be used in preferred embodiments, in particular for data exchange (sending and / or receiving) with other similar or different functional units (or possibly with other components which to the input or output interface (n ) of the functional units have compatible corresponding interfaces).

In a further advantageous embodiment, it is provided that at least one of the functional units is configured to receive data from the primary memory device and / or from the secondary memory device and / or from other peripheral components (eg from the addressable registers and / or memory areas of a DMA control unit) / or an interrupt request dispatcher and / or other hardware accelerators) to read and / or write to. In a preferred embodiment, this can be done in particular via a different (different) interface from the abovementioned input or output interface (s), for example also indirectly via the (different) interface different from the abovementioned input or output interface (s) and eg via at least one primary and / or secondary connection unit.

According to a further embodiment, the input interface and / or the output interface can be designed, for example, to receive first data intended for the functional unit in a predefinable format, for example in the form of data packets, or for output to another unit, for example another functional unit. certain second data in a predeterminable format, for example, again in the form of data packets output.

The input interface can be designed, for example, to be connected to the primary connection unit. Depending on the design of the primary connection unit, the input interface can thus be designed, for example, to be connected to a switching network and / or a bus system. Alternatively or additionally, the input interface can also be designed to establish a direct data connection between the relevant functional unit and at least one further functional unit, for example by means of directly interconnected data lines. The same statements apply in a corresponding manner to the formation of the output interface in further embodiments of the invention.

In a further embodiment, it is provided that at least one of the functional units has a local control device for controlling an operation of the functional unit. For example, such a local control device may comprise at least one state machine.

In a particularly preferred further embodiment, the local control device can also be assigned a local reconfiguration device, which enables a reconfiguration or configuration of the functional unit, in particular also dynamically, that is to say during the operation of the functional unit. In a further embodiment, it is also conceivable to map the functionality of the local reconfiguration device through a corresponding part of the state machine or the local control device.

In a further advantageous embodiment, at least one of the functional units has a local calculation unit. In a further advantageous embodiment, the local calculation unit may have at least one coarse granular hardware element or be designed as a coarse-granular hardware element. In a further advantageous embodiment, the local calculation unit may comprise at least one of the components: adder, multiplier, divider, shift register, barrel shifter, comparator, multiplication accumulator (MAC), arithmetic logic unit (ALU), memory unit, registers, multiplexer, demultiplexer, Interface, unit for evaluating exponential functions, unit for evaluating trigonometric functions.

In a further advantageous embodiment, it is provided that at least one of the functional units has a local configuration memory. Particularly preferably, the local configuration memory may comprise a register memory, wherein in particular the local configuration memory comprises a plurality of configuration registers. Thus, efficient configuration and reconfiguration, even during operation of the functional unit, is possible by modifying one or more configuration registers in the desired manner. The modifying of the configuration registers can be done, for example, by the functional unit itself and / or by another functional unit and / or another component of the arithmetic unit such as e.g. a calculation kernel done.

In a further advantageous embodiment, it is provided that at least one of the functional units has a local function memory. Particularly preferably, the local function memory may comprise a register memory or represent part of a register memory. In particular, the local function memory comprise at least one function register. The local function memory can advantageously be used for the at least temporary storage of input data and / or output data of the functional unit or of between results of calculations of the functional unit.

In a further advantageous embodiment, it is also conceivable to equip the functional unit with a plurality of register memories, wherein a first number of the register memories can be used as a configuration register, and wherein a second number of the register memories can be used as a function register. In further embodiments, it is also conceivable that the first number or the second number varies, and is changeable, for example, by configuration. In this way, operation of the functional unit can be made very flexible and in particular the local (register) memory can be adapted dynamically to calculations to be performed by the functional unit.

Further advantageous embodiments are the subject of the dependent claims.

Further solutions of the object of the present invention are specified by a control device according to claim 23 and a method according to claim 24.

Other features, applications and advantages of the invention will become apparent from the following description of embodiments of the invention, which are illustrated in the figures of the drawing. All described or illustrated features, alone or in any combination form the subject matter of the invention, regardless of their summary in the claims or their dependency and regardless of their formulation or representation in the description or in the drawing.

• 1A schematisch ein Blockdiagramm einer Ausführungsform der erfindungsgemäßen Recheneinheit,
• 1B-1H schematisch weitere Ausführungsformen der erfindungsgemäßen Recheneinheit,
• 2A schematisch ein vereinfachtes Blockdiagramm einer Funktionseinheit gemäß einer Ausführungsform der Erfindung,
• 2B schematisch eine Datenstruktur gemäß einer Ausführungsform der Erfindung,
• 2C schematisch ein vereinfachtes Blockdiagramm einer Funktionseinheit gemäß einer weiteren Ausführungsform der Erfindung,
• 3A, 3B schematisch jeweils ein vereinfachtes Blockdiagramm einer Funktionseinheit gemäß einer weiteren Ausführungsform der Erfindung,
• 4 schematisch eine Datenflusskette gemäß einer Ausführungsform,
• 5A schematisch ein vereinfachtes Flussdiagramm einer Ausführungsform des erfindungsgemäßen Verfahrens,
• 5B schematisch ein vereinfachtes Flussdiagramm einer weiteren Ausführungsform des erfindungsgemäßen Verfahrens,
• 5C schematisch ein vereinfachtes Flussdiagramm einer weiteren Ausführungsform des erfindungsgemäßen Verfahrens,
• 6 ein Betriebsszenario gemäß einer Ausführungsform,
• 7 schematisch ein vereinfachtes Blockdiagramm zweier Funktionseinheiten gemäß einer Ausführungsform,
• 8A schematisch einen vereinfachten Datenfluss einer Ausführungsform, und
• 8B schematisch einen Datenfluss gemäß 8A unter Einbeziehung einer primären Verbindungseinheit gemäß einer Ausführungsform.

In the drawing shows:

• 1A 2 is a schematic block diagram of an embodiment of the inventive computing unit.
• 1B - 1H schematically further embodiments of the computing unit according to the invention,
• 2A schematically a simplified block diagram of a functional unit according to an embodiment of the invention,
• 2 B schematically a data structure according to an embodiment of the invention,
• 2C schematically a simplified block diagram of a functional unit according to another embodiment of the invention,
• 3A . 3B 1 is a schematic block diagram of a functional unit according to a further embodiment of the invention,
• 4 schematically a data flow chain according to an embodiment,
• 5A schematically a simplified flow chart of an embodiment of the method according to the invention,
• 5B schematically a simplified flowchart of a further embodiment of the method according to the invention,
• 5C schematically a simplified flowchart of a further embodiment of the method according to the invention,
• 6 an operating scenario according to an embodiment,
• 7 2 is a simplified block diagram of two functional units according to one embodiment;
• 8A schematically a simplified data flow of an embodiment, and
• 8B schematically a data flow according to 8A including a primary connection unit according to an embodiment.

1A schematically shows a block diagram of an embodiment of the computing unit according to the invention 100 , The arithmetic unit 100 has several cores 110a . 110b . 110c and a primary storage device 120 , A main connection unit 130 , which may be, for example, a bus system or a crossbar switch, is provided for connecting the computing cores to one another or for connecting the computing cores to the primary memory device 120 , Optionally, the arithmetic unit points 100 other peripheral components, which in this case by the block shown in dashed lines 125 is indicated. By way of example, such peripheral components can be analog / digital converters, input / output interfaces, timer modules or the like.

The primary storage device 120 In one embodiment, it can advantageously have both at least one random access memory (RAM), in particular of the SRAM type and / or of the DRAM type, and at least one nonvolatile RAM (NVRAM), eg as Flash, EPROM, Ferroelectric RAM (FeRAM), Magnetoresistive RAM (MRAM), Phase-change RAM (PCRAM).

According to the invention, the arithmetic unit 100 at least two functional units, wherein at least a first functional unit 140a is configured to first data from at least one further functional unit 140 , 140b to receive and / or second data to at least one further functional unit 140 . 140b to send or to spend.

The functional units according to the invention 140 , 140a, 140b advantageously offer the possibility of expanding a computing power and / or the functionality of the computing unit 100. In particular, the inventive possibility of direct data exchange between the functional units enables a data flow which does not permit the further components of the arithmetic unit 100 such as their cores 110a . 110b . 110c or the primary storage device 120 or the main connection unit 130 involves. In this way, the cores can 110a . 110b . 110c , the primary storage device 120 , and the main connection unit 130 be relieved, while at the same time perform one or more inventive functional units 140, 140a, 140b provided for them computational tasks or other tasks.

For example, the functional units according to the invention 140 , 140a, 140b, which are preferably implemented predominantly, but particularly preferably completely, as a hardware circuit, be designed to carry out calculations and / or logic operations and / or other functions. The realization of look-up tables, curves and / or maps by functional units is also conceivable. Details of an internal structure of the functional units are described below with reference to, inter alia 2A . 2 B . 2C . 3A . 3B specified. However, the following will be first with reference to 1A to 1H to the arrangement of the functional units within the computing unit according to the invention 100 and their data connection to the central components 110a . 110b . 110c . 120 . 130 the arithmetic unit 100 received.

In an advantageous embodiment it is provided that at least one primary connection unit 150 is provided, which is designed, at least temporarily, a, in particular direct, data connection between the first functional unit 140a and at least one further functional unit 140, 140b. This advantageously makes it possible to control a data exchange or data flow between different functional units, so that a configuration or reconfiguration of the data connection (s) between the respective functional units is also possible during operation of the arithmetic unit, whereby an increased flexibility is achieved. In the present case, a direct data connection means that data can be exchanged between the functional units involved without the main connection unit 130 the arithmetic unit 100 to use. Rather, for example, allows the primary connection unit 150 such a direct data connection between the functional units connected to them, see. the arrows a1, a2, which indicate a data flow between the components 140 . 140a . 140b and the primary connection unit 150 suggest.

In a preferred embodiment, the primary connection unit 150 has at least one coupling network 152a on. Particularly preferably, the coupling network is designed as a blocking-free switching network. In this case, the switching network allows 152a at any time the production of data connections between all with the switching network 152a connected functional units 140 . 140a . 140b and optionally further units connected to the coupling network, such as components 130 the arithmetic unit.

Particularly advantageous for obtaining a blocking-free or reduced-blocking operation of the connection unit 150 According to one embodiment, the restriction of these to only write data connections, wherein read data connections are either not technically provided or can not be allowed or prevented. A ligation - if provided - can be advantageously activated and deactivated.

In further embodiments, it is also conceivable, the primary connection unit 150 designed as a non-blocking switching network.

In further embodiments, the primary connection unit 150 Other structures include, for example, at least one bus system, cf. 1B , which provides a data connection between the to the bus system 152b connected functional units 140 manufactures.

In further embodiments, the primary connection unit 150 also at least one direct data connection between at least two functional units 140 . 140a have, cf. the arrow 152c in 1A , Furthermore, in other embodiments, direct data connections between other or more than two functional units are conceivable.

In a further embodiment it can be provided that the at least one primary connection unit 150 has a plurality of the above-mentioned connection mechanisms, that is, for example, a switching network for connecting some functional units or all functional units with each other and, for example, a bus system which connects several or all functional units.

In another embodiment, at least one secondary connection unit 155 , see. 1A , provided, which is designed to provide a data connection, cf. Arrow a3, between the main connection unit 130 and at least one functional unit 140 either directly and / or indirectly via the primary connection unit 150 producing an efficient connection for data transmission between the respective functional units 140, 140a, 140b and 110a, 110b, 110c, 120, 125 via the main connection unit 130 given is.

The main connection unit 130 According to one embodiment, for example, it can be embodied as a so-called "core interconnect", ie as a central connection unit for the high-performance connection (in particular with high data rates and / or low latency times) of the components 110a , 110b, 110c, 120, 125, 140 of the computing unit according to the invention 100 among themselves. In a particularly preferred embodiment, the main connection unit 130 as already described above, also be designed as a coupling network, in particular as a blocking-free switching network.

Overall, the providence of the functional units allows 140 . 140a . 140b and their flexible connection with each other, by means of the primary connection unit 150 is produced, the provision of additional computing power or additional functionality within the computing unit according to the invention 100 , The entirety of the components 140 , 140a, 140b, 150 can thus also advantageously as "flexible hardware extension" 1500 of the arithmetic unit 100 be understood, with this flexible hardware extension 1500 Computing tasks particularly advantageous essentially independently, ie independent of the components 110a . 110b , 110c, 120, 125, 130, but if necessary via the connection of the secondary connection unit 155 efficient with at least one of the components 110a . 110b . 110c . 120 . 125 . 130 Can exchange data.

1B shows a further embodiment 100a the computing unit according to the invention. In the present embodiment, the components 110a, 110b, 110c, 120, 125, 130, 152c, 155 are substantially unchanged, but the flexible hardware extension herein has a different structure and is therefore in FIG 1B designated by the reference numeral 1500a. Present is the primary connection unit 150 in the form of a bus system 152b realized, to the several similar or different functional units 140 are connected. The functional units 140 can over the bus system 152b exchange data with each other. Some of the functional units 140 You can also use the direct connection 152c exchange data directly. A data connection between the main connection unit 130 and the bus system 152b is through the secondary connection unit 155 analogous to 1A realized, cf. the arrow a3.

1C shows a further embodiment 100b the computing unit according to the invention. Analogous to the 1A . 1B indicates the arithmetic unit 100b according to 1C again three cores 100a . 110b . 110c and a primary storage device 120 and optionally other peripheral units, which in 1C however, are not explicitly depicted, but by the three dots to the right of the primary memory device 120 are symbolized.

In the present embodiment, a flexible hardware extension in the form of multiple groups G1, G2 of functional units is provided. In the present case, a first group G1 has, for example, three functional units 140c , 140d, 140e connected to each other via a first primary connection unit 150_1. In the present case, a second group G2 has two functional units by way of example 140f . 140g which are connected to each other via a second primary connection unit 150_2. The first primary connection unit 150_1 is designed, at least temporarily, for a, in particular direct, data connection between the functional units 140c . 140d . 140e of the first group G1. The second primary connection unit 150_2 is designed, at least temporarily, for a, in particular direct, data connection between the functional units 140f . 140g of the second group G2. The first primary connection unit 150_1 and / or the second primary connection unit 150_2 may be designed, for example, as a switching network, in particular a blocking-free switching network, a bus system, a direct data connection, or in any other way. A corresponding data connection of the respective functional units of the same group is in 1C symbolized by unspecified block arrows between the respective functional units and the respectively associated primary connection unit.

By the present embodiment 100b The arithmetic unit can be provided as it were several clusters G1, G2 of functional units, which can each perform similar or different calculations or other tasks.

In the present case, a data connection between the groups G1, G2 and the Main connection unit 130 through a secondary connection unit 155a realized, which may be formed, for example, as a switching network, bus system, or in any other form. A corresponding data connection between the groups G1, G2 and the main connection unit 130 is symbolized by the block arrows a4, a5. The secondary connection unit 155a can also be designed to establish a direct data connection between the groups G1, G2 or their functional units, ie without the involvement of the main connection unit 130 for such a data connection.

In a further embodiment (not shown) it is provided that a primary connection unit 150_1, which is assigned to a group G1 of functional units, is designed to establish a data connection between functional units of different groups G1, G2.

In a further embodiment (not shown), it is provided that several groups are combined in several upper groups (OG). If we separate the upper group, group and functional units by name, the identifiers OG1-G1-140a or OG2-G3-140i result, for example. Within this hierarchical architecture is the primary connection architecture 150 designed to establish a data connection, in particular on the same hierarchical level between the functional units of a group (150-OG1-G1, 150-OG2-G3), between the individual groups of a super-group (150-OG1, 150-OG2), between the upper groups ( 150 views ) and between 150x and the secondary connection unit 155 as well as cross-hierarchy connections (eg between 150-OG1 and 150-OG1-G1 or between 150x and 150-OG1) as well as any existing non-hierarchical cross-connections between units.

In a further embodiment (not shown), further hierarchy levels may be present in analogous procedure.

1D shows a further embodiment 100c the computing unit according to the invention. In contrast to the embodiment according to 1C is a secondary connection unit 155c each of which provides a data connection a6, a7 between the primary connection units 150_1, 150_2 of the groups G1, G2, and a data connection a8 between these elements and the main connection unit 130 ,

1E shows a further embodiment 100d the computing unit according to the invention. Here are other peripheral components of the computing unit 100d such as analog / digital converters 125a , Interface chips 125b are shown. In this embodiment, as a secondary connection unit, there is further a bus system 155d providing a data connection a8 'between the main connection unit 130 and the primary connection unit 150. Preferably, the primary connection unit 150 again a switching network 152 on to the different functional units 140i . 140k , ..., 140p to connect with each other. Optionally, the functional unit points 140k in addition to its data connection to the switching network 152 a direct data connection a9 to the bus system 155d on. The further functional unit 140i is in a comparable manner both via the switching network 152 as well as a direct connection a10 to the bus system 155d tethered.

The primary storage device 120 the arithmetic unit 100 . 100a . 100b . 100c 100d may include at least one random access memory (RAM) in some embodiments. In addition, the primary storage device 120 Optionally, further storage systems, in particular also non-volatile storage systems have, such as one or more flash memory.

In some embodiments, it is possible for one or more functional units 140 to the primary storage device 120 access, which is usually using the main connection unit 130 , the secondary connection unit 155 and optionally a primary compound unit 150 ( 1A ) he follows.

In a further preferred embodiment 100e the computing unit according to the invention, the below with reference to 1F is described is at least one secondary storage device 160 intended. The secondary storage device 160 is preferably designed as random access memory (RAM), in particular as static random access memory (SRAM, static RAM). In the present case, a secondary storage device is an example 160 displayed; however, in further embodiments, multiple secondary storage devices may also be used 160 be provided. For such embodiments, the following described aspects, which exemplify the one in 1F illustrated secondary storage device 160 are explained accordingly.

In a particularly advantageous embodiment, the secondary storage device 160 several memory banks 162a . 162b . 162c , ..., 162n on. In particular, the secondary memory device may be configured to allow parallel data access to at least two of the plurality of memory banks 162a, 162b, 162c, ..., 162n. This advantageously provides a high bandwidth for accesses to the secondary storage device 160 or their banks allows, and in particular can also not contiguous blocks of data in parallel or simultaneously in the secondary storage device 160 written or from the secondary storage device 160 to be read.

In the present case is the secondary storage device 160 associated with a memory bus system 164 which accesses the memory banks of the secondary memory device 160 allows, cf. the block arrows a11. The memory bus system 164 is advantageously via a bus coupling unit 165 with the bus system 155d coupled, which the already described above data connection between the switching network 152 or the functional units 140i . 140k , ..., 140p and the main connection unit 130 allows. The bus coupling unit 165 allows data exchange between the bus system 155d and the memory bus system 164 , see. the arrow a14. This makes possible, in particular, that memory areas of the secondary memory device 160 in a global address space of the arithmetic unit 100e become visible and thus, for example, also accessible (reading and / or writing) for other peripheral components 125a . 125b the computing unit according to the invention 100 ,

In a particularly preferred embodiment, further, a direct data connection a12, a13 between individual functional units 140k . 140i and the memory bus system 164 so that the functional units concerned 140k . 140i directly to the secondary storage device 160 especially without the coupling network of the primary connection unit 150 or possibly the main connection unit 130 to use.

In a further embodiment (not shown), a plurality of parallel memory devices 160 be present with the aforementioned features.

1G shows a further embodiment 100f the computing unit according to the invention. Unlike the configuration according to 1F is a data connection a15 between the bus system 155d and the primary connection unit 150 provided such that data from the bus system 155d to the primary connection unit 150 can only be written. This may be, for example, data which is from one of the calculation cores 110a . 110b . 110c be provided and one or more functional units 140i . 140k should be forwarded. In particular, the data connection a15 does not allow read accesses from the bus system 155d out to the primary connection unit 150 ,

In a further embodiment of the 1G is a data connection a15 between the bus system 155d and the primary connection unit 150 provided such that of the primary connection unit 150 neither read nor write access to the bus system 155d is possible. Equivalently, functional units can thus access 155d or 164 or the subsequent units, eg 120 or 160, via possibly existing direct connections, but not via the primary connection unit 150 ,

In a further embodiment of the 1G are the data connections a150 between the functional units 140h . 140i , ... and the primary connection unit 150 exclusively writing, not reading, provided. Thus, a functional unit can actively write through a first data connection as well as be described by a second data connection (passive). In another embodiment, it may also be provided that this only applies to some of the existing functional units, ie only between some functional units and the primary connection unit 150 only write access permitting data connections a150 are provided.

1H shows a further embodiment 100 g the computing unit according to the invention. In addition to those already from the configuration according to 1G known components is in 1H an interrupt request dispatcher (English: interrupt router) 170 of the arithmetic unit 100 g shown, which in a conventional manner interrupt requests (English: interrupts) between components of the arithmetic unit 100 g distributed.

In the present embodiment it is provided that at least one of the functional units 140j . 140k at least one, in particular direct, preferably only via a within the flexible hardware extension 1500 located precursor 170a realized data connection to the interrupt request dispatcher 170 the arithmetic unit 100 g has, cf. the arrows a16. This advantageously provides the possibility that the relevant functional unit 140j . 140k directly to the processing of interrupt requests within the arithmetic unit 100 g or their interrupt request distributor 170 via a16, via 170a, via a18 can act, for example, to create interruption requests or influence in any other way (for example, to mask).

The in the flexible hardware extension 1500 pre-stage 170a may preferably be via the secondary connection unit 155 (or in 1H 155d) of the components of computer unit 100 g , in particular the computing cores 110a, 110b, 110c, configured and / or reset and / or otherwise set or read, in particular by accessing registers located within 170a. Also is an embodiment without the precursor 170a conceivable, so that the signals of the functional units 140j . 140k directly to the interrupt request dispatcher 170 (arrows a16 and a18 merge directly into each other).

It is also conceivable in another embodiment that a functional unit 140j is configured to interrupt requests from the interrupt request distribution means 170 possibly via the pre-stage 170a, cf. Arrows a16, a18. This advantageously gives the possibility of interruption requests from the other components of the arithmetic unit 100 over 170 and possibly 170a to the functional unit 140j to influence their operation or to change their configuration.

In a further advantageous embodiment, it is provided that at least one of the functional units 140l . 140m a, in particular direct, data connection a17 to an input interface and / or output interface (or a combined input and output interface) of the arithmetic unit 100 g having. Input and output interfaces are, for example, simple digital or analog or analog / digital pins (I / O pins) or interfaces that consist of one or more pins and in their joint interaction, for example, serve a special communication protocol. Such input and output interfaces of the arithmetic unit 100 g are in 1H exemplified by the block 180 represents. This is advantageous given the possibility that a functional unit 140m Input signals from the input interface 180 the arithmetic unit 100 g receives or outputs via the output interface 180 the arithmetic unit 100 g outputs, for example, from or to externally to the arithmetic unit 100 g arranged units (not shown).

In a further advantageous embodiment (not shown), 180 can be split into a part receiving or transmitting the data 180a and a part serving the communication protocol of the interface 180b , 180a is directly connected to the functional units 140m tethered. 180b can be inside or outside the flexible hardware extension 1500 are located. Advantageously, 180b can be used with other components of the arithmetic unit 100 g to be shared.

Hereinafter, details regarding a structure of the functional units according to the invention will be described in more detail with reference to FIGS. 2A, 2B, 2C. 2A schematically shows a simplified block diagram of a functional unit 1400 according to an embodiment of the invention. The following with reference to 2A described structure of the functional unit 1400 For example, in one or more or all of the above and with reference to the 1A to 1H described functional units 140 , 140a, ..., 140q in the 2A pictured manner or at least in a similar way. It is understood that further statements indicate deviations from the 2A described structure are also possible.

The functional unit 1400 has an input interface 1402 for receiving first data which, for example, from another functional unit (not shown) to the functional unit 1400 according to 2A be transmitted. For the further description of the 2A By way of example, it is assumed that the functional unit 1400 via its input interface 1402 at least one data connection to a primary connection unit 150 (see 1A ), wherein the primary connection unit 150 preferably a switching network 152a having. A corresponding output interface of the switching network 152a connected to the input interface 1402 the functional unit 1400 is connected in 2A symbolized by the dashed rectangle 1502. First input data, the input interface 1402 the functional unit 1400 via the output interface 1502 of the switching network 152 ( 1A ) are in 2A denoted by the block arrow a20.

In a further advantageous embodiment it can be provided that the functional unit 1400 a plurality of input data, in particular simultaneously, can be supplied, which is in 2A is indicated by the dashed block arrow a21 and the points between the block arrows a20, a21. For the simultaneous or parallel reception of input data, in one embodiment, for example, a corresponding number of input interfaces 1402 be provided (not shown).

In one embodiment, it is provided that the input interface 1402 is designed to receive first data or input data in the form of data packets. The data packets may, for example, have a format which is specific for a communication between a plurality of functional units according to the invention 1400 ,

In a further embodiment it can be provided that the input interface 1402 can receive only written data, but explicitly does not support read accesses from the outside or can prevent them alternatively. Likewise, it can be provided in a further embodiment that the functional unit 1400 No data transfer, neither read nor write via the interface 1402 can settle or initiate. This can be done by the interface 1402 be technically correspondingly restricted or this accessibility can be prevented.

In further embodiments (not shown) can also be provided that a functional unit 1400 several input interfaces 1402 of the type described above. By way of example, the input interface 1402 Also referred to as functional unit-specific input interface, because it is designed specifically for, preferably direct, data communication between different functional units with each other. Direct data communication between functional units here means data communication which, in addition to the functional units involved, is possibly still a primary connection unit 150 , for example with the switching network 152 , but not, for example, the main connection unit 130 the computing unit according to the invention 100 ( 1A ).

Alternatively, it is also conceivable in further embodiments (not shown) that a functional unit has no input interface 1402 of the type described above, ie no functional unit-specific input interface. Accordingly, a functional unit configured in this way can not receive input data from another functional unit via the above-mentioned input interface 1402 answer. For example, however, such a functional unit may be designed to load data from another source, for example from the primary memory device 120 of the arithmetic unit via the connection a9 (FIG. 1F ) and / or the secondary storage device 160 , compare 1F , The loading of such data from another source can be done via a differently configured interface, for example via a direct data connection, eg between the functional unit and the secondary storage device 160 like this in 1F is symbolized by the block arrow a12. Such a different interface is in 2A also indicated by the dashed block arrow a24.

In a preferred embodiment, the functional unit is designed to read in or output via the interface a24 a predefinable set of data words, for example at least one data word, or else e.g. N many data words, with N> = 1. This can preferably be done independently, so without a (re-) configuration of the functional unit or an interaction of the functional unit with other components is required before all data words to be read or written have been read or written are. Optionally, the functional unit can also be designed to output information characterizing the read-in or output quantity of data words to a subsequent functional unit.

Optionally, the functional unit may also be configured to output data to a subsequent functional unit, either once, e.g. after completion of the entire memory operation, or one or more times after completing parts of the (holistic) memory operation. These data output to a subsequent functional unit may contain, for example, information about the current progress and / or memory addresses and / or offsets, or else be detached therefrom.

Advantageously, functional units 1400 According to further embodiments, be designed such that by the functional unit via the input interface 1402 received first input data via the interface a24 are output unchanged or in edited form, in particular to the secondary memory device 160 and / or in particular also to one of the remaining components of the arithmetic unit 100 , in particular to the primary storage device 120 or to other peripheral components 125.

Output of output data is shown by the functional unit 1400 According to one embodiment, an output interface 1404 on. For example, output data is passed through the functional unit 1400 depending on the via the input interface 1402 received first data and as second data via the output interface 1404 output, for example, to one or more other functional units (not in 2A shown). A data output from the functional unit 1400 via its output interface 1404 to itself, eg via its input interface 1402 , is also conceivable in some embodiments. The output data is in 2A symbolized by the block arrow a22. Particularly advantageous is the output interface 1404 also to the switching network 152a ( 1A ), compare the in 2A by a dashed rectangle symbolized input interface 1504 of the switching network 152a ,

In further embodiments (not shown), it may also be provided that a functional unit has a plurality of output interfaces 1404 of the type described above. By way of example, the output interface 1404 also as a functional unit specific Output interface are called, because it is specifically designed for, preferably direct, data communication between different functional units with each other.

In a further advantageous embodiment it can be provided that the functional unit 1400 can output several output data, in particular simultaneously, what is in 2A indicated by the dashed block arrow a23 and the points between the block arrows a22, a23. For the simultaneous or parallel output as described above correspondingly many output interfaces 1404 be provided.

In a further embodiment it can be provided that the output interface 1404 can only write data, but does not support read access to the outside or can prevent it alternatively. Likewise, it can be provided in one embodiment that the functional unit 1400 No externally initiated data transfers, neither read nor write via the interface 1404 can receive. This can be done by the interface 1404 be technically correspondingly restricted or this accessibility can be prevented.

Alternatively, it is also conceivable in further embodiments (not shown) that a functional unit has no output interface at all 1404 of the type described above, ie no functional unit-specific output interface. Accordingly, a functional unit configured in this way can not output data via the abovementioned output interface 1404 to output to other functional units. For example, however, such a functional unit may be designed to output data to another unit, for example by writing to the primary memory device 120 the arithmetic unit, eg via the connection a9 ( 1F ), and / or the secondary storage device 160 , eg via the connection a12, compare 1F , The writing of such data can take place via a differently configured interface, for example via a direct data connection between the functional unit and the secondary storage device 160 like this in 1F is symbolized by the block arrow a12. Such a different interface is in 2A also indicated by the already mentioned above dashed block arrow a24.

Advantageously, functional units 1400 in further embodiments be designed such that the data received by the functional unit via the interface a24 via the output interface 1404 unchanged or in edited form to one or more subsequent functional units 1400 in particular data from the secondary storage device is output by means of the interface a24 160 and / or in particular also of the remaining components of the arithmetic unit 100 , esp. The primary storage device 120 or other peripheral components 125 , are read.

The functional unit 1400 also has a local control device 1410 to control the operation of the functional unit 1400 is trained. For example, the local control device 1410 at least one state machine 1410a. In alternative embodiments, the local controller 1410 also comprise other, preferably hardwired, hardware circuits.

In a particularly preferred further embodiment, the local control device 1410 also a local reconfiguration device 1412 be assigned, which is a configuration or reconfiguration of the functional unit 1400 , in particular also dynamically, ie during operation of the functional unit 1400 , allows. In a further embodiment, it is also conceivable that the functionality of the local reconfiguration device 1412 through a corresponding part of the state machine 1410a or the local control device 1410 map.

In another embodiment, the reconfiguration device is 1412 adapted to, during a configuration or reconfiguration, the possible configuration variants of the respective functional unit 1400 to take into account, and / or to ensure that a configuration starts from a defined, valid starting point or start state, and / or that a reconfiguration current calculations or other functions of the functional unit 1400 not impaired or unintentionally interrupts.

In a further advantageous embodiment, the functional unit has a local calculation unit 1420 on. According to a further advantageous embodiment, the local calculation unit 1420 have at least one grobgranulares hardware element or be designed as grobgranulares hardware element. In this case, the local reconfiguration device 1412 Advantageously, for example, control a (re-) configuration of coarse granular hardware elements.

For example, conventional hardware-configurable logic circuits such as FPGAs or CPLDs usually have only finely granular hardware elements whose configuration can only be changed by external specifications. Such conventional hardware configurable Logic circuits are thus to be regarded as (integrated) circuits, which can be programmed at the hardware level in a special programming phase. This also applies to FPGAs with the possibility of partial (partial) reconfiguration. Here, a corresponding number of function-determining re-configuration options is maintained, which are changed according to external specifications, wherein the FPGA parts in question are reprogrammed and interconnected by means of a partial Re-configurations in a respective special Re programming phase. The reconfigured FPGA parts change the logic function itself.

In contrast, the functional unit according to the invention 1400 a calculation unit or a component of a calculation unit whose elements, eg coarse-grained hardware elements, internally by the functional unit 1400 itself or its local control device 1410 configured in the function and, for example, can be interconnected again, for example, using and appropriate setting of multiplexers. Likewise, it can be provided that a further component of the arithmetic unit 100 ( 1A ), for example a calculation kernel 110a , the functional unit 1400 or their components configured.

Another aspect of the configurability according to the invention is that of influencing the communication and the data flow between different functional units 140 . 140a . 140b ( 1A ), which can be controlled, for example, by appropriate configuration of the respective functional units, and / or by controlling the operation of the primary connecting unit (s) connecting the respective functional units. 150 , see. 1A ,

In one embodiment, the internal function, eg logic function, of individual coarse-grained hardware elements or other elements of the functional unit 1400 each hard-wired and thus does not change in contrast to conventional hardware-configurable logic circuits. In this case, as described above, an influencing of the communication and of the data flow between different functional units can take place in order to achieve a reconfiguration.

Advantageously, a new or reconfiguration of the computing unit according to the invention or at least one of its functional units 1400 in some embodiments, by the computing unit 100 or in the relevant functional unit 1400 integrated control device 1410 itself, ie from the inside out, controlled, carried out and possibly supervised. The functional unit 1400 can thus independently and automatically reconfigure itself.

Particularly preferred may be a (re-) configuration during operation of the computing unit 100 or the functional unit 1400 take place, for example as part of an overall algorithm, by one or more of the functional units 1400 , 140, 140a, ... is to be evaluated. Advantageously, it can be provided that functional units 1400 For example, 140a and 140b, other functional units 1400 , For example, 140c and 140d, or configure their components, for example, to realize such a comprehensive overall algorithm.

In a preferred embodiment it is provided that the functional unit 1400 especially then reconfigured even if a predeterminable calculation section or a predefinable calculation task has been executed or terminated and thus the corresponding resources of the functional unit for this calculation task are no longer needed. In this case, the functional unit 1400 Advantageously, even change their configuration, for example, so that it is suitably configured for a subsequent calculation section or a subsequent calculation task.

According to further embodiments, algorithmically upstream functional units advantageously build 1400 on this reconfiguration of algorithmically downstream functional units 1400 Upon completion of a computing section without explicit reconfiguration measures, further data to be processed may be sent to the downstream functional units.

In an advantageous embodiment, a functional unit 1400 , eg 140a, the data to another functional unit 1400 , eg 140b, transmits another functional unit after completing a computing section 1400 , eg 140c, now transfer the data to the functional unit 140b to send. Due to the aforementioned reconfiguration, the functional unit 140c seamless with the sending of data to the functional unit 140b Continue.

In a further advantageous embodiment, the local calculation unit 1420 at least one of the components comprising: adder, multiplier, divider, shift register, barrel shifter, comparator, multiplication accumulator (MAC), arithmetic logic unit (ALU), memory unit, registers, multiplexer, demultiplexer, interface, in particular communication interface, memory access unit (eg DMA Unit), unit for calculating exponential functions, unit for calculating logarithmic functions, unit for calculating Exponential functions, unit for calculating root functions, unit for calculating trigonometric functions, lookup table (s). Combinations thereof are also conceivable in further embodiments. One or more of the abovementioned components may be preferred in the calculation unit 1420 of the functional unit according to the invention 1400 be arranged.

The calculation unit 1420 Accordingly, calculations on the functional unit 1400 feed input data and output results obtained from this, for example, as output data again. A data flow for this process preferably takes place via the input interface 1402 (Reception of input data), the calculation unit 1420 (Execution of the calculations), the output interface 1404 (Output of output data). This data flow is characteristic for the calculation or processing of data within a functional unit 1400 ,

Outside the functional unit 1400 According to a preferred embodiment, the data flow can be influenced by the specification as to which (further) functional unit output data of a first functional unit is to be forwarded, which is achieved by a corresponding control of the primary connection unit 150 can be accomplished. Advantageously, the control of the primary connection unit 150 be set once and thus permanently for a certain period of time. It may also be advantageous to control the primary connection unit 150 dependent on control data that are sent with individual or with each package, esp. By specifying a destination functional unit 1400 ,

If more complex calculations are to be carried out, in further embodiments, a plurality of functional units, for example, the in 2A imaged type, which are similar or non-uniformly configured calculation units 1420 exhibit. A data flow of data between the various functional units can advantageously be defined by an algorithm or the structure of the more complex calculations to be carried out.

In a further advantageous embodiment, it is provided that the functional unit 1400 a local configuration store 1430 having. Particularly preferred may be the local configuration memory 1430 a register memory, in particular the local configuration memory 1430 at least one, but advantageously a plurality of configuration registers 1432 . 1432b . 1432c . 1432d includes.

In another embodiment, the local configuration memory may also be represented by an SRAM or by a combination of register storage and SRAM. In the following, the embodiment comprising an SRAM is summarized as register memory.

Through the local configuration store 1430 is an efficient configuration and reconfiguration, even during the operation of the functional unit 1400 , possible, for example, by one or more configuration registers 1432 . 1432b , 1432c, 1432d are modified as desired. Modifying the configuration registers 1432 . 1432b . 1432c . 1432d For example, by the functional unit 1400 itself and / or by another functional unit (not shown).

Furthermore, it is conceivable that in further embodiments modifying the configuration registers of a functional unit 1400 through further components of the arithmetic unit 100 ( 1A ), for example by a calculation kernel 110a , is possible by the relevant component 110a corresponding data in the or the configuration register of the functional unit 1400 writes.

In a further advantageous embodiment, it is provided that the functional unit 1400 a local function memory 1440 having. Particularly preferably, the local function memory 1440 comprise a register memory or represent part of a register memory. In particular, the local function memory 1440 at least one function register 1442A include. The local function memory 1440 can advantageously for at least temporary storage of input data and / or output data of the functional unit 1400 or intermediate results of functional unit calculations 1400 as performed by the computing unit 1420 may be used.

In a further advantageous embodiment, it is also conceivable, the functional unit 1400 with a plurality of register memories, wherein a first number of the register memories are used as configuration registers 1432 , 1432b, 1432c, 1432d, and wherein a second number of register memories are used as function registers 1442A is usable.

In further embodiments, it is also conceivable that for different configuration options of a functional unit 1400 the first number of required register memories or the second number of required register memories varies and can be changed, for example, by a main configuration. In this way, operation of the functional unit 1400 be designed very flexible and in particular, the local (register) memory dynamically from the functional unit 1400 be adapted to be executed calculations.

In a preferred embodiment is for the data exchange between different functional units 1400 a specific data structure, for example in the form of a data packet provided. 2 B schematically shows a simplified representation of a data structure DS for such data packets according to one embodiment. The data structure DS has an address field ADR. The address field ADR is subdivided into a first address ADR1, which specifies a specific functional unit for which the data packet DS comprising the data structure is determined.

An optional second address ADR2 defines a destination address within the functional unit determined by the first address ADR1, which can advantageously be used to store in which local memory area of the destination functional unit data contained in the data packet is stored. For example, the second address ADR2 may be used to address particular storage registers of the destination functional unit.

In embodiments of the computing unit according to the invention, which, for example, some ten functional units 1400 usually a few bits, for example about the bits 10 to 5 (eg six bits) are sufficient to define the first address ADR1. The same applies to the "internal addressing" by means of the second address ADR2 with respect to that in the functional units 1400 available storage registers, which in one embodiment, for example, by the bits 4 to 0 be selected.

Further optionally, the data structure DS may comprise a data field DAT, which has input data, for example for calculation by the target functional unit, and / or configuration data, which are provided, for example, for controlling a configuration of the target functional unit.

In further embodiments, it is also possible for data packets to be exchanged between functional units which contain an empty data field DAT, that is to say neither input data for a calculation nor configuration data for the destination functional unit. This may be important for a synchronization of different functional units, for example.

Optionally, control data may also be contained in the data structure DS which may be arranged in the data field designated by the reference symbol CTRL. This may be, for example, additional control data (ie, in addition to the configuration data that may be included in the data field DAT), such as status information, security information, information on a loop depth or recursion depth in a nested execution of loops or recursive calculations. Alternatively or additionally, the control data CTRL may also contain parity information and / or checksums and the like. Combinations of the above information for the control data are also conceivable.

In a further preferred embodiment, at least one functional unit 1400 ( 3A ) are adapted to data with at least one other functional unit in the above with reference to 2 B designated format, ie in the form of data packets with the data structure DS, exchange, ie to send or receive.

In a further preferred embodiment, a newly arriving configuration containing the functional unit concerned 1400 receives, optionally (eg always) immediately in the local configuration memory 1430 be written or (eg always) discarded, if a new configuration (yet) is not possible or (eg always) held back until the functional unit 1400 to accept a new configuration in accordance with the regulations is ready or (eg always) cached in a buffer that may be read only when the functional unit 1400 is ready to receive a new configuration in accordance with the regulations. In the penultimate case, or in the latter case when the buffer is full, there is advantageously a blockade of the input data, the further writing to the functional unit 1400 with the local configuration store 1430 until the data can be processed. In a very advantageous manner, the blockade is also used as synchronization means between at least two functional units 1400 used.

Advantageously, this can be done by blocking synchronization in the functional unit 1400 also on the local function memory 1440 be applied. For example, performs a functional unit 1400 with two input interfaces 1402 For an addition operation A + B = C, preferably both A and B should be present in the registers of 1440 for the calculation of C to start. Only after reading A and B can new A 'and B' be received. Already before this time new A 'and / or B' should be sent to the corresponding registers in the function memory 1440 the functional unit 1400 be sent, then the functional unit 1400 if necessary, hold back this data until it can be received.

Advantageously, is for a functional unit 1400 configurable, which registers within the configuration memory 1430 and / or the function memory 1440 lead to a blockage and which not. Thus, it may be advantageous that individual registers must be written only once, for example, or may only be written once, for example, in order to be valid permanently or for a period of time determined according to certain criteria. In the aforementioned example of the addition operation, it could be configured, for example, that the value of register "B" only needs to be written once. For each received "A" then the operation A + B, A '+ B, A "+ B, etc. is executed until, for example, a new value B' is written to the register" B ".

In a further preferred embodiment, at least one of the functional units, as already indicated above, is designed as a hardware circuit, in particular completely as a hardware circuit. As a result, calculations, logic operations, memory operations and other functions provided by the relevant functional unit, such as the realization of look-up tables, characteristic curves and / or maps, can be carried out particularly quickly and efficiently.

In a further advantageous embodiment, it is provided that at least one of the functional units has at least one of the following elements: a microcontroller, a software executing computation core (eg a computation core designed to execute software), a digital signal processor (DSP), a programmable one Logic circuit (for example, an FPGA, field programmable gate array), an application-specific integrated circuit (ASIC, application specific integrated circuit), in particular a prefabricated by a gate and / or transistor array but not yet application-specific wired integrated circuit, eg is only application-specifically wired in a later manufacturing step, and the e.g. can be referred to as "Sea-of-Gates". As a result, if necessary, special functions can be realized within a functional unit according to the invention. In particular, the function to be performed of such functional units can be determined only at a later time and / or changed with a comparatively small effort.

In particular, for example, a comparatively small, at least partially programmable by software, microcontroller may be included in a particular functional unit to provide a possibly necessary for some applications flexibility and / or to be able to represent a higher complexity. In this case too, the interaction of the several functional units with each other results in the already described advantages with regard to the relief of the main connection unit 130 as well as the calculation cores 110a . 110b . 110c the computing unit according to the invention 100 . 100a . 100b . 100c . 100d . 100e . 100f . 100 g ,

In a particularly preferred embodiment, it is provided that all functional units are designed as a hardware circuit, in particular completely as a hardware circuit. This results in a particularly efficient, efficient and small-sized arrangement.

In other embodiments, it is possible for one or more functional units to be designed as a hardware circuit, in particular completely as a hardware circuit, and for at least one component or another component not completely formed as a hardware circuit to be provided in the form of at least one further functional unit. For example, in a particularly preferred embodiment, a first number of functional units may be provided, which are completely formed as a hardware circuit, and another functional unit, for example, a microcontroller or a programmable logic device or a programmable logic circuit or a comparatively easily changeable logic circuit.

In a further preferred embodiment, as already mentioned above, at least one of the functional units has at least one coarse-granular hardware element. Alternatively or additionally, at least one of the functional units can be designed as a coarse granular hardware element.

The term coarse granular here means that the relevant hardware element has more than one logical gate or is formed from more than one logical gate. The gates are in one embodiment, according to function and / or connection with each other unchangeable.

By coarse-granular hardware elements are thus to be understood in particular elements which can each automatically perform complex arithmetic operations, in particular without the need for further data interchange with each other, after previously described manner of sending and receiving the data via the output and input interfaces 1402 and 1404 is done. For example, the individual coarse granular hardware elements each formed as one of the following elements: highly complex elements such as arithmetic logic unit (ALU), memory access unit, communication interface and / or less complex units such as comparator, adder, multiplier, divider, shift register, barrel shifter, multiply-accumulate , (MAC)), Exponential Unit, Logarithm Unit, Trigonometric Unit, Register, Memory Unit (eg RAM, Flash etc.), Multiplexer (eg 2: 1 MUX, M: N-MUX).

An ALU calculates in particular arithmetic and logical functions. For example, it can perform at least one addition (ADD) as an arithmetic function and at least one negation (NOT) and a conjunction (AND, AND) as a logical function. As arithmetic function, it may also preferably include a subtraction (SUB) and / or a comparison (compare, CMP) and / or a multiplication (MUL) and / or a division and / or a decimal adjustment after addition (decimal adjustment after addition). carry out. As a logical function, it may also have a disjunction (OR, OR) and / or a contravalence (XOR, EOR) and / or a right and left shift (right-left, left-shift, ASR-arithmetic shift right, ASL - arithmetic shift left, LSR - logical shift to the right, LSL - logical shift to the left) and / or a left and right rotation (ROL, ROR) and / or register manipulations and / or bit changes (set bits , delete and test) and / or resorting to bits and bytes and / or perform AES commands and / or CRC commands.

In particularly preferred embodiments, a plurality of interconnected components such as adders, multipliers, dividers, shift registers, barrel shifters, comparator, multiplication accumulator, arithmetic logic unit, exponential unit, logarithm unit, trigonometric unit, memory unit, memory access unit, registers, multiplexer, interface, In particular, at least one first functional unit is configured to receive first data from at least one further functional unit and / or second Send data to at least one other functional unit, as has already been described above. As a result, a data flow can be defined which, inter alia, also makes it possible to carry out comparatively complex calculations, which use, for example, a multiplicity of the abovementioned components or coarse granular hardware elements, or generally calculation units which can be distributed over a number of functional units Order according to an algorithm to be evaluated or another calculation rule. The predeterminable sequence can be controlled, for example, by the data flow between the various functional units. As already described above, this can be done, for example, by the definition of corresponding destination addresses ADR1 within individual data packets, cf. 2 B ,

According to a further aspect of the present invention, this data flow can also be particularly advantageously also dynamically, that is to say influenced or changed, that is to say reconfigured, during a running time of the computing unit according to the invention. In a preferred embodiment, this can be done, for example, by appropriate control of the primary connection unit 150 be accomplished. In one embodiment, the control of the primary connection unit takes place 150 advantageously by the computing cores 110a . 110b . 110c and / or by another peripheral component 120 (in particular by a DMA controller). In a further embodiment, the control of the primary connection unit 150 is carried out alternatively or additionally advantageously by a functional unit 140.

According to a further advantageous embodiment, it is provided that the arithmetic unit 100a , ..., 100 g is configured to a configuration of at least one functional unit 1400 to change and / or a state or the configuration of at least one functional unit 1400 to check. As a result, the flexibility and the utility of the computing unit according to the invention is further increased. For example, in one embodiment it can be provided that at least one functional unit contains one or more of the configuration registers already described above 1432 . 1432b , ... and / or function registers 1442A ( 2A ), which may for example be arranged locally in the functional unit. By read accesses of the arithmetic unit, for example by virtue of one of its arithmetic cores 110a ( 1A ), the arithmetic unit can thus read out or monitor the configuration of the relevant functional unit, and possibly modify it by write accesses.

In a further embodiment it is provided that at least one of the functional units 140 . 140a . 140b , ..., 1400 is configured to a configuration of the primary connection unit 150 and / or at least one secondary connection unit 155 to change and / or a state or the configuration of at least the primary connection unit 150 and / or at least a secondary connection unit 155 to check.

In a further advantageous embodiment, it is provided that at least one of the functional units has a, in particular direct, data connection to a timer module of the arithmetic unit 100 and / or to an analog / digital converter and / or to at least one further optionally present component of the computing unit, such as a hardware accelerator unit or a communication interface unit or the like. This advantageously provides the possibility that the at least one functional unit can act directly on the timer module or can query data such as, for example, a counter reading of a timer, without the main connection unit 130 (FIG. 1A ) of the arithmetic unit 100 to use. Similar advantages apply to the aspects of the invention, which comprise a direct data connection between at least one functional unit and the analog / digital converter or to an optionally present hardware accelerator unit or to an optional communication interface unit.

In a further advantageous embodiment, it is provided that at least one of the functional units 1400 ( 2A ) is adapted to change its own configuration. Alternatively or additionally, the functional unit may be designed to change a configuration of at least one further functional unit. In a preferred embodiment, this may be done, for example, by having a first functional unit directly in a configuration register 1432 ( 2A ) writes corresponding configuration data to a second functional unit. The data connection required for this purpose from the first functional unit to the configuration registers of the second functional unit can, as already described above several times, for example by the primary connection unit 150 ( 1A ) be realized.

Alternatively or additionally, a direct data connection can also be provided 152c ( 1A ) between the respective functional units 140 140a, to be used by means of a first functional unit 140a the configuration data of another configuration unit 140 to manipulate.

In a further advantageous embodiment, provision is made for configuration or reconfiguration of one or more functional units to read out corresponding configuration information from a source, for example a configuration memory, and to write this configuration information into the corresponding configuration register of the relevant functional unit (s). The configuration memory may be in the secondary storage device, for example 160 ( 1F ) can be arranged. Alternatively or additionally, the configuration memory may also be in the primary memory device 120 be arranged, in particular in a non-volatile memory area of the primary memory device 120 ,

In further embodiments, it is also conceivable, the configuration information by means of the computing unit 100 provide external components, for example in the form of (serial) flash memory (SPI Flash), which are connected, for example, to corresponding interfaces of the arithmetic unit.

Below are examples of aspects of a data or. Information flow within the functional unit 1400 according to 2A described. As already mentioned above, the functional unit 1400 For example, one or more data packets of the in FIG 2 B closer structure DS via its input interface 1402 receive. Input data contained therein, which in this case may be configuration data, are received from the input interface 1402 to a specific configuration register 1432b forwarded as in 2A indicated by the arrow a25. The information in which configuration register the configuration data a25 are to be written is obtained either from address information a26, which are likewise contained in the relevant data packet, cf. the reference character ADR2 of the data structure DS 2A , or eg from another configuration register 1432c , The address information a26 or the configuration register 1432c are present through an address recognition and selection unit 1452 evaluated, which indicates that the configuration data a25 in the confirmation register 1432b to write.

The address recognition unit 1452 In a preferred embodiment, for example, it may have a demultiplexer structure which is controlled directly by the address information ADR2 contained in a data packet. Furthermore, the functional unit 1400 via a test unit 1453 by means of which it is possible to check whether valid input data is present in the functional unit 1400 available. This information may be from the test unit 1453, for example, to the local controller 1410 the functional unit 1400 are transmitted, see. the arrow a30 off 2A indicating the operation of the functional unit 1400 and for example the calculation unit 1420 in response to this information controls.

A data connection between the local controller 1410 and the configuration memory 1430 or the function memory 1440 is indicated here by the arrow a31. A data connection between the calculation unit 1420 and the configuration memory 1430 or the function memory 1440 is indicated here by the arrow a32. In some embodiments, a direct data connection between the control device can also be particularly advantageous 1410 and the calculation unit 1420 exist, see arrow a33.

In a further preferred embodiment, a multiplexer structure 1454 is provided, which is designed to determine from which or which register memories and / or configuration memories or from which other sources of the functional unit 1400 possible output data for output via the output interface 1404 to be obtained. By way of example, the multiplexer structure 1454 are controlled via the contents of a configuration register 1432d, see arrow a29.

For the compilation of a data packet to be output, the data to be output can be provided, for example, by the multiplexer structure 1454 be provided, see arrow a27. Address information for the data packet to be output can, for example, from a configuration register 1432c be provided or read, see arrow a28. The address information for the data packet to be output, for example, again the address ADR1 ( 2 B ) for a destination functional unit, to which the data packet to be output is to be output, as well as possibly the further address information ADR2 for internal addressing within the destination functional unit.

As already described above, in a functional unit 1400 according to another embodiment, in addition to an input interface 1402 or an output interface 1404 yet another data connection to one with respect to the functional unit 1400 be provided external component, for example, to another functional unit or other unit of the processing unit according to the invention. 2C shows a further embodiment of this 1400a the functional unit according to the invention. The structure of the functional unit 1400a according to 2C essentially corresponds to the configuration 2A , In contrast to this, however, in addition to or as an alternative to the local function memory, there is a peripheral memory 1460 provided, which in the present case three peripheral registers 1462A . 1462B . 1462c includes.

Also in 2C one is shown to the functional unit according to the invention 1400a external component 200 in which it is another peripheral component of the computing unit according to the invention 100 ( 1A ) can act. In the present case, a data connection a34 is present between the first peripheral register 1462A the functional unit 1400a and a register 202a of a register memory 202 the external component 200 provided, which of the functional unit 1400a a direct access (write and / or read) to the contents of the register 202a the external component 200 allowed. For example, the functional unit 1400a by a read access to the contents of the register memory 202a the external component 200 this over the data connection a34 in their local peripheral register 1462A transfer. Alternatively, it is possible to change the contents of the register 202a directly into the peripheral register 1462A to reflect. In further embodiments, in particular such a latter embodiment, it is conceivable to design the data connection a34 such that upon access (read, write) to the peripheral register of the functional unit directly to the "redirected" (mapped) register of the external component 200 is accessed.

For the further peripheral register 1462B is a similar data connection a35 to the register 202c the external component 200 intended. For the further peripheral register 1462c is a similar data connection a36 to the register 202d the external component 200 provided, but here is a buffer unit 1464 is arranged in the data connection a36, which is adapted to the data of the corresponding register 202d the external component 200 to buffer in the writing and / or reading direction. Alternatively or additionally, the buffer unit 1464 also be trained to the data of the corresponding register 202d of the external component 200 as it passes through the functional unit 1400a read and / or written.

The direct data connections a34, a35, a36 described above advantageously enable an efficient data exchange between the participating components 1400a . 200 in particular without any communication resources shared with other components, such as the switching network 152 or the main connection unit 130 are required for data exchange, so that a time-unaffected direct communication can take place. Such a direct data exchange is particularly preferred by the reading out of one or more registers of the external component 200 or by writing data to one or more registers of the external component 200 respectively.

In further embodiments, it is conceivable to register one or more external components 200 to the corresponding peripheral registers of one or more functional units 1400a map.

In further embodiments, one or more line signals (hereinafter referred to as "signals") of one or more external components can advantageously also be used directly 200 read in and / or written on these signals. In contrast to the aforementioned registers 202a . 20b . 202c . 202d For the purposes of the invention, signals are understood not to be direct accesses to registers or their input and output lines, but to read access as the result of a logical combination of registers and / or other signals and write access as the input into a logic circuit connection. All the embodiments previously mentioned for the registers are therefore also to be reproduced on signals, in particular the existence of a data connection between the signals of the external component 200 and 1400a, mirroring external component signals 200 in registers within 1400a, the ability to buffer data, and the ability to manipulate data while reading and / or writing to or from one or more external components 200 ,

In further embodiments, it is possible to obtain data from the functional unit 1400a be read or written over the data connection a34, a35, a36, in terms of their value and / or the timing for the respective read or write operation. In a further embodiment it is provided that the buffer unit 1464 is designed to carry out one or more of the modifications mentioned above.

In one embodiment, it is provided that values are not modified during reading and / or writing.

In another embodiment, it is provided that values are modified during reading and / or writing, in particular by the buffer unit 1464 , For example, the respective values may be read by the functional unit 1400a on a register 202d the external component 200 be modified before entering the peripheral register 1462c of the functional unit 1400a to be written. A modification of values in a write access by the functional unit 1400a on the register 202d the external component 200 is also possible in an analogous manner.

In further embodiments, modifying may comprise at least one of the following steps: changing one or more flags, in particular bit flags, values to be read or written, adding (adding) an offset, inverting, further logical or numerical manipulations of the data to be read or written writing values. This embodiment advantageously enables functional manipulations with respect to the values processed by the functional unit 1400a.

In further embodiments, it is conceivable to schedule a data transfer from an external register 200 2d to a local peripheral register of the functional unit 1400a or vice versa.

Preferably, in one embodiment no such temporal manipulation is applied. In other words, the corresponding data or register contents are transferred as quickly as possible from a source register to the destination register or mirrored.

In a further embodiment it can be provided to use a predefinable delay time during reading or during writing. The following variants are also conceivable: simple buffer, application of the FIFO (first in first out) principle, adjustable variable delay time, event-controlled delay time (the data to be read or written are delayed until a specifiable event occurs). The above measures, which can influence the timing of the data transmission between the various registers, can advantageously be used to intentionally bring about fluctuations in the temporal behavior of the data transmission or also for synchronization purposes, for example to read in or output data synchronized to predetermined time stamps, and / or to enable pulse width modulation, and / or to synchronize data with clock sources, and / or latency of the arithmetic unit 100 and / or system-wide latencies outside of the arithmetic unit 100 arise, compensate.

In a further advantageous embodiment, one or more aspects of the aforementioned functionality relating to the manipulation of data to be transmitted or the manipulation of the thereby occurring timing by the buffer unit 1464 will be realized. Alternatively or additionally, in the case of the arithmetic unit according to the invention, an external with respect to the considered functional unit 1400a arranged component (not shown) may be provided, which realizes the above-mentioned functionality.

• - Direkter Zugriff auf externe Ressourcen 200, insbesondere ohne zusätzlichen Kommunikationsaufwand (englisch: overhead), wodurch die Funktionalität der Funktionseinheit 1400a bzw. der gesamten erfindungsgemäßen Recheneinheit 100 erweitert und/oder beschleunigt werden kann. Dies ist besonders dann vorteilhaft, wenn die Funktionseinheit 1400a eine entsprechende Funktionalität benötigt, diese jedoch gar nicht oder nicht in der erforderlichen Form bzw. Leistungsfähigkeit in der Funktionseinheit 1400a selbst vorhanden ist.
• - Umgekehrt können auch externe Komponenten 200 direkt auf in der Funktionseinheit 1400a vorliegende Daten zugreifen, insbesondere ohne zusätzlichen Kommunikationsaufwand, wodurch die Funktionalität der externen Komponente 200 entsprechend erweitert und/oder beschleunigt werden kann.
• - Kombination der Funktionalitäten der Funktionseinheit 1400a mit den Funktionalitäten der externen Komponente 200.
• - Effiziente Synchronisierung zwischen der Funktionseinheit 1400a und der externen Komponente 200.
• - Direkter Datenaustausch zwischen den Komponenten 1400a, 200 mittels Hardware-Primitiven.
• - Sofern die externe Komponente 200 beispielsweise eine Kommunikationsschnittstelle aufweist, kann die Funktionseinheit 1400a über die direkte Datenverbindung a34 gegebenenfalls direkt die in der externen Komponente 200 angeordnete Kommunikationsschnittstelle zur Kommunikation mit weiteren Einrichtungen nutzen, ohne dass die Funktionalität der Kommunikationsschnittstelle in der Funktionseinheit 1400a vorhanden ist.

The above-mentioned direct data connections a34, a35, a36 between the functional unit 1400a and the external one component 200 enable the following features or benefits:

• - Direct access to external resources 200 , in particular without additional communication effort (English: overhead), whereby the functionality of the functional unit 1400a or the entire computing unit according to the invention 100 can be extended and / or accelerated. This is particularly advantageous when the functional unit 1400a requires a corresponding functionality, but this not at all or not in the required form or performance in the functional unit 1400a itself is present.
• - Conversely, external components can also be used 200 directly on in the functional unit 1400a present data available, in particular without additional communication overhead, whereby the functionality of the external component 200 can be extended and / or accelerated accordingly.
• - Combination of functionalities of the functional unit 1400a with the functionalities of the external component 200 ,
• - Efficient synchronization between the functional unit 1400a and the external component 200 ,
• - Direct data exchange between the components 1400a . 200 using hardware primitives.
• - If the external component 200 For example, has a communication interface, the functional unit 1400a via the direct data connection a34 optionally directly in the external component 200 arranged communication interface for communication with other facilities, without the functionality of the communication interface in the functional unit 1400a is available.

• - Die lokale Steuereinrichtung 1410 der Funktionseinheit 1400a veranlasst das Schreiben von Daten in ein externes Register 202a.
• - Bei dem Erhalt bestimmter Eingangsdaten, beispielsweise in Form eines oder mehrerer Datenpakete, können Adressinformationen ADR (2B) ermittelt werden, welche einen Schreibvorgang auf ein Peripherieregister 1462a veranlassen, welches direkt auf ein externes Register 202a gespiegelt ist. Mit anderen Worten wird durch die in dem empfangenen Datenpaket enthaltenen Adressinformationen ein Peripherieregister adressiert, welches auf das externe Register 202a gespiegelt ist.

The following are possible application examples or scenarios in which data is passed through the functional unit 1400a For example, written to a register of an external component 200 via a direct data connection a34:

• - The local control device 1410 the functional unit 1400a causes the writing of data in an external register 202a ,
• When receiving certain input data, for example in the form of one or more data packets, address information ADR ( 2 B ), which writes to a peripheral register 1462A which direct to an external register 202a is mirrored. In other words, a peripheral register addressed to the external register is addressed by the address information contained in the received data packet 202a is mirrored.

• - Die lokale Steuereinrichtung 1410 der Funktionseinheit 1400a veranlasst das Lesen von Daten aus einem externen Register 202a.
• - Bei dem Erstellen eines über die Ausgangsschnittstelle 1404 (2C) auszugebenden Datenpakets wird festgestellt, dass wenigstens ein Teil der auszugebenden Daten aus einem Peripherieregister 1462a der Funktionseinheit 1400a zu lesen ist, welches ein externes Register 202a spiegelt.

The following are possible application examples or scenarios in which data is passed through the functional unit 1400a be read via a direct data connection a34:

• - The local control device 1410 the functional unit 1400a causes the reading of data from an external register 202a ,
• - When creating one via the output interface 1404 ( 2C ) to be outputted data packets, it is determined that at least a part of the data to be output from a peripheral register 1462A the functional unit 1400a to read which is an external register 202a reflects.

In the following, further embodiments are described, by way of example specific types of possible external components 200 in the sense of the preceding description and associated data accesses on whose registers are called via direct data connections in the manner of the data connections a34, a35, a36 described above.

In one embodiment, the external component 200 as timer module (English: timer) of the arithmetic unit 100 be educated. For example, it may be an integrated (system) timer, or even a comparatively complex timer module, which is a peripheral component of the arithmetic unit 100 provided and preferably also integrated in this. For example, the comparatively complex timer module may be a timer module of the type described in the international patent application WO 2011/120823 A1 is described.

When running the external component 200 As a timer module can be a direct data access to a register 202a for example, reading a timer value or writing a timer value. Alternatively or additionally, a direct data access to the timer module or its registers can take place with the aim of reading or writing values of the so-called timer compare register or of generally reading or writing control registers of the timer module. In some embodiments, an operation of the timer module can also be controlled by such a data transmission, in particular the timer module can be activated or deactivated and / or switching times can be set.

In general, by a direct data access of the functional unit according to the invention 1400a to an external component designed as a timer module 200 the functionality of the functional unit 1400a according to the invention to the execution of time-controlled calculations or a synchronization with a global timer of the arithmetic unit 100 be extended. Furthermore, the functional unit 1400a thereby directly on system events of the arithmetic unit 100 , which are controlled by the timer module 200, respond, and / or calculation operations, for example by the local calculation unit 1420 , in a temporal relation with by the arithmetic unit 100 put processed data frames.

In a further embodiment, the external component 200 as input and / or output interface (for I / O pins) of the arithmetic unit 100 be educated, cf. also element 180 out 1H , A direct data connection a34 ( 2C ) allows the functional unit 1400a in this case, direct access to the interface 180 and thus the possibility of outputting or reading in data about this without system-related delay times of the arithmetic unit occurring. This also advantageous temporal variations (jitter) can be avoided and optionally blocking conditions, as they can occur in conventional computing units with shared access to such interfaces.

In a further embodiment, the external component 200 be designed as input and / or output interface, for example, to status values and / or the configuration of the calculation cores 110a . 110b . 110c and / or other peripheral components 125 the arithmetic unit 100 read out or set. A direct data connection a34 ( 2C In this case, the functional unit 1400a in this case allows direct access to the status values and / or the configuration registers and thus the possibility of outputting or reading in data thereon, without system-related delay times of the arithmetic unit occurring in this case.

In a further embodiment, the external component 200 be designed as external communication interface. External in this context means that the external communication interface 200 allows communication with at least one unit which external to the arithmetic unit according to the invention 100 is arranged. The external communication interface 200 itself can be in the arithmetic unit 100 integrated or outside the arithmetic unit 100 be arranged. For example, an external communication interface of the aforementioned type may be at least one interface module for at least one of the following communication protocols: SPI (Serial Peripheral Interface), CAN (Controller Area Network), CAN-FD (CAN Flexible Data Rate), FlexRay , Ethernet, SENT, Micro Second Channel, L2C, PSI5, LIN (Local Interconnect Network), UART (Universal Asynchronous Receiver Transmitter), and the like. As a result, the functional unit according to the invention 1400a Advantageously extended by the corresponding functionality of the aforementioned communication interface (s).

In a further embodiment, the external component 200 be designed as an analog / digital converter. As a result, the functional unit according to the invention 1400a advantageous to the corresponding functionality of the analog / digital converter 200 in particular, read out digital values derived directly from analog values detected by means of the analog / digital converter from one or more of the mirrored registers. Furthermore, the functional unit 1400a optionally read or write access to one or more control registers of the analog / digital converter to monitor the operation of the analog / digital converter and / or to control. In this case system-related delay times of the arithmetic unit due to the direct access by means of the data connection a34 are advantageously avoided.

In a further embodiment, the component 200 as a combination of the external component described above 200 as analog / digital converter as well as the external component 200 be designed as a timer module, ie, in this embodiment, the component realizes the functionality of at least one analog / digital converter and at least one timer module. This makes it possible, for example, to read the analog values and the derived digital values acquired by the analog / digital converter in a time-synchronized manner with a system clock signal of the timer module. Furthermore, the functional unit 1400a if appropriate, also reading or writing in time-synchronized access to one or more control registers of the analog / digital converter in order to monitor and / or control the operation of the analog / digital converter. In this case system-related delay times of the arithmetic unit due to the direct access by means of the data connection a34 are advantageously avoided.

In a further advantageous embodiment, the external component 200 may be formed as an error handling unit. As a result, the functional unit according to the invention 1400a advantageously directly error signals or error vectors to the error handling unit 200 output. Furthermore, there is advantageously the possibility that the functional unit 1400a possible Error conditions of other components queries, which may also be stored in at least one register of the error handling unit.

In a further advantageous embodiment, the external component 200 may also be designed as another hardware accelerator unit. This advantageously provides the possibility that the functional unit 1400a Data directly with the other hardware accelerator unit 200 exchanges. In particular, this makes use of the main connection unit 130 avoided and a time-tight coupling of 1400a and 200 allows.

In a further advantageous embodiment, the external component 200 can also be designed as a direct memory access (DMA) control unit. The DMA controller is a memory access unit, which may preferably actively and / or independently and directly access memory and / or other peripheral components within the addressable memory area. The DMA controller 200 is designed in a manner known per se to direct memory access via a bus system of the arithmetic unit, for example via a bus system of the main connection unit 130 to execute, making data between those through the main connection unit 130 Connected components can be transferred without requiring a computational core 110a . 110b . 110c is needed. This implies the advantage that the functional unit according to the invention 1400a can use the functionality of the DMA controller. For example, the functional unit 1400a in this way direct memory accesses between the primary storage unit 120 and another peripheral component 125 the arithmetic unit 100 without causing any interaction between the functional unit 1400a and the DMA controller 200 is required. Furthermore, in this embodiment there is the possibility that the functional unit 1400a by reading out or describing one or more control registers of the DMA control unit 200 Influence on the operation of the DMA control unit 200 ,

In a further advantageous embodiment, it is provided that the functional unit 1400a itself has a DMA control unit (not shown) to perform (memory) direct accesses to at least one bus system of the arithmetic unit 100, preferably to a bus system of the main connection unit 130. The DMA control unit can advantageously be integrated directly into the functional unit 1400a and, for example an access of the functional unit 1400a allow for a global address space of the arithmetic unit. Particularly preferably, the functional unit 1400a in a further embodiment operate as a "master" and thus via the main connection unit 130 actively and independently accessing and / or writing to the global address space. Access to the main connection unit 130 For example, through the interface a24 ( 2A ) respectively.

3A schematically shows a simplified block diagram of a functional unit 1400b according to a further embodiment of the invention. The functional unit 1400b is set up to implement the functionality of a multiplication accumulator (MAC). In this case, for example, three input quantities A, B, C are defined, which are evaluated according to the following equation and thus lead to the output variable Y: Y = A * B + C, where "*" defines the multiplication operator. The input variables A, B, C can the functional unit 1400b for example via at least one data packet contained in the input data a20 via the input interface 1402 can be supplied, and the output Y can be the functional unit 1400b as already described several times above as data packet a22 via the output interface 1404 to at least one other functional unit (not shown) spend. The computational steps multiplication, addition required for the evaluation of the above equation may be the local computation unit 1420a the functional unit 1400b To run. This is provided by the local calculation unit 1420a for example via a multiplier 1421a, preferably designed as a hardware circuit, and via an adder, which is preferably also designed as a hardware circuit 1421b According to further embodiments, the aim of an even more efficient implementation is also in a common multiplication accumulator, which is preferably designed as a hardware circuit 1420a , without separation into 1421a and 1421b, can be implemented. The remaining components 1410 . 1412 . 1430 . 1440 the functional unit 1400b can be identical to the configuration according to 2A be educated. In another embodiment, the remaining components 1410 . 1412 . 1430 . 1440 However, be deviating from this.

3B schematically shows a simplified block diagram of a functional unit 1400c according to a further embodiment of the invention. The functional unit 1400c For example, it is intended to provide data from two other functional units 1400 each with an output interface 1404 or from another functional unit 1400 with two output interfaces 1404, which in turn receive the data from, for example, the secondary memory device 160 ( 1F ) load. For this purpose, the functional unit 1400c for example, two input interfaces 1402a . 1402b of the above with reference to 2A described type 1402 have, so the functional unit 1400c Input data can be supplied via two parallel input interfaces. Particularly preferably, the data can be received independently of one another via the two input interfaces. Alternatively, using the two input interfaces 1402a . 1402b Data with twice the data width or word width are received, wherein the first input interface 1402a eg the low order bits a20_1 of the data is received and the second input interface 1402b eg the higher order bits a20_2 of the data is received. In a particularly powerful variant of the aforementioned multiplication accumulator 1440B (MAC, 3A ), the input variables A, B, C could, for example, via three parallel input interfaces 1402 (only one input interface 1402 shown) of the calculation unit 1420a be supplied.

According to a further embodiment, the functional unit 1400c be provided to output data to a data sink. For this purpose, the functional unit 1400c for example, two output interfaces 1404a , 1404b of the above with reference to 2A described type 1404, so that two parallel write operations are possible. Particularly preferably, the two write operations can be performed independently. Alternatively, using the two output interfaces 1404a . 1404b Data with twice the data width or word width are output, wherein the first output interface 1404a For example, the low-order bits a22_1 of the data are output, the second output interface 1404b For example, the higher-order bits a22_2 of the data outputs.

According to a further embodiment, the functional unit 1400c be provided to data from a data source such as the secondary storage device 160 ( 1F ) or to write in this. For this purpose, the functional unit 1400c For example, two different interfaces a24_1, a24_2 of the above with reference to 2A a24 so that two parallel read or two parallel writes or one parallel read and write or two parallel reads are possible along with two parallel writes. Most preferably, the read / write operations can be performed independently. Alternatively, using the two different interfaces a24_1, a24_2, data with twice the data width or word width can be read or written, wherein the first different type of interface a24_1 reads or writes eg the low-order bits of the data, and wherein the second different interface a24_2 eg the higher-order bits of the data are reading or writing.

In other embodiments, a different number of input interfaces 1402 or output interfaces 1404 as well as other interfaces a24 for the functional unit according to the invention also conceivable.

According to a further embodiment, a functional unit 1400 ( 2A ) Output data a22 via the output interface 1404 output such that the output data at least two address fields ADR ( 2 B ), each ADR being subdivided into a first address ADR1 specifying a particular functional unit for which the data packet DS comprising the data structure DS is determined, and an optional second address ADR2 defining a destination address within the functional unit designated by the first address ADR1. Through the primary connection unit 150 The output data a22 of a functional unit are then sent to the at least two destination functional units 1400 forwarded.

According to yet another embodiment, upon output of the output data, it may be indicated whether and which of the at least two addresses ADR are valid, such that the primary connection unit 150 the data corresponding to the respective target functional unit forwards or not forwarded. According to further embodiments, the specification of the validity of an address can be effected by additional fields in the output data, for example by an additional validity bit per address field. Alternatively or additionally, the validity of an address may be indicated, for example, by a specific value from the field ADR and / or ADR1 and / or ADR2.

A significant advantage of the present invention is that the functional units 140 . 140a , ..., 140q . 1400 . 1400a . 1400b . 1440c active, direct and autonomous (without the need for control by, for example, the computing cores of the arithmetic unit) communicate with each other or can exchange data. In one embodiment, this is advantageously achieved in that the functional units can output data packets, in particular functional unit-specific data packets, to other functional units. In a further embodiment, this is advantageously achieved in that the functional units can receive data packets, in particular functional unit-specific data packets, from other functional units.

According to a further embodiment, the functional units may particularly preferably determine to which further functional unit or data sink output data of the functional unit, for example in the form of one or more data packets, is output. In particular, such a determination can also dynamic, that is, during the runtime of the functional unit, are hit. For example, for this purpose, the address field ADR of the data structure DS ( 2 B ), wherein the data is output dynamically at runtime to different functional units or data sinks.

Particularly advantageous is in addition to the functional units and a primary connecting unit connecting them 150 - no further component of the arithmetic unit 100 required to enable the appropriate exchange of data between the functional units. In particular, there is no higher-level unit than the functional units, such as a calculation kernel 110a required to allow data exchange. Also particularly advantageous is none of the functional unit 1400 Parent unit required to determine a respective target for output data of a functional unit during the life of the functional units, because in preferred embodiments, this task by the local control device 1410 ( 2A ) or the specification of a destination address via the input interface 1402 obtained input and configuration data can be derived.

A further advantage of the functional units according to the invention is that they execute their calculation task (s) as soon as they are correctly configured and input data corresponding to them are supplied. In a preferred embodiment, the calculation data or output data of a functional unit depends on the functionality of the local calculation unit 1420 as well as from the local control device 1410 in conjunction with the local reconfiguration device 1412 See, for example, the above with reference to 3A described embodiment with the Multiplikationsakkumulator.

In further advantageous embodiments, the calculation data or output data of the functional unit may depend on the configuration of the functional unit, the input data supplied and possibly additional input data or input signals which can be supplied to the functional unit via further input interfaces, for example compare the data connection via the different interface a24 according to 2A and / or the direct data connection a34 according to 2C , For example, if a direct data connection a34 between the functional unit and an external component 200 ( 2C ), for example, values of one of the external component 200 in the functional unit mirrored register also have influence on the output data of the functional unit.

The inventive design of the functional unit with defined input interfaces 1402 and output interfaces 1404 advantageously allows a particularly simple and efficient data flow, which can also be analyzed in a simple manner, in particular with respect to a time course of the relevant data transfers. Moreover, interleaves of read accesses and write accesses are thereby advantageously avoided and a particularly deep pipelining is made possible both within individual functional units and in data flow chains comprising a plurality of functional units.

4 shows by way of example a total of three different functional units 1400e, 1400f, 1400g comprehensive data flow chain to illustrate a multiple functional units comprehensive data processing within the arithmetic unit according to the invention. Overall, the mapped data flow chain is used to evaluate the equation Z = D * exp (E) + F + sin (G), where exp () represents the exponential function, where sin () represents the sine function, where D, E, F, G are input data and Z represents the output data obtained by evaluating the equation. For the sake of clarity, only the local control unit is for the individual functional units 1410 and the local calculation unit 1420 displayed. The further internal structure of at least one of the functional units may, for example, be identical or at least similar to that in FIG 2A be pictured configuration.

The local calculation unit evaluates the exponential function exp (E) 1420 the functional unit 1400e a unit e1 for calculating the exponential function. Furthermore, the local calculation unit points 1420 the functional unit 1400e a multiplier e2 for calculating the expression D * exp (E). The input data is the functional unit 1400e the parameters D, E supplied, and as output data represents the functional unit 1400e the intermediate result Z1 = D * exp (E) ready. This intermediate result Z1, like the parameter F, becomes the further functional unit 1400F supplied as input data.

The local calculation unit 1420 the functional unit 1400F has an adder e3, which determines the further intermediate result Z2 = Z1 + F. The further intermediate result Z2 becomes, like the parameter G, the further functional unit 1400g supplied as input data.

The local calculation unit 1420 the functional unit 1400g indicates a unit e4 Calculation of the sine function sin (G) and an adder e5, which determine the final result Z as a function of the data Z2, G, which can finally be output by the output interface (not shown) of the functional unit 1400g.

Particularly advantageous is the in 4 In the illustrated configuration, the calculations of a data stream in a pipeline structure are performed. The data of the data stream, thus the input data D, E, F, G as well as the intermediate results Z1, Z2 and the result Z, receive eg an index "i", "i-1", "i-2", "i + 1 "," I + 2 ", etc., which is identical for all D, E, F, G, Z1, Z2, Z according to the logical identity of the calculation formula, for example Z [i] = D [i] * exp (E [ i]) + F [i] + sin (G [i]) and Z [i-1] = D [i-1] * exp (E [i-1]) + F [i-1] + sin ( G [i-1]) and Z [i-2] = D [i-2] * exp (E [i-2]) + F [i-2] + sin (G [i-2]). Thus, accordingly 4 the functional unit 1400e from the input data D [i], E [i] calculate the intermediate result Z1 [i], during which the functional unit 1400F the intermediate result Z2 [i-1] is calculated from the input data F [i-1] preceding by one index and the intermediate result Z1 [i-1] preceding by one index, and the functional unit is calculated accordingly 1400g From the turn an index previous input data G [i-2] and the intermediate result Z2 [i-2] the result Z2 [i-2] calculated.

Particularly advantageous is the in 4 illustrated configuration substantially autonomously evaluate the equation described above with the result Z, in particular without requiring an interaction with a computer core of the arithmetic unit, or accesses to the main distribution unit 130 or similar. Rather, for example, at the beginning of the evaluation of the equation described above can be ensured by a corresponding configuration that the individual functional units 1400e . 1400F . 1400g the correct input data are provided or their local calculation units 1420 be configured in the sense of the evaluation of the equation described above. Then, the functional units can be determined using their respective local computing unit 1420 autonomously calculate the equation described above, and only after the calculation, the result Z, for example, via the output interface 1404 optionally further functional units 1400 and / or via the different interface a24 ( 2A ) in the primary storage unit 120 ( 1A ) and / or in the secondary storage device 160 ( 1F ) and / or to another peripheral component 125 ( 1A ) and / or via the data connection a34 to an external component 200 ( 2C ) be transmitted.

In a further advantageous embodiment, it is provided to balance the throughput or data flow of all the functional units of the arithmetic unit according to the invention, which makes it possible to work as parallel as possible all processing stages, that means in particular all functional units and their calculation units. Optionally, the above with reference to 4 described, purely exemplary structure with regard to such a balance can be optimized.

According to further embodiments, the number and / or configuration of the functional units is particularly advantageous 1400 a flexible hardware extension 1500 ( 1A ) is chosen so that the data flow between the units is balanced, so that a blockage of a single functional unit does not adversely affect other functional units. If the complexity of an operation is too high, so that this balance can not be guaranteed by individual functional units, then in a particularly advantageous embodiment, for example, a plurality of similar functional units can be used.

For example, the functional unit could 1400g out 4 with the unit e4 for calculating the sine function sin (G) and the adder e5 to be present twice as "1400g_1" and "1400g_2" (not shown). The input data having the index "i-2", "i", "i + 2", etc. could then be supplied to the functional unit 1400g_1, for example, and the input data having the index "i-1", "i + 1", "i +3 "etc. could be supplied to the functional unit 1400g_2, for example. The functional unit 1400g_1 then supplies the results Z [i-2], Z [i], Z [i + 2], the functional unit 1400g_2 then supplies the results Z [i-1], Z [i + 1], Z [i +3]. The results Z can, for example, be brought together again by selecting or configuring the identical subsequent target functional unit.

Another significant advantage of the configuration according to the invention is that the system resources required for the exchange of data between the functional units essentially relate to the primary connection unit 150 ( 1A ), in particular not the main connection unit 130 to include. This advantageously allows efficient communication of the other components 110a . 110b . 110c . 120 , 125a, 125b of the computing unit according to the invention 100 using the main connection unit not substantially loaded by the functional units 130 and an efficient and accurate prediction of possible blocking conditions within flexible hardware extension 1500 ( 1A ). Therefore, using the principle according to the invention can advantageously also the risk be reduced or excluded by blocking in the data processing by the arithmetic unit according to the invention.

In a further advantageous embodiment, as already described several times above, it is provided that the data exchange between different functional units 140, 140 A, 140 B, compare 1A , via a primary connection unit 150 takes place, wherein the primary connection unit 150 is preferably designed as a coupling network, particularly preferably as a blocking-free coupling network. Particularly advantageous allows the primary connection unit 150 a plurality of simultaneous or at least partially temporally overlapping data transmissions between different functional units.

As an alternative or in addition to the provision of a switching network, one or more directly wired data connections can be provided between different functional units. For example, in the case of direct wiring between different functional units, it may be provided that a specific functional unit can select one or more or all other functional units as the target ("target functional unit") for the output of output data such as data packets. Depending on the number of possible destination functional units correspondingly many direct data connections are to be provided. Optionally, one or more of such direct-wired data connections may also be provided with adaptation logic (English: glue logic), for example comprising multiplexer or demultiplexer structures or the like. Furthermore, it is conceivable that for a particular functional unit which packets to e.g. should be able to output three possible destination functional units, three separate output interfaces are provided, each of which is directly connected to a corresponding input interface of one of the possible destination functional units.

In further embodiments, more flexible connection techniques than the above-mentioned directly wired or directly interconnected data connections may be used. Examples of this are coupling networks, bus systems and the like. Combinations of the aforementioned technologies are also conceivable.

In a further particularly preferred embodiment, the primary connection unit 150 adapted to modify a target data contained in it, such as data packets, for example, by subtracting an offset address of a destination functional unit, in particular before forwarding this data to the corresponding target functional unit, advantageously such that the data packet to the receiving destination Function unit comprises only a local address for the local configuration memory and / or the local function memory.

In a further particularly preferred embodiment, a plurality of similar or different functional units may be combined with each other and data-joined to each other via a primary connection unit, thereby obtaining a form of calculation network or calculating means which may be configured to calculate a particular algorithm. Particularly preferably, the calculation device can calculate algorithms which have a higher complexity than those algorithms that can be calculated by individual functional units that form components of the calculation device. Examples of such calculating means are described above by way of example with reference to FIG 1A . 1B . 1C . 4 already described. In particular, the "flexible hardware extension" 1500 1A Such a calculation device, as well as the further flexible hardware extension 1500a out 1B or also each of the groups G1, G2 1C ,

In a preferred embodiment, a calculation algorithm of the calculation network enabled according to the invention is characterized by one or more of the following: the specific functionality of each functional unit involved, the specific capabilities of the configurability of each functional unit involved, in particular its (computing) functionality, the specific connectivity or Connectivity of each participating functional unit with respect to the establishment of data connections to other functional units or the primary connection unit, the production of data connections via different interfaces a24, the production of data connections a34 to external components 200 the specific capabilities and capabilities of each functional unit involved to configure or reconfigure for connectivity with other functional units or primary interconnect unit, the initial functional configuration of each functional unit involved, initial configuration of the connectivity of each involved functional unit with respect to fabrication from data connections to other functional units or the primary connection unit, the initial configuration for establishing data connections via different interfaces a24, the initial configuration for establishing data connections a34 to external components 200 , the specific dynamic reconfiguration of each functional unit involved at runtime in terms of their functionality (for example, properties of the local calculation unit 1420 ), the specific dynamic (during the lifetime of the functional unit) reconfiguration of each participating functional unit with respect to their connectivity to other functional units or the primary connection unit, the specific dynamic configuration for establishing data connections via different interfaces a24, the specific dynamic configuration for establishing data connections a34 to external components 200 , an initial configuration at the beginning of the term of the functional units involved, input data, events that can influence the calculation results or a configuration of at least one participating functional unit or the primary connection unit.

In another particularly preferred embodiment, at least one of the functional units is configured to configure itself or another functional unit or to reconfigure it, in particular dynamically, ie during the runtime of a functional unit or the other functional unit. This eliminates the need for configuration by an external component. In other words, in this embodiment, no external component is required to configure or reconfigure the functional units according to the invention.

In further embodiments, however, it may be provided that at least one other component of the computing unit according to the invention 100 , for example, a calculation kernel 110a , or also one of the peripheral components 125a, 125b, is designed to configure or reconfigure at least one of the functional units according to the invention.

A further advantage of the functional units according to the invention is the high degree of "distributed intelligence" or computing capacity and flexibility resulting from the functionality of, for example, the individual local calculation units, their flexible configurability and reconfigurability. These advantages scale particularly advantageously with the number of functional units of a computing unit according to the invention. Such functionality and flexibility can not be realized economically with, for example, only one central, higher-level unit, as known from conventional systems. A significant advantage of the present invention is the multitude of possibilities with regard to the creation and (dynamic) change of data paths or linking of the functional units with one another, which is made possible for example by the use of corresponding addresses in data packets exchanged between the functional units. Another advantage is the high degree of parallelism that results from the fact that functional units can be operated algorithmically independently of each other. Another advantage is the high degree of parallelism which results from the fact that functional units can be operated algorithmically dependent on one another in a functional unit-spanning pipeline.

According to the invention, it has been recognized that the more data units are transmitted, the more functional units operate in parallel, wherein the destination address of individual data packets can also change between two successive transmissions of data packets according to preferred embodiments. In particular, the primary connection unit can also transmit a particularly large number of data packets at the same time or convey them to destination functional units, because the functional units according to the invention are themselves designed to correspond to the destination addresses.

In a further preferred embodiment, all components of the computing unit according to the invention are arranged on a same semiconductor substrate or manufactured using the same semiconductor manufacturing technology. The functional units according to the invention are also particularly advantageous 140 . 140a . 140b , ..., 140q ; 1400 . 1400a . 1400b , ..., 1400g arranged on the same semiconductor substrate as the other components 110a, 110b, 110c, 120, 125a, 125b, 130 of the computing unit. This advantageously results in a particularly small-sized configuration and the possibility of producing an efficient and high-performance data connection between the components, for example by including the main connection unit 130 and at least one primary connection unit 150.

The following describes aspects of the operating method according to the invention for a computing unit 100 ( 1A ) based on various embodiments and with reference to the flowcharts of 5A . 5B . 5C described. 5A schematically shows a simplified flowchart of an embodiment of a method for operating a computing unit according to the invention 100 . 100a . 100b . 100c . 100d . 100e . 100f . 100 g , see. the 1A to 1H , As already described above, the arithmetic unit has at least one arithmetic core 110a . 110b . 110c , a primary storage device 120 , and at least one main connection unit 130 for connecting the at least one calculation kernel 110a . 110b . 110c with the primary storage device 120 on, wherein the arithmetic unit further comprises at least two functional units 140 . 140a . 140b . 1400 having.

In an optional first step 300 a configuration of at least one first functional unit takes place 1400 ( 2A ). The optional configuration 300 For example, one or more of the configuration registers 1432a, 1432b, 1432c, 1432d of the functional unit may be described 1400 through the functional unit 1400 itself (for example by means of its reconfiguration device 1412 ), another functional unit or another component of the arithmetic unit, such as a computing core 110a. Alternatively, the functional unit may optionally be preconfigured by an initial configuration which is immediately available after its initial activation.

In the step 302 ( 5A ) receives the first functional unit 1400 first data from at least one further functional unit. These received first data can be used as input data for the first functional unit 1400 used and, for example, a calculation by the local calculation unit 1420 be based on.

In the step 304 sends the first functional unit 1400 second data to at least one further functional unit. By way of example, these second data may be output data which has been used in the preceding calculation by the first functional unit 1400 have been obtained. A corresponding calculation step could according to the embodiment of 5A between the steps 302 . 304 done, but is not shown.

The receiving or sending of data may, according to preferred embodiments, via corresponding input interfaces 1402 ( 2A ) or output interfaces 1404 and at least one, a data connection between the functional units or their interfaces 1402 , 1404 producing component, such as the primary connection unit 150 , respectively.

In a further embodiment of the method according to the invention, the optional step 300 also come up with it. In a further embodiment of the method according to the invention, only one of the two steps 302, 304 may be carried out and optionally repeated. In further advantageous embodiments of the method according to the invention, in which a multiplicity of functional units are contained in the arithmetic unit according to the invention, one or more of the functional units may comprise aspects of the above by way of example with reference to FIG 5A perform the described operating procedure.

5B schematically shows a simplified flow diagram of another embodiment of the method according to the invention. Here is an exemplary procedure from the perspective of a functional unit according to the invention 1400 ( 2A ).

In a first optional step 400 Optionally, input data to be provided to the functional unit for calculation is provided. Alternatively or additionally, configuration information, which controls, for example, an operation of the functional unit, in the step 400 to be provided. The functional unit receives in this step, for example via the input interface 1402 the input data. This can be done, for example, by storing the input data or the configuration information directly in the local configuration memory of the functional unit, for example in one or more of its configuration registers.

In the also optional step 402 Optionally, the functional unit waits for the aforementioned input data or configuration information and optionally stores incoming data. The saving takes place in the local configuration memory 1430 the functional unit and / or in one or more of its configuration registers and / or in the local function memory 1440 eg in one or more of its function registers.

step 404 , which is also optional, has an optional check as to whether the input data and / or configuration information is completely available for evaluation or calculation by the functional unit. If the input data and / or configuration information is not complete, the step 402 branched. Otherwise, provided that the input data and / or configuration information is complete, the step 406 passed.

step 406 , which is also optional, has the above-mentioned evaluation or calculation by the functional unit, for example using its local calculation unit 1420 , for example, controlled by the local control device 1410 , to the subject.

In step 408 , which is also optional, it is checked whether output data are available, which eg in the evaluation or calculation by the functional unit, see step 406 , have been received. Unless the review in step 408 shows that the output values are available becomes step 410 passed. Otherwise, turn to step 402 branches, whereby optionally further input data and / or configuration information can be obtained and optionally further calculations can be performed to obtain the desired output values.

In step 410 , which is also optional, the output values are output. Spending 410 the output values may include, for example: sending the output values to at least one further functional unit and / or sending the output values to at least one further component of the arithmetic unit, for example to the primary memory device 120 , the secondary storage device 160 , another peripheral component 125 , an external component 200 , the interrupt request dispatcher 170 or similar. The output values output can, for example, be results from the calculation 406 and / or status information and / or configuration data for configuring subsequent functional units.

For example, if output values are output, see step 410 , then according to another embodiment, in step 412 corresponding output data packets in the manner already described above via the output interface 1404 ( 2A ) are created and output.

In a further embodiment it can be provided that the formation 412 the output data packet also providing address information ADR ( 2 B ) and / or configuration information and / or control information CTRL, which according to the data structure DS 2 B as already described can also be integrated into the output data packet.

In each of the above steps 400 . 402 . 404 . 406 . 408 . 410 . 412 but especially in the steps 406 . 410 According to a further embodiment, the functional unit can, due to its specific functionality and / or its specific possibilities, the configurability and / or its initial functional configuration and / or its dynamic reconfiguration at runtime and / or its initial configuration at the beginning of the term, by input data, events and Calculation results optionally make an internal reconfiguration. In other words, according to a further embodiment, the functional unit may, depending on its specific functionality and / or its specific possibilities, the configurability and / or its initial functional configuration and / or its dynamic reconfiguration at runtime and / or its initial configuration at the beginning of the runtime, and / or, depending on input data and / or events and / or calculation results, optionally optionally carry out an internal reconfiguration.

In a particularly preferred embodiment, at least two, but in particular all of the aforementioned steps 400 . 402 . 404 . 406 , 408, 410, 412 are performed in parallel, for example, by an internal pipeline of the functional unit.

5C schematically shows a simplified flow diagram of another embodiment of the method according to the invention. Here is an exemplary procedure from the perspective of the processing unit according to the invention 100 ( 1A ) or one of their computing cores 110a described.

step 420 marks a start of the procedure. In the optional step 422 prepares the arithmetic unit 100 , For example, a computing core provided for this purpose 110a , Data before, which should be assigned later as input data of one or more functional units. In one embodiment of the method, the input data are preferred in the global address space of the arithmetic unit, in particular in the primary memory device 120 , filed.

In an optional step 424 a global configuration of the flexible hardware extension is made, which may include multiple functional units and / or the primary interconnect unit (s). The functional units are according to another embodiment, preferably not via the input interface 1402 configured. For example, the configuration may include adjusting the clock frequency and / or setting fault modes and / or handling interrupts, and / or connecting to the other components outside the flexible hardware extension, and so on.

According to further embodiments, the global configuration may also include an initial setting of the primary connection structure 150 in particular if the addressing of the data packets a20, a21, a22, a23 ( 2A ) not exclusively about a corresponding 2 B pronounced addressing using ADR, ADR1, ADR2.

In step 426 the at least one functional unit is preconfigured. This can be done, for example, by writing corresponding configuration information preferably via the input interface 1402 in this provided configuration register 1432 . 1432b . 1432c . 1432d ( 2A ) of the functional unit (s). The writing 426 The configuration information can be obtained, for example, by the calculation kernel 110a be executed. Alternatively or additionally, the writing can also be effected by a direct memory access (DMA) control device of the arithmetic unit. In this case, either no action of the calculation kernel is advantageous 110a or merely issuing a start command to the memory direct access Control device for executing the step 424 according to 5C required. When using a direct memory access control device, the configuration data are advantageously located in the primary memory device, especially before the start of this step 120 in front.

In step 428 the at least one functional unit is configured, which, according to a preferred embodiment, starts to perform calculations, preferably immediately after the configuration.

In step 430 the arithmetic unit or the arithmetic kernel waits 110a until the functional unit (s) have finished executing the calculations. In some embodiments, the completion of calculations by the functional unit (s) about the initiation of an interrupt request via the interrupt request dispatcher 170 to the particular arithmetic kernel 110a and / or to the memory direct access control means. Alternatively or additionally, the arithmetic unit or the arithmetic core 110a and / or another peripheral component 125 also use polling (cyclic query) mechanisms to determine an operating state of the functional unit (s), in particular a completion of calculations.

In step 432 reads the arithmetic unit or its arithmetic kernel 110a and / or its direct memory access control device and / or another peripheral component 125 the result of the calculation (s). In step 434 the procedure is terminated.

Optionally, after running the step 428 also in one step 431 be branched, which has a dynamic configuration or reconfiguration of one or more functional units to the object. In this case, a specific functional unit can itself configure or reconfigure and / or configure other functional units. Alternatively or additionally, a reconfiguration of at least one functional unit may also be performed by the computing core 110a or another component external to the functional unit to be reconfigured.

The steps 420 . 422 . 424 . 426 . 428 . 430 . 432 . 434 can be performed in a different embodiment in a changed order.

6 schematically shows an operating scenario of a computing unit 100 according to the present invention. The arithmetic unit 100 is part of a control unit 1004 for an internal combustion engine 1002 of a motor vehicle 1000 , The arithmetic unit 100 For example, as has been described above with reference to FIGS 1A to 1H described configuration, as well as at least two functional units 140 . 1400 , as described above, for example with reference to the 1A to 2C have been described. The computing unit according to the invention 100 has a particularly high flexibility, because the functional units contained in it can be dynamically configured or reconfigured. At the same time, the inventive functional units advantageously extend the computing power of the arithmetic unit 100 about the computing power of their cores 110a . 110b . 110c and other peripheral components 125 out, given.

Further advantageous fields of application for the principle according to the invention and the computing unit according to the invention are control devices for the operation of electric motors or generators, control units for batteries, driver assistance systems, chassis systems, power tools, household appliances, and the like.

Hereinafter, further advantageous embodiments and aspects of the present invention will be described.

In a particularly preferred embodiment, a plurality of functional units 1400 ( 2A ) by at least one data connection establishing connection structure, in particular the primary connection unit 150 ( 1A ), that is, for example, a switching network and / or a bus system and the like, connected to one another so that a comprehensive data flow is formed, which allows the calculation of a specific algorithm or the calculation of several parallel specific algorithms.

In further embodiments, at least some of these data connections are particularly preferably dynamically reconfigurable, so that the algorithm can also be dynamically changed. As already described above, this can be done, for example, by appropriate addressing of data packets exchanged between the participating functional units.

In other embodiments, for example, in the case of direct data connections between functional units, this may be indicated by the reference numeral 152c 1A , are realized using multiplexer structures or demultiplexer structures which are the direct data connections 152c under appropriate control to the modifications to be made to the algorithm in question.

In preferred embodiments, the primary connection unit 150 a high Parallelism, which allows many simultaneous or temporally overlapping data connections or data transmissions between different functional units.

Further advantageously, a high data throughput and a high computing performance in the data processing by the functional units of the invention according to an embodiment can be achieved in that the functional units their output data among each other preferably write, in particular only write, forward, creating a streaming mechanism is created. In particular, unwanted interruptions in the data flow can also be avoided in this way.

Particularly preferably, no central control of a data flow for the data processing by the functional units according to the invention is provided, as is customary in conventional microcontrollers, for example in the form of a calculation kernel. Rather, in the preferred embodiment of the invention, the data flow for the data processing by the functional units according to the invention is determined exclusively by the functional units themselves. In this case, in particular, the primary connection unit 150 ( 1A ), for example, directly and / or, for example, according to a configuration of a functional unit switched or controlled so that the output data of a functional unit are sent to a configured target functional unit. In some embodiments, for example, this may be for a particular period of time, in particular until the reconfiguration or reconfiguration of the primary connection unit 150 to be discontinued. In some embodiments, however, this can also be effected, for example, by at least some, but preferably all data packets sent by functional units being provided with a destination address which, for example, indicates the destination functional unit for a data transmission, optionally additionally a destination memory area or a destination Memory cell or the like in a local address space of the destination functional unit. Details on this are already given above with reference to the data structure DS according to FIG 2A been described.

In a further embodiment it is provided that a functional unit carries out an operation or calculation task (only) if the configured input data are available. If, for example, the local calculation unit of a functional unit is configured as multiplication accumulator (MAC) according to the following equation O = A * B + C only to the calculation mode "multiplication", it is sufficient if the two input values A, B are present, so that the relevant functional unit or their local calculation unit can start the calculation. In contrast, the functional unit or its local calculation unit would additionally have to wait for the presence of the further input value C if the functional unit or its local calculation unit is configured for the calculation types "multiplication" and "addition", ie a complete multiplication accumulation.

In a further embodiment, it is provided that a functional unit, for example in terms of the functionality of its local calculation unit, is designed so flexible that it can be optionally, e.g. Depending on a configuration, it can be used for different types or variants of a corresponding calculation task. For example, an adder of a local calculation unit may preferably be designed so that it can also perform a subtraction instead of the addition, wherein the different functionality or a change between these functionalities can be set by means of a configuration. Furthermore, it may be configurable at the adder whether the addition is carried out with "carry", with or without accumulation register, and the like.

In a further embodiment, at least one, preferably a plurality of configurable offset registers may optionally be provided in a functional unit that is configured to load data and / or to store data. In a fixed or preferably configurable manner, with each data access operation, there is a change in that at least one offset, for example incrementing or decrementing with a value greater than, less than or equal to 0, shifting N bits left or right, resetting to 0 or another value, As a so-called "bit inverse" value (English bit-reverse, high-order bits are mirrored to lower bits and vice versa), etc. If desired, at least two offsets can optionally be set interdependent and / or independently configurable, so that, for example, a first Offset with each data access changes and a second offset, for example, changes only when the first offset has made a certain number of accesses. Particularly preferably, a functional unit for loading and / or storing data has a, preferably configurable, integrated units for type conversion, in particular of floating-point numbers in fixed-point numbers and vice versa and / or for adapting the bit widths, for example from 16 bits to 32 bits, and so on.

In a further advantageous embodiment, a functional unit 1400e ( 4 ) be adapted to account for characteristics of an algorithmic loop. In particular, the functional unit 1400e be trained to a current loop depth of a considered arithmetic operation to subsequent functional units 1400F output, for example in the form of control data CTRL, compare the data structure DS 2A , whereupon at least one such data receiving functional unit 1400F For example, a conditional execution of by their local calculation unit 1420 provided calculation steps depending on the by the previous functional unit 1400e can communicate with specified loop depth.

In a further advantageous embodiment, a functional unit may be designed to determine information about a beginning and / or an end of at least one algorithmic loop (or several first-pass / last-transfer loops). For example, the functional unit may operate its own local computing unit 1410 depending on the information thus determined.

In a further advantageous embodiment, a functional unit may be designed to transmit previously determined information about a beginning and / or an end of at least one algorithmic loop to at least one further (target) functional unit. The (target) functional unit can, in turn, advantageously perform, for example, a conditional execution of computational tasks, depending on the received information. By way of example, according to one embodiment, an accumulation of data in a functional unit is considered, which is designed to execute the arithmetic operation "addition". At a loop start, a reset of the accumulator register occurs during the execution of the loop, an accumulation (that is, during the loop consecutive input data is continuously added and latched in the accumulator register) and at the end of the loop, especially only then , the accumulated data is forwarded as output data, for example to a subsequent functional unit.

In a further advantageous embodiment, a functional unit may be designed to perform an internal reconfiguration, advantageously according to likewise configurable specifications, based on the determined information about the beginning and / or the end of at least one algorithmic loop within or outside the same functional unit, such that, for example calculated function is changed. For example, a multiplication accumulator is reconfigured at the end of a determined loop into a pure multiplier, ie without further addition.

In a further embodiment it is provided that a plurality of functional units, e.g. two functional units, optionally separated, in particular independently of each other, can work and in this case, for example, several data words, for example two, with a first, each low bit width of 32 bits, for example, simultaneously process, or optionally, the plurality of functional units can be interconnected or cooperate in the sense in that they can jointly process a reduced number of data words, for example one, but with a higher bit width of, for example, 64 bits.

In a further advantageous embodiment it is provided that one or more configuration registers 1432 . 1432b . 1432c . 1432d ( 2A ) of the functional unit 1400 be mapped directly or indirectly into other registers of the arithmetic unit according to the invention 100 ( 1A ), for example, in higher-level peripheral registers within the flexible hardware extension 1500 and / or outside the flexible hardware extension 1500 , for example, in another peripheral component 125 or in an external component 200 , As a result, other components of the computing unit according to the invention 100 such as a calculation kernel 110a efficiently access the or the configuration register of the functional unit 1400.

In a further advantageous embodiment it can be provided that a method for the synthesis of a circuit layout for the production of the arithmetic unit according to the invention or individual functional units or other components thereof is used, as described in the German patent application DE 102015207323.8 is described. According to a preferred embodiment, this method comprises the following steps: primary circuit functions are placed on the circuit layout, secondary circuit functions are placed on the circuit layout, at least one first mask is generated such that the first mask maps the primary circuit functions and the secondary circuit functions concealed when a semiconductor substrate is patterned by the at least first mask according to the circuit layout, and ⊐⊐ placing the circuit functions such that at least one modified mask maps the primary circuit functions and the secondary circuit functions when the semiconductor substrate is interconnected by at least a second one according to the circuit layout Mask is structured.

An advantage of this embodiment lies in the opened possibility of implementing functions which are not required for the time being, in order then to implement them relatively inexpensively later by way of a Mask change and the changed function as a meaningful functional extension - such as in a microcontroller such as the present inventive computing unit 100 - to be able to use. A particular advantage here is that the costs for the implementation of the new function, which ideally requires only a mask change or the change only requires fewer masks, are comparatively low, since instead of a complete mask set only individual masks must be generated. Also, area overhead, as known from conventional fully programmable logic devices, such as FPGAs, is not needed in the present embodiment because both the selection and number of finely granular base elements within the designated semiconductor substrate can be constrained, and because there are no multiplexers. / Demultiplexer circuits are to be provided for a dynamic connection between these base elements, since the compounds within the designated semiconductor substrate are hardwired directly by means of a mask. Finally, functional enhancements according to the present embodiment may be much later and faster compared to conventional circuit layouts.

Over the considerable duration of relevant development projects, which can be up to the series production of the resulting circuit quite five years, depending on the project various requirements such as algorithm, the required computing power or throughput and latency, adjustments in late development phases, etc. According to the invention by the flexible Hardware extension, possibly in conjunction with the extension according to the method according to patent application DE 102015207323.8 to adapt the hardware circuit, implement. The substitution or supplementation of software - with the inherent disadvantage of a less efficient da rechnerleistungsschwächeren execution of the subsequent circuit functions - can be avoided in this way.

Below are further advantageous embodiment of the present invention, their benefits and preferred examples of application given.

The computing unit according to the invention 100 advantageously allows the efficient execution of computation-intensive and complex mathematical calculations (in particular with large (computational) depth, many computational operations), without requiring special accelerator hardware such as the use of multiple digital signal processors (DSP) or ASICs in addition to a conventional microcontroller or integrated in a microcontroller or the like would be required. Rather, the computation-intensive and complex mathematical calculations can advantageously be carried out by the functional units according to the invention 140 , ..., 1400 are executed, which are also flexibly interconnected, whereby a simple adaptation of the computing unit according to the invention 100 At various computationally intensive and complex mathematical calculations or algorithms is possible. For example, the arithmetic unit according to the invention 100 advantageously used for processing sensor values, for example in a control unit of a motor vehicle.

In a preferred embodiment, an exemplary data processing chain results as follows: A sensor signal (for example a speed sensor) forms input data for the arithmetic unit 100 , Calculations within a calculation kernel 110a the arithmetic unit 100 , further calculations by the functional units according to the invention 140 , re-calculations by the calculator 110a , Generation of a control signal as an output signal of the arithmetic unit 100 for downstream systems such as actuators or power amplifiers for controlling actuators.

In other embodiments, other orders of the aforementioned elements of an exemplary data processing chain may also result. For example, the functional units according to the invention can also be used instead of the calculation kernel 110a directly at the beginning of the data processing chain or at the very end of the data processing chain. In further embodiments, multiple input variables and / or multiple output variables are possible instead of a sensor signal.

In some embodiments, the output of an output at the end of such a data processing chain may be formed, for example, directly by a driven pin of the arithmetic logic unit ("output pin"), or by the output of a calculated numerical value. for example by means of a suitable communication interface. In particular, in some embodiments, the output of an output at the end of such a data processing chain may be formed, for example, by a pin directly driven by the flexible hardware circuit or a particular functional unit thereof.

In general, the application of the principle according to the invention, which is based on the provision of several functional units, makes it possible to relieve the computing cores 110a . 110b . 110c the arithmetic unit 100 , Particularly preferably, a pipeline of the calculation unit represented by the functional units is filled and operates (massively) in parallel, which makes a very fast calculation possible.

Because of its performance, the arithmetic unit according to the invention is particularly suitable for control devices for internal combustion engines, especially motor vehicles, where a plurality of input values such as sensor signals of complex processing is subjected to corresponding output signals for actuators such as magnetically or piezoelectrically actuated injectors for a fuel injection system To form internal combustion engine.

The arithmetic unit according to the invention can also be advantageously used in control units for driver assistance systems, for example for the evaluation of radar data for controlling driver assistance functions in which conventional control units typically have a plurality of digital signal processors in order to process the accumulating data volumes of the radar sensor.

The arithmetic unit according to the invention with the flexible hardware extension can also be advantageously used in control units in which complex control engineering models are calculated and / or in which complex digital signal processing takes place.

In addition to the previously described calculation options, which by individual functional units 1400 ( 2A ) or by a combination of individual functional units, in particular by their respective local calculation unit (s) 1420 can be realized, it is also possible to provide the following functionalities by one or more functional units according to the invention in combination, if in a corresponding expansion stage of the flexible hardware extension 1500 the required basic functionalities in the form of functional units including calculation units at all and additionally in the required number, configuration and connection with each other and allow a calculation with the required total computing power: calculation of (even high-dimensional) maps (with eg more than five dimensions), calculation of data-based Models, calculation of physical models, calculation of neural networks, solution of linear equation systems, formation of inverse matrices (in particular higher-order matrices), solution of non-linear equation systems, time-to-frequency conversion, for example by calculation of Fast Fourier Transformation (FFT), frequency-to-frequency -Time Conversion, for example, by calculating the inverse Fast Fourier Transform (iFFT), calculating various filter types such as FIR (Finite Impulse Response), IIR (Infinite Impulse Response), etc.

In a further advantageous embodiment it is provided that at least two functional units are coupled together in order to make it possible to increase the data width of data to be processed. 7 schematically shows a simplified block diagram in which two functional units 1400h . 1400i a computing unit according to an embodiment are shown.

In the presently described embodiment, the functional units 1400h . 1400i work independently in a first mode. In this case, for example, the functional unit 1400h processes its input data a40 of a first data width of, for example, 32 bits, whereby output data a42, for example also having a data width of 32 bits, are obtained. The functional unit 1400i processes its input data a41 (with a data width of, for example, also 32 bits) independently of the operation of the functional unit 1400h or independently of the processing of the input data a40, whereby output data a43, for example also with a data width of 32 bits, are obtained.

In a second mode, the functional units 1400h . 1400i However, also be coupled to each other, which is indicated by the block arrow a44. This allows an increase in the data width of the functional units 1400h . 1400i now jointly processed data, for example, now at 64 bits. Particularly preferably, the functional units involved can be designed to distribute operands and the computing steps to be performed on them among one another and / or between the functional units 1400h . 1400i or their respective local calculation units (not shown), cf. Arrow a44. Arrow a44 characterizes a separate data connection between the functional units 1400h . 1400i which enables coordination of the functional units 1400h, 1400i with respect to the common data processing.

In one embodiment, the functional units 1400h . 1400i be configured to dynamically (during operation of the functional units 1400h, 1400i) to switch between the first mode and the second mode. This can be done, for example, by appropriate configuration of the functional units 1400h . 1400i be achieved.

In a further advantageous embodiment, it is provided that the functional units synchronize with respect to the reception of their respective input data a40, a41 in order to be able to execute the common data processing correctly. This may include, for example, all of the functional units involved waiting to perform calculations until all have completed participating function units have valid input data, especially if an unsynchronized calculation start would result in a faulty calculation. Advantageously, the functional units also synchronize with one another during the execution of the calculations. If the output data resulting from the joint data processing exceeds the data width of a functional unit, for example 32 bits, it may be provided in some embodiments that the functional units 1400h . 1400i send the output data, for example, in a split form to one or more destination functional units.

In one embodiment, the partial output data may be sent by only a part of the functional units involved, for example by exactly one.

In an alternative embodiment, all participating functional units can send the corresponding part of the split partial output data.

In both of the aforementioned embodiments, the sending of the partial output data may, for example, take place in succession in time, in the latter embodiment also in parallel.

For example, according to one embodiment, both functional units 1400h, 1400i may be configured to perform additions ("ADD") or subtractions ("SUB") with a data width of 32 bits. In the coupled mode corresponding to the second mode, the functional units 1400h . 1400i thus perform an addition or subtraction with a data width of 64 bits. For example, the functional unit 1400h calculates the 32 high-order bits while the functional unit 1400i calculates the 32 least significant bits. Furthermore, it can be provided that a carry bit (English_ "carry bit") from the functional unit 1400i to the functional unit 1400a is transmitted, see block arrow a44.

In a further mode of operation, in particular two fixed-point numbers can execute functional units 1400h . 1400i be coupled in such a way that in the composite now a floating-point calculation is made possible. In an advantageous embodiment, in particular the calculations required for a floating-point calculation on the mantissa and the calculations on the exponent are carried out in a respectively different functional unit.

In further embodiments, it is also conceivable to intercouple more than two functional units in the manner described above by way of example, whereby the processed data width increases correspondingly further.

8A schematically shows a simplified data flow according to another embodiment, in which, for example, a total of four functional units 1400_A1, 1400_A2, 1400_B, 1400_C are shown. A possible data flow from the functional unit 1400_A1 to the functional unit 1400_B is indicated by the arrow a50. A possible data flow from the functional unit 1400_A2 to the functional unit 1400_B is indicated by the arrow a51. A possible data flow from the functional unit 1400_B to itself (enables recursion) is indicated by the arrow a52. A possible data flow from the functional unit 1400_B to the functional unit 1400_C is indicated by the arrow a53. Output data of the functional unit 1400_C are indicated by the arrow a54.

How out 8A can be seen, the function unit 1400_B input side data from the two different functional units 1400_A1, 1400A2 are supplied. For example, the functional unit 1400_B may be configured to accept data a50 from the first functional unit 1400_A1, while data a51 from the second functional unit 1400_A2, however, is not already accepted. Further, the functional unit 1400_B may be configured to accept data a51 from the second functional unit 1400_A2, while data a50 from the first functional unit 1400_A1, however, is not already adopted. Furthermore, the functional unit 1400_B may be configured to accept data about the recurrence branch a52 on its own, while data a50, a51 are not already accepted by the functional units 1400_A1, 1400_A2. Other constellations for controlling the data flow between the functional units are also conceivable according to further embodiments. In particular, in further embodiments, simultaneous reception of data or information from more than one functional unit 1400_A1, 1400_A2 or recursion of 1400_B to itself is also possible.

8B shows a comparable data flow including one in 8A pictured functional units connecting primary connection unit 150 in the present case, for example, is designed as a coupling network or at least has a coupling network.

Order the correct order of dates in the 8A . 8B In the case of preferred embodiments of the invention, one or more of the measures listed below can each be carried out individually or used in any combination with each other. The measures mentioned below, according to an advantageous embodiment, for example, by the local control device 1410 ( 2A ) of the functional unit.

measure 1 : "Busy Status" (German: "busy" state), indicating whether data is present at an input interface 1402 ( 2A ) can be received by a functional unit. Particularly preferably, such a "busy status" in one embodiment can be displayed for each input interface (alternatively only for some input interfaces) of a functional unit. For example, a primary connection unit 150 ( 1A ) be designed to transmit data or data packets only to such input interfaces of functional units or to send for which no "busy" state is signaled, which are therefore ready to receive data or data packets.

In a further embodiment it can be provided that the primary connection unit 150 is designed to at least temporarily store data or data packets that are provided for currently occupied input interfaces, possibly for a future transmission or transmission to the corresponding input interface. The "busy" state, in one embodiment, may be, for example, a local controller 1410 a functional unit determined or specified.

measure 2 : Specification of a packet type (English: "packet type identifier") for one or more data packets. In preferred embodiments, data packets may have a packet type to distinguish between data packets of different types. In particular, according to some embodiments, a differentiation of different packet types can take place, which distinguishes between data packets intended for processing and data packets containing configuration data. For example, data packets with configuration data may be used in some embodiments to alter a data flow between different functional units. For example, the packet type may be listed as a separate value in a data packet, for example in the control data CTRL (FIG. 2 B ), or the packet type may, according to further embodiments, be derivable from other values, for example from a source and / or destination address of a data packet or from any other information identifying a source and / or destination functional unit.

In a further embodiment it can be provided that a functional unit which outputs a data packet is designed to specify a corresponding packet type for the data packet. It is also conceivable in other variants of the invention to make the output of the packet type configurable, i. to determine by configuration whether a functional unit defines and indicates a packet type (and if so which), or not.

In a further embodiment it can be provided that the primary connection unit 150 which forwards data packets, is designed to specify a corresponding packet type for the data packet.

In further embodiments, it is conceivable that a functional unit specifies that it receives (only) data packets of a specific packet type via a specific input interface. For example, a primary connection unit 150 ( 1A ), which, for example, a switching network 152 may forward only those data packets to an input interface of a particular functional unit signaling that it is capable of accepting data packets of a particular data type.

measure 3 In one embodiment, a functional unit may be designed to monitor and / or check data received by it or data processed or processed by it. For example, if for a computational task two operands are expected as input values, one embodiment of the functional unit may be configured to monitor that both operands are received or used exactly once for each computational task, and not more often or less often. For example, it can be recognized that there is an error case when a first operand has already been received and is then received again. Rather, the first received operand would first have to be based on the calculation, the calculation would have to be carried out after the second operand is present, and then the functional unit could receive, for example, a further first operand and a further second operand from another functional unit. In a further advantageous embodiment, it can be provided that a functional unit does not perform a configuration or reconfiguration during a running calculation, but rather that the current calculation is first completed or that any necessary (further) operands which may be required are awaited as input data.

measure 4 : Rejection of data packets. In some embodiments, it can be provided that at least one functional unit is designed to reject a data packet that is associated with it on the input side, for example via an input interface or a direct data connection, is supplied. In a variant it can be provided that the rejection is possible at least temporarily.

Unless the primary connection unit 150 ( 1A ) detects that a data packet supplied to a functional unit has been rejected, the primary connection unit may prevent it from sending the same data packet to the action unit again, for example, until the functional unit has received at least one other data packet. In a preferred embodiment, the primary connection unit is configured to prioritize other pending transmission requests with respect to further data packets to the functional unit so that, for example, further data packets can be sent to the functional unit that has previously rejected a specific data packet.

In a further embodiment, the primary connection unit is designed to carry out a retransmission of the rejected data packet, for example periodically or at least when all data packets that have since been assigned to the functional unit have been transmitted to it, thus no further than the previously rejected data packet for the particular Function unit is present. In a further advantageous embodiment it can be provided that the primary connection unit monitors all write accesses to one or more, preferably all, input interfaces of functional units that are connected to it, whereby the above-mentioned steps can be carried out particularly efficiently and precisely. In one embodiment, it may be provided that data packets rejected at least temporarily are buffered or buffered within the primary connection unit, and / or within the functional unit transmitting them.

In a further advantageous embodiment, it can be provided that a functional unit is designed to indicate that you can now receive or receive a previously rejected data packet. A corresponding signaling can take place, for example, from the respective functional unit to the primary connection unit. As a result, advantageously repeated rejections of data packets can be avoided by the primary connection unit, after receiving the signaling, sending the previously rejected data packet again to the functional unit ready for reception.

measure 5 Prioritization of data packets, in particular as a function of a position of a respective functional unit in a data flow graph of a group of functional units or of a computer unit according to the invention.

In a particularly preferred embodiment, it is possible to prioritize data packets that are addressed to the same input interface of a particular functional unit. Such prioritization particularly preferably depends on a priority of all functional units and / or a priority of all output interfaces of functional units 1400_A1, 1400_A2, 1400_B ( 8A ), which at the same time access the same input interface of the particular functional unit 1400_B. According to a preferred embodiment, prioritization allows a distinction to be made between different functional units and / or between different output interfaces of functional units which all write to the same target functional unit (by sending data packets) but which eg at different locations in a data flow graph of a group of Functional units or the arithmetic unit according to the invention are arranged.

In a particularly preferred embodiment, it is possible to specify a prioritization for an individual input interface of a functional unit. It is also conceivable to specify a different prioritization for different input interfaces of the functional unit.

In a further advantageous embodiment, it is possible to predetermine such prioritization for all possible relations between a functional unit transmitting the data or data packets and a receiving functional unit or its input interface.

In a further embodiment, it is provided that the prioritization is statically fixed wired. Alternatively or additionally, a static but configurable prioritization can be provided. Alternatively or additionally, a dynamic prioritization can also be provided. The dynamic prioritization may, for example, be suitable for ensuring that all functional units can transmit an equal number of data packets, or a functional unit can receive an equal number of data packets from different functional units, and / or downgrade the priority if data packets do not or at that particular time not preferably be accepted and / or downgrade the priority when functional units are busy at the current time and / or downgrade the priority when data packet buffers in the primary connection unit are completely or partially filled, and / or downgrade the priority if internal buffers Function units are completely or partially filled, and / or increase the priority if data packets have an appropriate label, etc.

Advantageously, any existing dynamic prioritization is configurable in its behavior.

The prioritization is realized independently of the embodiment, preferably by means of a hardware circuit.

In further embodiments, it is possible to implement measures for implementing the aforementioned prioritization both within the primary connection unit 150 ( 8B ) as well as within at least one functional unit 1400_A1, 14000_A2.

In an advantageous embodiment, it is possible to provide a prioritization as a function of contents of the data packets to be transmitted, for example as a function of control flags or control information, which may be contained in data packets.

The above measures may be advantageously combined with some or all of the other aspects of the embodiments mentioned above. In particular, the above-mentioned measures can also be used with a coupling of a plurality of functional units, as described above by way of example with reference to FIG 7 has been described.

According to further embodiments, the aforementioned measures for data flow control or generally for influencing a data flow individually or in any combination with each other, for example, also be used for the transmission of data between one or more functional units according to the invention and at least one memory device such as the secondary memory device 160 ( 1F ).

By the measures mentioned above, blockages (English: deadlocks) can be advantageously avoided.

In further embodiments, it is also conceivable to design at least one functional unit such that it has one or more of the abovementioned measures for influencing a data flow with respect to itself and / or the primary connection unit 150 and / or with regard to at least one further functional unit and / or with respect to the secondary storage device 160 can perform.

In a further advantageous embodiment, it is provided that the arithmetic unit has at least one watchdog, which is designed to detect a blockage of at least one functional unit and / or at least one arithmetic and then optionally countermeasures such as an error response or a Restart the arithmetic unit or the respective functional unit to initiate. In one embodiment, a restart of the respective functional unit can, for example, directly and / or indirectly by restarting the entire flexible hardware extension 1500 and / or indirectly by restarting the entire arithmetic unit 100 respectively. The monitoring unit may for example be integrated into a functional unit, and / or be associated with other components of the computing unit according to the invention and / or be located external to the computing unit. For example, in another embodiment, the functionality of the monitoring unit may also be assigned to the primary connection unit.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• WO 2011/120823 A1 [0193]
• DE 102015207323 [0284, 0286]

Claims (25)

Computing unit (100; 100a; 100b; 100c; 100d; 100e; 100f; 100g), in particular microcontroller for a control unit (1004) for an internal combustion engine (1002) of a motor vehicle (1000), having at least one arithmetic core (110a, 110b, 110c) a primary memory device (120), and at least one main connection unit (130) for connecting the at least one arithmetic core (110a, 110b, 110c) to the primary memory device (120), wherein the arithmetic unit (100) comprises at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g), wherein at least a first functional unit (140a) of the at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a 1400b, 1400c, 1400e, 1400f, 1400g) is adapted to a) first data from at least one further functional unit (140, 140b) of the at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b ; 1400c; 1400e; 1400f; 1400g) to receive (302) and / or b) second data to at least one further functional unit (140, 140b) of the at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400F; 1400g) (304). Arithmetic unit (100) according to Claim 1 , wherein at least one primary connection unit (150) is provided, which is designed, at least temporarily, a, in particular direct, data connection (a1, a2) between the first functional unit (140a) and at least one further functional unit (140, 140b) of the at least two Functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g). Arithmetic unit (100) according to Claim 2 wherein the primary connection unit (150) comprises at least one of: a switching network (152a), a bus system (152b), at least one direct data connection (152c) between at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g). Arithmetic unit (100) according to one of the preceding claims, wherein a plurality of groups (G1, G2) of functional units (140c, 140d, 140e; 140f, 140g) are provided, and wherein each of the plurality of groups (G1, G2) comprises at least one primary connection unit ( 150_1, 150_2), which is designed to produce, at least temporarily, a, in particular direct, data connection between functional units (140c, 140d, 140e) of the relevant group (G1, G2). The computing unit (100) of any one of the preceding claims, wherein there is provided at least one secondary connection unit (155; 155a; 155c; 155d) adapted to: a) a data connection (a3; a4, a5; a9, a10) between the main connection unit (130) and at least one functional unit (140, 140a, 140b, 140c, 140d, 140e, 140f, 140g, 140h, 140i) and / or b) a data connection (a3, a4, a5, a6, a7, a8, a8 ' , a15) between the main connection unit (130) and at least one primary connection unit (150; 150a, 150b). Arithmetic unit (100) according to one of the preceding claims, wherein at least one secondary memory device (160) is provided, wherein between the at least one secondary memory device (160) and at least one functional unit (140i, 140k) a direct data connection (a13, a12) exists. Arithmetic unit (100) according to Claim 6 wherein the at least one secondary memory device (160) comprises a plurality of memory banks (162a, 162b, 162c, ..., 162n), wherein in particular the at least one secondary memory device (160) is adapted to provide parallel data access to at least two of the plurality of memory banks (162a, 162b, 162c, ..., 162n). Arithmetic unit (100) according to one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g) is designed as a hardware circuit, in particular completely as a hardware circuit is. The computing unit (100) of any one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g) comprises at least one of: a microcontroller , a software executing kernel, a digital signal processor, a programmable logic circuit, an application specific integrated circuit, a pre-fabricated by a gate and / or transistor array but not yet application-specific wired integrated circuit. The arithmetic unit (100) of any of the preceding claims, wherein at least one of the functional units (140, 140a, 140b) comprises at least one of: adder, multiplier, divider, shift register, barrel shifter, comparator, multiplication accumulator, arithmetic logic unit, Memory unit, memory access unit, register, multiplexer, demultiplexer, interface, communication interface, unit for calculating exponential functions, unit for calculating trigonometric functions, unit for calculating logarithmic Functions, unit for calculating root functions, lookup table (s). Arithmetic unit (100) according to one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b) has at least one coarse granular hardware element (e1, e2; 1420) or is designed as a coarse-granular hardware element. Arithmetic unit (100) according to any one of the preceding claims, wherein the arithmetic unit (100) is adapted to change a configuration of at least one functional unit (140, 140a, 140b, ..., 140p) and / or a state or the configuration at least a functional unit (140, 140a, 140b, ..., 140p) to check. The arithmetic unit (100) according to one of the preceding claims, wherein the arithmetic unit (100) is adapted to modify a configuration of the primary connection unit (150) and / or at least one secondary connection unit (150a, 150b) and / or a state or the Configuration of at least the primary connection unit (150) and / or at least one secondary connection unit (150a, 150b) to check. Arithmetic unit (100) according to one of the preceding claims, wherein at least one of the functional units (140j, 140k, 140l) has at least one, in particular direct, data connection (a16) to an interrupt request distributor device (170) of the arithmetic unit (100), and / or at least one, in particular indirectly via a preliminary stage (170a) extending, data connection (a16, a18) to an interrupt request distribution means (170) of the arithmetic unit (100). Arithmetic unit (100) according to one of the preceding claims, wherein at least one of the functional units (140l, 140m) has at least one, in particular direct, data connection (a17) to an input interface (180) and / or output interface (180) of the arithmetic unit (100). Arithmetic unit (100) according to one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b) is adapted to change its own configuration and / or a configuration of at least one further functional unit (140c). The arithmetic unit (100) of any one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b) is adapted to alter a configuration of the primary connection unit (150) and / or at least one secondary connection unit (150a, 150b). or to check a state or configuration of at least the primary connection unit (150) and / or at least one secondary connection unit (150a, 150b). Arithmetic unit (100) according to one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b) is adapted to receive data from the primary memory device (120) and / or from the secondary memory device (160) and / or from other peripheral components (125) to read and / or write in these. The arithmetic unit (100) of any of the preceding claims, wherein at least one of the functional units (140, 140a, 140b; 1400) has an input interface (1402) for receiving the first data and / or an output interface (1404) for outputting the second data. The arithmetic unit (100) of any one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b; 1400) includes local control means (1410) for controlling operation of the functional unit. The computing unit (100) of any one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b; 1400) comprises a local computing unit (1420). The computing unit (100) of any one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b; 1400) includes a local configuration memory (1430), the local configuration memory (1430) having in particular a plurality of configuration registers (1432a, 1432b, 1432c , 1432d). The arithmetic unit (100) of any one of the preceding claims, wherein at least one of the functional units (140, 140a, 140b; 1400) comprises a local function memory (1440), the local functional memory (1440) comprising in particular at least one function register (1442a). Control unit (1004), in particular for an internal combustion engine (1002) of a motor vehicle (1000), having at least one computing unit (100; 100a; 100b; 100c; 100d; 100e; 100f; 100g) according to one of the preceding claims. Method for operating a computing unit (100; 100a; 100b; 100c; 100d; 100e; 100f; 100g), in particular a microcontroller for a control unit (1004) for an internal combustion engine (1002) of a motor vehicle (1000), having at least one arithmetic core (110a , 110b, 110c), a primary storage device (120), and at least one main connection unit (130) for connecting the at least one arithmetic core (110a, 110b, 110c) with the primary memory device (120), wherein the arithmetic unit (100) has at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f 1400g), wherein at least a first functional unit (140a) of the at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g) a) first data of at least one another functional unit (140, 140b) of the at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g) receives (302) and / or b) second data at least another functional unit (140, 140b) of the at least two functional units (140, 140a, 140b, .., 140m; 1400; 1400a; 1400b; 1400c; 1400e; 1400f; 1400g) transmits (304).

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