DE102015223589A1 - Switching converter with cyclic frequency change - Google Patents

Abstract

The invention relates to a driver circuit for operating a load (3), preferably at least one luminous means, in particular an LED, comprising: a first clocked converter (1) having at least one switch (S3) clocked by a control unit (4), wherein the first converter (1) generates a regulated DC voltage (UBus) at its output; at least one supplied from the regulated DC voltage second clocked converter (2) starting from the output of the load (3) can be supplied; wherein the control unit (4) is adapted to cyclically change the timing of the switch (S3) of the first converter (1) such that - even if the input voltage of the first converter (1) and the load (3) are constant - a Residual ripple in the regulated DC voltage (UBus) is present; and wherein this residual ripple of the regulated DC voltage (UBus) can be reduced by means of the second converter (2). The invention further relates to an operating device for lighting means and a method for operating lighting means by means of the driver circuit.

Description

The invention relates to a driver circuit for operating a load, preferably at least one luminous means, in particular an LED. The invention also relates to a corresponding operating device and a method for operating the load.

In particular, the invention relates to a multi-stage driver circuit consisting of successively switched clocked converters, wherein the clocking of a first clocked converter is cyclically changed to produce a varying clocking in a subsequent second switching converter.

In particular, the present invention relates to the operation of bulbs, such as LED or OLED as a load.

Basically, it is already known to provide an LED track, which may have one or more LEDs connected in series, starting from an operating device by means of a constant current source with electrical power. It is also known that to produce this electrical power, the operating device comprises a resonant switching converter, for example in the form of an LLC converter.

The problem is that a regulated DC voltage, for example, a bus voltage of a first clocked converter, especially at low loads on the driver circuit of the operating device is very constant. Therefore, the operating frequency of the downstream second switching converter is very constant. In particular, this constant operating frequency of the downstream second transducer is problematic in terms of electromagnetic compatibility, short EMC. The constant operating frequency of a half-bridge circuit of the second switching converter and its harmonics of this constant operating frequency optionally prevent the operating device from being operated within permissible standards for LED operation.

For example, from the WO 2014/100844 A2 known to interfere with the regulation resulting operating frequency of a resonance switching converter targeted. In this case, a clock change is applied by a so-called sweep mode in the LLC resonance converter.

To improve the EMC characteristics of such driver circuits, this sweep mode of the half-bridge circuit of the resonant switching converter could be used. However, operating the resonant switching converter in sweep mode results in audible noise or visible flicker, both of which are undesirable.

It is therefore an object of the present invention to provide a driver circuit whose EMC compatibility is improved without causing an impairment, such as an audible noise or a visible flickering of the connected load by the driver circuit.

This object is achieved with the features described in the independent claims. Preferred embodiments are described in the respective dependent claims.

In a first aspect of the invention, a driver circuit is provided for operating a load, preferably at least one luminous means, in particular an LED. The driver circuit has a first clocked converter with at least one switch clocked by a control unit, wherein the first converter generates a regulated DC voltage at its output. The driver circuit furthermore has at least one second clocked converter, which is supplied from the regulated DC voltage, the load being able to be supplied from the output thereof. The control unit is designed to cyclically change the timing of the switch of the first converter such that even if the input voltage of the first converter and the load are constant there is a residual ripple in the regulated DC voltage and this ripple of the regulated DC voltage can be reduced by means of the second converter is.

A central idea of the invention is therefore a deliberate cyclical change in the timing, that is, for example, the operating frequency or the turn-on time of the first switching converter. This cyclic change in the timing of the switch of the first converter is designed such that it must be reduced in a first switching converter following the converter of forced dimensions, ideally even regulated. In this way, the load will be supplied with constant electrical parameters, but it is achieved by the artificially induced ripple that the EMC characteristic of the driver circuit is significantly improved.

In order to achieve this consciously brought about change in the timing of the switch of the second switching converter, therefore, the timing of the switch of the first converter cyclically - ie in the context of a periodically recurring change - varies. Due to this cyclical variation, the regulated DC voltage is also cyclically changed by means of residual waves. As a result of this ripple The second switching converter must vary its timing to compensate for the ripple in the regulated DC voltage.

As a ripple, English ripple, hereinafter a ripple current or a ripple voltage is understood, which arises by rectifying an AC voltage. If a DC voltage is to be generated from a sinusoidal AC voltage by rectification, a mixed voltage of DC and superimposed AC voltage always arises. The fact that, despite smoothing, an AC component still remains, is called residual ripple. The residual ripple is inventively deliberately provoked to improve the EMC characteristics of a subsequent converter stage.

The conscious ripple therefore also arises when the load is constant and when the input voltage is constant, so that the characteristics of the first converter are deliberately degraded.

The input voltage is preferably an AC mains voltage, for example 230 V, or an already rectified voltage. The regulated DC voltage generated by means of the first switching converter is, for example, the bus voltage in a lighting system, also referred to as an intermediate voltage in the driver circuit.

The second clocked switching converter is connected downstream of the first clocked switching converter. By cyclically changing the timing, that is, deliberately applying changes in the frequency and / or the turn-on time of the switch of the first converter, the regulated DC voltage is modulated. This provided with a ripple regulated DC voltage is in turn an input voltage of the second clocked converter.

In order to compensate for the residual ripple by means of the second transducer, its timing must be varied, thereby causing an improved EMC characteristic.

In a preferred embodiment, the residual ripple can be reduced by cyclically changing the timing of a switch of the second converter. In this case, the operating frequency or at least the turn-on time of the switch of the second converter will be varied. Thus, in particular harmonic oscillations of the switching frequency can be compensated out by a forced cyclic changing of the frequency of the second transducer and the electromagnetic compatibility of the driver circuit is enormously improved.

In a preferred embodiment, the second converter is a resonant converter, preferably an LLC resonant converter, which is operated by means of a half-bridge circuit. The half-bridge circuit can be operated with two switches, to which a second switching signal can be applied, the second switching signal having a first switching signal component and a switching signal component complementary thereto. Thus, the forced cyclic variation of the timing of the switches of the second switching converter, due to the complementary nature of the second switching signal, will result in complete cancellation or at least significant reduction of the harmonic power amplitude of the switching frequency of the second transducer, thereby eliminating the EMC characteristic with no audible noise or visible flicker is improved.

Due to the residual ripple in the regulated DC voltage, a change in the half-bridge clocking is achieved, resulting in the improved EMC compatibility. Independently of this, since the LLC resonator compensates for this residual ripple of the regulated DC voltage by changing the half-bridge timing, a very constant output voltage for operating the lighting means is obtained.

In a preferred embodiment, the first converter has a control unit in order to clock the first switch of the first converter by means of a first switching signal. To the control unit to a control signal of the control unit for cyclically changing the timing of the first switch of the first converter is applied. In this way, the cyclic changing of the timing can be controlled. In this way, both the frequency deviation of the residual ripple and the amplitude level of the residual waves can be adjusted. This adjustment of the change in the timing is achieved that the ripple is safely reduced and ideally completely regulated out, in any case, a constant load voltage at the output of the driver circuit can be tapped.

In a preferred embodiment, a set value for the control unit is applied by the control signal to a cyclically changing additional value in order to effect the cyclic change in the timing of the first switch of the first converter. The Applying is done by adding and / or subtracting in a cyclic manner. The desired value is, for example, the input voltage or a value proportional thereto.

Alternatively or additionally, an actual variable for the control unit is acted upon by the control signal a cyclically changing additional value in order to effect the cyclical change of the timing of the first switch of the first converter. The loading is done by adding and / or subtracting in a cyclic manner. The actual variable is, for example, the output voltage of the first converter or a value proportional thereto.

By cyclically applying additional values to the desired value or the actual variable, the result of the control unit is intentionally falsified, whereby the timing of the first switching signal is changed cyclically.

Alternatively or additionally, the Anschaltzeitwert the first switching signal by the control signal, a cyclically changing additional time value is applied to cause the cyclic change in the timing of the first switch of the first converter.

Preferably, the cyclic timing change is applied only when the load has a load value below a predefined threshold. Load value is in particular an ohmic resistance value, with which the load can be characterized in the context of an equivalent circuit diagram.

In particular, low loads are to be described by the driver circuit proposed here, since, in particular at low loads, the first converter stage supplies a highly accurate regulated DC voltage, which causes the disadvantageous EMC effects. The inventive generated artificial ripple this accuracy is reduced.

In a preferred embodiment, the load is at least one LED. The load value of the LED is defined by a dimming value specification, preferably a dimming value of less than 50 percent, more preferably less than 25 percent of the total light output of the at least one LED. This Dimmwertvorgabe for adjusting the light source is supplied in particular to the control unit. Thus, the control signal is able to be activated in response to a Dimmwertvorgabe.

Alternatively or additionally, the load is at least one LED and the load value is determined by a load current measurement and / or a load voltage measurement.

In a preferred embodiment, the load is at least one LED and the load value is determined by the duration of the turn-on time of the switch of the first converter. In this way, the low loads can be determined very easily and an electromagnetic compatibility can be increased.

In a preferred embodiment, a variable clocking of the second switching signal of the second converter is adjustable by the ripple of the regulated DC voltage.

Preferably, at least one third clocked converter is connected downstream of the second converter, wherein the third converter operates the load by means of a clocking of a switch of the third converter.

The first converter is preferably a PFC converter or a buck converter or a fly-back converter. All these clocked switching converters can now selectively vary their operating frequency cyclically. In this way, a sufficient residual ripple in the regulated DC voltage is generated, this residual ripple can be easily reduced by a subsequent switching converter to obtain a constant load capacity.

For example, if the first switching converter is a PFC converter, then a control unit is provided to convert an input voltage into a regulated DC voltage. For this purpose, a control loop is provided in the first converter, which compares an actual size and a desired size with one another. In order to enable the cyclical change of the clocking of the first converter, either the actual variable or the set value are changed by applying cyclic additional values. This results in a control algorithm that has the previous effects.

The control unit thus serves to calculate a suitable turn-on time for a switch based on an actual value. However, before a switch signal for the switch in the first switching converter is generated on the basis of the control unit determined by the control period, the switch-on is, however, supplemented by an additional value, so either extended or shortened. This additional value changes cyclically.

In a preferred embodiment, the third converter is a down converter, also referred to as buck converter, buck regulator, step-down converter or buck converter. In such a buck converter, the output voltage is always smaller than the amount of the input voltage.

According to a second aspect of the invention, an operating device for a luminous means is provided which has a driver circuit of the type described above.

According to a third aspect of the invention, a method is provided for operating at least one luminous means by means of a driver circuit according to the previously described type. The method comprises the steps of: converting an input voltage into a regulated DC voltage by means of a first clocked converter using a switch clocked by a control unit of the converter; Converting the regulated DC voltage into a load voltage for operating the load by means of at least one second clocked converter using a switch of the second converter clocked by the control unit; Cyclically changing the timing of the switch of the first converter, that even if the input voltage of the converter and the load are constant, there is a ripple in the regulated DC voltage; and reducing this residual ripple of the regulated DC voltage by means of the second converter.

The residual ripple is preferably provided to change the operating frequency of the second converter.

Preferably, a desired value and / or an actual variable and / or a turn-on time of the switching signal of the first converter is cyclically changed by means of the control signal.

Preferably, the cyclic frequency change is only applied if the luminous means has a load value below a predefined threshold value.

The invention or further embodiments and advantages of the invention will be explained in more detail with reference to figures, the figures only describe embodiments of the invention. Identical components in the figures are given the same reference numerals. The figures are not to be considered as true to scale, it can be exaggerated large or exaggerated simplified individual elements of the figures.

Show it:

1 a first embodiment of a driver circuit according to the invention shown as a block diagram;

2 a second embodiment of a driver circuit according to the invention shown as a block diagram;

3 an embodiment of a first converter for a driver circuit according to the invention;

4a Fig. 5 shows exemplary waveforms for cyclically varying the frequency according to the invention;

5 a first embodiment of a second converter for a driver circuit according to the invention;

6 A second embodiment of a second converter for a driver circuit according to the invention;

7 an exemplary half-bridge circuit for a second converter of a driver circuit according to the invention;

8th a combination of resonant circuit and transformer for a second converter of a driver circuit according to the invention;

9 an embodiment of a third converter for a driver circuit according to the invention; and

10 a process flow diagram for a method according to the invention.

In 1 a first embodiment of a driver circuit according to the invention is shown. Here is a first converter 1 connected to an input voltage L, N. The input voltage is shown here as mains voltage, wherein a live conductor L of the mains voltage and a neutral conductor N of the mains voltage are shown symbolically. At the output of the first converter stage 1 is a regulated DC voltage U _BUS based on a ground potential GND taped. According to the driving circuit of the invention, the first converter 1 a second converter 2 downstream. In this case, the regulated input voltage U _{BUS is converted} into a load voltage U _LAST or a load current I _LAST . At the output of the second converter 2 is a burden 3 connectable, according to 1 exemplified as an ohmic resistance.

As a burden 3 In particular, a light source, for example at least one LED, is provided. Weight 3 can symbolize an LED track from a plurality of LEDs connected in series. Moreover, it is also possible to connect several LEDs in parallel as the load 3 to watch.

According to the invention, a conversion of the input voltage L, N into a regulated direct voltage U _BUS by means of the first converter is now performed 1 so obtained that in the first converter stage 1 generated timing is changed by applying a first switching signal Sig to the switch S3 in a cyclical manner. This cyclic change of the timing causes a ripple, which in the subsequent second converter stage 2 is reduced to the load 3 nevertheless to provide a constant voltage U _LAST or a constant current I _LAST or a constant power PLAST. By ripple is meant the cyclic change in amplitude.

The cyclic changing of the timing, such as the operating frequency or the Clock ratio of the switching signal Sig by changing the on time t _on or the off time t _off , the first converter stage 1 leads to a cyclical change of the clocking in the downstream second converter stage 2 , whereby in particular harmonic oscillations of the switching frequency in the second converter 2 be compensated. This improves the EMC characteristic of the driver circuit and allows the driver circuit to have no annoying audible noise and no annoying flicker of the lamps as a load 3 generated.

Changing the timing of the first converter stage 1 is achieved in particular by a control signal PFC, which is the first converter 1 is supplied. This control signal PFC is, for example, by a control unit 4 generated. The control signal PFC has a direct influence on a control loop within the first converter 1 , In particular, an actual variable or a desired variable within the control loop of the converter stage 1 varies by means of cyclic manipulation, so that a ripple on the regulated DC voltage U _{BUS is} generated. This residual ripple will in turn cause the second converter stage 2 has a changed timing.

In 2 a second embodiment of a driver circuit according to the invention is shown. Below, only the differences between the driver circuit according to 1 and the driver circuit according to 2 described. According to 2 is a third converter stage 5 shown between the second converter stage 2 and the load 3 is arranged. The third converter stage 5 is preferably a buck converter.

As the first converter 1 For example, a power factor correction circuit, PFC, is provided. Generally, however, any type of clocked converter as a switching converter 1 be considered. Thus, it is also possible Tiefsetzsteller or boost converter, especially in the form of fly-back converters or buck converters as the first converter 1 provided.

It is provided that the timing of the switching signal Sig of the first converter 1 is cyclically varied to deliberately generate a ripple on the regulated DC voltage U _bus , which causes the second converter 2 his timing also changes. By cyclically changing the timing of the first switching signal Sig, the timing of the second switching signal HS, LS of the second converter changes 2 cyclically, in particular the compensation of disturbing influences, in particular harmonic oscillations etc. is made possible.

In 3 is an embodiment of a first converter stage 1 for a driver circuit according to the invention shown in detail. According to 3 is a power factor correction circuit, English Power Factor Correction, short PFC, as the first converter 1 intended. It is to the converter 1 a mains voltage L, N applied. This mains voltage L, N is by means of a rectifier unit 24 rectified. Then follows an active PFC circuit consisting of a PFC coil L4, a PFC diode D5 and a PFC switch S3. Finally, a smoothing capacitor C _{BUS is connected in} parallel. At the output of the first converter 1 is a rectified voltage U _{BUS can be} tapped.

In 3 is a so-called boost PFC converter 1 shown. The boost PFC converter 1 has a PFC coil L4. This L4 coil has a first connection to the rectifier 24 connected and connected with a second terminal to a first terminal of the PFC switch S4 and to the anode D5. A second terminal of the switch S3 is connected to the ground potential GND. Thus, the switch S3 can either short the second terminal of the coil L4 to ground GND or turn on the diode D5. The cathode of the diode D5 is connected to the output U _BUS .

According to the invention it is now provided that the switch S4 by means of a control unit 11 is switched. This control unit has a first input to connect to a desired size. The desired size can be tapped, for example, from the first terminal of the coil L4 and becomes the control unit 11 provided directly or via a voltage divider.

The control unit 11 has a second port to connect to an actual size. This actual size is preferably tapped off from the cathode of the diode D5 and directly to the control unit 11 or via a voltage divider 11 provided.

A first switching signal Sig is from the control unit 11 generated to control the switch S4 based on the values of the target size and the actual size. The switching signal Sig is a pulse width modulated signal whose timing is cyclically varied according to the invention by a control signal PFC. In this way, a regulated DC voltage U _{BUS is} obtained, which has a deliberate residual ripple. Especially at low loads 3 For example, a dimming value of less than 50% of the total light output of a lamp, the driver circuit is equipped with improved EMC compatibility.

The control signal PFC is from a control unit 4 provided. The control signal PFC is in particular a cyclic manipulation in the frame an additional value that is either added to the actual size or the target size or subtracted. Thus, the result of the control unit 11 deliberately manipulated to obtain a cyclic timing modulation. Alternatively, the _turn- on time t _{on_PFC of} the switch S4 can be subjected to cyclic variations by means of the control signal PFC. Such a cyclical change of the on-time t _{on_PFC} is for example in the 4c shown.

The output voltage of the PFC converter 1 is a _bus voltage U _bus in the form of a DC voltage or a substantially constant voltage. Starting from a 230 volt AC mains voltage L, N, the _bus voltage U _{bus can be,} for example, 400 volts. Due to the mains voltage frequency of 50 Hz in Europe, that of the PFC circuit 1 provided _bus voltage V _bus usually a residual ripple with twice the mains frequency, in Europe 100 Hz, 120 Hz in USA.

At the converter 1 it may be, for example, a boost converter, a flyback converter or an isolated flyback converter. The _bus voltage V _bus is subsequently a second converter 2 fed. Furthermore, a control unit 11 provided, which may be implemented in particular as an integrated circuit, such as ASIC or microprocessor or hybrid thereof.

The control unit 11 communicates for example via a galvanic decoupling with an interface. This interface has ports for interfacing an external analog or digital bus (not shown), which may be configured according to, for example, the DALI industry standard. Thereby, data according to this protocol can be transmitted bi-directionally or unidirectionally, for example a dimming preset or a color temperature. Alternatively or additionally, however, unidirectional or bidirectional signals can also be transmitted at this interface in accordance with other standards.

In the 4a is first a first switching signal Sig of the first converter 1 shown. This switching signal Sig is a PWM signal with an on time t _{on_PFC} , which is controlled by the control unit 11 is determined.

In 4b is a time course of a first half-wave of the input signal L compared to the cathode _{current signal} I _{D5_Kathode} the diode D5 shown. The graph shows the current waveform I _L4 through the coil L4 when the PFC is operating in a critical conduction mode, CRM, where the current through the coil at each switching cycle of the switch S3 is once zero amps, as much as possible to ensure low-loss switching. The _turn- on time t _{on_PFC of} the switching signal is the time between a zero point of the current I _L4 and a peak value of the current I _L4 . The turn-off time t _{off_PFC} is the time between a peak value of the current I _L4 and a zero point of the current I _L4 . The sum of t _{on_PFC} and t _{off_PFC} is the time duration T of the switching signal.

Alternative and in 4b not shown, the control unit 11 be configured to set a non-contiguous mode, CCM, or a discontinuous current conduction mode, DCM.

In 4c is now shown a course of a time value of the on time t _{on_PFC} over time. The Y-axis corresponds to the duration of the turn-on time of the switch S3.

Based on a standard value t _{on_norm} (shown in dashed lines), the value for the _turn- on time t _{on_PFC is} incremented and decremented step by step. The time interval between the individual stages for incrementing or decrementing is determined by the clock frequency of the converter 1 certainly. The incrementing and decrementing is repeated cyclically, so that the mean value of the _{turn-on time} t _{on_PFC} corresponds to the standard value t _{on_norm} . The incrementing and / or decrementing is done by the control unit 11 performed and the control unit provided as a control signal PFC.

The height of all levels is called sweep amplitude. The residual ripple of the regulated DC voltage can be _adjusted by the "sweep amplitude" or by the length of the sweep period T _SWEEP or the frequency of the cycle T ^sweep-1 , so that it is possible to ensure that the residual ripple from the downstream converter 2 can be compensated.

By changing the switching frequency according to the invention - the frequency deviation, for example in the range of a few kilohertz, an EMC reduction in the sense of the EMC regulations can be achieved.

The previously mentioned 100 Hertz residual ripple at the output of the PFC converter 1 is through the second converter 2 reduced. In particular, the amplitude of the residual waves is reduced, ideally the residual ripple is completely out-regulated.

Thus, according to the present invention, the artificial fixed frequency sweep can be selectively switchable provided that a low light power is required at which the fluctuation in the Output voltage of the PFC converter 1 not by itself to changing the operating frequency of the second converter 2 leads.

It can thus be provided that this sweep operation adaptively, d. H. For example, it can also be carried out selectively depending on the current dimming value of the LED route. In particular, it can only be executed when the light output is below a predetermined threshold.

Now, if according to the invention, the PFC converter 1 provides an output voltage with a ripple at a frequency of 100 hertz, the operating frequency of the second converter 2 specifically applied to a cyclically altered clocking in the range of a few kilohertz. In addition, the frequency deviation is relatively low, so that the fluctuation lying in the area of the cyclic change in timing is invisible to humans.

For example, if the time average of the operating frequency of the first converter 1 is in a range between 80 kHz and 100 kHz, the frequency deviation, ie the symmetrical frequency sweep, is within a range of a few kilohertz.

In 5 is a first embodiment of a second converter stage 2 for a driver circuit of the invention. The second converter stage 2 according to 5 includes four functional units. First is a half-bridge circuit 21 provided to which a regulated input voltage U _BUS with artificially generated ripple can be applied. The half-bridge circuit 21 has two series-connected switches S1, S2, which are switched by means of complementarily switched switching signal components HS, LS. At the output of the half-bridge circuit 21 Thus, again an AC signal is obtained, with a DC offset of the height Ubus / 2. The signal toggles between Ubus and Gnd.

Thus, the output voltage of the PFC converter 1 a half-bridge circuit acting as an inverter 21 be supplied. The control signals HS, LS for the timing of the switches S1, S2 can also by the control unit 11 be generated.

Between the switches S1, S2 of the half-bridge 21 closes the resonant circuit 22 at. The resonant circuit 22 can be configured arbitrarily and is in the case according to 5 is formed as a so-called LLC resonant circuit. In this case, a first capacitor C1 is connected in series with a first coil L1 and a second coil L2. The second coil L2 is according to 5 at the same time the primary winding of a transformer T of a downstream transformer stage 23 , This transformer 23 serves the load 3 to be galvanically isolated from the regulated DC voltage U _BUS . The secondary winding L3 of the transformer stage 23 is in turn with a rectifier circuit 24 connected. According to 5 there is the rectifier circuit 24 of four diodes D1, D2, D3 and D4 connected as a Graetz circuit to form a full-bridge rectifier. At the output of the rectifier 24 is a constant regulated voltage U _LAST or a constant regulated current I _LAST tapable.

If now the regulated DC voltage U _BUS imposes a residual ripple by means of the control signal PFC, then the second converter stage 2 deliberately forced to vary their operating frequency by applying the appropriate switching signal components HS, LS also to improve the EMC characteristics.

In 6 is a second embodiment of a second converter 2 for a driver circuit according to the invention. Below are just the differences between the converter 2 according to 5 and the second converter 2 according to 6 explained in more detail. In contrast to 5 is the rectifier 24 alternatively configured by the secondary winding L3 of the transformer stage 23 has a center tap and two diodes D1 and D2.

In 7 is an example of an improved half-bridge circuit 21 for a second converter 2 a driver circuit according to the invention shown. The half-bridge circuit 21 has two field effect transistors Q1, Q2 as switches S1, S2 connected in series. A switching signal component HS is connected to the gate terminal of the field effect transistor Q1. A complementary to the switching signal component HS second switching signal component LS is connected to the gate terminal of the field effect transistor Q2. In order to reduce switching capacitances, compensation capacitors C _Q are connected between the respective drain and source terminals of the field-effect transistors Q1, Q2. Such a half-bridge circuit 21 allows the flanks of the half-bridge mid-point voltage to flatten, resulting in an improvement in the EMI spectrum.

In 8th is an alternative combination of resonant circuit 22 and transformer 23 shown. Unlike the in 5 respectively. 6 illustrated variants here is the primary coil L2 'of the transformer 23 separated from the second coil L2 of the resonant circuit 22 shown. This allows for improved tuning of the resonant circuit 22 by means of the coils L1 and L2. The transformer 23 according to 8th is preferably formed as an ideal transformer T.

Preferably, the following structure is used. The coils L1 and L2 are integrated in the transformer T, L1 is the leakage inductance from the transformer T and L2 is the magnetizing inductance. In this way, only one component is used, in which L1 and L2 are formed together. Alternatively and also preferably, the coil L1 is connected as an additional external inductance in series with the primary winding of the transformer T, so that two components are used, the inductance L1 and the primary winding L2 'of the transformer T.

In 9 is an exemplary third converter 5 a driver circuit according to the invention according to the 2 shown. At the entrance of the third converter stage 5 is an output signal of the second converter stage 2 connected.

By means of a buck converter consisting of a buck switch S4, a buck inductor L5 and a buck diode D6 can now be the input voltage of the third converter 5 be converted into the load voltage U _load or the load current I _load . A charging capacitor C _BUCK makes it possible to prevent further residual ripples, so that a very constant output voltage U _LAST or a high-constant current HAST can be set.

In 10 is a process flow diagram for a method according to the invention 100 shown. In step 101 the conversion of an input voltage L, N takes place in a regulated DC voltage U _BUS by means of a first clocked converter 1 , According to the step 102 the regulated DC voltage U _{BUS is converted} into a load voltage U _LAST by means of at least one second clocked converter 2 , In step 103 is achieved by cyclically changing the timing of the first switch S3 of the first converter 1 get a ripple on the regulated DC voltage U _bus . In the following step 104 the residual ripple is through the second converter 2 reduced.

All described, shown and / or claimed features can be combined with each other.

LIST OF REFERENCE NUMBERS

1

First converter, boost PFC converter

11

control unit

2

Second converter, LLC converter

21

half bridge

22

resonant circuit

23

transformer

24

rectifier

3

load

4

control unit

5

Third transducer, buck converter

BUCK

Third switching signal

C1, Cr

resonant capacitor

C _Buck

Charging capacitor Buck converter

C _out

Charging capacitor rectifier

C _PFC

Charging capacitor PFC converter

C _Q

compensation capacitor

D1-D4

Rectifier diodes

D5

PFC diode

D6

Buck diode

Gnd

Ground potential, Ground

HS

First switching signal component of the half-bridge

I _load

load current

L

Live conductor of the mains voltage

L1, Lr

First resonance coil

L2, Lm

Second resonance coil

L2 '

First transformer winding

L3, L3a

Second transformer winding

L3b

Third transformer winding

L4

PFC coil

L5

Buck coil

LS

Second switching signal component of the half-bridge

N

Neutral conductor of the mains voltage

PFC

Control signal of the first converter

S1, Q1

First switch of the half bridge

S2, Q2

Second switch of the half bridge

S3

Switch of the first converter

S4

Switch of the third converter

Sig

First switching signal

t _{on_add}

Additional time value

t _{on_PFC}

On-time PFC switch

T _sweep

Period of cyclical change

U _bus

bus voltage

U _load

load voltage

U _sweep

Sweep amplitude

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• WO 2014/100844 A2 [0006]

Claims (22)

Driver circuit for operating a load ( 3 ), preferably at least one luminous means, in particular an LED, comprising: a first clocked converter ( 1 ) with at least one of a control unit ( 4 ) clocked switch (S3), wherein the first converter ( 1 ) generates at its output a regulated DC voltage (U _bus ); at least one second clocked converter powered by the regulated DC voltage ( 2 ) from whose output the load ( 3 ) is available; the control unit ( 4 ) is adapted to the timing of the switch (S3) of the first converter ( 1 ) so cyclically that - even if the input voltage of the first converter ( 1 ) and the load ( 3 ) are constant - there is a residual ripple in the regulated DC voltage (U _bus ); and wherein this residual ripple of the regulated DC voltage (U _bus ) by means of the second converter ( 2 ) is reducible. Driver circuit according to claim 1, wherein the residual ripple by cyclically changing the timing of a switch (S1, S2) of the second converter ( 2 ) is reducible. Driver circuit according to one of the preceding claims, wherein the second converter ( 2 ) is a resonant converter, preferably an LLC resonant converter, which is connected by means of a half-bridge circuit ( 21 ) is operated; and wherein the half-bridge circuit ( 21 ) is operated with two switches (S1, S2), to which a second switching signal (HS, LS) can be applied, wherein the second switching signal (HS, LS) has a first switching signal component (HS) and a complementary switching signal component (LS). Driver circuit according to one of the preceding claims, wherein the first converter ( 1 ) a control unit ( 11 ) to the first switch (S3) of the first converter ( 1 ) to be clocked by means of a first switching signal (Sig); and where to the control unit ( 11 ) a control signal (PFC) of the control unit ( 4 ) for cyclically changing the timing of the first switch (S3) of the first converter ( 1 ) is created. Driver circuit according to claim 4, wherein a setpoint (Soll) for the control unit ( 11 ) by the control signal (PFC) a cyclically changing additional value is applied to the cyclic change of the timing of the first switch (S3) of the first converter ( 1 ) to effect. Driver circuit according to claim 4 or 5, wherein an actual variable (actual) for the control unit ( 11 ) by the control signal (PFC) a cyclically changing additional value is applied to the cyclic change of the timing of the first switch (S3) of the first converter ( 1 ) to effect. Driver circuit according to one of claims 4 to 6, wherein the Anschaltzeitwert (T _on ) of the first switching signal (Sig) by the control signal (PFC) a cyclically changing additional time value (t _add ) is applied to the cyclic change of the timing of the first switch ( S3) of the first converter ( 1 ) to effect. Driver circuit according to one of the preceding claims, wherein the cyclic change of the clocking is applied only when the load ( 3 ) has a load value below a predefined threshold. Driver circuit according to claim 8, wherein the load ( 3 ) is at least one LED; and wherein the load value of the LED is determined by a Dimmwertvorgabe, preferably a dimming value below 50 percent, more preferably below 25 percent of the total light output of the at least one LED. Driver circuit according to claim 8 or 9, wherein the load ( 3 ) is at least one LED; and wherein the load value is determined by a load current measurement and / or a load voltage measurement. Driver circuit according to one of claims 8 to 10, wherein the load ( 3 ) is at least one LED; and wherein the load value is determined by the duration of the turn-on time (t _on ) of the first switch (S3) of the first converter ( 1 ) is determined. Driver circuit according to one of the preceding claims, wherein due to the ripple of the regulated DC voltage (U _bus ) a cyclic clocking of a switch (S1, S2) of the second converter ( 2 ) is adjustable. Driver circuit according to one of the preceding claims, wherein at least a third clocked converter ( 5 ) the second clocked converter ( 2 ) is connected downstream; and wherein the third transducer ( 5 ) by means of a clocking of a switch (S4) of the third converter ( 5 ) weight ( 3 ) operates. Driver circuit according to one of the preceding claims, wherein the first converter ( 1 ) is a PFC converter or a buck converter or a fly-back converter. Driver circuit according to one of the preceding claims, wherein the third converter ( 5 ) is a buck converter. Operating device for a luminous means comprising a driver circuit according to one of the preceding claims. Procedure ( 100 ) for operating a load ( 3 ), preferably at least one luminous means, in particular an LED, by means of a driver circuit according to one of claims 1 to 15, with the method steps: conversion ( 101 ) of an input voltage (L, N) into a regulated DC voltage (U _bus ) by means of a first clocked converter ( 1 ) using one of a control unit ( 4 ) clocked switch (S3) of the converter ( 1 ); Implement ( 102 ) of the regulated DC voltage (U _bus ) into a load voltage (U _load ). to operate the load ( 3 ) by means of at least one second clocked converter ( 2 ) using one of the control unit ( 4 ) clocked switch (S1, S2) of the second converter ( 2 ); Cyclic change ( 103 ) the timing of the switch (S3) of the first converter ( 1 ), that - even if the input voltage (L, N) of the converter ( 1 ) and the load ( 3 ) are constant, there is a residual ripple in the regulated DC voltage (U _bus ); and Decrease ( 104 ) this residual ripple of the regulated DC voltage (U _bus ) by means of the second converter ( 2 ). The method of claim 17, wherein the residual ripple is the operating frequency of the second converter ( 2 ) changed. Method according to one of claims 17 or 18, wherein a setpoint (nominal) of a control unit ( 11 ) of the first converter ( 1 ) by means of a control signal (PFC) of the control unit ( 4 ) is cyclically changed. Method according to one of claims 17 to 19, wherein an actual variable (actual) of a control unit ( 11 ) of the first converter ( 1 ) by means of a control signal (PFC) of the control unit ( 4 ) is cyclically changed. Method according to one of claims 17 to 20, wherein an on-time (t _on ) of the clocking of the first converter ( 1 ) by means of a control signal (PFC) of the control unit ( 4 ) is cyclically changed. Method according to one of claims 17 to 21, wherein the cyclical change of the clocking is applied only when the load ( 3 ) has a load value below a predefined threshold.

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