DD204557A1 - EVALUATION FOR SURVEILLANCE SIGNALS IN INDUSTRIAL CONTROLS - Google Patents

Abstract

The invention can be used in industrial control systems, which are constructed to meet extremely high demands on reliability with redundant control logic and their logic levels are monitored with a traversed by a control signal Ueberwachungskette. The evaluation circuit influences the control element of the control device with the monitoring signal occurring at the end of the monitoring chain. If the monitoring signal fails, a non-hazardous operating condition is established. The self-monitoring is improved by arranging the self-holding branch of the evaluation circuit between its output and the primary winding of the input transformer.

Description

Inventor! DiBl.-Ing. Hartmut Bunzel Berlin, 22.12.1981 lied. Manfred Schäfer P 1253

Zustellungsbevollm .:

Institute of Balancing Technology in Combine TEB EAW Berlin-Ereptow

"Friedrich Bbert"

1055 Berlin, Storkower Str. 101 S05B - 9/02

Pat.-Ing. Günther Scheufeie (G05B -23 / 02)

Evaluation circuit for monitoring signals in industrial controls

Field of application of the invention

The invention can be used in industrial control systems, in which extremely high! Requirements on the reliability must be met must be, because when ühlfunktionen large damage or even human lives are at risk. This applies, for example, to control systems for large presses, rolling mills, nuclear power plants and the like.

Characteristic of the known technical solutions

For the monitoring of the error-free operation of industrial control systems, several principal solutions have been developed. One of these approaches, in which the invention can also be used, is to construct the controller with normal logic components whose security against failure or faulty behavior only satisfies the normal requirements As a security measure, the entire control logic is constructed redundantly in a two-fold structure the two structures are either logically identical or logically inverse and are always operated simultaneously At all stages of the control logic, if the function is error-free, then equivalently equivalent or antivalente logic signalpass occurs at the respectively equal-order logic gates of both structures

on. With the help of surveillance members, the presence of Äqaivalens or Antivalenz is constantly monitored.

For safety against failure and Eehlverhalten the monitoring members themselves, it is common to connect all monitoring elements of the relevant control system in chain and loop through a rectangular AC voltage of several KHz as a control signal through this chain of custody and evaluate their sine as a monitoring signal. Each monitoring element is constructed in such a way that it interrupts the control signal when the logic signal pair monitored by it deviates from the required signal combination or when an error occurs in the monitoring element itself. At the bottom of the chain of custody is an evaluation circuit which, if the monitoring signal fails, brings about the stopping of the controlled device or brings about a safe operating state. Such an evaluation circuit is the subject of the present invention.

Ss an evaluation circuit is already known, which is realized as a gate with delay-off latching. It contains two gate elements designed as ШШ-gates. The monitoring signal is supplied to the first door member via its information input from the person in charge of the monitoring chain, and the deceleration-delayed control signal of the second door member is aur-returned to the control input of the first door member for latching. Sas direct control signal enters the information input of the second door member and is turned on by this in trouble-free operation on the output and thus to the actuator. This evaluation circuit is constructed selbstüberwaqhend in such a way aa internal Peüler always cause a blocking of the control signal. However, it adheres to the Hachteil that the second gate member is not included in the self-monitoring, because the feedback for latching is already derived from its control input, whereby the presence of Eontrollsignals at the output of the evaluation circuit is not checked.

Object of the invention

The object of the invention is to increase the reliability of the control system by improving the self-monitoring of the Aaswerte circuit.

Essence of the invention Object of the invention

The invention has the object augrunde to provide an evaluation circuit for monitoring signals that occur at the Snde of monitoring chains with which the redundantly arranged control logic is monitored by means of an Eontrollsignals in industrial controls. The evaluation should be executed self-monitoring and switch through the control signal to its output when existing or briefly interrupted monitoring signal. In the event of the absence of the monitoring signal, the control signal is blocked, and if the monitoring signal is repeated, this blockage must not be canceled automatically. Only the entry of a start signal may cause the suspension of the suspension.

Features of the invention

The evaluation circuit, which converts the monitoring signal with a diode and a storage capacitor in a manner known per se into a waste-delayed control signal for a gate signal switching the control signal, is characterized by the following features:

With the output of the gate member and with the control-side ground, the terminals of the primary winding of a Kückführübertragers are connected. The terminals of its secondary winding lead via an arrangement of a diode and a charge stabilizer to the base 3n ± ter 8trecke a holding transistor. The collector-smitter path is arranged between the logic-side and the ground-side connection of the primary winding of a per se known transductor, which transmits the

Monitoring signal transmits. The base of the holding transistor is connected via a decoupling diode to a start input.

The control signal, which arrives at the output via the door member in the presence of a monitoring signal after a start, is branched off there for feedback and converted after passing through the HücJdTührübertragers in a DC voltage, which keeps the holding transistor in a conductive state. If the monitoring signal is longer than it corresponds to the deceleration delay, the gate member blocks, and the output eliminates the e-control signal and, consequently, the DC voltage at the holding transistor, which then blocks, whereby the self-holding is canceled. Even when the monitoring signal is repeated, renewed latching occurs only after a starting operation, in which the holding transistor is kept conducting with a DC voltage until all charging operations have been completed and latching is again active.

embodiment

The invention will be explained in more detail in an embodiment. The accompanying drawing shows the evaluation circuit according to the invention in conjunction with a symbolically represented monitoring chain which serves to monitor the error-free control sequence.

At the beginning of the monitoring unit ÜK, there is a control signal generator KG, which generates a control signal ES in 3 ° of a rectangular alternating voltage of a few kHz, which passes through all monitoring components ÜG of the monitoring chain ÜK. Each monitoring member ÜG has the property of transmitting the control signal KS when the monitored logic gates of the control logic are operating properly or to disable the control signal KS when a fault occurs. The control signal KS is also disabled when a monitoring member ÜG itself is faulty. At the end of the surveillance chain ÜK

In the event of fault-free operation, the control signal KS acts as a monitoring signal UB.

The control logic, not shown in the drawing is to achieve the required reliability redundant off, run and consists of two identical or two logically inverse structures that are always operated simultaneously, in the respective equal-level logic gates of the two structures, the logic signals are tapped and from the Surveillance members ÜG monitored in pairs for equivalence or antivalence.

Seen from its mode of action, the evaluation circuit is a gate circuit with a delay-delayed latching of the control signal. The evaluation circuit consists of a gate TG in the embodiment as a gate, a circuit part for generating the control signal and a circuit part for latching. First, the state is to be considered, which takes the evaluation circuit when all startup and startup operations are completed and an undisturbed operation of the control system takes place, so that both a control signal ES and a monitoring signal OS are present.

The control signal XS enters the control input EE and from there into the information input IE of Tolgliedes TG. The monitoring signal US is fed into the monitoring input ÜB and passes through there from any required decoupling gate EC, possibly even a gate resistance and is then transmitted from the input transformer Üi. U ± e is still shown, the Haltetraßsistor Ts is always in the through state during an undisturbed operation, so that the terminal 12 of the Eingangsübertragers Ü1 has the potential of the logic-side ground M1.

The monitoring signal coming from the input transformer Ü1 is rectified with the diode 31 and smoothed at the storage capacitor 01. This DC voltage is as logic control signal S3 with dera.logikpegel L at the control input S3 of the gate member TG. Dis Ε diode ZD limits the control

Signal SS aiii a voltage that is independent of the widely tolerated supply voltage of the logic gates. Thus, the discharge time of Spelcuerkonäe'nsators 01, which will be discussed later, regardless of the level of the supply voltage. Wt Logikpsgel the L at its control input, the SE gate member TG turns on the Inforinationseingang IB existing control signal ES to the output A by where there is a not shown in the drawing actuator available.

Between the output A and the control-side ground M2 a feedback of the control signal for latching is still diverted. The transmitted from Büekführübertrager Ü2 EoQtrollsignal is rectified in the diode D2 and smoothed by the charging capacitor 02. With the resulting DC voltage of the holding transistor Ts is held in the on state. If necessary, a sense resistor can be inserted between the charging capacitor C2 and the base of the holding transistor Ts.

After this undisturbed operation, a case of failure is to be considered in which e.g. a .Störung in the control logic occurs, so that one of the monitoring ÜG blocks the 7ieiterleitung the control signal KS, whereupon the monitoring input UB the monitoring signal US fails. As an annual value of this, the DC voltage decreases at the storage capacitor 01, and the control input SS switches the Ijogic spectrum of the control signal SS from L to 0. When the switching element TG is reached, this blocks the control signal KS present at itsinforination input 13, whereby the actuator connected as output A switches off or brings about a safe operating state.

The / / efall of the Eontrollsignals аді output A also leads to cancel the latching, because the rectified voltage at the charging capacitor G2 is also eliminated, - »preceded by the holding transistor Ts blocks. As a result, the connection between the primary winding of the Eingangsübertragers Ü1 and the mass Ы1 is interrupted.

Also wean the disturbance after some time eliminates wirä and when as a result of the monitoring signal Ü3 returns, this can not get to the secondary side de * s Eingangübertragers Ü1 because of the locked holding transistor Ts. At the control input S3, therefore, the O level remains active as the control signal SS, and the gate TG continues to be kept in the locked state.

3rst when the self-holding is reactivated, the control signal 5CS can reach the output A again. For activation, the start input ST is supplied with a start signal in the form of a DC voltage, which sets the holding transistor Ts in the conducting state. The monitoring signal US can then pass through the input transformer 01 again and cause a control signal SS with the logic level L at the control input SS which opens the gate TG again for the control signal EB. The start signal mus but be entered so long until the storage capacitor C1 and the charging capacitor 02 are charged, only then is the self-holding effective again. A Bntkopplungsdiode SD prevents unwanted derivation of the base potential of the holding transistor Ts to the source input ST connected source.

The last-described process corresponds exactly to the starting of the evaluation circuit in the case of an operational bit string of the control system after a pause in operation. Again, the monitoring signal US occurs at Überwachtingseingang ÜE, the latching is not yet activated because of the locked Haitetransistors Ts. By a start signal at the start input ST, the evaluation circuit is ready for operation.

In the illustrated up to here Tjirkungsweise been simplified based on the assumption that the Eoutrollsignal KS passes in a faultless operation of all Jber ~ v ^r achungsgiieder HG continuously and that accordingly, the monitoring signal U3 is continuously present at the on-7 / achungseingang ÜZ. i) this assumption, however, does not take into account the logic of the logic gates with which they are to be controlled

Control logic is constructed. As already stated, because of the redundant double structure of the control logic, each logic gate is duplicated, and if the respective parallel logic gates simultaneously provide the expired η logic signals, the associated monitoring element ÜG- passes the control signal ES.

In the practical operation of the control logic, however, the fact must be taken into account that the response thresholds and the switching sides of the logic gates of the exemplar su exemplar are different. As a result, time differences occur when switching the logic gates in identical stages of the two parallel structures. In these short periods, the proper equivalence or antivalence is absent. Although this does not involve an activation function of the control logic, these time periods with slow, interference-proof logic are quite sufficient for a brief response of the monitoring components ÜG. However, the resulting short-term interruptions of the monitoring signal US must not affect the output A and thus the actuator. ,

To bridge these operational interruptions of the storage capacitor 01. 3r can z. S. be gradually switched over and be set to such a value that during the discharge the control signal SS a corresponding side section above the Abschaltschwells the door member TG maintains, ia interaction with the adjustable Sntladewiderstand He results in the deceleration delay for latching. Their drop occurs only when the Sontrollsignal fails at the output A. In practical Aaswirkung of course, a response delay of latching, which does not fall into court, if the start signal at the start input ST is entered sufficiently long.

The self-monitoring of this evaluation circuit is ensured by the fact that any error or voltage failure results in

that at the output A always only a static signal, in particular logic 0 is formed, but the control signal is blocked. The improvement in self-monitoring achieved by the invention results from the fact that the presence of the control signal at the output A is used as a criterion for the occurrence of latching.

Claims (1)

Srfindungsanspruch Evaluation circuit for monitoring signals in industrial control systems with redundantly arranged control logic and a monitoring chain, the output signal of which comprises the monitoring signal, which is converted in the anis value circuit into a rectified and decay-delayed control signal for a control signal switching gate element, characterized in that the output of the gate member (Td) and to the control-side hatch (M2) the terminals (21s 22) of the primary winding of a Eückführütertragers (Ü2) are connected, that the terminals (23; 2 *) of its secondary winding with the interposition of a diode (D2) and parallel a charging charger (C2) are connected to the base-emitter path of a holding transistor (Ts) whose collector-Bmitter path between the logifcseitigen mass (И1) and the ground-side terminal (12) of the primary winding of a known input transformer (tf1) f is arranged for the monitoring signal (Ш), and that the base terminal of the holding transistor (2s) via a Sntkopplungsdiode (ED) is connected to a start input (ST). For this 1 page drawings