CN218549895U - Broadband prescaler - Google Patents
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- CN218549895U CN218549895U CN202023289828.3U CN202023289828U CN218549895U CN 218549895 U CN218549895 U CN 218549895U CN 202023289828 U CN202023289828 U CN 202023289828U CN 218549895 U CN218549895 U CN 218549895U
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Abstract
The utility model provides a broadband prescaler, which comprises a first data selector, a second data selector, a first NAND gate, a second NAND gate and a first trigger, wherein a frequency division trigger group is arranged between the first data selector and the second data selector; the first data selector is respectively connected with the frequency division trigger group and the first NAND gate; the first NAND gate and the second NAND gate are both connected with the first trigger; the second data selector is respectively connected with the frequency division trigger group and the second NAND gate; the second NAND gate is connected with the frequency division trigger group; the utility model realizes the switching of frequency bands by adding two data selectors, thereby simplifying the complexity of the circuit, reducing the design difficulty of the circuit and effectively avoiding the reduction of the working speed of the circuit; different prescaler ratios can be realized aiming at different frequency bands, the working frequency range of the broadband prescaler is greatly expanded, and the universality and the applicability of the broadband prescaler are greatly enhanced.
Description
Technical Field
The utility model relates to an electricity field especially relates to frequency division technique, especially a broadband prescaler.
Background
The frequency divider is a key module in the frequency synthesizer and the clock generator, and has the main function of completing the frequency division of high-frequency signals, namely realizing the conversion from the high-frequency signals to low-frequency signals. The frequency divider is one of circuit modules with extremely high working speed, the working frequency range of the frequency divider needs to be wide enough to meet the universality, and the prescaler is a module which is directly connected with a high-frequency signal in the frequency divider and is very critical when the frequency divider can work at high speed and in a wide frequency range; in the development process of an integrated circuit, the requirement on the operating speed of the circuit is higher and higher, and the operating frequency range of an input signal is wider and wider, and the operating frequency of the frequency divider is closely related to the circuit structure and the adopted process node, and is particularly limited by the process node, so that it is difficult to satisfy the normal operation in the wide input frequency range and realize the required frequency division ratio.
In order to solve the above problems, the currently adopted method usually implements a multiband function in a prescaler of a frequency divider, but the existing multiband prescaler often implements switching of different frequency bands through a complex combinational logic circuit, which, on one hand, increases the complexity of the circuit, increases the difficulty of circuit design, and consumes more time cost; on the other hand, the logic gate added on the key signal link can greatly reduce the working speed of the circuit, and is not suitable for being used in the high-frequency field, so that the applicability of the circuit is reduced.
SUMMERY OF THE UTILITY MODEL
In view of the above prior art's shortcoming, the utility model aims to provide a broadband prescaler for solve the problem that current multiband prescaler circuit structure is complicated, the circuit design degree of difficulty is high.
To achieve the above and other related objects, the present invention provides a wideband prescaler, comprising: the circuit comprises a first data selector, a second data selector, a first NAND gate, a second NAND gate and a first trigger, wherein a frequency division trigger set is arranged between the first data selector and the second data selector; a signal selection end of the first data selector is connected with a frequency band selection signal, an input end of the first data selector is connected with the frequency division trigger set, and an output end of the first data selector is connected with a first input end of the first NAND gate; a second input end of the first NAND gate is connected with a frequency division mode control signal, and an output end of the first NAND gate is connected with a first end of the first trigger; a second end of the first trigger is connected with an input signal, and the input signal is connected with the frequency division trigger set; a signal selection end of the second data selector is connected to the band selection signal, an input end of the second data selector is connected to the frequency division flip-flop group, and an output end of the second data selector is connected to a first input end of the second nand gate; the second input end of the second NAND gate is connected with the third end of the first trigger, and the output end of the second NAND gate is connected with the frequency division trigger group; selecting and accessing different frequency band selection signals according to the frequency of the input signal so as to realize the frequency band switching of the broadband prescaler and enable the broadband prescaler to work in different frequency division ratio modes; when the broadband prescaler works in the same frequency dividing ratio mode, the broadband prescaler is controlled to work in different frequency dividing modes by accessing different frequency dividing mode control signals.
In an embodiment of the present invention, the frequency division trigger set includes: at least two second flip-flops; the number of second flip-flops determines the divide ratio mode in which the wideband prescaler operates.
In an embodiment of the present invention, the number of ports at the input end of the first data selector and the second data selector is equal to at least two, and the number of ports at the signal selection end of the first data selector and the second data selector is equal to at least one.
In an embodiment of the present invention, the frequency division trigger set includes: four second flip-flops, respectively: the first trigger, the second trigger, the third trigger and the fourth trigger are connected in series; the number of ports of the input ends of the first data selector and the second data selector is two, the ports are respectively a first input end and a second input end, and the number of ports of the signal selection ends of the first data selector and the second data selector is one; a first end of the first second flip-flop is connected with an output end of the second nand gate, a second end of the first second flip-flop is respectively connected with a second end of the second flip-flop, a second end of the third second flip-flop, a second end of the fourth second flip-flop and a second end of the first flip-flop, and the second ends of the first and fourth flip-flops are jointly connected with the input signal, and a third end of the first second flip-flop is connected with a first end of the second flip-flop; a third end of the second flip-flop is connected with a first end of the second flip-flop and a first input end of the second data selector respectively, and a fourth end of the second flip-flop is connected with a first input end of the first data selector; the third end of the third trigger is connected with the first end of the fourth trigger; a third end of the second flip-flop fourth is connected with the second input end of the second data selector, and a fourth end of the second flip-flop fourth is connected with the second input end of the first data selector; when the band selection signal is at a low level, the wideband prescaler works in a 4/5 frequency division ratio mode, and when the wideband prescaler works in the 4/5 frequency division ratio mode, and when the frequency division mode control signal is at a low level, the wideband prescaler works in a 4 frequency division mode; when the frequency division mode control signal is at a high level, the broadband prescaler works in a frequency division mode of 5; when the band selection signal is at a high level, the wideband prescaler works in an 8/9 frequency division ratio mode, and when the wideband prescaler works in the 8/9 frequency division ratio mode, the wideband prescaler works in an 8 frequency division mode when the frequency division mode control signal is at a low level; when the frequency division mode control signal is at a high level, the broadband prescaler works in a frequency division mode of 9.
In an embodiment of the present invention, the method further includes: a post-stage circuit; the post-stage circuit is connected with the fourth end of the first trigger.
As mentioned above, the broadband prescaler of the utility model has the following beneficial effects:
(1) Compared with the prior art, the utility model discloses an increase the switching that two data selector realized the frequency band promptly, both simplified the complexity of circuit, reduced the design degree of difficulty of circuit, effectively avoided the reduction of circuit operating speed again.
(2) The utility model discloses can realize different presorting ratios to different frequency bands, greatly expand the operating frequency range of this broadband presorting ware to effectively guarantee that back stage circuit still can continue work under wide frequency range condition, work under the same frequency even, consequently, need not consider the frequency range that the trigger can work under the different input frequency of trigger, strengthened the commonality and the suitability of this broadband presorting ware greatly.
Drawings
Fig. 1 is a circuit diagram of a wideband prescaler according to an embodiment of the present invention.
Fig. 2 is an equivalent circuit diagram of the wideband prescaler of the present invention operating in the 4/5 division ratio mode in one embodiment.
Fig. 3 is an equivalent circuit diagram of the wideband prescaler of the present invention operating in the 8/9 division ratio mode in one embodiment.
Description of the reference symbols
1-a frequency division flip-flop group; 2-the latter stage circuit.
Detailed Description
The following description is provided for illustrative embodiments of the present invention, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
Compared with the prior art, the broadband prescaler of the utility model realizes the switching of frequency bands by adding two data selectors, thereby simplifying the complexity of the circuit, reducing the design difficulty of the circuit and effectively avoiding the reduction of the working speed of the circuit; the utility model discloses can realize different presorting ratios to different frequency bands, greatly expand the operating frequency range of this broadband presorting ware to effectively guarantee that back stage circuit still can continue work under wide frequency range condition, work under the same frequency even, consequently, need not consider the frequency range that the trigger can work under the different input frequency of trigger, strengthened the commonality and the suitability of this broadband presorting ware greatly.
As shown in fig. 1, in an embodiment, the wideband prescaler of the present invention includes a first data selector MUX1, a second data selector MUX2, a first NAND gate NAND1, a second NAND gate NAND2, and a first flip-flop DFF, and a frequency division flip-flop group 1 is disposed between the first data selector MUX1 and the second data selector MUX 2.
Specifically, a signal selection end of the first data selector MUX1 is connected to a band selection signal SW, an input end of the first data selector MUX1 is connected to the frequency division flip-flop group 1, and an output end of the first data selector MUX1 is connected to a first input end (1) of the first NAND gate NAND 1; a second input end (2) of the first NAND gate NAND1 is connected with a frequency division mode control signal MC, and an output end (3) of the first NAND gate NAND1 is connected with a first end (1) of the first trigger DFF; a second end (2) of the first trigger DFF is connected with an input signal FIN, and the input signal FIN is connected with the frequency division trigger group 1; the signal selection end of the second data selector MUX2 is connected to the band selection signal SW, the input end of the second data selector MUX2 is connected to the frequency division flip-flop group 1, and the output end of the second data selector MUX2 is connected to the first input end (1) of the second NAND gate NAND 2; and a second input end (2) of the second NAND gate NAND2 is connected with a third end (3) of the first trigger DFF, and an output end (3) of the second NAND gate NAND2 is connected with the frequency division trigger group 1.
It should be noted that, according to the frequency of the input signal FIN, different band selection signals SW are selectively accessed to control the band switching of the wideband prescaler, so that the wideband prescaler operates in different frequency division ratio modes.
Furthermore, when the broadband prescaler works in the same frequency division ratio mode, the broadband prescaler is controlled to work in different frequency division modes by accessing different frequency division mode control signals.
In one embodiment, the divide-by-flip-flop group 1 includes at least two second flip-flops.
It should be noted that the number of the second flip-flops determines the frequency division ratio mode in which the wideband prescaler operates.
In an embodiment, the number of the ports at the input ends of the first data selector MUX1 and the second data selector MUX2 is equal to at least two, and the number of the ports at the signal selection ends of the first data selector MUX1 and the second data selector MUX2 is equal to at least one.
It should be noted that, when the number of the ports at the input ends of the first data selector MUX1 and the second data selector MUX2 is two, that is, the first data selector MUX1 and the second data selector MUX2 are both two-out-of-one data selectors, that is, one input signal is selected from two input signals as its output signal and output, at this time, the number of the ports at the signal selection ends of the first data selector MUX1 and the second data selector MUX2 is one, that is, when the frequency band selection signal SW accessed by the signal selection end is high level 1, one of the input signals is selected as its output signal and output, and when the frequency band selection signal SW accessed by the signal selection end is low level 0, the other input signal is selected as its output signal and output; similarly, when the number of the input ends of the first data selector MUX1 and the second data selector MUX2 is three, that is, the first data selector MUX1 and the second data selector MUX2 are both one-out-of-three data selectors, that is, an input signal is selected from three input signals as an output signal thereof and output, at this time, the number of the input ends of the signal selection ends of the first data selector MUX1 and the second data selector MUX2 is two, that is, signals input from two ports of the signal selection end are used as the band selection signal SW, and when the signals input from two ports of the signal selection end are 00 (the SW signal is 00), a first input signal of the three input signals is selected as the output signal and output; when the signals input by the two ports of the signal selection end are 01 (the SW signal is 01), selecting the second input signal of the three input signals as an output signal and outputting the output signal; when the signals input by the two ports of the signal selection end are 10 (the SW signal is 10), the third input signal in the three input signals is selected as the output signal and output; by analogy, the band switching of the wideband prescaler can be realized by selecting different data selectors and combining with the second flip-flop in the frequency division flip-flop group 1, so that the wideband prescaler works in different frequency division ratio modes.
As shown in fig. 1, in an embodiment, the frequency division flip-flop group 1 includes four second flip-flops, i.e., a first flip-flop-DFF 1, a second flip-flop-second DFF2, a second flip-flop-third DFF3, and a second flip-flop-fourth DFF4; the number of the ports of the input ends of the first data selector MUX1 and the second data selector MUX2 is two, the ports are respectively a first input end (1) and a second input end (2), and the number of the ports of the signal selection ends of the first data selector MUX1 and the second data selector MUX2 is one.
Specifically, a first end (1) of the first flip-flop-DFF 1 is connected to an output end (3) of the second NAND gate NAND2, a second end (2) of the first flip-flop-DFF 1 is respectively connected to a second end (2) of the second flip-flop-DFF 2, a second end (2) of the second flip-flop-DFF 3, a second end (2) of the second flip-flop-DFF 4, and a second end (2) of the first flip-flop-DFF, and the input signal FIN is commonly accessed, and a third end (3) of the first flip-flop-DFF 1 is connected to a first end (1) of the second flip-flop-DFF 2; a third end (3) of the second flip-flop DFF2 is respectively connected with a first end (1) of the second third flip-flop DFF3 and a first input end (1) of the second data selector MUX2, and a fourth end (4) of the second flip-flop DFF2 is connected with the first input end (1) of the first data selector MUX 1; a third end (3) of the second trigger three DFF3 is connected with a first end (1) of the second trigger four DFF4; a third end (3) of the second flip-flop four DFF4 is connected to the second input end (2) of the second data selector MUX2, and a fourth end (4) of the second flip-flop four DFF4 is connected to the second input end (2) of the first data selector MUX 1.
It should be noted that the broadband prescaler includes the basic units of the 4/5 frequency divider and the 8/9 frequency divider at the same time, and in actual operation, the two alternative data selectors MUX1 and MUX2 select whether the broadband prescaler operates in the 4/5 frequency divider or the 8/9 frequency divider; specifically, by setting the SW signal and the MC signal to 00, 01, 10 and 11 respectively for the broadband prescaler, 4-frequency division, 5-frequency division or 8-frequency division and 9-frequency division can be realized; when the highest frequency of an input signal FIN is smaller, the 4/5 frequency division function of the broadband prescaler is adopted; when the highest frequency of the input signal FIN is larger, the 8/9 frequency division function of the broadband prescaler is adopted, so that after prescaled by the broadband prescaler, the circuit at the next stage can adopt the same unit without redesigning to adapt to a wide input signal working frequency range, the design difficulty of the circuit is greatly reduced, and the circuit structure is simplified.
For example, when the frequency range of the input signal is 500M-6G, the broadband prescaler adopts 4/5 frequency division when the frequency range is 500M-3G, and the frequency of the input signal obtained by the later stage is 750M or 600M at most; when the frequency range is 3G-6G, the broadband prescaler adopts 8/9 frequency division, and the frequency of the input signal of the later stage is 750M or 666M at most.
Furthermore, by spreading on the basis of the broadband prescaler, other frequency division ratio circuits can be realized.
It should be noted that, when the band selection signal SW is at low level 0, the wideband prescaler operates in a 4/5 frequency division ratio mode, and when the wideband prescaler operates in the 4/5 frequency division ratio mode, and when the frequency division mode control signal is at low level 0, the wideband prescaler operates in a 4 frequency division mode; and when the frequency division mode control signal is at a high level 1, the broadband prescaler works in a frequency division mode of 5.
Specifically, when the SW signal is 0, the first data selector MUX1 selects the QB2 signal output from the fourth terminal of the second flip-flop two DFF2 to the first input terminal (1) of the first NAND gate NAND1, and the second data selector MUX2 selects the signal Q2 output from the third terminal of the second flip-flop two DFF2 and inputs the signal Q2 to the first input terminal (1) of the second NAND gate NAND2, at this time, the wideband frequency divider operates in a frequency division 4/5 mode, and the circuit at this time is equivalent to that shown in fig. 2.
It should be noted that the 4/5 prescaler unit is formed by the first flip-flop-DFF 1, the second flip-flop-DFF 2, the first flip-flop DFF, the first NAND gate NAND1, and the second NAND gate NAND 2.
Further, if the MC signal is set to 0, the wideband prescaler operates in a frequency division mode of 4 at this time; if the MC signal is set to 1, the broadband prescaler works in a frequency division 5 mode at the moment.
It should be noted that, when the band selection signal SW is at a high level 1, the wideband prescaler operates in an 8/9 frequency division ratio mode, and when the wideband prescaler operates in the 8/9 frequency division ratio mode, and when the frequency division mode control signal is at a low level 0, the wideband prescaler operates in the 8 frequency division mode; and when the frequency division mode control signal is at a high level 1, the broadband prescaler works in a frequency division mode of 9.
Specifically, when the SW signal is 1, the first data selector MUX1 selects the QB4 signal output from the fourth terminal of the second flip-flop four DFF4 to the second input terminal (2) of the first NAND gate NAND1, and the second data selector MUX2 selects the signal Q4 output from the third terminal of the second flip-flop four DFF4 and inputs the signal Q4 to the second input terminal (2) of the second NAND gate NAND2, at this time, the wideband frequency divider operates in a frequency division 8/9 mode, and the circuit at this time is equivalent to that shown in fig. 3.
It should be noted that the 8/9 prescaler unit is formed by the first flip-flop-DFF 1, the second flip-flop-DFF 2, the second flip-flop-DFF 3, the second flip-flop-DFF 4, the first flip-flop DFF, the first NAND gate NAND1, and the second NAND gate NAND 2.
Further, if the MC signal is set to 0, the wideband prescaler operates in the frequency division by 8 at this time; if the M C signal is set to 1, then the wideband prescaler is operating in divide by 9 mode at this time.
The easy-to-spread characteristic of the wideband prescaler can be easily found through the circuit description of the two operation modes, namely the 4/5 frequency division mode and the 8/9 frequency division mode, namely, the 4/5 or 8/9 multiband prescaler designed in the embodiment can be changed into the prescaler of other values, such as 8/9 or 16/17, 16/17 or 32/33, even 4/5 or 32/33, by changing the number of the triggers existing between the two ends of the data selector; in addition, by changing the one-out-of-three data selector to the one-out-of-two data selector, three different sets of prescaler ratios can also be implemented, such as: 4/5, 8/9 or 16/17 prescaler ratio can be realized, and the working frequency range of the broadband prescaler is further expanded; by analogy, the structure that this broadband prescaler provided can be as required very convenient realization different prescaled frequency ratio, and this kind of easy expansion characteristic has greatly realized the utility model discloses the application range of circuit can fabulous time and the cost that reduces circuit design.
In one embodiment, the following stage circuit 2 is further included.
Specifically, the rear stage circuit 2 is connected to the fourth terminal (4) of the first flip-flop DFF.
It should be noted that, through the design of the wideband prescaler circuit structure, it is ensured that the post-stage circuit 2 can still continue to operate under the condition of a wide frequency range on the basis that the post-stage circuit 2 does not need to be redesigned.
To sum up, compared with the prior art, the broadband prescaler of the utility model realizes the switching of frequency bands by adding two data selectors, thereby simplifying the complexity of the circuit, reducing the design difficulty of the circuit, and effectively avoiding the reduction of the working speed of the circuit; the utility model discloses can realize different prescaler than to different frequency bands, greatly expand the operating frequency range of this broadband prescaler to effectively guarantee that back-stage circuit still can continue to work under wide frequency range condition, even work under the same frequency, consequently, need not consider the frequency range that the trigger can work under the different input frequency of trigger, strengthened the commonality and the suitability of this broadband prescaler greatly; therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (5)
1. A wideband prescaler, comprising: the circuit comprises a first data selector, a second data selector, a first NAND gate, a second NAND gate and a first trigger, wherein a frequency division trigger set is arranged between the first data selector and the second data selector;
a signal selection end of the first data selector is connected with a frequency band selection signal, an input end of the first data selector is connected with the frequency division trigger set, and an output end of the first data selector is connected with a first input end of the first NAND gate;
a second input end of the first NAND gate is connected with a frequency division mode control signal, and an output end of the first NAND gate is connected with a first end of the first trigger;
the second end of the first trigger is connected with an input signal, and the input signal is connected with the frequency division trigger set;
the signal selection end of the second data selector is connected with the frequency band selection signal, the input end of the second data selector is connected with the frequency division trigger group, and the output end of the second data selector is connected with the first input end of the second NAND gate;
the second input end of the second NAND gate is connected with the third end of the first trigger, and the output end of the second NAND gate is connected with the frequency division trigger group;
selecting and accessing the frequency band selection signal according to the frequency of the input signal to realize the frequency band switching of the broadband prescaler, so that the broadband prescaler works in a suitable frequency dividing ratio mode;
when the broadband prescaler works in the same frequency division ratio mode, the broadband prescaler is controlled to work in the adaptive frequency division mode by accessing the frequency division mode control signal.
2. The wideband prescaler of claim 1, wherein the set of divide-down flip-flops comprises: at least two second flip-flops; the number of the second triggers determines the frequency dividing ratio mode of the broadband prescaler.
3. The wideband prescaler of claim 2, wherein the number of ports at the input terminals of the first data selector and the second data selector is equal and is at least two, and the number of ports at the signal selection terminals of the first data selector and the second data selector is equal and is at least one.
4. The wideband prescaler of claim 3, wherein the set of divide flip-flops comprises: four second flip-flops, respectively: the first trigger, the second trigger, the third trigger and the fourth trigger are connected with the first trigger; the number of ports of the input ends of the first data selector and the second data selector is two, the ports are respectively a first input end and a second input end, and the number of ports of the signal selection ends of the first data selector and the second data selector is one;
a first end of the first second flip-flop is connected with an output end of the second nand gate, a second end of the first second flip-flop is respectively connected with a second end of the second flip-flop, a second end of the third second flip-flop, a second end of the fourth second flip-flop and a second end of the first flip-flop, and the second ends of the first and fourth flip-flops are jointly connected with the input signal, and a third end of the first second flip-flop is connected with a first end of the second flip-flop;
a third end of the second trigger II is respectively connected with a first end of the second trigger III and a first input end of the second data selector, and a fourth end of the second trigger II is connected with a first input end of the first data selector;
the third end of the third trigger is connected with the first end of the fourth trigger;
a third end of the second flip-flop fourth is connected with the second input end of the second data selector, and a fourth end of the second flip-flop fourth is connected with the second input end of the first data selector;
when the band selection signal is at a low level, the wideband prescaler works in a 4/5 frequency division ratio mode, and when the wideband prescaler works in the 4/5 frequency division ratio mode, and when the frequency division mode control signal is at a low level, the wideband prescaler works in a 4 frequency division mode; when the frequency division mode control signal is at a high level, the broadband prescaler works in a frequency division mode of 5;
when the band selection signal is at a high level, the wideband prescaler works in an 8/9 frequency division ratio mode, and when the wideband prescaler works in the 8/9 frequency division ratio mode, the wideband prescaler works in an 8 frequency division mode when the frequency division mode control signal is at a low level; when the frequency division mode control signal is at a high level, the broadband prescaler works in a frequency division mode of 9.
5. The wideband prescaler of claim 1, further comprising: a post-stage circuit; the rear-stage circuit is connected with the fourth end of the first trigger.
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| CN202023289828.3U CN218549895U (en) | 2020-12-31 | 2020-12-31 | Broadband prescaler |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112511157A (en) * | 2020-12-31 | 2021-03-16 | 麦堆微电子技术（上海）有限公司 | Broadband prescaler |
| CN112511157B (en) * | 2020-12-31 | 2024-05-17 | 麦堆微电子技术（上海）有限公司 | Broadband prescaler |
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2020
- 2020-12-31 CN CN202023289828.3U patent/CN218549895U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112511157A (en) * | 2020-12-31 | 2021-03-16 | 麦堆微电子技术（上海）有限公司 | Broadband prescaler |
| CN112511157B (en) * | 2020-12-31 | 2024-05-17 | 麦堆微电子技术（上海）有限公司 | Broadband prescaler |
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