CN218415792U - Semiconductor circuit having a plurality of transistors - Google Patents

Abstract

The utility model discloses a semiconductor circuit, this semiconductor circuit include HVIC chip, three-phase drive circuit, sampling circuit, fortune circuit, first filter circuit and second filter circuit, three-phase drive circuit includes U looks drive unit, V looks drive unit and W looks drive unit, U looks drive unit, V looks drive unit and W looks drive unit divide equally respectively with HVIC chip, sampling circuit, fortune circuit and first filter circuit electricity are connected; the operational amplifier circuit is also electrically connected with the HVIC chip, the first filter circuit and the second filter circuit respectively; the first filter circuit is electrically connected with the HVIC chip and the sampling circuit respectively. The utility model discloses a function of semiconductor circuit current protection.

Description

Semiconductor circuit having a plurality of transistors

Technical Field

The utility model relates to a semiconductor circuit technical field, concretely relates to semiconductor circuit.

Background

The semiconductor circuit is a power driving product combining power electronics and integrated circuit technology, integrates an intelligent control IC, high-power devices for power output such as an IGBT, a MOSFET and an FRD and a plurality of resistance-capacitance elements, and the devices are welded on an aluminum PCB through tin-based solder.

MCU among the current external control circuit can't acquire three-phase current real-time value and judge when motor current is too low among the semiconductor circuit, then can open the normal drive logic of motor, and the duty cycle of continuous increase PWM leads to motor actual current constantly to increase, makes semiconductor circuit damage easily.

SUMMERY OF THE UTILITY MODEL

A primary object of the present invention is to provide a semiconductor circuit to solve the problem of the conventional semiconductor circuit being damaged by excessive current.

In order to achieve the above object, the present invention provides a semiconductor circuit, which includes an HVIC chip, a three-phase driving circuit, a sampling circuit, an operational amplifier circuit, a first filter circuit and a second filter circuit, wherein the three-phase driving circuit includes a U-phase driving unit, a V-phase driving unit and a W-phase driving unit, and the U-phase driving unit, the V-phase driving unit and the W-phase driving unit are electrically connected to the HVIC chip, the sampling circuit, the operational amplifier circuit and the first filter circuit, respectively; the operational amplifier circuit is also electrically connected with the HVIC chip, the first filter circuit and the second filter circuit respectively; the first filter circuit is electrically connected with the HVIC chip and the sampling circuit respectively.

Preferably, the operational amplifier circuit includes an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor, wherein an IN + end of the operational amplifier is connected to the U-phase driving unit, the V-phase driving unit, the W-phase driving unit, the first filter circuit and the sampling circuit through the first resistor, an IN + end of the operational amplifier is electrically connected to a VCC end of the operational amplifier through the second resistor, an IN + end of the operational amplifier is electrically connected to a GND terminal of the operational amplifier through the third resistor, an IN-end of the operational amplifier is electrically connected to the sampling circuit through the fourth resistor, a VCC end of the operational amplifier is electrically connected to the HVIC chip, an OUT end of the operational amplifier is electrically connected to an IN-end of the operational amplifier through the fifth resistor, an OUT end of the operational amplifier is electrically connected to a GND terminal of the second filter circuit, and an OUT end of the operational amplifier is electrically connected to the second filter circuit.

Preferably, the second filter circuit includes a sixth resistor and a first capacitor, one end of the sixth resistor is electrically connected to the OUT terminal of the operational amplifier, the other end of the sixth resistor serves as an output terminal, one end of the first capacitor is electrically connected to the sixth resistor, and the other end of the first capacitor is electrically connected to the HVIC chip and the GND terminal of the operational amplifier, respectively.

Preferably, the first filter circuit includes a seventh resistor and a second capacitor, one end of the seventh resistor is electrically connected to the first resistor, the sampling circuit, the U-phase driving unit, the V-phase driving unit, and the W-phase driving unit, respectively, and the other end of the seventh resistor is electrically connected to the HVIC chip and is also electrically connected to the HVIC chip through the second capacitor.

Preferably, the sampling circuit includes an eighth resistor, one end of the eighth resistor is electrically connected to the first resistor, the first filter circuit, the U-phase driving unit, the V-phase driving unit, and the W-phase driving unit, respectively, and the other end of the eighth resistor is electrically connected to the fourth resistor.

Preferably, the HVIC chip has twenty-six pins, a first pin and a second pin of the twenty-six pins are used for inputting a first supply voltage, and the second pin is further electrically connected with the first filter circuit; third pins to eighth pins of the twenty-six pins are used for inputting PWM wave signals; a ninth pin of the twenty-six pins is used for outputting fault data; a tenth pin of the twenty-six pins is used for setting fault message data output interval time; an eleventh pin and a twelfth pin of the twenty-six pins are used for outputting temperature data; the thirteenth pin to the fifteenth pin, the seventeenth pin to the nineteenth pin and the twenty first pin to the twenty third pin of the twenty six pins are used for being electrically connected with the three-phase driving circuit; a fourteenth pin, an eighteenth pin and a twenty-second pin of the twenty-six pins are used for inputting a second power supply voltage; a twenty-fifth pin of the twenty-six pins is electrically connected with the first filter circuit; and a twenty-sixth pin of the twenty-six pins is electrically connected with the operational amplifier circuit.

Preferably, the semiconductor circuit further includes a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor, two ends of the third capacitor are electrically connected to the first pin and the second pin of the twenty-six pins, two ends of the fourth capacitor are electrically connected to the fourteenth pin and the sixteenth pin of the twenty-six pins, two ends of the fifth capacitor are electrically connected to the eighteenth pin and the twenty-six pin, and two ends of the sixth capacitor are electrically connected to the twenty-second pin and the twenty-fourth pin of the twenty-six pins.

Preferably, a power supply unit, an undervoltage power protection unit, a high-side driving unit, a functional unit, a delay unit, an overcurrent protection unit, an interlock and dead zone unit, and a low-side driving unit are integrated in the HVIC chip, the power supply unit is electrically connected with the undervoltage power protection unit, the high-side driving unit, and the overcurrent protection unit, the high-side driving unit is electrically connected with the functional unit, the overcurrent protection unit, the interlock and dead zone unit, and the low-side driving unit, the functional unit is further electrically connected with the delay unit, and the interlock and dead zone unit is further electrically connected with the low-side driving unit.

Preferably, the semiconductor circuit further comprises a PCB and a plurality of pins disposed on the PCB, and the HVIC chip, the three-phase driving circuit, the sampling circuit, the operational amplifier circuit, the first filter circuit and the second filter circuit are all disposed on the PCB and electrically connected to the corresponding pins.

Preferably, the PCB is rectangular, the length of the PCB is 38 ± 0.2mm, the width of the PCB is 20 ± 0.2mm, twenty two pins are arranged on the PCB, the first pin to the fourteenth pin of the twenty two pins are located on one side of the PCB and are sequentially arranged at intervals of 2.54 ± 0.2mm, the fifteenth pin to the twenty two pins are located on the other side of the PCB, and the fifteenth pin and the sixteenth pin of the twenty two pins are spaced at intervals of 6 ± 0.2mm, the sixteenth pin and the seventeenth pin of the twenty two pins are spaced at intervals of 6 ± 0.2mm, the seventeenth pin and the eighteenth pin of the twenty two pins are spaced at intervals of 4 ± 0.2mm, the eighteenth pin and the nineteenth pin of the twenty two pins are spaced at intervals of 6 ± 0.2mm, the nineteenth pin and the twenty second pin are spaced at intervals of 4 ± 0.2mm, and the twenty second pin are spaced at intervals of 6 ± 0.2mm.

The embodiment of the utility model provides a semiconductor circuit, the first filter circuit of current input through sampling circuit collection three-phase drive circuit carries out filtering processing, then inputs the current signal after will handling to HVIC chip to be convenient for utilize HVIC chip to input the break-make of three-phase circuit PWM ripples according to current signal control. Meanwhile, the current of the three-phase driving circuit is collected through the sampling circuit and input into the operational amplifier circuit for amplification, and then the current signal is output to an external MCU after being processed through the second filter circuit, so that the external MCU can control the operation of the whole device conveniently, and the current protection function of the semiconductor circuit is realized.

Drawings

FIG. 1 is a schematic diagram of a semiconductor circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another embodiment of a semiconductor circuit according to the present invention;

FIG. 3 is a schematic diagram of the HVIC chip shown in FIG. 2;

FIG. 4 is a schematic diagram of an internal module of the HVIC chip shown in FIG. 3;

FIG. 5 is a schematic diagram of a semiconductor circuit according to another embodiment of the present invention;

fig. 6 is a schematic structural diagram of another embodiment of a semiconductor circuit according to the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present invention, and should not be construed as limiting the present invention, and all other embodiments obtained by those skilled in the art without creative efforts based on the embodiments of the present invention belong to the protection scope of the present invention.

The utility model provides a semiconductor circuit is one kind and is in the same place power switch device and high voltage drive circuit etc. are integrated to carry out the circuit module of seal package in the surface, use extensively in the power electronics field, use like fields such as driving motor's converter, various inverter voltage, variable frequency speed governing, metallurgical machinery, electric traction, frequency conversion household electrical appliances. The semiconductor circuit may be referred to by various other names, such as a Modular Intelligent Power System (MIPS), an Intelligent Power Module (IPM), or a hybrid integrated circuit, a Power semiconductor module, a Power module, and so on. In the following embodiments of the present invention, it is collectively referred to as a Modular Intelligent Power System (MIPS).

The utility model provides a modularization intelligent power system, as shown in fig. 1 and fig. 2, this modularization intelligent power system includes HVIC chip 10, three-phase drive circuit 20, sampling circuit 30, fortune circuit 40, first filter circuit 50 and second filter circuit 60, three-phase drive circuit 20 includes U looks drive unit 21, V looks drive unit 22 and W looks drive unit 23, U looks drive unit 21, V looks drive unit 22 and W looks drive unit 23 equally divide respectively with HVIC chip 10, sampling circuit 30, fortune circuit 40 and first filter circuit 50 electricity be connected; the operational amplifier circuit 40 is also electrically connected with the HVIC chip 10, the first filter circuit 50 and the second filter circuit 60, respectively; the first filter circuit 50 is electrically connected to the HVIC chip 10 and the sampling circuit 30, respectively.

In this embodiment, the three-phase drive circuit 20 may be arranged by referring to the existing form, for example, the U-phase drive unit 21 includes a U-phase upper arm and a U-phase lower arm, the V-phase drive unit 22 includes a V-phase upper arm and a V-phase lower arm, and the W-phase drive unit 23 includes a W-phase upper arm and a W-phase lower arm. The upper bridge arm and the lower bridge arm of each phase comprise an IGBT and an FRD, the C ends of the upper bridge arm of the U phase, the upper bridge arm of the V phase and the upper bridge arm of the W phase are all connected to one point to form a P end of the modular intelligent power system, the G ends and the E ends of the upper bridge arm of the U phase, the upper bridge arm of the V phase and the upper bridge arm of the W phase, and the G ends of the lower bridge arm of the U phase, the lower bridge arm of the V phase and the lower bridge arm of the W phase are all electrically connected with an HVIC chip 10, the E ends of the lower bridge arm of the U phase, the lower bridge arm of the V phase and the lower bridge arm of the W phase are all connected with one point to be electrically connected with one end of a sampling circuit 30, and the other end of the sampling circuit 30 forms an N end of the modular intelligent power system. At this time, one end of the second filter circuit 60 serves as an output terminal so as to output the collected current information. In this embodiment, the sampling circuit 30 collects the current of the three-phase driving circuit 20 and inputs the current into the first filter circuit 50 for filtering, and then inputs the processed current signal into the HVIC chip 10, so that the HVIC chip 10 can control the on/off of the PWM wave input to the three-phase circuit according to the current signal. Meanwhile, the current of the three-phase driving circuit 20 collected by the sampling circuit 30 is input into the operational amplifier circuit 40 for amplification, and then is processed by the second filter circuit 60, so that a corresponding current signal can be output to an external MCU, the external MCU can control the operation of the whole device conveniently, and the function of semiconductor circuit current protection is realized.

IN a preferred embodiment, as shown IN fig. 2, the operational amplifier circuit 40 preferably includes an operational amplifier U1, a first resistor R2, a second resistor R3, a third resistor R4, a fourth resistor R7 and a fifth resistor R6, an IN + terminal of the operational amplifier U1 is electrically connected to the U-phase driving unit 21, the V-phase driving unit 22, the W-phase driving unit 23, the first filter circuit 50 and the sampling circuit 30 through the first resistor R2, an IN + terminal of the operational amplifier U1 is also electrically connected to a VCC terminal of the operational amplifier U1 through the second resistor R3, the IN + terminal of the operational amplifier U1 is also electrically connected to a GND terminal of the operational amplifier U1 through the third resistor R4, the IN-terminal of the operational amplifier U1 is electrically connected to the sampling circuit 30 through the fourth resistor R7, a VCC terminal of the operational amplifier U1 is electrically connected to the HVIC chip 10, an OUT terminal of the operational amplifier U1 is also electrically connected to a GND terminal of the operational amplifier U1 through the fifth resistor R6, an OUT terminal of the operational amplifier U1 is also electrically connected to the second filter circuit 60, and a GND terminal of the operational amplifier U1 is also electrically connected to the second filter circuit 60. The signal of the operational amplifier U1 and the resistances of the first resistor R2, the second resistor R3, the third resistor R4, the fourth resistor R7, and the fifth resistor R6 may be selected according to actual situations, which is not limited herein, and the specific connection manner may refer to fig. 2.

In a preferred embodiment, as shown in fig. 2, it is preferable that the second filter circuit 60 includes a sixth resistor R5 and a first capacitor C4, one end of the sixth resistor R5 is electrically connected to the OUT terminal of the operational amplifier U1, the other end of the sixth resistor R5 is used as an output terminal, one end of the first capacitor C4 is electrically connected to the sixth resistor R5, and the other end of the first capacitor C4 is electrically connected to the HVIC chip 10 and the GND terminal of the operational amplifier U1, respectively. One end of the sixth resistor R5 electrically connected to the first capacitor C4 is used as an I-IPM end of the modular intelligent power system, and the resistance of the sixth resistor R5 and the capacitance of the first capacitor C4 may be selected according to actual conditions, which are not limited herein, and as for a specific connection manner, refer to fig. 2.

In a preferred embodiment, as shown in fig. 2, it is preferable that the first filter circuit 50 includes a seventh resistor R8 and a second capacitor C5, one end of the seventh resistor R8 is electrically connected to the first resistor R2, the sampling circuit 30, the U-phase driving unit 21, the V-phase driving unit 22, and the W-phase driving unit 23, respectively, and the other end of the seventh resistor R8 is electrically connected to the HVIC chip 10 and is also electrically connected to the HVIC chip 10 through the second capacitor C5. The resistance of the seventh resistor R8 and the capacitance of the second capacitor C5 may be selected according to actual situations, and are not limited herein, as for the specific connection manner, refer to fig. 2.

In a preferred embodiment, as shown in fig. 2, the sampling circuit 30 preferably includes an eighth resistor R1, one end of the eighth resistor R1 is electrically connected to the first resistor R2, the first filter circuit 50, the U-phase driving unit 21, the V-phase driving unit 22, and the W-phase driving unit 23, respectively, and the other end of the eighth resistor R1 is electrically connected to the fourth resistor R7. One end of the eighth resistor R1 electrically connected to the fourth resistor R7 serves as an N-terminal of the modular intelligent power system, and a resistance value of the eighth resistor R1 may be selected according to an actual situation, which is not limited herein.

In a preferred embodiment, as shown in fig. 3, the HVIC chip 10 preferably has twenty-six pins, wherein a first pin and a second pin of the twenty-six pins are used for inputting the first supply voltage, and the second pin is further electrically connected to the first filter capacitor; the third pin to the eighth pin of the twenty-six pins are used for inputting PWM wave signals; a ninth pin of the twenty-six pins is used for outputting fault data; a tenth pin of the twenty-six pins is used for setting fault message data output interval time; an eleventh pin and a twelfth pin of the twenty-six pins are used for outputting temperature data; thirteenth to fifteenth pins, seventeenth to nineteenth pins, and twenty first to twenty third pins among the twenty-six pins are used for electrically connecting with the three-phase driving circuit 20; a fourteenth pin, an eighteenth pin and a twenty-second pin of the twenty-six pins are used for inputting a second power supply voltage; a twenty-fifth pin of the twenty-six pins is electrically connected with the first filter circuit 50; a twenty-sixth pin of the twenty-six pins is electrically connected to the op-amp circuit 40. The second pin is electrically connected to the second capacitor C5, preferably, the twenty-sixth pin is connected to a VCC terminal of the operational amplifier U1 to provide a voltage of 5V, the thirteenth to fifteenth pins are electrically connected to the W-phase driving unit 23, specifically, the thirteenth pin is electrically connected to a G terminal of the W-phase lower arm, the fourteenth pin is electrically connected to an E terminal of the W-phase upper arm, the fifteenth pin is electrically connected to a G terminal of the W-phase upper arm, the seventeenth to nineteenth pins are electrically connected to the V-phase driving unit 22 according to the above-mentioned form, and the twenty-first to twenty-third pins are electrically connected to the U-phase driving unit 21 according to the above-mentioned form. Meanwhile, the fourteenth pin is also used for inputting a second power supply voltage to the W-phase driving unit 23, the value of the second power supply voltage may be in a conventional form, and the eighteenth pin and the twenty-second pin may be used for inputting the second power supply voltage to the V-phase driving unit 22 and the U-phase driving unit 21, respectively, with reference to the above form.

In a preferred embodiment, as shown in fig. 2, the modular smart power system further includes a third capacitor C6, a fourth capacitor C3, a fifth capacitor C2, and a sixth capacitor C1, wherein two ends of the third capacitor C6 are electrically connected to the first pin and the second pin of the twenty-six pins, two ends of the fourth capacitor C3 are electrically connected to the fourteenth pin and the sixteenth pin of the twenty-six pins, two ends of the fifth capacitor C2 are electrically connected to the eighteenth pin and the twentieth pin of the twenty-six pins, and two ends of the sixth capacitor C1 are electrically connected to the twenty-second pin and the twenty-fourth pin of the twenty-six pins. The capacitances of the third capacitor C6, the fourth capacitor C3, the fifth capacitor C2 and the sixth capacitor C1 may be set according to actual conditions, and the fourth capacitor C3, the fifth capacitor C2 and the sixth capacitor C1 are used as bootstrap capacitors to boost the input voltage, which is not limited herein.

In a preferred embodiment, as shown in fig. 4, preferably, a power unit 11, an under-voltage power protection unit 12, a high-side driving unit 13, a functional unit 14, a delay unit 15, an over-current protection unit 16, an interlock and dead zone unit 17 and a low-side driving unit 18 are integrated inside the HVIC chip 10, the power unit 11 is electrically connected with the under-voltage power protection unit 12, the high-side driving unit 13 and the over-current protection unit 16, the high-side driving unit 13 is electrically connected with the functional unit 14, the over-current protection unit 16, the interlock and dead zone unit 17 and the low-side driving unit 18, respectively, the functional unit 14 is further electrically connected with the delay unit 15, and the interlock and dead zone unit 17 is further electrically connected with the low-side driving unit 18. The inner ends of a first pin, a second pin and a twenty-sixth pin of the twenty-six pins are respectively electrically connected with the power supply unit 11, the inner ends of a third pin to a fifth pin, a fourteenth pin to a sixteenth pin, an eighteenth pin to a twentieth pin and a twenty-second pin to a twenty-fourth pin of the twenty-six pins are respectively electrically connected with the high-side driving unit 13, the inner end of a ninth pin of the twenty-six pins is electrically connected with the functional unit 14, the inner end of a twenty-fifth pin of the twenty-six pins is electrically connected with the overcurrent protection unit 16, the inner end of a tenth pin of the twenty-six pins is electrically connected with the delay unit 15, and the sixth pin to the eighth pin, the thirteenth pin, the seventeenth pin and the twenty-first pin of the twenty-six pins are electrically connected. At this time, the power supply unit 11 supplies two voltages of 5V and 15V to all units in the whole chip and supplies 5V voltage to the current sampling circuit 30, the high-side driving unit 13 includes a high-side under-voltage protection subunit and a bootstrap subunit inside to realize a high-side driving under-voltage protection function and a bootstrap power supply function, the high-side driving unit 13 and the low-side driving unit 18 are electrically connected with each other to realize an interlocking and dead zone function with the dead zone unit 17, the power supply unit 11 is electrically connected with the power supply under-voltage protection unit 12 to realize a power supply under-voltage protection function, and the function unit 14 includes an enable subunit to realize an enable function; the overcurrent protection subunit realizes an overcurrent protection function; the overvoltage protection subunit realizes an overvoltage protection function; the over-temperature protection subunit realizes an over-temperature protection function; when the conditions such as undervoltage, overcurrent, overvoltage and overtemperature appear inside the error reporting subunit, an error reporting signal is output externally, the inner end of a twenty-fifth pin of the twenty-six pins is electrically connected with the inner end of the second pin through a ninth capacitor so as to realize a voltage pull-down function, and an IGBT grid electrode driving unit is integrated inside the chip and can be directly connected with an IGBT grid electrode, so that the area of a substrate is saved.

In a preferred embodiment, as shown in fig. 5, the modular smart power system further includes a PCB board 70 and a plurality of pins 71 disposed on the PCB board 70, and the hvic chip 10, the three-phase driving circuit 20, the sampling circuit 30, the operational amplifier circuit 40, the first filter circuit 50 and the second filter circuit 60 are all disposed on the PCB board 70 and electrically connected to the corresponding pins 71. The PCB 70 and the pins 71 may be arranged according to the conventional manner, and are not limited herein.

In a preferred embodiment, as shown in fig. 5 and 6, it is preferable that the PCB board 70 is rectangular, the length of the PCB board 70 is 38 ± 0.2mm, the width of the PCB board 70 is 20 ± 0.2mm, twenty-two pins are provided on the PCB board 70, a first pin to a fourteenth pin of the twenty-two pins are located on one side of the PCB board 70 and are sequentially spaced at 2.54 ± 0.2mm intervals, a fifteenth pin to a twenty-second pin of the twenty-two pins are located on the other side of the PCB board 70, a fifteenth pin and a sixteenth pin of the twenty-two pins are spaced at 6 ± 0.2mm intervals, a sixteenth pin and a seventeenth pin of the twenty-two pins are spaced at 6 ± 0.2mm intervals, a seventeenth pin and an eighteenth pin of the twenty-two pins are spaced at 4 ± 0.2mm intervals, an eighteenth pin and a nineteenth pin of the twenty-two pins are spaced at 6 ± 0.2mm intervals, a nineteenth pin and a twenty-second pin and a twenty-0.2 mm interval of the twenty-second pin and the twenty-second pin are spaced at 4 ± 0.2mm intervals. Wherein, IGBT1, IGBT2, IGBT 3's C end is walked the line through the copper sheet and is connected once to be connected to modularization intelligent power system's sixteenth pin, and this copper sheet is walked line width more than or equal to 3mm, should walk the width as far as on the basis that PCB board 70 space allows on this copper sheet is walked the line to make things convenient for IGBT's heat dissipation. The G ends of the IGBT1, the IGBT2 and the IGBT3 are electrically connected with a twenty-third pin, a nineteenth pin and a fifteenth pin of the HVIC chip 10 through jumper wires. The lower bridge IGBT4, the IGBT5 and the IGBT6 are placed above the corresponding upper bridge IGBT, so that jumper wires connected with the C end of the IGBT4, the IGBT5 and the C end of the IGBT6 and the E end of the IGBT1, the IGBT2 and the E end of the IGBT3 are shortest respectively, the E end of the IGBT1, the IGBT2 and the IGBT3 is connected to a twenty-first pin, a nineteenth pin and a seventeenth pin of the modular intelligent power system through the jumper wires, the twenty-first pin, the nineteenth pin and the seventeenth pin of the modular intelligent power system are close to the IGBT1, the IGBT2 and the IGBT3 respectively and are arranged on the lower long side of the PCB 70, a twenty-second pin, a twenty-fifth pin and an eighteenth pin of the modular intelligent power system are arranged on the right sides of the twenty-first pin, the nineteenth pin and the seventeenth pin respectively, and are connected with the twenty-second pin, the twentieth pin and the eighteenth pin of the HVIC chip 10 through the jumper wires. The HVIC chip 10 is located in the middle of the long edge of the PCB 70, the first pin, the third pin, the ninth pin, the eleventh pin and the twelfth pin on the HVIC chip 10 are connected to the twelfth pin, the sixth pin, the fourth pin, the second pin and the first pin of the modular intelligent power system respectively through jumper wires, the pins are placed close to the IGBT6, one end of the eighth resistor R1 is connected with the E end of the IGBT6 through a wiring copper sheet, the width of the wiring copper sheet is larger than 3mm, and the inductance of the wiring is smaller than 10nH. The E ends of the IGBT4, the IGBT5 and the IGBT6 can be connected together through a jumper wire. The other end of the eighth resistor R1 is connected to the fifteenth pin of the modular smart power system through a routing copper sheet, and the width of the routing copper sheet is greater than 3mm.

The operational amplifier circuit 40 is arranged on the left side of the HVIC chip 10 and above the eighth resistor R1, one end of the first resistor R2 is connected with the eighth resistor R1 through a wiring copper sheet, the other end of the first resistor R2 is connected with the IN + end of the operational amplifier U1 and the middle connection point of the second resistor R3 and the third resistor R4, and the second resistor R3 and the third resistor R4 are divider resistors. One end of the fourth resistor R7 is connected with one end of the eighth resistor R1 through the wiring copper sheet. One end of the second resistor R3 is electrically connected to the VCC terminal of the operational amplifier U1 and the twenty-sixth pin on the HVIC chip 10 through a jumper wire. At the moment, the two wires need to be short and wide (experience is 0.6-0.8 mm), so that the impedance of the wires is reduced, and the two wires adopt differential wires. Differential signal wiring requirements:

A. isometric: equal length means that the lengths of the two lines are as long as possible, in order to ensure that the two differential signal times maintain opposite polarities. Reducing the common mode component.

B. Equal width and equal distance: the equal width means that the widths of the two signal lines need to be kept consistent, and the equal distance means that the distance between the two lines needs to be kept unchanged and kept parallel. (line width and line spacing are determined by the impedance required for the differential signal)

C. The purpose of meeting the equal-width equidistant requirements is to maintain the consistency of the differential impedance. If the widths of the two routing lines are inconsistent and the distance is short and short, the differential impedance is inconsistent, and the integrity and the time delay of the signal are affected.

D. And once the line lengths are not matched, common-mode components are introduced into differential signals to reduce the signal quality and increase the EMI besides the deviation in time sequence.

The advantage of the differential line:

A. under the condition that the coupling between the two wires of the differential line is good, when noise interference exists outside, the two wires are coupled to the differential line almost at the same time, and the receiving end only concerns the difference value of the two signals, so that the common mode noise outside can be almost completely cancelled.

B. The EMI can be effectively inhibited, and as the polarities of the two signals are opposite, the electromagnetic fields radiated by the two signals can be mutually offset, and the tighter the coupling is, the less electromagnetic energy is released to the outside.

C. The time sequence is accurately positioned, and because the switching change of the differential signal is positioned at the intersection point of two signals, the common single-ended signal is not judged by depending on two threshold voltages, the influence of the process and the temperature is small, the error on the time sequence can be reduced, and the method is more suitable for a circuit with low-amplitude signals.

One end of the eighth resistor R1 is connected to a second filter circuit 60 formed by a seventh resistor R8 and a second capacitor C5, one end of the seventh resistor R8 in the second filter circuit 60 is connected to one end of the second capacitor C5 and then electrically connected to a twenty-fifth pin of the HVIC chip 10 through a jumper wire, and the second capacitor C5 is as close as possible to the twenty-fifth pin of the HVIC chip 10.

The other end of the fourth resistor R7 is connected with one end of the fifth resistor R6 and is electrically connected with the IN-end of the operational amplifier U1 through a jumper wire, wherein the fifth resistor R6 is a feedback resistor.

The other end of the fifth resistor R6 is connected with the OUT end of the operational amplifier U1 through a jumper wire, the OUT end of the operational amplifier U1 is connected with a second filter circuit 60 formed by a sixth resistor R5 and a first capacitor C4, one end of the sixth resistor R5 in the second filter circuit 60 and one end of the first capacitor C4 are connected to a fourteenth pin of the modular intelligent power system, and the first capacitor C4 is as close to the fourteenth pin as possible. In this case, the dark areas shown in fig. 6 are copper sheets.

The above is only the part or the preferred embodiment of the present invention, no matter the characters or the drawings can not limit the protection scope of the present invention, all under the whole concept of the present invention, the equivalent structure transformation made by the contents of the description and the drawings is utilized, or the direct/indirect application in other related technical fields is included in the protection scope of the present invention.

Claims (10)

1. A semiconductor circuit is characterized by comprising an HVIC chip, a three-phase driving circuit, a sampling circuit, an operational amplifier circuit, a first filter circuit and a second filter circuit, wherein the three-phase driving circuit comprises a U-phase driving unit, a V-phase driving unit and a W-phase driving unit, and the U-phase driving unit, the V-phase driving unit and the W-phase driving unit are respectively and electrically connected with the HVIC chip, the sampling circuit, the operational amplifier circuit and the first filter circuit; the operational amplifier circuit is also electrically connected with the HVIC chip, the first filter circuit and the second filter circuit respectively; the first filter circuit is electrically connected with the HVIC chip and the sampling circuit respectively.

2. The semiconductor circuit according to claim 1, wherein the operational amplifier circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor, wherein an IN + terminal of the operational amplifier is electrically connected to the U-phase driving unit, the V-phase driving unit, the W-phase driving unit, the first filter circuit, and the sampling circuit through the first resistor, the IN + terminal of the operational amplifier is further electrically connected to a VCC terminal of the operational amplifier through the second resistor, the IN + terminal of the operational amplifier is further electrically connected to a GND terminal of the operational amplifier through the third resistor, the IN-terminal of the operational amplifier is electrically connected to the sampling circuit through the fourth resistor, the VCC terminal of the operational amplifier is electrically connected to the HVIC chip, the OUT terminal of the operational amplifier is electrically connected to the IN-terminal of the operational amplifier through the fifth resistor, the OUT terminal of the operational amplifier is further electrically connected to the second filter circuit, and the GND terminal of the operational amplifier is further electrically connected to the second filter circuit.

3. The semiconductor circuit according to claim 2, wherein the second filter circuit includes a sixth resistor and a first capacitor, one end of the sixth resistor is electrically connected to an OUT terminal of the operational amplifier, the other end of the sixth resistor serves as an output terminal, one end of the first capacitor is electrically connected to the sixth resistor, and the other end of the first capacitor is electrically connected to GND terminals of the HVIC chip and the operational amplifier, respectively.

4. The semiconductor circuit according to claim 2, wherein the first filter circuit includes a seventh resistor and a second capacitor, one end of the seventh resistor is electrically connected to the first resistor, the sampling circuit, the U-phase drive unit, the V-phase drive unit, and the W-phase drive unit, respectively, and the other end of the seventh resistor is electrically connected to the HVIC chip and is also electrically connected to the HVIC chip through the second capacitor.

5. The semiconductor circuit according to claim 2, wherein the sampling circuit includes an eighth resistor, one end of the eighth resistor is electrically connected to the first resistor, the first filter circuit, the U-phase drive unit, the V-phase drive unit, and the W-phase drive unit, respectively, and the other end of the eighth resistor is electrically connected to the fourth resistor.

6. The semiconductor circuit according to claim 1, wherein the HVIC chip has twenty-six pins, a first pin and a second pin of the twenty-six pins are used for inputting a first supply voltage, and the second pin is further electrically connected with the first filter circuit; a third pin to an eighth pin of the twenty-six pins are used for inputting PWM wave signals; a ninth pin of the twenty-six pins is used for outputting fault data; a tenth pin of the twenty-six pins is used for setting fault message data output interval time; an eleventh pin and a twelfth pin of the twenty-six pins are used for outputting temperature data; the thirteenth pin to the fifteenth pin, the seventeenth pin to the nineteenth pin and the twenty first pin to the twenty third pin of the twenty-six pins are used for being electrically connected with the three-phase driving circuit; a fourteenth pin, an eighteenth pin and a twenty-second pin of the twenty-six pins are used for inputting a second power supply voltage; a twenty-fifth pin of the twenty-six pins is electrically connected with the first filter circuit; and a twenty-sixth pin of the twenty-six pins is electrically connected with the operational amplifier circuit.

7. The semiconductor circuit according to claim 6, further comprising a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor, wherein two ends of the third capacitor are electrically connected to the first pin and the second pin of the twenty-six pins, respectively, two ends of the fourth capacitor are electrically connected to the fourteenth pin and the sixteenth pin of the twenty-six pins, two ends of the fifth capacitor are electrically connected to the eighteenth pin and the twentieth pin of the twenty-six pins, respectively, and two ends of the sixth capacitor are electrically connected to the twenty-second pin and the twenty-fourth pin of the twenty-six pins, respectively.

8. The semiconductor circuit according to claim 1, wherein a power supply unit, an under-voltage power supply protection unit, a high-side driving unit, a functional unit, a delay unit, an over-current protection unit, an interlock and dead zone unit, and a low-side driving unit are integrated inside the HVIC chip, the power supply unit is electrically connected to the under-voltage power supply protection unit, the high-side driving unit, the functional unit, the interlock and dead zone unit, and the low-side driving unit, the high-side driving unit is electrically connected to the functional unit, the over-current protection unit, the interlock and dead zone unit, and the low-side driving unit, respectively.

9. The semiconductor circuit according to claim 1, further comprising a PCB board and a plurality of pins disposed on the PCB board, wherein the HVIC chip, the three-phase driving circuit, the sampling circuit, the operational amplifier circuit, the first filter circuit and the second filter circuit are all located on the PCB board and electrically connected to the corresponding pins.

10. The semiconductor circuit according to claim 9, wherein the PCB is rectangular, the length of the PCB is 38 ± 0.2mm, the width of the PCB is 20 ± 0.2mm, twenty two pins are provided on the PCB, a first pin to a fourteenth pin of the twenty two pins are located on one side of the PCB and sequentially arranged at intervals of 2.54 ± 0.2mm, a fifteenth pin to a twenty second pin of the twenty two pins are located on the other side of the PCB, and a fifteenth pin and a sixteenth pin of the twenty two pins are spaced at intervals of 6 ± 0.2mm, a sixteenth pin and a seventeenth pin of the twenty two pins are spaced at intervals of 6 ± 0.2mm, a seventeenth pin and an eighteenth pin of the twenty two pins are spaced at intervals of 4 ± 0.2mm, an eighteenth pin of the twenty two pins is spaced at intervals of 6 ± 0.2mm from a nineteenth pin, and a nineteenth pin of the twenty two pins is spaced at intervals of 4 ± 0.2mm from the twenty second pin, and the twenty second pin is spaced at intervals of 6 ± 0.2mm from the twenty second pin and the twenty second pin.

Images