CN217279309U - High-speed network card - Google Patents
High-speed network card Download PDFInfo
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- CN217279309U CN217279309U CN202123319867.8U CN202123319867U CN217279309U CN 217279309 U CN217279309 U CN 217279309U CN 202123319867 U CN202123319867 U CN 202123319867U CN 217279309 U CN217279309 U CN 217279309U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The utility model discloses a high-speed network card, including communication circuit, a plurality of power supply circuit and chronogenesis management circuit. The communication circuit is used for communicating with the equipment terminal. The output ends of the plurality of power supply circuits are connected with the communication circuit, and the plurality of power supply circuits are used for outputting different power supply voltages to the communication circuit. The time sequence management circuit is provided with a plurality of power supply time sequence control ends, the power supply time sequence control ends are connected with the power supply circuits in a one-to-one correspondence mode, and the time sequence management circuit is used for outputting a plurality of time sequence control signals so as to control the power supply circuits to output power supply voltage according to a preset time sequence. The utility model discloses a time schedule management circuit control is a plurality of power supply circuit realizes more accurate time schedule control according to predetermineeing chronogenesis work.
Description
Technical Field
The utility model relates to a time sequence control, concretely relates to high-speed network card.
Background
In an internal circuit of the high-speed network card, for example, a complex integrated circuit or system such as a switching chip, a Central Processing Unit (CPU) chip, and the like, a plurality of power supply voltages are required to optimize performance and reduce power consumption. However, the user must apply these power supply voltages to the devices and power them up and down in a predetermined sequence to prevent damage to the devices. To implement the power management, many comparators, resistors, capacitors, timers and logic devices are used, which takes a lot of time in design, occupies a space of a circuit board, and increases the circuit cost.
The existing high-speed network card controls the time sequence of a plurality of power supply circuits by configuring capacitors on corresponding pins of a time sequence management chip, but the capacitors and other components are greatly influenced by environmental factors such as temperature and the like, so that the time sequence control is inaccurate.
SUMMERY OF THE UTILITY MODEL
The utility model mainly aims at providing a high-speed network card aims at realizing more accurate sequential control.
In order to achieve the above object, the utility model provides a high-speed network card, high-speed network card includes:
a communication circuit for communicating with a device terminal;
a plurality of power supply circuits, output terminals of which are connected to the communication circuit, for outputting different supply voltages to the communication circuit;
the time sequence management circuit is provided with a plurality of power supply time sequence control ends, the plurality of power supply time sequence control ends are connected with the plurality of power supply circuits in a one-to-one correspondence mode, and the time sequence management circuit is used for outputting a plurality of time sequence control signals so as to control the plurality of power supply circuits to output power supply voltage according to a preset time sequence.
In one embodiment, the timing management circuit includes a timing management chip;
the time sequence management chip is provided with a plurality of power supply time sequence control ends, and the plurality of power supply time sequence control ends of the time sequence management chip are connected with the plurality of power supply circuits in a one-to-one correspondence mode.
In one embodiment, the timing management chip is an SLG46824DS chip.
In one embodiment, the high-speed network card further comprises a communication interface;
the communication interface is used for being connected with an equipment terminal, the time sequence management circuit is also provided with a communication end, and the communication end of the time sequence management circuit is electrically connected with the communication interface.
In one embodiment, the communication circuit includes a control circuit, a signal transmitting circuit, and a signal receiving circuit;
the control circuit is provided with a plurality of power supply input ends, a first communication end and a second communication end, and the plurality of power supply input ends of the control circuit are connected with the plurality of power supply circuits in a one-to-one correspondence manner;
the signal transmitting circuit is provided with a power supply input end, a signal transmitting end and a signal receiving end, the power supply input end of the signal transmitting circuit is connected with a corresponding power circuit, the signal receiving end of the signal transmitting circuit is connected with the first communication end of the control circuit, and the signal transmitting end of the signal transmitting circuit is electrically connected with the communication interface;
the signal receiving circuit is provided with a power supply input end, a signal sending end and a signal receiving end, the power supply input end of the signal receiving circuit is connected with a corresponding power circuit, the signal receiving end of the signal transmitting circuit is electrically connected with the communication interface, and the signal transmitting end of the signal transmitting circuit is connected with the second communication end of the control circuit;
the signal receiving circuit is used for receiving a communication signal of an equipment terminal and outputting the communication signal to the control circuit, and the signal transmitting circuit is used for receiving the communication signal of the control circuit and outputting the communication signal to the equipment terminal.
In one embodiment, the high-speed network card further comprises a plurality of functional interfaces;
the functional interface is used for accessing a functional circuit;
the time sequence management circuit is also provided with a plurality of control signal output ends, the control signal output ends of the time sequence management circuit are connected with the functional interfaces in a one-to-one correspondence mode, and the time sequence management circuit is further used for outputting control signals to the functional interfaces.
In one embodiment, the high-speed network card further comprises a power supply circuit;
the time sequence management circuit is also provided with a power supply input end, the input end of the power supply circuit is used for being connected with a power supply, the output end of the power supply circuit is connected with the power supply input end of the time sequence management circuit, and the power supply circuit is used for converting power supply voltage into first voltage.
In one embodiment, the high-speed network card further includes:
a module cage;
the communication circuit, the plurality of power supply circuits, the timing management circuit and the power supply circuit are arranged on the circuit board;
the communication interface is arranged on the module cage, and the circuit board is accommodated in the module cage.
The utility model discloses a time sequence management circuit control is a plurality of power supply circuit realizes more accurate time sequence control according to predetermineeing chronogenesis work. The time delay of a plurality of time sequence control ports can be flexibly configured by modifying the operation program of the time sequence communication circuit. Hardware does not need to be replaced when the time sequence design is changed, and debugging is simple. The utility model discloses the components and parts that need are few, and are with low costs, can effectively shorten development cycle, reduce the development input.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of the high-speed network card of the present invention;
fig. 2 is a schematic structural diagram of the communication circuit of the present invention;
fig. 3 is a schematic structural diagram of a timing management circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first power circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a second power circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a third power circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a fourth power circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a control circuit according to an embodiment of the present invention.
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front, rear … …) in the embodiments of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory to each other or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, the present invention provides a high-speed network card, which includes a communication circuit 10, a plurality of power circuits 20 and a timing management circuit 30.
The communication circuit 10 is used for communicating with a device terminal.
The output terminals of the plurality of power supply circuits 20 are connected to the communication circuit 10, and the plurality of power supply circuits 20 are configured to output different supply voltages to the communication circuit 10.
The timing management circuit 30 includes a plurality of power timing control terminals, the plurality of power timing control terminals are connected to the plurality of power circuits 20 in a one-to-one correspondence manner, and the timing management circuit 30 is configured to output a plurality of timing control signals to control the plurality of power circuits 20 to output a power supply voltage according to a preset timing.
In an embodiment, the high-speed network card specifically includes a first power circuit, a second power circuit, a third power circuit, and a fourth power circuit. The first power supply circuit is used for outputting 3.3V power supply voltage, the second power supply circuit 0 is used for outputting 1.8V power supply voltage, the third power supply circuit is used for outputting 1.1V power supply voltage, and the fourth power supply circuit is used for outputting 0.9V power supply voltage.
The high-speed network card has higher requirement on the time sequence accuracy. The utility model discloses a time delay of a plurality of sequential control ends of sequential management circuit 30 configuration, and then control a plurality of power supply circuit 20 is according to the electric work on the predetermined chronogenesis. The voltage detection circuit is not required to detect whether the power supply circuit 20 is powered on for operation. The timing management circuit 30 adopts an internal clock technology, and the delay precision can reach ns level. When the time sequence design needs to be changed, the time sequence design code is burned again, and hardware does not need to be replaced.
The utility model discloses a time sequence management circuit control is a plurality of power supply circuit realizes more accurate time sequence control according to predetermineeing chronogenesis work. By modifying the operation program of the time sequence communication circuit, the time delay of a plurality of time sequence control ports can be flexibly configured. When the time sequence design is changed, hardware does not need to be replaced, and debugging is simple. The utility model discloses the components and parts that need are few, and are with low costs, can effectively shorten development cycle, reduce the development input.
In one embodiment, the timing management circuit 30 includes a timing management chip U1.
The timing management chip U1 has a plurality of power timing control terminals, and the plurality of power timing control terminals of the timing management chip U1 are connected to the plurality of power circuits 20 in a one-to-one correspondence.
In this embodiment, the timing management chip U1 configures delays of a plurality of timing control terminals to control timings of the plurality of power supply circuits 20, thereby implementing more accurate timing control and reducing hardware cost.
In one embodiment, the timing management chip U1 is an SLG46824DS chip.
In one embodiment, the high-speed network card also includes a communication interface 40.
The communication interface 40 is used for connecting with a device terminal, the timing management circuit 30 further has a communication end, and the communication end of the timing management circuit 30 is electrically connected with the communication interface 40.
The timing management circuit 30 is connected to the device terminal through the communication interface 40 to implement power supply and signal transmission functions of the timing management circuit 30.
In one embodiment, the communication circuit 10 includes a control circuit 11, a signal transmitting circuit 12, and a signal receiving circuit 13.
The control circuit 11 has a plurality of power supply input terminals, a first communication terminal and a second communication terminal, and the plurality of power supply input terminals of the control circuit 11 are connected to the plurality of power supply circuits 20 in a one-to-one correspondence.
The signal transmitting circuit 12 has a power supply input end, a signal transmitting end and a signal receiving end, the power supply input end of the signal transmitting circuit 12 is connected with the corresponding power circuit 20, the signal receiving end of the signal transmitting circuit 12 is connected with the first communication end of the control circuit 11, and the signal transmitting end of the signal transmitting circuit 12 is electrically connected with the communication interface 40.
The signal receiving circuit 13 has a power supply input terminal, a signal transmitting terminal and a signal receiving terminal, the power supply input terminal of the signal receiving circuit 13 is connected to the corresponding power circuit 20, the signal receiving terminal of the signal transmitting circuit 12 is electrically connected to the communication interface 40, and the signal transmitting terminal of the signal transmitting circuit 12 is connected to the second communication terminal of the control circuit 11.
The signal receiving circuit 13 is configured to receive a communication signal of an equipment terminal and output the communication signal to the control circuit 11, and the signal transmitting circuit 12 is configured to receive the communication signal of the control circuit 11 and output the communication signal to the equipment terminal.
In an embodiment, the timing management circuit 30 further has a power state output terminal, and the control circuit 11 further has a power state receiving terminal, and the power state output terminal of the timing management circuit 30 is connected to the power state receiving terminal of the control circuit 11. The timing management circuit 30 is further configured to output a power status signal according to a preset timing, and the control circuit 11 is further configured to start operating after receiving the power status signal.
In an embodiment, the high-speed network card further includes a plurality of functional interfaces.
The functional interface is used for accessing a functional circuit.
The timing management circuit 30 further has a plurality of control signal output ends, the plurality of control signal output ends of the timing management circuit 30 are connected to the plurality of functional interfaces in a one-to-one correspondence manner, and the timing management circuit 30 is further configured to output control signals to the plurality of functional interfaces.
In the embodiment, a plurality of functional interfaces are arranged, and a user can install a functional module, such as an optical module, according to requirements. The timing management circuit 30 is further configured to output a control signal to a plurality of the functional interfaces, for example, control power supply and power off to the functional interfaces according to a preset requirement.
In this embodiment, a plurality of function interfaces are provided, so that a user can install a corresponding function module by himself, and realize related functions by cooperation of the timing management circuit 30, which is highly flexible.
In an embodiment, the high-speed network card further includes a power supply circuit.
The timing management circuit 30 further has a power supply input end, the input end of the power supply circuit is used for accessing a power supply, the output end of the power supply circuit is connected with the power supply input end of the timing management circuit 30, and the power supply circuit is used for converting a power supply voltage into a first voltage.
In one embodiment, the high-speed network card further comprises a module cage and a circuit board.
The communication circuit 10, the plurality of power supply circuits 20, the timing management circuit 30, and the power supply circuit are disposed on the circuit board.
The communication interface 40 is provided on the module cage, and the circuit board is housed in the module cage.
The above is only the optional embodiment of the present invention, and not therefore the scope of the present invention is limited, all the equivalent structure changes made by the contents of the specification and the drawings are utilized under the inventive concept of the present invention, or the application directly/indirectly in other related technical fields are included in the patent protection scope of the present invention.
Claims (8)
1. A high-speed network card, comprising:
a communication circuit for communicating with a device terminal;
a plurality of power supply circuits, output terminals of which are connected to the communication circuit, the plurality of power supply circuits being configured to output different supply voltages to the communication circuit;
the time sequence management circuit is provided with a plurality of power supply time sequence control ends, the plurality of power supply time sequence control ends are connected with the plurality of power supply circuits in a one-to-one correspondence mode, and the time sequence management circuit is used for outputting a plurality of time sequence control signals so as to control the plurality of power supply circuits to output power supply voltage according to a preset time sequence.
2. The high-speed network card of claim 1, wherein the timing management circuit comprises a timing management chip;
the time sequence management chip is provided with a plurality of power supply time sequence control ends, and the plurality of power supply time sequence control ends of the time sequence management chip are connected with the plurality of power supply circuits in a one-to-one correspondence mode.
3. The high-speed network card of claim 2, wherein the timing management chip is an SLG46824DS chip.
4. The high-speed network card of claim 1, wherein the high-speed network card further comprises a communication interface;
the communication interface is used for being connected with an equipment terminal, the time sequence management circuit is also provided with a communication end, and the communication end of the time sequence management circuit is electrically connected with the communication interface.
5. The high-speed network card of claim 4, wherein the communication circuit comprises a control circuit, a signal transmitting circuit and a signal receiving circuit;
the control circuit is provided with a plurality of power supply input ends, a first communication end and a second communication end, and the plurality of power supply input ends of the control circuit are connected with the plurality of power supply circuits in a one-to-one correspondence manner;
the signal transmitting circuit is provided with a power supply input end, a signal transmitting end and a signal receiving end, the power supply input end of the signal transmitting circuit is connected with a corresponding power circuit, the signal receiving end of the signal transmitting circuit is connected with the first communication end of the control circuit, and the signal transmitting end of the signal transmitting circuit is electrically connected with the communication interface;
the signal receiving circuit is provided with a power supply input end, a signal sending end and a signal receiving end, the power supply input end of the signal receiving circuit is connected with the corresponding power circuit, the signal receiving end of the signal sending circuit is electrically connected with the communication interface, and the signal sending end of the signal sending circuit is connected with the second communication end of the control circuit;
the signal receiving circuit is used for receiving a communication signal of an equipment terminal and outputting the communication signal to the control circuit, and the signal transmitting circuit is used for receiving the communication signal of the control circuit and outputting the communication signal to the equipment terminal.
6. The high-speed network card of claim 1, wherein the high-speed network card further comprises a plurality of functional interfaces;
the functional interface is used for accessing a functional circuit;
the time sequence management circuit is also provided with a plurality of control signal output ends, the control signal output ends of the time sequence management circuit are connected with the functional interfaces in a one-to-one correspondence mode, and the time sequence management circuit is further used for outputting control signals to the functional interfaces.
7. The high-speed network card of claim 4, wherein the high-speed network card further comprises a power supply circuit;
the time sequence management circuit is also provided with a power supply input end, the input end of the power supply circuit is used for being connected with a power supply, the output end of the power supply circuit is connected with the power supply input end of the time sequence management circuit, and the power supply circuit is used for converting power supply voltage into first voltage.
8. The high-speed network card of claim 7, wherein the high-speed network card further comprises:
a module cage;
the communication circuit, the plurality of power supply circuits, the timing management circuit and the power supply circuit are arranged on the circuit board;
the communication interface is arranged on the module cage, and the circuit board is contained in the module cage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123319867.8U CN217279309U (en) | 2021-12-27 | 2021-12-27 | High-speed network card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123319867.8U CN217279309U (en) | 2021-12-27 | 2021-12-27 | High-speed network card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217279309U true CN217279309U (en) | 2022-08-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123319867.8U Active CN217279309U (en) | 2021-12-27 | 2021-12-27 | High-speed network card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217279309U (en) |
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2021
- 2021-12-27 CN CN202123319867.8U patent/CN217279309U/en active Active
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