CN216623246U - Chip and mainboard - Google Patents
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- CN216623246U CN216623246U CN202123388117.6U CN202123388117U CN216623246U CN 216623246 U CN216623246 U CN 216623246U CN 202123388117 U CN202123388117 U CN 202123388117U CN 216623246 U CN216623246 U CN 216623246U
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Abstract
The utility model provides a chip and a mainboard, wherein the chip comprises: the chip comprises a communication pin, a receiving circuit, a sending circuit and a digital circuit, wherein the communication pin is used for connecting other chips, the receiving circuit is connected with the communication pin, and the sending circuit is connected with the communication pin; the digital circuit is connected with the receiving circuit and the transmitting circuit. The receiving circuit is used for converting the first communication signals sent by other chips into communication signals which can be identified by the digital circuit and sending the communication signals to the digital circuit; the transmitting circuit is used for converting the second communication signal transmitted by the digital circuit into a communication signal which can be identified by other chips and transmitting the communication signal to other chips. The receiving circuit and the transmitting circuit can enable the chip to accurately identify the first communication signals transmitted by other chips and transmit the second communication signals according with the power supply voltages of other chips, and meanwhile, the circuit cost can be reduced.
Description
Technical Field
The utility model relates to the technical field of electronic circuits, in particular to a chip and a mainboard.
Background
In system-level applications of integrated circuits, IC, it is common to involve communication between multiple chips. Different chips adopt different manufacturing processes, and the chips at different positions pursue different performance indexes, so that the power supply voltages required by the chips are different. On many motherboards, two chips communicating use different power supply voltages, and the amplitude of the communication signal sent by the chip is related to the power supply voltage of the chip. If the chip with lower power supply voltage sends a communication signal to the chip with higher power supply voltage, the risk that the chip with higher power supply voltage cannot identify the communication signal is easily caused; if the voltage chip with higher supply voltage sends a communication signal to the chip with lower supply voltage, the communication signal is easy to damage the voltage chip with lower supply voltage.
The existing solution is to add a level conversion chip between two chips, as shown in fig. 1, the power supply voltage of the a chip is 1.2V, and the amplitude of the signal a output by the a chip is 1.2V. The power supply voltage of the chip B is 5V, the amplitude of a signal B output by the chip B is 5V, the signal A output by the chip A and the signal B output by the chip B are subjected to level conversion through the level conversion chip, the area cost and the material cost of a circuit can be increased, and extra power consumption can be brought.
SUMMERY OF THE UTILITY MODEL
The utility model mainly aims to provide a chip, which aims to reduce the circuit cost and can accurately identify signals sent by other chips and send signals according with the power supply voltage of other chips.
In a first aspect, the present invention provides a chip, comprising:
the communication pin is used for connecting other chips;
the receiving circuit is connected with the communication pin, and the sending circuit is connected with the communication pin;
the digital circuit is connected with the receiving circuit and the transmitting circuit, and the receiving circuit is used for converting the first communication signal transmitted by the other chip into a communication signal which can be identified by the digital circuit and transmitting the communication signal to the digital circuit; the transmitting circuit is used for converting the second communication signal transmitted by the digital circuit into a communication signal which can be identified by the other chip and transmitting the communication signal to the other chip.
In one embodiment, the receiving circuit includes a comparator; a first input end of the comparator is connected with the communication pin and used for receiving first communication signals sent by other chips; the second input end of the comparator is used for receiving a reference voltage signal, and the output end of the comparator is connected with the digital circuit;
the comparator is used for generating a communication signal which can be identified by the digital circuit according to the reference voltage signal and the first communication signal.
In one embodiment, the receiving circuit further comprises a glitch filter connected between the output of the comparator and the digital circuit; the burr filter is used for filtering burr signals in the communication signals output by the comparator.
In one embodiment, the glitch filter includes a delay circuit and a phase follower circuit;
the input end of the delay circuit is connected with the output end of the comparator and is used for delaying the communication signal output by the comparator so as to output a delayed signal;
the phase following circuit is connected with the output end of the delay circuit and the output end of the comparator, and is used for filtering the communication signal output by the comparator according to the delay signal and sending the communication signal to the digital circuit.
In one embodiment, the transmit circuit includes a digital buffer;
the input end of the digital buffer is connected with the first output end of the digital circuit, the power supply end of the digital buffer is used for receiving power supply voltage, and the output end of the digital buffer is used for being connected with the communication pin;
the digital buffer is used for generating communication signals which can be identified by other chips according to the power supply voltage and the second communication signals.
In one embodiment, the enable terminal of the digital buffer is connected to the second output terminal of the digital circuit, and is configured to receive an enable signal; the enable signal is used for controlling the digital buffer to be in a high impedance state or a low impedance state.
In one embodiment, the chip further comprises a reference voltage circuit; the input end of the reference voltage circuit is connected with a preset voltage source;
a first output end of the reference voltage circuit is connected with a second input end of the comparator and used for outputting a reference voltage signal to the second input end of the comparator;
the second output end of the reference voltage circuit is connected with the power supply end of the digital buffer and used for providing the power supply voltage for the power supply end of the digital buffer.
In an embodiment, the control terminal of the reference voltage circuit is connected to the third output terminal of the digital circuit, and the third output terminal of the digital circuit is configured to output a voltage adjustment signal;
the voltage adjusting signal is used for adjusting the reference voltage signal so as to enable the reference voltage signal to be matched with the corresponding amplitude of the second communication signal;
the voltage adjustment signal is further configured to adjust the power supply voltage such that the power supply voltage matches a corresponding amplitude of the first communication signal.
In a second aspect, an embodiment of the present invention further provides a motherboard, including the chip according to any one of the embodiments.
In an embodiment, the motherboard further includes another chip, and the another chip is connected to the chip through a bus.
The utility model provides a chip and a mainboard, wherein the chip comprises a communication pin, a receiving circuit, a sending circuit and a digital circuit, the communication pin is used for connecting other chips, the receiving circuit is connected with the communication pin, and the sending circuit is connected with the communication pin; the digital circuit is connected with the receiving circuit and the transmitting circuit. The receiving circuit is used for converting the first communication signals sent by other chips into communication signals which can be identified by the digital circuit and sending the communication signals to the digital circuit; the transmitting circuit is used for converting the second communication signal transmitted by the digital circuit into a communication signal which can be identified by other chips and transmitting the communication signal to other chips. The receiving circuit and the transmitting circuit can enable the chip to accurately identify the first communication signals transmitted by other chips and transmit the second communication signals according with the power supply voltages of other chips, and a level conversion chip is not required to be arranged, so that the circuit cost and the circuit size can be reduced, and the power consumption can be reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a circuit diagram of an embodiment of a chip provided in an embodiment of the present application;
FIG. 2 is a circuit diagram of an embodiment of a chip according to an embodiment of the present disclosure;
FIG. 3 is a circuit diagram of another embodiment of a chip provided by an embodiment of the present application;
FIG. 4 is a circuit diagram of another embodiment of a chip provided by an embodiment of the present application;
FIG. 5 is a circuit diagram of another embodiment of a chip provided by an embodiment of the present application;
FIG. 6 is a circuit diagram of another embodiment of a chip provided by an embodiment of the present application;
FIG. 7 is a circuit diagram of another embodiment of a chip provided by an embodiment of the present application;
fig. 8 is a schematic structural diagram of a main board provided in an embodiment of the present application;
fig. 9 is another schematic structural diagram of the motherboard according to the embodiment of the present application.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Referring to fig. 2, fig. 2 is a circuit diagram of an embodiment of a chip according to an embodiment of the present disclosure.
As shown in fig. 2, the chip includes a communication pin 110, a receiving circuit 120, a transmitting circuit 130, and a digital circuit 140. The communication pin 110 is used for connecting other chips, the receiving circuit 120 is connected with the communication pin 110, and the sending circuit 130 is connected with the communication pin 110; the digital circuit 140 is connected to the receiving circuit 120 and the transmitting circuit 130. The receiving circuit 120 is configured to convert the first communication signal sent by the other chip into a communication signal that can be recognized by the digital circuit 140 and send the communication signal to the digital circuit 140; the transmission circuit 130 is configured to convert the second communication signal transmitted by the digital circuit 140 into a communication signal that can be recognized by another chip and transmit the communication signal to the other chip. The chip can accurately identify the first communication signals sent by other chips through the receiving circuit and the sending circuit, and send the second communication signals which accord with the power supply voltages of other chips.
It should be noted that, compared with the circuit shown in fig. 1, the receiving circuit 120 and the transmitting circuit 130 of the present embodiment are integrated inside a chip, and a level conversion chip is not required to be additionally provided, so that the circuit cost and the circuit volume can be reduced, and the power consumption can be effectively reduced.
In an embodiment, as shown in fig. 2, an input end (end a) of the receiving circuit 120 is connected to the communication pin 110, the communication pin 110 is configured to receive a first communication signal sent by another chip, the receiving circuit 120 is configured to perform level conversion on the first communication signal sent by the other chip to obtain a communication signal that can be recognized by the digital circuit 140, and the digital circuit 140 is configured to control the sending circuit 130 to be in a High impedance state (High impedance); an output terminal (terminal C) of the receiving circuit 120 is connected to the digital circuit 140 for transmitting a communication signal that can be recognized by the digital circuit 140 to the digital circuit 140.
As shown in fig. 2, the input end (D end) of the transmitting circuit 130 is connected to the digital circuit 140, the digital circuit 140 can transmit the second communication signal to another chip, and the transmitting circuit 130 is configured to perform level conversion on the second communication signal transmitted by the digital circuit 140 to obtain a communication signal that can be recognized by another chip; an output terminal (terminal B) of the transmitting circuit 130 is connected to the communication pin 110, and is used for transmitting a communication signal that can be recognized by another chip to the other chip through the communication pin 110.
In one embodiment, the communication pins 110 may be one or more. Illustratively, when there is one communication pin 110, the communication pin 110 is connected to the input terminal of the receiving circuit 120 and the output terminal of the transmitting circuit 130; when there are two communication pins 110, one of the communication pins 110 is connected to the input terminal of the receiving circuit 120, and the other communication pin 110 is connected to the output terminal of the transmitting circuit 130; when there are a plurality of communication pins 110, each communication pin 110 can be connected to other chips; it is understood that the other chips may be one or more.
Illustratively, the supply voltage of the other chip connected to the communication pin 110 is lower than that of the chip, and the amplitude of the signal on the communication pin 110 is consistent with that of the other chip. When the chip sends the second communication signal, the input end A of the receiving circuit is in a High impedance state (High impedance), which indicates that the input end A of the receiving circuit has relatively higher impedance relative to other end points in the circuit, and the quality of the second communication signal is ensured; when the chip receives the first communication signal sent by other chips, the output end B of the sending circuit is in a high-impedance state, and the output end B of the sending circuit has relatively higher impedance compared with other end points in the circuit, so that the quality of the first communication signal is not influenced.
As shown in fig. 2, the digital circuit 140 is a circuit for performing arithmetic operation and logic operation on digital quantities by using digital signals inside a chip. The digital circuit 140 includes a plurality of logic gates, which are basic elements of the digital circuit. The digital circuit 140 has logic operation and logic processing functions, and is also called a digital logic circuit. Alternatively, digital circuit 140 is constructed from several digitally integrated devices fabricated in semiconductor processes.
In one embodiment, as shown in fig. 3, the receiving circuit 120 includes a comparator 121, and the comparator 121 is, for example, a voltage comparator, and includes a same-direction comparator and an inverse-direction comparator. In an integrated circuit, the input of comparator 121 is the gate of a CMOS device and therefore assumes a high impedance state.
A first input end of the comparator 121 is connected to the communication pin 110, and the comparator 121 is configured to receive a first communication signal sent by the other chip; a second input of the comparator 121 is configured to receive a reference voltage signal, and an output of the comparator 121 is connected to the digital circuit 140.
The function of the comparator 121 includes generating an input signal for the digital circuit 140, and a power supply terminal of the comparator 121 is connected to a power supply voltage of the digital circuit 140, so that the comparator 121 can output a communication signal that can be recognized by the digital circuit 140. Specifically, the comparator 121 is configured to generate a communication signal that can be identified by the digital circuit 140 according to the reference voltage signal and the first communication signal, and send the communication signal to the digital circuit 140, where a supply voltage of the digital circuit 140 is, for example, 5V.
Illustratively, the magnitude Vr of the reference voltage signal may be determined according to the magnitude of the first communication signal transmitted by other chips, for example, the magnitude of the reference signal is 1/2 of the magnitude of the first communication signal, so that the detection point of the comparator 121 on the first communication signal is guaranteed to be exactly half of the magnitude of the first communication signal, and thus the comparator 121 identifies that the communication signal has the best anti-noise capability and communication signal quality.
Illustratively, the comparator 121 is a homodromous comparator, a non-inverting input terminal of which is connected to the communication pin 110, and an inverting input terminal of which is used for receiving a reference voltage signal. Assuming that the amplitude of the first communication signal input to the non-inverting input terminal is 1.2V and the amplitude Vr of the reference voltage signal is 0.6V which is a half of 1.2V, the amplitude of the communication signal output from the output terminal of the homodyne comparator to the digital circuit 140 is a voltage amplitude recognizable by the digital circuit 140, for example, 5V.
It should be noted that the power supply of the comparator 121 is the power supply of the chip, and the advantage of using the comparator 121 in the receiving circuit 120 is that: 1. the comparator 121 has high precision and has good identification capability for very low signal amplitude; 2. the comparator 121 has stable performance and has more stable detection capability compared with a schmitt trigger or an inverter under different process deviations, temperature deviations and voltage deviations.
In one embodiment, the comparator 121 is a hysteresis comparator, which can enhance its noise immunity.
In one embodiment, as shown in fig. 4, the receiving circuit 120 further includes a glitch filter 122, wherein the glitch filter 122 is connected between the output terminal of the comparator 121 and the digital circuit 140; the spur filter 122 is configured to filter a spur signal in the communication signal output by the comparator 121.
It should be noted that, the glitch filter 122 is connected to the output end of the comparator 121, and since the comparator 121 is sensitive, a small glitch on the external signal may also be identified, so that a glitch filter 122 is added to the output end of the comparator 121, which can filter out a signal glitch with a fixed width, and ensure the signal quality.
Illustratively, as shown in fig. 5, the glitch filter 122 includes a delay circuit and a phase follower circuit; the input end of the delay circuit is connected to the output end of the comparator 121, and is configured to delay the communication signal output by the comparator 121 to output a delayed signal; the phase follower circuit is connected to the output end of the delay circuit and the output end of the comparator 121, and is configured to filter the communication signal output by the comparator 121 according to the delay signal and send the filtered communication signal to the digital circuit 140.
As shown in fig. 5, if the phase of the communication signal received by the phase follower circuit at the current time is the same as the phase of the delayed signal, the communication signal output by the phase follower circuit is the filtered communication signal, and if the phase of the communication signal received by the phase follower circuit at the current time is opposite to the phase of the delayed signal, the communication signal output by the phase follower circuit is the same as the communication signal output at the previous time. Therefore, the glitch filter 122 can stably implement the glitch filtering, and simplify the structure of the glitch filter 122 to reduce the occupied space.
Exemplarily, the delay circuit includes a charge-discharge module and an inversion module, the charge-discharge module includes a capacitor unit and a charge-discharge unit connected to the capacitor unit, and the charge-discharge unit is connected to an output end of the comparator 121 and is configured to charge and discharge the capacitor unit according to a communication signal output by the comparator 121; the input end of the turnover module is connected with the capacitor unit, the output end of the turnover module is connected with the phase following circuit, and the turnover module is used for outputting the delay signal according to the voltage of the input end.
In one embodiment, as shown in fig. 6, the transmitting circuit 130 includes a digital buffer 131, and the digital buffer 131 is, for example, a single-input logic gate with logic gates isolated from each other or used for driving and switching higher than normal loads.
Wherein, the input end of the digital buffer 131 is connected to the first output end of the digital circuit 140, the power supply end of the digital buffer 131 is used for receiving a power supply voltage, and the output end of the digital buffer 131 is used for being connected to the communication pin 110; the digital buffer 131 is configured to generate a communication signal that can be recognized by the other chip according to the power supply voltage and the second communication signal. The transmitting circuit may be implemented by a digital buffer 131, the amplitude of the second communication signal output by the digital circuit 140 is the power supply voltage of the chip, and the digital buffer 131 can convert the amplitude of the second communication signal voltage into the voltage amplitude of the communication signal that can be recognized by other chips.
For example, the amplitude of the power voltage received by the power supply terminal of the digital buffer 131 may be determined according to the amplitude of the first communication signal sent by the other chip, for example, the amplitude of the power voltage is equal to the amplitude of the first communication signal, and the communication signal sent by the digital buffer 131 can be successfully identified by the other chip without the occurrence of a chip damage event. Optionally, the amplitude of the reference voltage signal is Vr, and the amplitude of the power supply voltage is 2 Vr.
In one embodiment, as shown in fig. 6, the enable terminal of the digital buffer 131 is connected to the second output terminal of the digital circuit 140; the enable terminal of the digital buffer 131 is configured to receive an enable signal, and the enable signal is used to control the digital buffer 131 to be in a high impedance state or a low impedance state.
Illustratively, the enable signal includes a first enable signal and a second enable signal, the second output of the digital circuit 140 is configured to output the first enable signal when the communication pin 110 transmits the first communication signal, and the first enable signal is configured to control the output of the digital buffer 131 to be in a high impedance state; the second output terminal of the digital circuit 140 is further configured to output a second enable signal when the digital circuit 140 sends the second communication signal, and the second enable signal is used to control the output terminal of the digital buffer 131 to be in a low impedance state.
It should be noted that, when the chip receives a signal, the output terminal of the digital buffer 131 is in a high impedance state, and therefore, the quality of the first communication signal received on the communication pin is not affected. When the chip transmits the second communication signal, since the output terminal of the digital buffer 131 is in the low impedance state, the input terminal of the receiving circuit is in the high impedance state, and therefore the quality of the transmitted second communication signal is not affected.
Illustratively, as shown in fig. 6, when the receiving circuit includes the comparator 121 and the transmitting circuit includes the digital buffer 131, it can recognize and transmit a communication signal lower than the power supply voltage of the present chip. For example, the supply voltage of the other chips is 1.2V, and the amplitude of the first communication signal output by the other chips is 1.2V. The power supply voltage of the chip is 5V, and the amplitude of the second communication signal output by the chip is 5V. Based on the circuit diagram of the chip shown in fig. 6, the first communication signal with lower voltage sent by another chip can be directly received and identified by the chip, and the second communication signal with lower voltage sent by the chip can also be directly received by another chip.
In one embodiment, as shown in FIG. 7, the chip further includes a reference voltage circuit 150; the input end of the reference voltage circuit 150 is connected with a preset voltage source; a first output terminal of the reference voltage circuit 150 is connected to a second input terminal of the comparator 121, and is configured to output a reference voltage signal to the second input terminal of the comparator 121; a second output terminal of the reference voltage circuit 150 is connected to the power supply terminal of the digital buffer 131, and is configured to provide the power supply voltage to the power supply terminal of the digital buffer 131.
The voltage of the preset voltage source may be set according to an actual situation, for example, the voltage of the preset voltage source is a supply voltage of the chip, and the voltage of the preset voltage source may be greater than or equal to the supply voltage of the other chips. A first output terminal of the reference voltage circuit 150 is configured to output a reference voltage signal to a second input terminal of the comparator 121, where the amplitude of the reference voltage signal may be half of the supply voltage of the chip; the second output terminal of the reference voltage circuit 150 is configured to provide the power supply voltage to the power supply terminal of the digital buffer 131, and the magnitude of the power supply voltage may be the power supply voltage of another chip or equal to the voltage magnitude of the first communication signal output by another chip.
Illustratively, the control terminal of the reference voltage circuit 150 is connected to a third output terminal of the digital circuit 140, and the third output terminal of the digital circuit 140 is used for outputting a voltage adjustment signal; the voltage adjusting signal is used for adjusting the reference voltage signal so as to enable the reference voltage signal to be matched with the corresponding amplitude of the second communication signal and enable the second communication signal to be converted into a communication signal which can be identified by the digital circuit; the voltage adjusting signal is further configured to adjust the power supply voltage, so that the power supply voltage matches with a corresponding amplitude of the first communication signal, and the first communication signal is converted into a communication signal that can be recognized by the other chips.
For example, the voltage adjustment signal includes an amplitude corresponding to the second communication signal, and the control end of the reference voltage circuit 150 adjusts the reference voltage signal output by the first output end of the reference voltage circuit 150 according to the voltage adjustment signal after receiving the voltage adjustment signal, so that the amplitude of the reference voltage signal is the amplitude corresponding to the second communication signal; for example, the voltage adjustment signal includes an amplitude corresponding to the first communication signal, and the control terminal of the reference voltage circuit 150 adjusts the power supply voltage output by the first output terminal of the reference voltage circuit 150 according to the voltage adjustment signal after receiving the voltage adjustment signal, so that the amplitude of the reference voltage signal is the amplitude corresponding to the first communication signal.
The chip according to the above embodiment includes a communication pin 110, a receiving circuit 120, a transmitting circuit 130, and a digital circuit 140. The communication pin 110 is used for connecting other chips, the receiving circuit 120 is connected with the communication pin 110, and the sending circuit 130 is connected with the communication pin 110; the digital circuit 140 is connected to the receiving circuit 120 and the transmitting circuit 130. The receiving circuit 120 is configured to convert the first communication signal sent by the other chip into a communication signal that can be recognized by the digital circuit 140 and send the communication signal to the digital circuit 140; the transmitting circuit 130 is configured to convert the second communication signal transmitted by the digital circuit 140 into a communication signal that can be recognized by the other chip and transmit the communication signal to the other chip. The receiving circuit 120 and the transmitting circuit 130 can enable the chip to accurately identify the first communication signal transmitted by other chips and transmit the second communication signal according with the power supply voltage of other chips, and a level conversion chip is not required, so that the circuit cost and the circuit volume can be reduced, and the power consumption can be reduced.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a motherboard according to an embodiment of the present disclosure.
As shown in fig. 8, the main board 200 includes: chip 201, chip 201 includes communication pin, receiving circuit, transmitting circuit and digital circuit. The chip 201 may be the chip shown in fig. 2 to 7 in the foregoing embodiments.
In an embodiment, as shown in fig. 9, the motherboard 200 further includes another chip 202, and the another chip 202 is connected to the chip 201 through a bus 203. For example, the other chips 202 are connected to the communication pins of the chip 201 via a bus 203.
In the motherboard 200 according to the above embodiment, the chip 201 in the motherboard 200 includes a communication pin, a receiving circuit, a transmitting circuit, and a digital circuit, the communication pin is used to connect to another chip 202, the receiving circuit is connected to the communication pin, and the transmitting circuit is connected to the communication pin; the digital circuit is connected with the receiving circuit and the transmitting circuit. The receiving circuit is used for converting the first communication signal sent by the other chip 202 into a communication signal which can be identified by the digital circuit and sending the communication signal to the digital circuit; the transmitting circuit is configured to convert the second communication signal transmitted by the digital circuit into a communication signal that can be recognized by the other chip 202 and transmit the communication signal to the other chip. The chip 201 can accurately identify the first communication signals sent by other chips 202 through the receiving circuit and the sending circuit, and send the second communication signals according with the power supply voltages of other chips 202, without setting a level conversion chip, so that the circuit cost and the circuit volume can be reduced, and the power consumption can be reduced.
In the description of the present application, it is to be noted that the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected unless otherwise explicitly stated or limited. Either mechanically or electrically. Either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The above disclosure provides many different embodiments or examples for implementing different structures of the application. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
In the description herein, references to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above embodiments are only preferred embodiments of the present application, and the protection scope of the present application is not limited thereto, and any insubstantial changes and substitutions made by those skilled in the art based on the present application are intended to be covered by the present application.
Claims (10)
1. A chip, wherein the chip comprises:
the communication pin is used for connecting other chips;
the receiving circuit is connected with the communication pin, and the sending circuit is connected with the communication pin;
the digital circuit is connected with the receiving circuit and the transmitting circuit, and the receiving circuit is used for converting the first communication signal transmitted by the other chip into a communication signal which can be identified by the digital circuit and transmitting the communication signal to the digital circuit; the transmitting circuit is used for converting the second communication signal transmitted by the digital circuit into a communication signal which can be identified by the other chip and transmitting the communication signal to the other chip.
2. The chip of claim 1, wherein the receive circuit comprises a comparator; a first input end of the comparator is connected with the communication pin and used for receiving first communication signals sent by other chips; the second input end of the comparator is used for receiving a reference voltage signal, and the output end of the comparator is connected with the digital circuit;
the comparator is used for generating a communication signal which can be identified by the digital circuit according to the reference voltage signal and the first communication signal.
3. The chip of claim 2, wherein the receive circuit further comprises a glitch filter connected between the output of the comparator and the digital circuit; the burr filter is used for filtering burr signals in the communication signals output by the comparator.
4. The chip of claim 3, wherein the glitch filter includes a delay circuit and a phase follower circuit;
the input end of the delay circuit is connected with the output end of the comparator and is used for delaying the communication signal output by the comparator so as to output a delayed signal;
the phase following circuit is connected with the output end of the delay circuit and the output end of the comparator, and is used for filtering the communication signal output by the comparator according to the delay signal and sending the communication signal to the digital circuit.
5. The chip of claim 2, wherein the transmit circuit comprises a digital buffer;
the input end of the digital buffer is connected with the first output end of the digital circuit, the power supply end of the digital buffer is used for receiving power supply voltage, and the output end of the digital buffer is used for being connected with the communication pin;
the digital buffer is used for generating communication signals which can be identified by other chips according to the power supply voltage and the second communication signals.
6. The chip of claim 5, wherein the enable terminal of the digital buffer is connected to the second output terminal of the digital circuit for receiving an enable signal; the enable signal is used for controlling the digital buffer to be in a high impedance state or a low impedance state.
7. The chip of claim 5, wherein the chip further comprises a reference voltage circuit; the input end of the reference voltage circuit is connected with a preset voltage source;
a first output end of the reference voltage circuit is connected with a second input end of the comparator and used for outputting a reference voltage signal to the second input end of the comparator;
and the second output end of the reference voltage circuit is connected with the power supply end of the digital buffer and is used for supplying the power supply voltage to the power supply end of the digital buffer.
8. The chip of claim 7, wherein the control terminal of the reference voltage circuit is connected to a third output terminal of the digital circuit, the third output terminal of the digital circuit being configured to output a voltage adjustment signal;
the voltage adjusting signal is used for adjusting the reference voltage signal so as to enable the reference voltage signal to be matched with the corresponding amplitude of the second communication signal;
the voltage adjustment signal is further configured to adjust the power supply voltage such that the power supply voltage matches a corresponding amplitude of the first communication signal.
9. A motherboard comprising a chip as claimed in any one of claims 1 to 8.
10. The motherboard of claim 9, further comprising other chips, the other chips connected to the chips by a bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123388117.6U CN216623246U (en) | 2021-12-29 | 2021-12-29 | Chip and mainboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123388117.6U CN216623246U (en) | 2021-12-29 | 2021-12-29 | Chip and mainboard |
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| CN216623246U true CN216623246U (en) | 2022-05-27 |
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| CN202123388117.6U Active CN216623246U (en) | 2021-12-29 | 2021-12-29 | Chip and mainboard |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116165510A (en) * | 2022-12-29 | 2023-05-26 | 无锡晟朗微电子有限公司 | Communication device for chip test |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116165510A (en) * | 2022-12-29 | 2023-05-26 | 无锡晟朗微电子有限公司 | Communication device for chip test |
| CN116165510B (en) * | 2022-12-29 | 2023-11-24 | 无锡晟朗微电子有限公司 | Communication device for chip test |
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