CN203930404U - A kind of novel master control borad circuit - Google Patents
A kind of novel master control borad circuit Download PDFInfo
- Publication number
- CN203930404U CN203930404U CN201320609586.2U CN201320609586U CN203930404U CN 203930404 U CN203930404 U CN 203930404U CN 201320609586 U CN201320609586 U CN 201320609586U CN 203930404 U CN203930404 U CN 203930404U
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- chip
- master control
- control borad
- borad circuit
- fpga chip
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Abstract
The utility model provides a kind of novel master control borad circuit, it comprises the fpga chip as mutual core, as the dsp chip at calculation process center with as the ARM chip of function control center, described fpga chip is connected with described dsp chip and described ARM chip communication respectively, by the master control borad of the multiple processor structure based on fpga chip, dsp chip and ARM chip, can make full use of the performance advantage of each processor, improve the ability of computing, IO expansion, function control and the extensibility of control panel; In addition, by a power transfer module is set, can directly connect external power source, outside can be accessed to power supply and be converted to fpga chip, dsp chip and the required Power Level of ARM chip difference.
Description
Technical field
The utility model relates to electric and electronic technical field, in particular, relates to a kind of novel master control borad circuit.
Background technology
High voltage converter, SVG(Static Var Generator, static reacance generator), the power electronic equipment such as photovoltaic DC-to-AC converter is because its electric pressure is high, power is large, therefore the power unit module structures that adopt more, this structure adopts the mode of cascade of power units, power ratio control unit carries out directly link, due to high, easy to maintenance being widely used of the degree of modularity of this structure.Adopting cascade of power units mode to control needs master control borad to possess a large amount of IO interfaces, power electronic equipment has higher computing ability because the complicacy of its control needs master control borad, for improving the automaticity of power electronic equipment, controller also needs to possess abundant peripheral interface and carries out the expansion of function simultaneously.
At present, the single dsp processor structure adopting or DSP+CPLD, DSP+FPGA architecture mode, because the IO quantity of these several architecture modes is few or expanded function is not enough and cannot reach requirement, therefore, a kind of novel master control borad circuit is provided, realizing the novel master control borad circuit that arithmetic capability is powerful, logic control can be expanded, peripheral function is abundant, is those skilled in the art's problem demanding prompt solutions.
Utility model content
In view of this, the utility model provides a kind of novel master control borad circuit, to realize the problem that arithmetic capability is powerful, logic control can be expanded, peripheral function is abundant.
For achieving the above object, the utility model provides following technical scheme:
A kind of novel master control borad circuit, described master control borad circuit comprises the fpga chip as mutual core, and as the dsp chip at calculation process center with as the ARM chip of function control center, described fpga chip is connected with described dsp chip and described ARM chip communication respectively, wherein
Described fpga chip is realized the data real-time, interactive transmission between described dsp chip and described fpga chip, described dsp chip and described ARM chip, described FGPA chip and described ARM chip, described master control borad circuit and power unit module, expanding communication optical fiber IO interface, receive and process the real-time information of uploading, power ratio control unit module output PWM waveform, the failure message that fast processing holding circuit collects;
Described dsp chip is responsible for the work of external control analog acquisition, and completes real-time control algolithm high-speed computation work;
Described ARM chip is responsible for the collecting work of the control of power electronic equipment external switch, logical signal, the judgement of system logic function and work for the treatment of and peripheral communications Function Extension.
Preferably, described master control borad circuit also comprises power transfer module, and outside input power is converted to described fpga chip, described dsp chip and the required Power Level of described ARM chip difference by described power transfer module.
Preferably, described master control borad circuit also comprises and described dsp chip communication connection, gathers the A/D module of external control analog quantity.
Preferably, described master control borad circuit also comprises and described fpga chip communication connection, the Fiber Optic Extension plate of expansion Fiber Optic Extension interface.
Wherein, on described Fiber Optic Extension plate, be provided with at least one Fiber Optic Extension interface.
Preferably, described master control borad circuit also comprises and described fpga chip communication connection, the hardware fault detecting is fed back to the protection module of described fpga chip.
Preferably, described master control borad circuit also comprises with described ARM chip communication and being connected, realize RS485 communication RS485 module, realize the ethernet communication module of ethernet communication, IO expansion board and the expansion board of communicating by letter of expansion interface.
Wherein, in described IO expansion board, be provided with at least one IO expansion interface, in described communication expansion board, be provided with at least one communication expansion interface.
Wherein, described ethernet communication module is connected with display device, the amendment of master control borad circuit parameter described in described display device control, checks and record.
Known via above-mentioned technical scheme, compared with prior art, the utility model openly provides a kind of novel master control borad circuit, it comprises the fpga chip as mutual core, as the dsp chip at calculation process center with as the ARM chip of function control center, described fpga chip is connected with described dsp chip and described ARM chip communication respectively, by based on fpga chip, the master control borad of the multiple processor structure of dsp chip and ARM chip, can make full use of the performance advantage of each processor, improve the computing of control panel, IO expansion, the ability of function control and extensibility, in addition, by a power transfer module is set, can directly connect external power source, outside can be accessed to power supply and be converted to fpga chip, dsp chip and the required Power Level of ARM chip difference.
Brief description of the drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment of the present utility model, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, other accompanying drawing can also be provided according to the accompanying drawing providing.
Fig. 1 is the structural representation of the disclosed a kind of novel master control borad circuit of the utility model embodiment;
Fig. 2 is the structural representation of the novel master control borad circuit of the disclosed another kind of the utility model embodiment;
Fig. 3 is the topological structure schematic diagram of the peripheral circuit of the disclosed novel master control borad circuit of the utility model embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
The utility model openly provides a kind of novel master control borad circuit, it comprises the fpga chip as mutual core, as the dsp chip at calculation process center with as the ARM chip of function control center, described fpga chip is connected with described dsp chip and described ARM chip communication respectively, by the master control borad of the multiple processor structure based on fpga chip, dsp chip and ARM chip, can make full use of the performance advantage of each processor, improve the ability of computing, IO expansion, function control and the extensibility of control panel.In addition, by a power transfer module is set, can directly connect external power source, outside can be accessed to power supply and be converted to fpga chip, dsp chip and the required Power Level of ARM chip difference.
Embodiment mono-
Referring to accompanying drawing 1, is the structural representation of the disclosed a kind of novel master control borad circuit of the utility model embodiment.The utility model embodiment discloses a kind of novel master control borad circuit, it comprises the fpga chip 101 as mutual core, as the dsp chip 102 at calculation process center with as the ARM chip 103 of function control center, described fpga chip 101 communicates to connect with described dsp chip 102 and described ARM chip 103 respectively, wherein, fpga chip 101 is realized dsp chip 102 and fpga chip 101, dsp chip 102 and ARM chip 103, FGPA chip 101 and ARM chip 103, data real-time, interactive transmission between master control borad circuit and power unit module, expanding communication optical fiber IO interface, receive and process the real-time information of uploading, power ratio control unit module output PWM waveform, the failure message that fast processing holding circuit collects, dsp chip 102 is responsible for the work of external control analog acquisition, and completes real-time control algolithm high-speed computation work, ARM chip 103 is responsible for the collecting work of the control of power electronic equipment external switch, logical signal, the judgement of system logic function and work for the treatment of and peripheral communications Function Extension.
The utility model openly provides a kind of novel master control borad circuit, by the master control borad of the multiple processor structure based on fpga chip, dsp chip and ARM chip, can make full use of the performance advantage of each processor, computing, the IO that improves control panel expands, the ability of function controlled stage extensibility.
Embodiment bis-
Referring to accompanying drawing 2, is the structural representation of the novel master control borad circuit of the disclosed another kind of the utility model embodiment.On the basis of above-described embodiment one, described master control borad circuit also comprises power transfer module 104, and outside input power is converted to described fpga chip 101, described dsp chip 102 and the required Power Level of described ARM chip 103 difference by described power transfer module 104.
Power transfer module 104 is used outside 24V, ± 15V, the input of 5V multiple power sources, and external power source is converted to the required Power Level of each control chip, for master control borad provides reliable and stable power supply, and master control borad integrated power supply modular converter.
Embodiment tri-
Concrete, refer to accompanying drawing 3, be the topological structure schematic diagram of the peripheral circuit of the disclosed novel master control borad circuit of the utility model embodiment.
On the basis of embodiment mono-or embodiment bis-, above-mentioned master control borad circuit also comprises:
Communicate to connect with dsp chip 102, gather the A/D module 105 of external control analog quantity;
Communicate to connect the Fiber Optic Extension plate 108 of expansion Fiber Optic Extension interface with fpga chip 101;
Communicate to connect with ARM chip 103, realize RS485 module 106, ethernet communication module 107, IO expansion board 109 and the expansion board 110 of communicating by letter of RS485 and ethernet communication.
Preferably, above-mentioned master control borad circuit also comprises:
With fpga chip communication connection, the hardware fault detecting is fed back to the protection module 111 of fpga chip, described protection module 111 detects the fault such as overcurrent or overvoltage of power electronic equipment.
Communicate to connect with ARM chip 103, realize RS485 module 106, ethernet communication module 107, IO expansion board 109 and the expansion board 110 of communicating by letter of RS485 and ethernet communication.
Wherein, on above-mentioned Fiber Optic Extension plate 108, be provided with at least one Fiber Optic Extension interface, in above-mentioned IO expansion board 109, be provided with at least one IO expansion interface.
Wherein, be provided with at least one communication expansion interface in described communication expansion board 110, communication expansion interface can be realized outside various communications protocols by ARM controller, and for example profibus agreement strengthens control panel and outside contiguity.
Wherein, above-mentioned ethernet communication module 107 is connected with display device 112, the amendment of display device control master control borad circuit parameter, checks and record.
Above-mentioned fpga chip is realized the data real-time, interactive transmission between dsp chip and fpga chip, dsp chip and ARM chip, fpga chip and ARM chip.Dsp chip by with A/D module high speed acquisition external analog signal, and carry out the calculating of power electronic equipment algorithm, calculate gained control signal and be issued to other modules after fpga chip decoding.And ARM chip carries out function control and the peripheral interface realization of control panel, ARM controller is connected with exterior I O expansion interface, IO expansion board comprises multiple switching signal input interfaces and relay output interface, realize control and arbitration functions to outside switchgear, carry out the operation control of power electronic equipment in conjunction with external logic state.Ethernet module is realized the communication function between external display device and control panel, display device can control parameter amendment, check and the function such as record.
The utility model openly provides a kind of novel master control borad circuit, it comprises the fpga chip as mutual core, as the dsp chip at calculation process center with as the ARM chip of function control center, described fpga chip is connected with described dsp chip and described ARM chip communication respectively, by the master control borad of the multiple processor structure based on fpga chip, dsp chip and ARM chip, can make full use of the performance advantage of each processor, improve the ability of computing, IO expansion, function control and the extensibility of control panel.
In addition, by a power transfer module is set, can directly connect external power source, outside can be accessed to power supply and be converted to fpga chip, dsp chip and the required Power Level of ARM chip difference.
To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the utility model.To be apparent for those skilled in the art to the multiple amendment of these embodiment, General Principle as defined herein can, in the situation that not departing from spirit or scope of the present utility model, realize in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (8)
1. a novel master control borad circuit, it is characterized in that, described master control borad circuit comprises the fpga chip as mutual core, as the dsp chip at calculation process center with as the ARM chip of function control center, described fpga chip is connected with described dsp chip and described ARM chip communication respectively, wherein
Described fpga chip is realized the data real-time, interactive transmission between described dsp chip and described fpga chip, described dsp chip and described ARM chip, described fpga chip and described ARM chip, described master control borad circuit and power unit module, expanding communication optical fiber IO interface, receive and process the real-time information of uploading, power ratio control unit module output PWM waveform, the failure message that fast processing holding circuit collects;
Described dsp chip is responsible for the work of external control analog acquisition, and completes real-time control algolithm high-speed computation work; Described dsp chip specifically passes through A/D module high speed acquisition external analog signal, and carries out the calculating of power electronic equipment algorithm, calculates gained control signal and be issued to other modules after fpga chip decoding;
Described ARM chip is responsible for the collecting work of the control of power electronic equipment external switch, logical signal, the judgement of system logic function and work for the treatment of and peripheral communications Function Extension, ARM controller is connected with exterior I O expansion interface, carries out function control and the peripheral interface of control panel and realizes;
Described master control borad circuit also comprises power transfer module, and outside input power is converted to described fpga chip, described dsp chip and the required Power Level of described ARM chip difference by described power transfer module.
2. master control borad circuit according to claim 1, is characterized in that, described master control borad circuit also comprises and described dsp chip communication connection, gathers the A/D module of external control analog quantity.
3. master control borad circuit according to claim 1, is characterized in that, described master control borad circuit also comprises and described fpga chip communication connection, the Fiber Optic Extension plate of expansion Fiber Optic Extension interface.
4. master control borad circuit according to claim 3, is characterized in that, is provided with at least one Fiber Optic Extension interface on described Fiber Optic Extension plate.
5. according to the master control borad circuit described in claim 1 or 3, it is characterized in that, described master control borad circuit also comprises and described fpga chip communication connection, the hardware fault detecting is fed back to the protection module of described fpga chip.
6. master control borad circuit according to claim 1, it is characterized in that, described master control borad circuit also comprises with described ARM chip communication and being connected, realize RS485 communication RS485 module, realize the ethernet communication module of ethernet communication, IO expansion board and the expansion board of communicating by letter of expansion interface.
7. master control borad circuit according to claim 6, is characterized in that, is provided with at least one IO expansion interface in described IO expansion board, is provided with at least one communication expansion interface in described communication expansion board.
8. master control borad circuit according to claim 6, is characterized in that, described ethernet communication module is connected with display device, the amendment of master control borad circuit parameter described in described display device control, checks and record.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320609586.2U CN203930404U (en) | 2013-09-29 | 2013-09-29 | A kind of novel master control borad circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320609586.2U CN203930404U (en) | 2013-09-29 | 2013-09-29 | A kind of novel master control borad circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203930404U true CN203930404U (en) | 2014-11-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320609586.2U Expired - Lifetime CN203930404U (en) | 2013-09-29 | 2013-09-29 | A kind of novel master control borad circuit |
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| CN (1) | CN203930404U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741535A (en) * | 2017-09-08 | 2018-02-27 | 山东锦华电力设备有限公司 | Sampling protection control sequential system and method based on ARM FPGA |
| CN112286104A (en) * | 2020-10-30 | 2021-01-29 | 民广电气科技有限公司 | PWM module integrated controller based on DSP |
| CN112559415A (en) * | 2020-12-02 | 2021-03-26 | 海鹰企业集团有限责任公司 | Control system of universal expansion interface |
-
2013
- 2013-09-29 CN CN201320609586.2U patent/CN203930404U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107741535A (en) * | 2017-09-08 | 2018-02-27 | 山东锦华电力设备有限公司 | Sampling protection control sequential system and method based on ARM FPGA |
| CN112286104A (en) * | 2020-10-30 | 2021-01-29 | 民广电气科技有限公司 | PWM module integrated controller based on DSP |
| CN112559415A (en) * | 2020-12-02 | 2021-03-26 | 海鹰企业集团有限责任公司 | Control system of universal expansion interface |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20141105 |
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| CX01 | Expiry of patent term |