CN202663288U - Single bridge arm drive circuit of inverter and application circuit thereof - Google Patents
Single bridge arm drive circuit of inverter and application circuit thereof Download PDFInfo
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- CN202663288U CN202663288U CN 201220234646 CN201220234646U CN202663288U CN 202663288 U CN202663288 U CN 202663288U CN 201220234646 CN201220234646 CN 201220234646 CN 201220234646 U CN201220234646 U CN 201220234646U CN 202663288 U CN202663288 U CN 202663288U
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Abstract
The application provides a single bridge arm drive circuit of an inverter. The drive circuit comprises a pulse interlock circuit which receives two ways of PWM signals, generates high-level and non-overlapped first pulse control signals and second pulse control signals, and transmits the first pulse control signals and the second pulse control signals through a first output terminal and a second output terminal respectively; and a first isolation drive circuit and a second isolation drive circuit which are connected with the first output terminal and the second output terminal of the pulse interlock circuit respectively, receive the first pulse control signals and the second pulse control signals respectively, generate first drive pulse signals and second drive pulse signals, and transmit the first drive pulse signals and the second drive pulse signals through a first output terminal and a second output terminal of the single bridge arm drive circuit of the inverter respectively. An application circuit of the single bridge arm drive circuit of the inverter is characterized by comprising at least two single bridge arm drive circuits of the inverter.
Description
Technical field
The application relates to electric and electronic technical field, particularly a kind of inverter list brachium pontis drive circuit and application circuit thereof.
Background technology
With reference to figure 1, it is that single-phase inverter adopts the topological diagram of full bridge inversion circuit, and wherein, this single-phase inverter contains two groups of bridge arm circuit, and every group of bridge arm circuit contains upper and lower two groups of device for power switching on ground altogether not.When this single-phase inverter carries out work, every group of device for power switching all needs one tunnel drive pulse signal independently, and every group of brachium pontis be inverter bridge two groups the drive pulse signal of device for power switching must be complementary up and down, high level can not appear in up and down two-way drive pulse signal simultaneously that be every group of brachium pontis, otherwise, can cause the device for power switching generation common conduct of every group of brachium pontis, be short-circuited.Therefore, the drive circuit that is used for generating drive pulse signal of every group of brachium pontis in the single-phase inverter is the key that guarantees the single-phase inverter reliability service.
At present, single-chip microcomputer inverter bridge drive circuit does not have special-purpose PWM output port cheaply, can't directly produce four road drive pulse signals that can guarantee the single-phase inverter reliability service, has reduced thus the reliability of inverter bridge.
And common single-phase inverter adopts the drive IC of the intelligent devices such as High Performance SCM, DSP, special use, can directly obtain four road pulse width modulation (PWM)s (Pulse Width Modulation) drive pulse signal by programming and drive two groups of inverter bridge, obtain desirable single-phase sinewave output waveform, but the cost of these devices is higher, is difficult to extensively use on the low power inverter of low cost.
The utility model content
The application's technical problem to be solved is, a kind of inverter list brachium pontis drive circuit and application circuit thereof are provided, single-chip microcomputer inverter bridge drive circuit does not have special-purpose PWM output port owing to have now cheaply in order to solve, can't directly produce four road drive pulse signals that can guarantee the single-phase inverter reliability service, and reduce thus the technical problem of the reliability of inverter bridge; And being used for solving existing inverter driving circuit under the prerequisite that guarantees the single-phase inverter reliability service, cost is higher, the technical problem that can't extensively use on the low power inverter of low cost.
The application provides a kind of inverter list brachium pontis drive circuit, comprising:
Receive the two-way pwm signal, generate non-overlapped the first pulse control signal and the second pulse control signal of high level, and the pulse interlock circuit that described the first pulse control signal and described the second pulse control signal are transmitted by the first output and the second output respectively;
Be connected with the second output with the first output of described pulse interlock circuit respectively, receive respectively described the first pulse control signal and described the second pulse control signal, generate the first drive pulse signal and the second drive pulse signal, and with described the first drive pulse signal and described the second drive pulse signal the first isolated drive circuit and the second isolated drive circuit that transmit of the first output and the second output by this inverter list brachium pontis drive circuit respectively.
Above-mentioned inverter list brachium pontis drive circuit, preferably, described pulse interlock circuit comprise XOR gate, first and the door and second with, wherein:
The first input end of described XOR gate is connected with described two-way pwm signal respectively with the second input;
The output of described XOR gate is connected with the first input end of door with described second with the first input end of door with described first respectively;
Described first with the door the second input with described second with the second input be connected with described two-way pwm signal respectively.
Above-mentioned inverter list brachium pontis drive circuit, preferably, described the first isolated drive circuit comprises the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the first triode T1, the second triode T2, the 3rd triode T3, the 4th triode T4, the first diode D1 and the first photoelectrical coupler N1, described the first photoelectrical coupler N1 comprises four exits, wherein:
The first output of described pulse interlock circuit links to each other with the first end of described the first triode T1 by described the first resistance R 1;
Forward input voltage VCC is connected with the first exit of described the first photoelectrical coupler N1 by described the second resistance R 2;
The second exit of described the first photoelectrical coupler N1 is connected with the second end of described the first triode T1;
The second end of described the second triode T2, the first end of described the 4th resistance R 4 are connected with the first end of described the 3rd resistance R 3, and are connected to power supply E1;
The second end of the first end of described the 3rd triode T3, described the 3rd resistance R 3 is connected with the three terminal of described the first photoelectrical coupler N1;
The second end of the 4th exit of the 3rd end of described the 3rd triode T3, described the first photoelectrical coupler N1, the anode of described the first diode D1, described the 4th triode T4 is connected, and is connected to the ground of power supply E1;
The second end of described the 4th resistance R 4, described the 3rd triode T3 the second end, the negative electrode of described the first diode D1, the first end of described the second triode T2 and the first end of described the 4th triode T4 are connected;
The ground of the 3rd termination power VCC of described the first triode T1;
The 3rd end of described the second triode T2 is connected with the 3rd end of described the 4th triode T4, and is connected with the first output of this inverter list brachium pontis drive circuit.
Above-mentioned inverter list brachium pontis drive circuit, preferably, described the second isolated drive circuit comprises the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 5th triode T5, the 6th triode T6, the 7th triode T7, the 8th triode T8, the second diode D2 and the second photoelectrical coupler N2, described the second photoelectrical coupler N2 comprises four exits, wherein:
The second output of described pulse interlock circuit links to each other with the first end of described the 5th triode T5 by described the 5th resistance R 5;
Forward input voltage VCC is connected with the first exit of described the second photoelectrical coupler N2 by described the 6th resistance R 6;
The second exit of described the second photoelectrical coupler N2 is connected with the second end of described the 5th triode T5;
The second end of described the 6th triode T6, the first end of described the 7th resistance R 7 are connected with the first end of described the 8th resistance R 8, and meet power supply E2;
The second end of the first end of described the 7th triode T7, described the 7th resistance R 7 is connected with the three terminal of described the second photoelectrical coupler N2;
The second end of the 3rd end of described the 7th triode T7, the anode of described the second diode D2, described the 8th triode T8, the 4th exit of described the second photoelectrical coupler N2 are connected, and are connected to the ground of power supply E2;
The first end of the second end of the second end of described the 8th resistance R 8, described the 7th triode T7, the negative electrode of described the second diode D2, described the 6th triode T6 and the first end of described the 8th triode T8 are connected;
The ground of the 3rd termination power VCC of described the 5th triode T5;
The 3rd end of described the 6th triode T6 is connected with the 3rd end of described the 8th triode T8, and is connected with the second output of this inverter list brachium pontis drive circuit.
Above-mentioned inverter list brachium pontis drive circuit, preferably, described the first triode T1, described the second triode T2 and described the 3rd triode T3 are the NPN triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd end is emitter.
Above-mentioned inverter list brachium pontis drive circuit, preferably, described the 4th triode T4 is the PNP triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd section is emitter.
Above-mentioned inverter list brachium pontis drive circuit, preferably, described the 5th triode T5, described the 6th triode T6 and described the 7th triode T7 are the NPN triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd end is emitter.
Above-mentioned inverter list brachium pontis drive circuit, preferably, described the 8th triode T8 is the PNP triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd section is emitter.
The application also provides a kind of application circuit of inverter list brachium pontis drive circuit, comprises at least two as the described inverter list of above-mentioned any one brachium pontis drive circuit, wherein:
Each output of described at least two single brachium pontis drive circuits is connected with the input of respectively organizing device for power switching of single-phase inverter or polyphase inverter respectively.
From the above, with respect in the prior art since cheaply single-chip microcomputer inverter bridge drive circuit do not have special-purpose PWM output port, can't directly produce four road drive pulse signals that can guarantee the single-phase inverter reliability service, the technical problem that causes thus the reliability reduction of inverter bridge, inverter list brachium pontis drive circuit and application circuit thereof that the application provides are comprised of pulse interlock circuit and isolated drive circuit, by in the pulse interlock circuit so that the two-way output signal of pulse interlock circuit again phenomenon can not occur at the high level place, realized the non-overlapped pwm signal output of two-way high level, avoided the device for power switching generation common conduct that causes when overlapping when high level occurring, thereby situation about being short-circuited has guaranteed the reliability of invertor operation.
Further, higher with respect to drive circuit cost of the prior art, the technical problem that can't use at the low power inverter of low cost, inverter list brachium pontis drive circuit and application circuit thereof that the application provides are comprised of common resistance, diode, triode and photoelectrical coupler, thus, under the prerequisite that guarantees the inverter reliability service, cost is lower, can extensive use on the low power inverter of low cost.
Certainly, arbitrary product of enforcement the application might not need to reach simultaneously above-described all advantages.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the present application, the accompanying drawing of required use was done to introduce simply during the below will describe embodiment, apparently, accompanying drawing in the following describes only is some embodiment of the application, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 adopts the topological diagram of full bridge inversion circuit for existing single-phase inverter;
The structural representation of a kind of inverter list brachium pontis drive circuit that Fig. 2 provides for the embodiment of the present application one;
Fig. 3 is the high-low level distribution schematic diagram of PWM1 signal described in the embodiment of the present application one and PWM2 signal and described PWMD1 signal and PWMD2 signal;
The part topological diagram of a kind of inverter list brachium pontis drive circuit that Fig. 4 provides for the embodiment of the present application two;
The part topological diagram of a kind of inverter list brachium pontis drive circuit that Fig. 5 provides for the embodiment of the present application three;
Another part topological diagram of a kind of inverter list brachium pontis drive circuit that Fig. 6 provides for the embodiment of the present application three;
The whole topological diagram of a kind of inverter list brachium pontis drive circuit that Fig. 7 provides for the embodiment of the present application three
Fig. 8 is the structural representation that the embodiment of the present application four is applied to single-phase inverter.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment only is the application's part embodiment, rather than whole embodiment.Based on the embodiment among the application, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the application's protection.
With reference to figure 2, it shows the structural representation of a kind of inverter list brachium pontis drive circuit that the embodiment of the present application one provides, and described inverter list brachium pontis drive circuit comprises:
Receive the two-way pwm signal, generate non-overlapped the first pulse control signal and the second pulse control signal of high level, and the pulse interlock circuit 201 that described the first pulse control signal and described the second pulse control signal are transmitted by the first output and the second output respectively;
Be connected with the second output with the first output of described pulse interlock circuit respectively, receive respectively described the first pulse control signal and described the second pulse control signal, generate the first drive pulse signal and the second drive pulse signal, and with described the first drive pulse signal and described the second drive pulse signal the first isolated drive circuit 202 and the second isolated drive circuit 203 that transmit of the first output and the second output by this inverter list brachium pontis drive circuit respectively.
Described pulse interlock circuit 201 receives after the described two-way pwm signal, utilize described two-way pwm signal to generate non-overlapped the first pulse control signal and the second pulse control signal of high level, described the first pulse control signal is transmitted by the first output, and described the second pulse control signal is transmitted by the second output.
Described the first isolated drive circuit 202 is connected with the first output of described pulse interlock circuit 201, receive described the first pulse control signal, generate the first drive pulse signal, and first output of described the first drive pulse signal by this inverter list brachium pontis drive circuit transmitted.
Described the second isolated drive circuit 203 is connected with the second output of described pulse interlock circuit 201, receive described the second pulse control signal, generate the second drive pulse signal, and second output of described the second drive pulse signal by this inverter list brachium pontis drive circuit transmitted.
Wherein, described two-way pwm signal is respectively PWM1 signal and PWM2 signal, described pulse interlock circuit 201 receives described PWM1 signal and described PWM2 signal, through after the circuit conversion, generate described the first pulse control signal and described the second pulse control signal, be PWMD1 signal and PWMD2 signal, the high level of described PWMD1 signal and described PWMD2 signal is not overlapping, and namely described two-way pulse control signal high level can not occur simultaneously.
Wherein, drive input signal is that described two-way pwm signal can come from single-chip microcomputer, can also come from analog control circuit.
For example, with reference to figure 3, it shows the high-low level distribution schematic diagram of the embodiment of the present application one described pulse interlock circuit input signal PWM1 signal and PWM2 signal and output signal PWMD1 signal and PWMD2 signal.Wherein, the corresponding described PWMD1 signal of described PWM1 signal, the corresponding described PWMD2 signal of described PWM2 signal, A place in the drawings, the PWM1 abnormal signal broadens and is overlapping with the high level of described PWM2 signal, high level namely occurs simultaneously, and PWMD1 signal and the PWMD2 signal of the output of described pulse interlock circuit are low level; B place in the drawings, interference signal appears in described PWM2 signal, and is overlapping with the high level of described PWM1 signal, high level namely occurs simultaneously, and PWMD1 signal and the PWMD2 signal of the output of described pulse interlock circuit are low level.
Need to prove that it is sinusoidal wave with photovoltaic generation that the embodiment of the present application one is applicable to square-wave inverter (modified sine wave), SPWM sinewave inverter, intelligent vehicle-mounted sine wave and family.
From the above, with respect in the prior art since cheaply single-chip microcomputer inverter bridge drive circuit do not have special-purpose PWM output port, can't directly produce four road drive pulse signals that can guarantee the single-phase inverter reliability service, the technical problem that causes thus the reliability reduction of inverter bridge, the inverter list brachium pontis drive circuit that the application provides is comprised of pulse interlock circuit and isolated drive circuit, by the pulse interlock circuit so that the two-way output signal of pulse interlock circuit again phenomenon can not occur at the high level place, realized the non-overlapped pwm signal output of two-way high level, avoided the device for power switching generation common conduct that causes when overlapping when high level occurring, thereby situation about being short-circuited has guaranteed invertor operation section reliability.
With reference to figure 4, it shows the part topological diagram of a kind of inverter list brachium pontis drive circuit that the embodiment of the present application two provides, described inverter list brachium pontis drive circuit comprises pulse interlock circuit 201, the first isolated drive circuit 202 and the second isolated drive circuit 203, wherein, described the first isolated drive circuit 202 and the second isolated drive circuit 203 are with consistent described in the embodiment of the present application one, and described pulse interlock circuit 201 comprises:
The first input end 2111 of described XOR gate 211 is connected with described two-way pwm signal respectively with the second input 2112;
The output 2113 of described XOR gate 211 is connected with the first input end 2131 of door 213 with described second with the first input end 2121 of door 212 with described first respectively;
Described first is connected with described two-way pwm signal respectively with the second input 2132 of 213 with described second with door the second input 2122 of 212.
Wherein, described first with i.e. the first output 214 of this pulse interlock circuit of door 212 output, described second with i.e. the second output 215 of this pulse interlock circuit of the output of door 213.
Wherein, a kind of two-way pwm signal of described two-way pwm signal and the embodiment of the present application is consistent, is PWM1 signal and PWM2 signal.Described PWM1 signal and PWM2 signal through described XOR gate 211, described first with the logic budget of door 212 and described second and door 213 after, output two-way pulse control signal, i.e. the first pulse control signal PMWD1 signal and the second pulse control signal PWMD2 signal, described PWMD1 signal and PWMD2 signal transmit by the first output 214 and second output 215 of described pulse interlock circuit 201 respectively.
For example, such as Fig. 3, A place in the drawings, the PWM1 abnormal signal broadens and is overlapping with the high level of described PWM2 signal, high level namely appears simultaneously, by described XOR gate, first and door and second carry out logical operation with door so that PWMD1 signal and PWMD2 signal that described pulse interlock circuit is exported are low level; B place in the drawings, interference signal appears in described PWM2 signal, overlapping with the high level of described PWM1 signal, high level namely appears simultaneously, by described XOR gate, first and door and second carry out logical operation with door so that PWMD1 signal and PWMD2 signal that described pulse interlock circuit is exported are low level.
From the above, with respect in the prior art since cheaply single-chip microcomputer inverter bridge drive circuit do not have special-purpose PWM output port, can't directly produce four road drive pulse signals that can guarantee the single-phase inverter reliability service, the technical problem that causes thus the reliability reduction of inverter bridge, the inverter list brachium pontis drive circuit that the embodiment of the present application two provides is comprised of pulse interlock circuit and isolated drive circuit, by the XOR gate in the pulse interlock circuit and with door, so that the two-way output signal of pulse interlock circuit again phenomenon can not occur at the high level place, realized the non-overlapped pwm signal output of two-way high level, avoided the device for power switching generation common conduct that causes when overlapping when high level occurring, thereby situation about being short-circuited has guaranteed invertor operation section reliability.
With reference to figure 5, it shows the part topological diagram of a kind of inverter list brachium pontis drive circuit that the embodiment of the present application three provides, described inverter list brachium pontis drive circuit comprises pulse interlock circuit 201, the first isolated drive circuit 202 and the second isolated drive circuit 203, wherein, described pulse interlock circuit 201 is with consistent described in the embodiment of the present application one, and described the first isolated drive circuit 202 comprises:
The first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the first triode T1, the second triode T2, the 3rd triode T3, the 4th triode T4, the first diode D1 and the first photoelectrical coupler N1, described the first photoelectrical coupler N1 comprises four exits, wherein:
The first output 214 of described pulse interlock circuit 201 links to each other with the first end of described the first triode T1 by described the first resistance R 1;
Forward input voltage VCC is connected with the first exit S11 of described the first photoelectrical coupler N1 by described the second resistance R 2;
The second exit S12 of described the first photoelectrical coupler N1 is connected with the second end of described the first triode T1;
The second end of described the second triode T2, the first end of described the 3rd resistance R 3 are connected with the first end of described the 4th resistance R 4, and are connected to power supply E1;
The second end of the first end of described the 3rd triode T3, described the 3rd resistance R 3 is connected with the three terminal S13 of described the first photoelectrical coupler N1;
The second end of the anode of the 3rd end of described the 3rd triode T3, the 4th exit S14 of described the first photoelectrical coupler N1, described the first diode D1, described the 4th triode T4 is connected, and is connected to the ground E1G of power supply E1;
The first end of the second end of the second end of described the 4th resistance R 4, described the 3rd triode T3, the negative electrode of described the first diode D1, described the second triode T2 and the first end of described the 4th triode T4 are connected;
The ground GND of the 3rd termination power VCC of described the first triode T1;
The 3rd end of described the second triode T2 is connected with the 3rd end of described the 4th triode T4, and is connected with the first output O1 of this inverter list brachium pontis drive circuit.
Wherein, preferably, described the first triode T1, described the second triode T2 and described the 3rd triode T3 are the NPN triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd end is emitter.
Wherein, preferably, described the 4th triode T4 is the PNP triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd section is emitter.
Wherein, the high level of described PWM1 signal is through making described the first triode T1 conducting to described the first resistance R 1 behind the described pulse interlock circuit 201, described the first photoelectrical coupler N1 work, its second exit S12 is that collector electrode becomes low level, described the 3rd triode T3, described the first resistance R 1, described the second resistance R 2 consist of inverters at this moment, and the collector electrode of described the 3rd triode T3 uprises level; Described the second triode T2, described the 4th triode T4 form emitter follower, described the first isolated drive circuit 202 output high level.In like manner, when described PWM1 is low level, described the first isolated drive circuit 202 output low levels.
With reference to figure 6, it shows another part topological diagram of the embodiment of the present application three, and in the embodiment of the present application three, described the second isolated drive circuit 203 can comprise:
The 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 5th triode T5, the 6th triode T6, the 7th triode T7, the 8th triode T8, the second diode D2 and the second photoelectrical coupler N2, described the second photoelectrical coupler N2 comprises four exits, wherein:
The second output 215 of described pulse interlock circuit 201 links to each other with the first end of described the 5th triode T5 by described the 5th resistance R 5;
Forward input voltage VCC is connected with the first exit S21 of described the second photoelectrical coupler N2 by described the 6th resistance R 6;
The second exit S22 of described the second photoelectrical coupler N2 is connected with the second end of described the 5th triode T5;
The second end of described the 6th triode T6, the first end of described the 7th resistance R 7 are connected with the first end of described the 8th resistance R 8, and meet power supply E2;
The second end of the first end of described the 7th triode T7, described the 7th resistance R 7 is connected with the three terminal S23 of described the second photoelectrical coupler N2;
The 3rd end of described the 7th triode T7, the anode of described the second diode D2 are connected with the second end of described the 8th triode T8, the 4th exit S24 of described the second photoelectrical coupler N2, and are connected to the ground E2G of power supply E2;
The first end of the second end of the second end of described the 8th resistance R 8, described the 7th triode T7, the negative electrode of described the second diode D2, described the 6th triode T6 and the first end of described the 8th triode T8 are connected;
The ground GND of the 3rd termination power VCC of described the 5th triode T5;
The 3rd end of described the 6th triode T6 is connected with the 3rd end of described the 8th triode T8, and is connected with the second output O2 of this inverter list brachium pontis drive circuit.
Wherein, preferably, described the 5th triode T5, described the 6th triode T6 and described the 7th triode T7 are the NPN triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd end is emitter.
Wherein, preferably, the 8th triode T8 is the PNP triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd section is emitter.
Wherein, the high level of described PWM2 signal is through making described the 5th triode T5 conducting to described the 5th resistance R 5 behind the described pulse interlock circuit 201, described the second photoelectrical coupler N2 work, its second exit S22 is that collector electrode becomes low level, described the 7th triode T7, described the 5th resistance R 5, described the 6th resistance R 6 consist of inverters at this moment, and the collector electrode of described the 7th triode T7 uprises level; Described the 6th triode T6, described the 8th triode T8 form emitter follower, described the second isolated drive circuit 203 output high level.In like manner, when described PWM2 is low level, described the first isolated drive circuit 203 output low levels.
With reference to figure 7, it shows the whole topological diagram of a kind of inverter list brachium pontis drive circuit that the embodiment of the present application three provides, described inverter list brachium pontis drive circuit comprises pulse interlock circuit 201, the first isolated drive circuit 202 and the second isolated drive circuit 203, wherein:
Described pulse interlock circuit 201 comprises:
The first input end 2111 of described XOR gate 211 is connected with described two-way pwm signal respectively with the second input 2112;
The output 2113 of described XOR gate 211 is connected with the first input end 2131 of door 213 with described second with the first input end 2121 of door 212 with described first respectively;
Described first is connected with described two-way pwm signal respectively with the second input 2132 of 213 with described second with door the second input 2122 of 212.
Described the first isolated drive circuit 202 comprises:
The first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the first triode T1, the second triode T2, the 3rd triode T3, the 4th triode T4, the first diode D1 and the first photoelectrical coupler N1, described the first photoelectrical coupler N1 comprises four exits, wherein:
The first output 214 of described pulse interlock circuit 201 links to each other with the first end of described the first triode T1 by described the first resistance R 1;
Forward input voltage VCC is connected with the first exit S11 of described the first photoelectrical coupler N1 by described the second resistance R 2;
The second exit S12 of described the first photoelectrical coupler N1 is connected with the second end of described the first triode T1;
The second end of described the second triode T2, the first end of described the 3rd resistance R 3 are connected with the first end of described the 4th resistance R 4, and are connected to power supply E1;
The second end of the first end of described the 3rd triode T3, described the 3rd resistance R 3 is connected with the three terminal S13 of described the first photoelectrical coupler N1;
The second end of the anode of the 3rd end of described the 3rd triode T3, the 4th exit S14 of described the first photoelectrical coupler N1, described the first diode D1, described the 4th triode T4 is connected, and is connected to the ground E1G of power supply E1;
The first end of the second end of the second end of described the 4th resistance R 4, described the 3rd triode T3, the negative electrode of described the first diode D1, described the second triode T2 and the first end of described the 4th triode T4 are connected;
The ground GND of the 3rd termination power VCC of described the first triode T1;
The 3rd end of described the second triode T2 is connected with the 3rd end of described the 4th triode T4, and is connected with the first output O1 of this inverter list brachium pontis drive circuit.
Described the second isolated drive circuit 203 can comprise:
The 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 5th triode T5, the 6th triode T6, the 7th triode T7, the 8th triode T8, the second diode D2 and the second photoelectrical coupler N2, described the second photoelectrical coupler N2 comprises four exits, wherein:
The second output 215 of described pulse interlock circuit 201 links to each other with the first end of described the 5th triode T5 by described the 5th resistance R 5;
Forward input voltage VCC is connected with the first exit S21 of described the second photoelectrical coupler N2 by described the 6th resistance R 6;
The second exit S22 of described the second photoelectrical coupler N2 is connected with the second end of described the 5th triode T5;
The second end of described the 6th triode T6, the first end of described the 7th resistance R 7 are connected with the first end of described the 8th resistance R 8, and meet power supply E2;
The second end of the first end of described the 7th triode T7, described the 7th resistance R 7 is connected with the three terminal S23 of described the second photoelectrical coupler N2;
The 3rd end of described the 7th triode T7, the anode of described the second diode D2 are connected with the second end of described the 8th triode T8, the 4th exit S24 of described the second photoelectrical coupler N2, and are connected to the ground E2G of power supply E2;
The first end of the second end of the second end of described the 8th resistance R 8, described the 7th triode T7, the negative electrode of described the second diode D2, described the 6th triode T6 and the first end of described the 8th triode T8 are connected;
The ground GND of the 3rd termination power VCC of described the 5th triode T5;
The 3rd end of described the 6th triode T6 is connected with the 3rd end of described the 8th triode T8, and is connected with the second output O2 of this inverter list brachium pontis drive circuit.
From the above, with respect in the prior art since cheaply single-chip microcomputer inverter bridge drive circuit do not have special-purpose PWM output port, can't directly produce four road drive pulse signals that can guarantee the single-phase inverter reliability service, the technical problem that causes thus the reliability reduction of inverter bridge, the inverter list brachium pontis drive circuit that the embodiment of the present application three provides is comprised of pulse interlock circuit and isolated drive circuit, by in the pulse interlock circuit so that the two-way output signal of pulse interlock circuit again phenomenon can not occur at the high level place, realized the non-overlapped pwm signal output of two-way high level, avoided the device for power switching generation common conduct that causes when overlapping when high level occurring, thereby situation about being short-circuited has guaranteed the invertor operation reliability.
Further, higher with respect to drive circuit cost of the prior art, the technical problem that can't use at the low power inverter of low cost, the inverter list brachium pontis drive circuit that the embodiment of the present application three provides is comprised of common resistance, diode, triode and photoelectrical coupler, thus, under the prerequisite that guarantees the inverter reliability service, cost is lower, can extensive use on the low power inverter of low cost.
The embodiment of the present application four also provides a kind of application circuit of inverter list brachium pontis drive circuit, and described application circuit comprises at least two as the described inverter list of above-mentioned the embodiment of the present application one to three any one brachium pontis drive circuit, wherein:
Each output of described at least two single brachium pontis drive circuits is connected with the input of respectively organizing device for power switching of single-phase inverter or polyphase inverter respectively.
When the embodiment of the present application four comprised two described inverter list brachium pontis drive circuits, the embodiment of the present application four was applied to single-phase inverter, and with reference to figure 8, it shows the structural representation that the embodiment of the present application four is applied to single-phase inverter, wherein:
As shown in Figure 8, the second output O2 of the first output O1 of the second output O2 of the first output O1 of the first described inverter list brachium pontis drive circuit P1, the first described inverter list brachium pontis drive circuit P1, the second described inverter list brachium pontis drive circuit P2 and the second described inverter list brachium pontis drive circuit P2 is connected with four groups of device for power switching of this single-phase inverter respectively.
Need to prove that this moment, the embodiment of the present application four was two brachium pontis, four pulse driving circuits.
When the embodiment of the present application four comprised four or 2N (N＞2) described inverter list brachium pontis drive circuit, the embodiment of the present application four was applied to polyphase inverter, and this moment, the embodiment of the present application four was N brachium pontis 2N pulse driving circuit.
From the above, with respect in the prior art since cheaply single-chip microcomputer inverter bridge drive circuit do not have special-purpose PWM output port, can't directly produce four road drive pulse signals that can guarantee the single-phase inverter reliability service, the technical problem that causes thus the reliability reduction of inverter bridge, the inverter list brachium pontis drive circuit application circuit that the embodiment of the present application four provides is comprised of pulse interlock circuit and isolated drive circuit, by in the pulse interlock circuit so that the two-way output signal of pulse interlock circuit again phenomenon can not occur at the high level place, realized the non-overlapped pwm signal output of two-way high level, avoided the device for power switching generation common conduct that causes when overlapping when high level occurring, thereby situation about being short-circuited has guaranteed single-phase or the polyphase inverter reliability of operation.
Further, higher with respect to drive circuit cost of the prior art, the technical problem that can't use at the low power inverter of low cost, the inverter list brachium pontis drive circuit application circuit that the embodiment of the present application four provides is comprised of common resistance, diode, triode and photoelectrical coupler, thus, under the prerequisite that guarantees single-phase or polyphase inverter reliability service, cost is lower, can extensive use on the low power inverter of low cost.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the utility model.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation that does not break away from spirit or scope of the present utility model, realize in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (9)
1. an inverter list brachium pontis drive circuit is characterized in that, comprising:
Receive the two-way pwm signal, generate non-overlapped the first pulse control signal and the second pulse control signal of high level, and the pulse interlock circuit that described the first pulse control signal and described the second pulse control signal are transmitted by the first output and the second output respectively;
Be connected with the second output with the first output of described pulse interlock circuit respectively, receive respectively described the first pulse control signal and described the second pulse control signal, generate the first drive pulse signal and the second drive pulse signal, and with described the first drive pulse signal and described the second drive pulse signal the first isolated drive circuit and the second isolated drive circuit that transmit of the first output and the second output by this inverter list brachium pontis drive circuit respectively.
2. inverter list brachium pontis drive circuit according to claim 1 is characterized in that, described pulse interlock circuit comprise XOR gate, first and the door and second with, wherein:
The first input end of described XOR gate is connected with described two-way pwm signal respectively with the second input;
The output of described XOR gate is connected with the first input end of door with described second with the first input end of door with described first respectively;
Described first with the door the second input with described second with the second input be connected with described two-way pwm signal respectively.
3. inverter list brachium pontis drive circuit according to claim 1 and 2, it is characterized in that, described the first isolated drive circuit comprises the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the first triode T1, the second triode T2, the 3rd triode T3, the 4th triode T4, the first diode D1 and the first photoelectrical coupler N1, described the first photoelectrical coupler N1 comprises four exits, wherein:
The first output of described pulse interlock circuit links to each other with the first end of described the first triode T1 by described the first resistance R 1;
Forward input voltage VCC is connected with the first exit of described the first photoelectrical coupler N1 by described the second resistance R 2;
The second exit of described the first photoelectrical coupler N1 is connected with the second end of described the first triode T1;
The second end of described the second triode T2, the first end of described the 4th resistance R 4 are connected with the first end of described the 3rd resistance R 3, and are connected to power supply E1;
The second end of the first end of described the 3rd triode T3, described the 3rd resistance R 3 is connected with the three terminal of described the first photoelectrical coupler N1;
The second end of the 4th exit of the 3rd end of described the 3rd triode T3, described the first photoelectrical coupler N1, the anode of described the first diode D1, described the 4th triode T4 is connected, and is connected to the ground of power supply E1;
The first end of the second end of the second end of described the 4th resistance R 4, described the 3rd triode T3, the negative electrode of described the first diode D1, described the second triode T2 and the first end of described the 4th triode T4 are connected;
The ground of the 3rd termination power VCC of described the first triode T1;
The 3rd end of described the second triode T2 is connected with the 3rd end of described the 4th triode T4, and is connected with the first output of this inverter list brachium pontis drive circuit.
4. inverter list brachium pontis drive circuit according to claim 1 and 2, it is characterized in that, described the second isolated drive circuit comprises the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 5th triode T5, the 6th triode T6, the 7th triode T7, the 8th triode T8, the second diode D2 and the second photoelectrical coupler N2, described the second photoelectrical coupler N2 comprises four exits, wherein:
The second output of described pulse interlock circuit links to each other with the first end of described the 5th triode T5 by described the 5th resistance R 5;
Forward input voltage VCC is connected with the first exit of described the second photoelectrical coupler N2 by described the 6th resistance R 6;
The second exit of described the second photoelectrical coupler N2 is connected with the second end of described the 5th triode T5;
The second end of described the 6th triode T6, the first end of described the 7th resistance R 7 are connected with the first end of described the 8th resistance R 8, and meet power supply E2;
The second end of the first end of described the 7th triode T7, described the 7th resistance R 7 is connected with the three terminal of described the second photoelectrical coupler N2;
The second end of the 3rd end of described the 7th triode T7, the anode of described the second diode D2, described the 8th triode T8, the 4th exit of described the second photoelectrical coupler N2 are connected, and are connected to the ground of power supply E2;
The first end of the second end of the second end of described the 8th resistance R 8, described the 7th triode T7, the negative electrode of described the second diode D2, described the 6th triode T6 and the first end of described the 8th triode T8 are connected;
The ground of the 3rd termination power VCC of described the 5th triode T5;
The 3rd end of described the 6th triode T6 is connected with the 3rd end of described the 8th triode T8, and is connected with the second output of this inverter list brachium pontis drive circuit.
5. inverter list brachium pontis drive circuit according to claim 3, it is characterized in that described the first triode T1, described the second triode T2 and described the 3rd triode T3 are the NPN triode, described first end is base stage, described the second end is collector electrode, and described the 3rd end is emitter.
6. inverter list brachium pontis drive circuit according to claim 3 is characterized in that, described the 4th triode T4 is the PNP triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd section is emitter.
7. inverter list brachium pontis drive circuit according to claim 4, it is characterized in that described the 5th triode T5, described the 6th triode T6 and described the 7th triode T7 are the NPN triode, described first end is base stage, described the second end is collector electrode, and described the 3rd end is emitter.
8. inverter list brachium pontis drive circuit according to claim 4 is characterized in that, described the 8th triode T8 is the PNP triode, and described first end is base stage, and described the second end is collector electrode, and described the 3rd section is emitter.
9. the application circuit of an inverter list brachium pontis drive circuit is characterized in that, comprises at least two such as the described inverter list of claim 1 to 8 any one brachium pontis drive circuit, wherein:
Each output of described at least two single brachium pontis drive circuits is connected with the input of respectively organizing device for power switching of single-phase inverter or polyphase inverter respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220234646 CN202663288U (en) | 2012-05-22 | 2012-05-22 | Single bridge arm drive circuit of inverter and application circuit thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220234646 CN202663288U (en) | 2012-05-22 | 2012-05-22 | Single bridge arm drive circuit of inverter and application circuit thereof |
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| CN202663288U true CN202663288U (en) | 2013-01-09 |
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| CN 201220234646 Expired - Fee Related CN202663288U (en) | 2012-05-22 | 2012-05-22 | Single bridge arm drive circuit of inverter and application circuit thereof |
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| CN103138554A (en) * | 2013-04-03 | 2013-06-05 | 西安西驰电子传动与控制有限公司 | Upper half-bridge and lower half-bridge driving interlocking method of brushless direct current motor driver |
| CN104009615A (en) * | 2013-02-22 | 2014-08-27 | 台达电子工业股份有限公司 | Bridge-type on-off control circuit and operation method thereof |
| CN104579305A (en) * | 2013-10-17 | 2015-04-29 | 峰岹科技（深圳）有限公司 | Double-high interlocking circuit and high-voltage integrated circuit consisting of double-high interlocking circuit |
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| CN104579305A (en) * | 2013-10-17 | 2015-04-29 | 峰岹科技（深圳）有限公司 | Double-high interlocking circuit and high-voltage integrated circuit consisting of double-high interlocking circuit |
| TWI513157B (en) * | 2013-11-29 | 2015-12-11 | Ind Tech Res Inst | Interlocking apparatus and three-phase interlocking apparatus for dc-to-ac inverter |
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| CN105720808A (en) * | 2016-03-16 | 2016-06-29 | 珠海格力电器股份有限公司 | Inverter startup short-circuit protection method and device |
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| CN115206067A (en) * | 2022-07-11 | 2022-10-18 | 上海茵特格锐科技有限公司 | PWM signal alarm circuit for inverter |
| CN116707336A (en) * | 2023-08-03 | 2023-09-05 | 鹏元晟高科技股份有限公司 | Three-level inversion wave-by-wave current limiting circuit and power supply device |
| CN116707336B (en) * | 2023-08-03 | 2024-02-20 | 鹏元晟高科技股份有限公司 | Three-level inversion wave-by-wave current limiting circuit and power supply device |
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