CN202661533U - Alternating voltage detection circuit and safety capacitor discharge circuit - Google Patents
Alternating voltage detection circuit and safety capacitor discharge circuit Download PDFInfo
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- CN202661533U CN202661533U CN 201220343469 CN201220343469U CN202661533U CN 202661533 U CN202661533 U CN 202661533U CN 201220343469 CN201220343469 CN 201220343469 CN 201220343469 U CN201220343469 U CN 201220343469U CN 202661533 U CN202661533 U CN 202661533U
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Abstract
The utility model provides an alternating voltage detection circuitry and safety regulation electric capacity discharge circuit, alternating voltage detection circuitry can be used to detect whether normal the inserting of alternating current power supply. The alternating voltage detection circuit includes: a rectifier circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal and the second input terminal are coupled to an alternating current power supply to receive an alternating current voltage, and the output terminal outputs a rectified signal based on the alternating current voltage; a comparator circuit having an input coupled to an output of the rectifier circuit to receive a rectified signal and an output to output a square wave signal based on the rectified signal; and the power failure indicating circuit is provided with an input end and an output end, wherein the input end is coupled to the comparison circuit to receive the square wave signal, and the output end outputs a power failure indicating signal based on the square wave signal.
Description
Technical field
The utility model relates to alternating circuit, and more particularly, the utility model relates to the ac voltage detection circuit in the alternating circuit.
Background technology
Nowadays, many electronic equipments all need DC-voltage supply, and this DC voltage is converted by alternating voltage usually.Fig. 1 shows the electrical block diagram of AC/DC (interchange turns direct current) circuit.As shown in Figure 1, the AC/DC circuit comprises full-bridge rectifier 101 and DC/DC (DC-DC) circuit 102.Full-bridge rectifier 101 obtains alternating voltage VIN from AC power 100, be converted into one and do not control DC voltage VDC, and DC/DC circuit 102 is not controlled DC voltage VDC with this and is converted to required DC voltage and offers load.
In Fig. 1, X electric capacity (safety electric capacity) CX is coupled in the two ends of AC power 100, to improve the EMI characteristic of AC/DC circuit.Capacitor C 1 is in parallel with full-bridge rectifier 101, has the effect of filtering and energy storage.In actual applications, when AC/DC circuit and AC power 100 disconnected, X capacitor C X will untimelyly have electric charge residual because discharging, and may cause security incident.Therefore when the AC/DC circuit disconnects from AC power 100, need to discharge to X capacitor C X.VIN detects to alternating voltage, in time X capacitor C X is discharged when AC/DC circuit and AC power 100 are disconnected.
The utility model content
Consider one or more technical matterss of prior art, propose ac voltage detection circuit, in order to detect in time the situation of AC power, thus can be in time to the X capacitor discharge.
According to the embodiment of present technique, a kind of ac voltage detection circuit has been proposed, comprising: rectification circuit, has first input end, the second input end and output terminal, wherein said first input end and the second input end are coupled to AC power and receive alternating voltage, described output terminal output rectified signal; Testing circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to rectification circuit receives rectified signal, described output terminal output square-wave signal; And the outage indicating circuit, having input end and output terminal, wherein said input end is coupled to testing circuit and receives square-wave signal, described output terminal output outage indicator signal.
According to embodiment of the present utility model, described testing circuit comprises:
Delay circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to rectification circuit receives rectified signal, and described output terminal provides the time-delay rectified signal; And
Comparer, have first input end, the output terminal that the second input end and output terminal, wherein said first input end are coupled to rectification circuit receives rectified signal, described the second input end is coupled to the output terminal reception delay rectified signal of delay circuit, and described comparer is exported square-wave signal at output terminal.
According to embodiment of the present utility model, described outage indicating circuit comprises:
The rising edge trigger has input end and output terminal, and the output terminal that wherein said input end is coupled to testing circuit receives square-wave signal, and described output terminal is exported the rising edge pulse signal when the rising edge of square-wave signal;
The negative edge trigger has input end and output terminal, and the output terminal that wherein said input end is coupled to testing circuit receives square-wave signal, and described output terminal is exported the negative edge pulse signal when the negative edge of square-wave signal;
Supercircuit has first input end, the second input end and output terminal, and wherein said first input end is coupled to the output terminal of rising edge trigger, and described the second input end is coupled to the output terminal of negative edge trigger, described output terminal output superimposed pulse signal; And
Timing circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to supercircuit receives the superimposed pulse signal, described output terminal output outage indicator signal;
Wherein said timing circuit carries out timing to the superimposed pulse signal, described outage indicator signal is invalid when be less than or equal to the first preset value the interpulse period of superimposed pulse signal, and described outage indicator signal is effective during greater than the first preset value in interpulse period of superimposed pulse signal.
According to embodiment of the present utility model, described outage indicating circuit comprises:
The rising edge trigger has input end and output terminal, and the output terminal that wherein said input end is coupled to testing circuit receives square-wave signal, and described output terminal is exported the rising edge pulse signal when the rising edge of square-wave signal; And
Timing circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to the rising edge trigger receives the rising edge pulse signal, described output terminal output outage indicator signal;
Wherein said timing circuit carries out timing to the rising edge pulse signal, described outage indicator signal is invalid when be less than or equal to the second preset value the interpulse period of rising edge pulse signal, and described outage indicator signal is effective during greater than the second preset value in interpulse period of rising edge pulse signal.
According to embodiment of the present utility model, described outage indicating circuit comprises:
The negative edge trigger has input end and output terminal, and the output terminal that wherein said input end is coupled to testing circuit receives square-wave signal, and described output terminal is exported the negative edge pulse signal when the negative edge of square-wave signal; And
Timing circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to the negative edge trigger receives the negative edge pulse signal, described output terminal output outage indicator signal;
Wherein said timing circuit carries out timing to the negative edge pulse signal, described outage indicator signal is invalid when be less than or equal to the 3rd preset value the interpulse period of negative edge pulse signal, and described outage indicator signal is effective during greater than the 3rd preset value in interpulse period of negative edge pulse signal.
According to embodiment of the present utility model, described timing circuit comprises:
Charging current source has first end and the second end, and described first end is coupled to chip power, and described the second end provides charging current;
Electric capacity has first end and the second end, and described first end is coupled to the second termination of charging current source and receives charging current, described the second end ground connection;
Time switch has first end, the second end and control end, and described first end is coupled to the first end of electric capacity, described the second end ground connection, described control end is coupled to described timing circuit input end; And
The timing comparer has first input end, the second input end and output terminal, and wherein said first input end is coupled to the first end of electric capacity, and described the second input end receives reference voltage, described output terminal output outage indicator signal.
On the other hand of the present utility model, a kind of safety capacitor discharging circuit is provided, comprise described ac voltage detection circuit, also comprise:
Safety electric capacity has first end and the second end, and described safety electric capacity is in parallel with AC power;
Discharge circuit has first end, the second end and control end, and described first end is coupled to the first end of safety electric capacity, described the second end ground connection, the output terminal that described control end is coupled to ac voltage detection circuit receives the outage indicator signal.
According to embodiment of the present utility model, described discharge circuit comprises discharge current source and the discharge switch that is connected in series, and wherein said discharge switch receives the outage indicator signal, and is closed when the outage indicator signal is effective; When the outage indicator signal is invalid, disconnect.
According to embodiment of the present utility model, described discharge current source comprises resistance.
According to the ac voltage detection circuit of the above-mentioned aspect of the utility model, can detect rapidly whether normally access of AC power, and be used for instructing work, the especially control of discharge of X electric capacity of other circuit.
Description of drawings
In order better to understand the utility model, will be described in detail the utility model according to the following drawings:
Fig. 1 shows AC/DC circuit diagram of the prior art;
Fig. 2 shows the electrical block diagram according to the ac voltage detection circuit 200 of the utility model one embodiment;
Fig. 3 shows the signal waveforms of the ac voltage detection circuit 200 among Fig. 2;
Fig. 4 shows the electrical block diagram according to the ac voltage detection circuit 400 of the utility model one embodiment;
Fig. 5 shows the electrical block diagram according to the ac voltage detection circuit 500 of the utility model one embodiment;
Fig. 6 shows the electrical block diagram according to the timing circuit 207 of the utility model one embodiment;
Fig. 7 shows the signal waveform schematic diagram in the timing circuit shown in Figure 6 207;
Fig. 8 a shows the electrical block diagram according to the X capacitor discharging circuit of the utility model one embodiment;
Fig. 8 b shows the electrical block diagram according to the X capacitor discharging circuit of the utility model one embodiment.
Embodiment
The below will describe specific embodiment of the utility model in detail, should be noted that the embodiments described herein only is used for illustrating, and be not limited to the utility model.In the following description, in order to provide thorough understanding of the present utility model, a large amount of specific detail have been set forth.Yet, it is evident that for those of ordinary skills: needn't adopt these specific detail to carry out the utility model.In other examples, for fear of obscuring the utility model, do not specifically describe known circuit, material or method.
In whole instructions, " embodiment ", " embodiment ", " example " or mentioning of " example " are meaned: special characteristic, structure or characteristic in conjunction with this embodiment or example description are comprised among at least one embodiment of the utility model.Therefore, phrase " in one embodiment ", " in an embodiment ", " example " or " example " that occurs in each place of whole instructions differs to establish a capital and refers to same embodiment or example.In addition, can with any suitable combination and/or sub-portfolio with specific feature, structure or property combination in one or more embodiment or example.In addition, it should be understood by one skilled in the art that at this accompanying drawing that provides all be for illustrative purposes, and accompanying drawing is drawn in proportion not necessarily.Should be appreciated that when claiming element " to be connected to " or during " being couple to " another element, it can be directly to connect or be couple to another element or can have intermediary element.On the contrary, when claiming element " to be directly connected to " or during " being directly coupled to " another element, not having intermediary element.The identical identical element of Reference numeral indication.Term used herein " and/or " comprise any and all combinations of one or more relevant projects of listing.
Fig. 2 shows the electrical block diagram according to the ac voltage detection circuit 200 of the utility model one embodiment.Shown in ac voltage detection circuit 200 comprise: rectification circuit 210, has first input end, the second input end and output terminal, wherein said first input end and the second input end are coupled to AC power 100 and receive alternating voltage VIN, based on described alternating voltage VIN, described output terminal output rectified signal HV; Testing circuit 201 has input end and output terminal, and the output terminal that wherein said input end is coupled to rectification circuit 210 receives rectified signal HV, based on described rectified signal HV, and described output terminal output square-wave signal SP; And outage indicating circuit 202, having input end and output terminal, wherein said input end is coupled to testing circuit 201 and receives square-wave signal SP, based on described square-wave signal SP, described output terminal output outage indicator signal BRE.
In one embodiment, described ac voltage detection circuit 200 also comprises bleeder circuit.Described bleeder circuit is coupled between the output terminal and ground of rectification circuit 210, and rectified signal HV is carried out dividing potential drop, so that the rectified signal after the dividing potential drop is in the input range of testing circuit 201.Bleeder circuit is the common practise of this area, for simplicity, is not specifically addressed.If those of ordinary skills should be understood that the magnitude of voltage of rectified signal HV in the input range of testing circuit 201, then can omit need not for bleeder circuit.For narrating for simplicity, the signal that hereinafter is input in the testing circuit 201 de-emphasizes the dividing potential drop whether it passes through bleeder circuit.It will be understood by those skilled in the art that rectified signal HV had hereinafter described both comprised the rectified signal of directly being exported by rectification circuit 201, also comprised through the rectified signal after the bleeder circuit dividing potential drop.
In one embodiment, described testing circuit 201 comprises: delay circuit 203, have input end and output terminal, and the output terminal that wherein said input end is coupled to rectification circuit 210 receives rectified signal HV, and described output terminal provides time-delay rectified signal HVD; And detection comparator 204, has first input end (normal phase input end), the second input end (inverting input) and output terminal, the output terminal that wherein said first input end is coupled to rectification circuit 210 receives rectified signal HV, described the second input end is coupled to the output terminal reception delay rectified signal HVD of delay circuit 203, based on rectified signal HV and time-delay rectified signal HVD, described detection comparator 204 is at output terminal output square-wave signal SP.
In one embodiment, described outage indicating circuit 202 comprises: rising edge trigger 205, have input end and output terminal, the output terminal that wherein said input end is coupled to testing circuit 201 receives square-wave signal SP, based on described square-wave signal SP, described output terminal is exported rising edge pulse signal 211 when the rising edge of square-wave signal SP; Negative edge trigger 206, have input end and output terminal, the output terminal that wherein said input end is coupled to testing circuit 201 receives square-wave signal SP, and based on described square-wave signal SP, described output terminal is exported negative edge pulse signal 212 when the negative edge of square-wave signal SP; Supercircuit 208, has first input end, the second input end and output terminal, the output terminal that wherein said first input end is coupled to rising edge trigger 205 receives rising edge pulse signal 211, the output terminal that described the second input end is coupled to negative edge trigger 206 receives negative edge pulse signal 212, described output terminal output superimposed pulse signal 213; And timing circuit 207, having input end and output terminal, the output terminal that wherein said input end is coupled to supercircuit 208 receives superimposed pulse signal 213, based on superimposed pulse signal 213, described output terminal output outage indicator signal BRE; 207 pairs of superimposed pulse signals of wherein said timing circuit 213 carry out timing, when be less than or equal to the first preset value PT1 the interpulse period of superimposed pulse signal 213, described outage indicator signal BRE is invalid, when interpulse period of superimposed pulse signal 213 during greater than the first preset value PT1, described outage indicator signal BRE is effective.
Fig. 3 shows the waveform schematic diagram of each signal in the ac voltage detection circuit shown in Fig. 2 200.The course of work of ac voltage detection circuit 200 is described below in conjunction with Fig. 2 and Fig. 3.
At period T1, AC power 100 accesses are normal.Rectified signal HV has waveform as shown in Figure 3.Through the time-delay of delay circuit 203, obtain falling behind than rectified signal HV the time-delay rectified signal HVD of certain phase value.The phase differential of rectified signal HV and time-delay rectified signal HVD is directly proportional with the delay time of delay circuit 203, and delay time is longer, and phase differential is larger.Detection comparator 204 compares the size of rectified signal HV and time-delay rectified signal HVD, obtains square-wave signal SP.In one embodiment, the normal phase input end of detection comparator 204 receives rectified signal HV, inverting input reception delay rectified signal HVD.As shown in Figure 3, as rectified signal HV during greater than time-delay rectified signal HVD, square-wave signal SP is high level; When rectified signal HV was less than or equal to time-delay rectified signal HVD, square-wave signal SP was low level.Rising edge trigger 205 and negative edge trigger 206 receive square-wave signal SP.At each rising edge of square-wave signal SP, the 205 output rising edge pulses 211 of rising edge trigger; At each negative edge of square-wave signal SP, the 206 output negative edge pulses 212 of negative edge trigger.Supercircuit 208 is superimposed with rising edge pulse 211 and negative edge pulse 212, obtains superimposed pulse signal 213.In one embodiment, supercircuit 208 comprises OR circuit.Timing circuit 207 receives superimposed pulse signal 213, to carrying out timing the interpulse period of superimposed pulse signal 213.In one embodiment, when interpulse period of superimposed pulse signal 213 during less than the first preset value PT1, the outage indicator signal BRE of timing circuit 207 outputs is low level, and the indicator signal of namely cutting off the power supply BRE is in disarmed state, shows that AC power 100 connections this moment are normal.
At period T2, AC power 100 disconnects.Because the effect of X electric capacity (safety electric capacity), rectified signal HV and time-delay rectified signal HVD can not reduce to zero immediately, have waveform shown in Figure 3.Square-wave signal SP remains low level.Rising edge pulse signal 211, no pulse produces in negative edge pulse signal 212 and the superimposed pulse signal 213.This moment, superimposed pulse signal 213 recurrent interval duration surpassed the first preset value PT1, so the outage indicator signal BRE that timing circuit 207 is exported is high level, and BRE is effective for the indicator signal of namely cutting off the power supply, and shows that AC power 100 work this moment are undesired.AC power 100 shown in Figure 3 is separated in the waveform rising stage of rectified signal HV, so that in period T2, the value of rectified signal HV is larger than the value of time-delay rectified signal HVD.Those of ordinary skills will be appreciated that, AC power 100 disconnects constantly in difference, to cause rectified signal HV to have different values with time-delay rectified signal HVD, such as in AC power 100 when the waveform decrement phase of rectified signal HV is separated, with so that the value of rectified signal HV less than the value of time-delay rectified signal HVD, thereby will make square-wave signal SP remain high level.If square-wave signal SP remains high level, then at rising edge pulse signal 211, same no pulse produces in negative edge pulse signal 212 and the superimposed pulse signal 213.Whether the indicator signal of namely cutting off the power supply BRE still can indicate AC power 100 to disconnect exactly.
At period T3, AC power 100 accesses again.Rectified signal HV and time-delay rectified signal HVD have the waveform shown in period T3 among Fig. 3.After AC power 100 accesses again, rectified signal HV and time-delay rectified signal HVD because the relation of phase differential so that square-wave signal SP again have at the waveform shown in the period T1.At each rising edge of square-wave signal SP, the 205 output rising edge pulses 211 of rising edge trigger; At each negative edge of square-wave signal SP, the 206 output negative edge pulses 212 of negative edge trigger.Supercircuit 208 is superimposed with rising edge pulse 211 and negative edge pulse 212, obtains superimposed pulse signal 213.Timing circuit 207 receives superimposed pulse signal 213, to carrying out timing the interpulse period of superimposed pulse signal 213.When the interpulse period of superimposed pulse signal 213 was less than the first preset value PT1 at this moment, the outage indicator signal BRE of timing circuit 207 outputs was low level, and the indicator signal of namely cutting off the power supply BRE is in disarmed state, showed that AC power 100 connections this moment are normal.
In one embodiment, AC power 100 has work frequency 50Hz, and namely the cycle of alternating voltage VIN is 20mS.The frequency of rectified signal HV and time-delay rectified signal HVD is the twice of the frequency of alternating voltage VIN, and namely the cycle of rectified signal HV and time-delay rectified signal HVD is 10mS.As can be seen from Figure 3, when AC power 100 normal access, square-wave signal SP has the frequency consistent with rectified signal HV, and namely the cycle of square-wave signal also is 10mS.Therefore, when AC power 100 normal access, be 10mS the interpulse period of rising edge pulse signal 211 and negative edge pulse signal 212, and be 5mS the interpulse period of superimposed pulse signal 213.Therefore, the value of the first preset value PT1 in the timing circuit 207 can be one greater than the value of 5mS.Namely the value of the first preset value PT1 is greater than the recurrent interval duration of superimposed pulse signal 213 when AC power 100 normal access, for example 7mS.In actual applications, can to set the first preset value PT1 according to frequency and the system requirements of alternating voltage VIN.
Fig. 4 shows ac voltage detection circuit 400 schematic diagram according to the utility model one embodiment.Compare with the ac voltage detection circuit 200 among Fig. 2, in this embodiment, described outage indicating circuit 402 comprises: rising edge trigger 205, have input end and output terminal, the output terminal that wherein said input end is coupled to testing circuit 201 receives square-wave signal SP, based on described square-wave signal SP, described output terminal is exported rising edge pulse signal 211 when the rising edge of square-wave signal SP; And timing circuit 207, having input end and output terminal, the output terminal that wherein said input end is coupled to rising edge trigger 205 receives rising edge pulse signal 211, based on rising edge pulse signal 211, described output terminal output outage indicator signal BRE; 207 pairs of rising edge pulse signals of wherein said timing circuit 211 carry out timing, when be less than or equal to the second preset value PT2 the interpulse period of rising edge pulse signal 211, described outage indicator signal BRE is invalid, when interpulse period of rising edge pulse signal 211 during greater than the second preset value PT2, described outage indicator signal BRE is effective.
As mentioned before, when AC power 100 normal access, the recurrent interval duration of rising edge pulse signal 211 is twices of the recurrent interval duration of superimposed pulse signal 213, therefore in outage indicating circuit 402, the value of the second preset value PT2 is greater than the first preset value PT1 in the outage indicating circuit 202, and namely the value of the second preset value PT2 is greater than the recurrent interval duration of rising edge pulse signal 211 when AC power 100 normal access.Ac voltage detection circuit 400 shown in Figure 4 is identical with the principle of work of ac voltage detection circuit 200 shown in Figure 2, and is simple and clear for narrating, and no longer elaborates herein.
Fig. 5 shows ac voltage detection circuit 500 schematic diagram according to the utility model one embodiment.Compare with the ac voltage detection circuit 200 among Fig. 2, in this embodiment, described outage indicating circuit 502 comprises: negative edge trigger 206, have input end and output terminal, the output terminal that wherein said input end is coupled to testing circuit 201 receives square-wave signal SP, based on described square-wave signal SP, described output terminal is exported negative edge pulse signal 212 when the negative edge of square-wave signal SP; And timing circuit 207, having input end and output terminal, the output terminal that wherein said input end is coupled to negative edge trigger 206 receives negative edge pulse signal 212, based on negative edge pulse signal 212, described output terminal output outage indicator signal BRE; 207 pairs of negative edge pulse signals of wherein said timing circuit 212 carry out timing, the interpulse period of rushing signal 212 along the pulse when descending is when being less than or equal to the 3rd preset value PT3, described outage indicator signal BRE is invalid, along the pulse the interpulse period rush signal 212 when descending, described outage indicator signal BRE was effective during greater than the 3rd preset value PT3.
As mentioned before, when AC power 100 normal access, the recurrent interval duration of negative edge pulse signal 212 is identical with the recurrent interval duration of rising edge pulse signal 211.Therefore the value of the 3rd preset value PT3 is identical with the value of the second preset value PT2, and namely the value of the 3rd preset value PT3 is greater than to descend when AC power 100 normal access and rushes the recurrent interval duration of signal 212 along the pulse.Ac voltage detection circuit 500 shown in Figure 5 is identical with the principle of work of ac voltage detection circuit 200 shown in Figure 2, and is simple and clear for narrating, and no longer elaborates herein.
Fig. 6 shows the electrical block diagram according to the timing circuit 207 of the utility model one embodiment.As shown in Figure 6, timing circuit 207 comprises: charging current source I1, have first end and the second end, and described first end is coupled to chip power VCC, and described the second end provides charging current; Capacitor C 2 has first end and the second end, and described first end is coupled to the second termination of charging current source I1 and receives charging current, described the second end ground connection; Time switch M1, have first end, the second end and control end, described first end is coupled to the first end of capacitor C 2, described the second end ground connection, described control end is coupled to the input end of described timing circuit 207, based on the signal that the input end of described timing circuit receives, described time switch M1 or open or turn-off; And timing comparer 602, has first input end (normal phase input end), the second input end (negative-phase input) and output terminal, wherein said first input end is coupled to the first end of capacitor C 2, described the second input end receives reference voltage V REF, based on the voltage VC on the electric capacity and reference voltage V REF, described timing comparer 602 is at output terminal output outage indicator signal BRE.
In one embodiment, ac voltage detection circuit and DC/DC circuit 102 are integrated in the chip of same, and described chip power VCC is provided by DC/DC circuit 102.In one embodiment, ac voltage detection circuit is integrated in separately on the chip piece, and chip power VCC can be provided by other power circuit, also can provide by DC/DC circuit 102.
Fig. 7 shows the signal waveform schematic diagram in the timing circuit shown in Figure 6 207.Timing circuit shown in Figure 6 can be used for Fig. 2, among Fig. 4 and Fig. 5 in arbitrary ac voltage detection circuit.The below is applied in the ac voltage detection circuit shown in Figure 2 in conjunction with Fig. 7, the course of work of this timing circuit 207 to be described as example take timing circuit shown in Figure 6.In one embodiment, the first end that the normal phase input end of timing comparer 602 is coupled to capacitor C 2 receives the voltage VC on the capacitor C 2, and inverting input receives reference voltage V REF.The output terminal that the control end of time switch M1 is coupled to supercircuit 208 receives superimposed pulse signal 213.In one embodiment, the pulse of superimposed pulse signal 213 is closed with time switch M1, and namely as shown in Figure 7, when superimposed pulse signal 213 produced pulse, time switch M1 was closed, and when the end-of-pulsing of superimposed pulse signal 213, time switch M1 disconnects.When AC power 100 normal access: before the voltage VC on capacitor C 2 was charged to reference voltage V REF, superimposed pulse signal 213 had pulse to produce, and made time switch M1 closed, and capacitor C 2 is discharged.Behind the end-of-pulsing of superimposed pulse signal 213, time switch M1 disconnects, and charging current source I1 to capacitor C 2 chargings, goes round and begins again again.Therefore the outage indicator signal BRE of timing comparer 602 outputs remains low level, and namely disarmed state shows that AC power 100 accesses this moment are normal.When AC power 100 is disconnected: until after the voltage VC on the capacitor C 2 is charged to reference voltage V REF, superimposed pulse signal 213 still no pulse produces, time switch M1 remains open state, 602 upsets of timing comparer, outage indicator signal BRE is high level, namely effective, show that AC power 100 is disconnected.The highest chip power VCC that is charged to of voltage VC on the capacitor C 2.
When timing circuit shown in Figure 6 207 was used for ac voltage detection circuit 400 shown in Figure 4, the output terminal that the control end of time switch M1 is coupled to rising edge trigger 205 received rising edge pulse signal 211.When timing circuit shown in Figure 6 was used for ac voltage detection circuit 500 shown in Figure 5, the output terminal that the control end of time switch M1 is coupled to negative edge trigger 206 received negative edge pulse signal 212.
The timing circuit that the utility model embodiment adopts is simple, circuit or unit commonly used, and those skilled in the art can grasp and replace these unit easily under the instruction of the utility model embodiment.Particularly along with the development of Digital Design software and digital design language, such as VHDL (Very-High-Speed Integrated Circuit Hardware Description Language, be Very High Speed Integrated Circuit (VHSIC) hardware description language) and Verilog HDL (hardware description language, be hardware description language), the function that those skilled in the art will finish timing circuit just can generate corresponding circuit after using the description of predicate speech automatically.
Fig. 8 a shows according to the X electric capacity of the utility model one embodiment (safety electric capacity) discharge circuit schematic diagram.Shown in Fig. 8 a, described X capacitor discharging circuit comprises: X capacitor C X, have first end and the second end, and described X capacitor C X is in parallel with AC power 100; Discharge circuit 801, has first end, the second end and control end, described first end is coupled to the first end of X capacitor C X, described the second end ground connection, the output terminal that described control end is coupled to ac voltage detection circuit receives outage indicator signal BRE, and described discharge circuit 801 discharges to X capacitor C X when outage indicator signal BRE is effective.
In one embodiment, described discharge circuit 801 comprises discharge current source I2 and the discharge switch M2 that is connected in series, wherein said discharge switch M2 receives outage indicator signal BRE, it is closed when outage indicator signal BRE is effective, first end with described X capacitor C X, form path between discharge current source I2 and the ground, so that X capacitor C X is discharged; When outage indicator signal BRE is invalid, disconnect, with the first end of described X capacitor C X, form between discharge current source I2 and the ground and open circuit.
Embodiment shown in Fig. 8 a, discharge current source I2 are coupled between the first end and discharge switch M2 of X capacitor C X.Described discharge switch M2 has control end, and described control end receives outage indicator signal BRE, and when outage indicator signal BRE was effective, discharge switch M2 was closed, and discharge current source I2 discharges to X capacitor C X.
Those of ordinary skills should be understood that discharge current source I2 can be realized by multiple device and circuit.Fig. 8 b shows according to the X electric capacity of the utility model one embodiment (safety electric capacity) discharge circuit schematic diagram.Compare with Fig. 8 a, the discharge circuit 801 ' among Fig. 8 b adopts resistance R 0 and the discharge switch M2 of series connection to realize.That is to say, discharge current source I2 adopts resistance R 0 to realize.The resistance of resistance R 0 can be set according to the actual practical situation of circuit.
Those of ordinary skills should be understood that the position of the discharge current source I2 shown in Fig. 8 a and discharge switch M2 can exchange.Discharge circuit 801 can adopt any circuit that can discharge to X electric capacity when outage indicator signal BRE is effective.
Although described the utility model with reference to several exemplary embodiments, should be appreciated that used term is explanation and exemplary and nonrestrictive term.Because the utility model is implementation and do not break away from spirit or the essence of utility model in a variety of forms, so be to be understood that, above-described embodiment is not limited to any aforesaid details, and should be in the spirit and scope that the claim of enclosing limits explain widely, therefore fall into whole variations in claim or its equivalent scope and remodeling and all should be the claim of enclosing and contain.
Claims (9)
1. an ac voltage detection circuit is characterized in that, comprising:
Rectification circuit has first input end, and the second input end and output terminal, wherein said first input end and the second input end are coupled to AC power and receive alternating voltage, described output terminal output rectified signal;
Testing circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to rectification circuit receives rectified signal, described output terminal output square-wave signal; And
The outage indicating circuit has input end and output terminal, and wherein said input end is coupled to testing circuit and receives square-wave signal, described output terminal output outage indicator signal.
2. ac voltage detection circuit as claimed in claim 1 is characterized in that, described testing circuit comprises:
Delay circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to rectification circuit receives rectified signal, and described output terminal provides the time-delay rectified signal; And
Comparer, have first input end, the output terminal that the second input end and output terminal, wherein said first input end are coupled to rectification circuit receives rectified signal, described the second input end is coupled to the output terminal reception delay rectified signal of delay circuit, and described comparer is exported square-wave signal at output terminal.
3. ac voltage detection circuit as claimed in claim 1 is characterized in that, described outage indicating circuit comprises:
The rising edge trigger has input end and output terminal, and the output terminal that wherein said input end is coupled to testing circuit receives square-wave signal, and described output terminal is exported the rising edge pulse signal when the rising edge of square-wave signal;
The negative edge trigger has input end and output terminal, and the output terminal that wherein said input end is coupled to testing circuit receives square-wave signal, and described output terminal is exported the negative edge pulse signal when the negative edge of square-wave signal;
Supercircuit has first input end, the second input end and output terminal, and wherein said first input end is coupled to the output terminal of rising edge trigger, and described the second input end is coupled to the output terminal of negative edge trigger, described output terminal output superimposed pulse signal; And
Timing circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to supercircuit receives the superimposed pulse signal, described output terminal output outage indicator signal;
Wherein said timing circuit carries out timing to the superimposed pulse signal, described outage indicator signal is invalid when be less than or equal to the first preset value the interpulse period of superimposed pulse signal, and described outage indicator signal is effective during greater than the first preset value in interpulse period of superimposed pulse signal.
4. ac voltage detection circuit as claimed in claim 1 is characterized in that, described outage indicating circuit comprises:
The rising edge trigger has input end and output terminal, and the output terminal that wherein said input end is coupled to testing circuit receives square-wave signal, and described output terminal is exported the rising edge pulse signal when the rising edge of square-wave signal; And
Timing circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to the rising edge trigger receives the rising edge pulse signal, described output terminal output outage indicator signal;
Wherein said timing circuit carries out timing to the rising edge pulse signal, described outage indicator signal is invalid when be less than or equal to the second preset value the interpulse period of rising edge pulse signal, and described outage indicator signal is effective during greater than the second preset value in interpulse period of rising edge pulse signal.
5. ac voltage detection circuit as claimed in claim 1 is characterized in that, described outage indicating circuit comprises:
The negative edge trigger has input end and output terminal, and the output terminal that wherein said input end is coupled to testing circuit receives square-wave signal, and described output terminal is exported the negative edge pulse signal when the negative edge of square-wave signal; And
Timing circuit has input end and output terminal, and the output terminal that wherein said input end is coupled to the negative edge trigger receives the negative edge pulse signal, described output terminal output outage indicator signal;
Wherein said timing circuit carries out timing to the negative edge pulse signal, described outage indicator signal is invalid when be less than or equal to the 3rd preset value the interpulse period of negative edge pulse signal, and described outage indicator signal is effective during greater than the 3rd preset value in interpulse period of negative edge pulse signal.
6. such as each described ac voltage detection circuit of claim 3～5, it is characterized in that, described timing circuit comprises:
Charging current source has first end and the second end, and described first end is coupled to chip power, and described the second end provides charging current;
Electric capacity has first end and the second end, and described first end is coupled to the second termination of charging current source and receives charging current, described the second end ground connection;
Time switch has first end, the second end and control end, and described first end is coupled to the first end of electric capacity, described the second end ground connection, described control end is coupled to described timing circuit input end; And
The timing comparer has first input end, the second input end and output terminal, and wherein said first input end is coupled to the first end of electric capacity, and described the second input end receives reference voltage, described output terminal output outage indicator signal.
7. a safety capacitor discharging circuit is characterized in that, comprises each described ac voltage detection circuit of claim 1～5, also comprises:
Safety electric capacity has first end and the second end, and described safety electric capacity is in parallel with AC power;
Discharge circuit has first end, the second end and control end, and described first end is coupled to the first end of safety electric capacity, described the second end ground connection, the output terminal that described control end is coupled to ac voltage detection circuit receives the outage indicator signal.
8. safety capacitor discharging circuit as claimed in claim 7 is characterized in that, described discharge circuit comprises discharge current source and the discharge switch that is connected in series, and wherein said discharge switch receives the outage indicator signal, and is closed when the outage indicator signal is effective; When the outage indicator signal is invalid, disconnect.
9. safety capacitor discharging circuit as claimed in claim 8 is characterized in that, described discharge current source comprises resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220343469 CN202661533U (en) | 2012-07-16 | 2012-07-16 | Alternating voltage detection circuit and safety capacitor discharge circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220343469 CN202661533U (en) | 2012-07-16 | 2012-07-16 | Alternating voltage detection circuit and safety capacitor discharge circuit |
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| CN202661533U true CN202661533U (en) | 2013-01-09 |
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| CN 201220343469 Expired - Lifetime CN202661533U (en) | 2012-07-16 | 2012-07-16 | Alternating voltage detection circuit and safety capacitor discharge circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102749498A (en) * | 2012-07-16 | 2012-10-24 | 成都芯源系统有限公司 | Alternating voltage detection circuit and method thereof and safety capacitor discharge circuit |
| CN105572528A (en) * | 2014-11-04 | 2016-05-11 | 意法半导体股份有限公司 | Detection circuit, related active discharge circuit, integrated circuit and method |
| CN107179433A (en) * | 2017-06-07 | 2017-09-19 | 上海乐野网络科技有限公司 | A kind of electric voltage observation circuit |
| CN108020793A (en) * | 2017-12-19 | 2018-05-11 | 湖南大学 | Special power supply exports pulse-detecting circuit and special power supply dead electricity detection method |
| CN108429443A (en) * | 2018-03-08 | 2018-08-21 | 青岛海信电器股份有限公司 | Switching Power Supply power-off protection apparatus, Switching Power Supply and electronic equipment |
| CN117155101A (en) * | 2023-10-31 | 2023-12-01 | 茂睿芯（深圳）科技有限公司 | Discharge control circuit and method for X capacitor and switching power supply |
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- 2012-07-16 CN CN 201220343469 patent/CN202661533U/en not_active Expired - Lifetime
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| CN102749498A (en) * | 2012-07-16 | 2012-10-24 | 成都芯源系统有限公司 | Alternating voltage detection circuit and method thereof and safety capacitor discharge circuit |
| CN102749498B (en) * | 2012-07-16 | 2015-02-04 | 成都芯源系统有限公司 | Alternating voltage detection circuit and method thereof and safety capacitor discharge circuit |
| CN105572528A (en) * | 2014-11-04 | 2016-05-11 | 意法半导体股份有限公司 | Detection circuit, related active discharge circuit, integrated circuit and method |
| US10345348B2 (en) | 2014-11-04 | 2019-07-09 | Stmicroelectronics S.R.L. | Detection circuit for an active discharge circuit of an X-capacitor, related active discharge circuit, integrated circuit and method |
| CN105572528B (en) * | 2014-11-04 | 2020-01-07 | 意法半导体股份有限公司 | Detection circuit, related active discharge circuit, integrated circuit and method |
| CN110940937A (en) * | 2014-11-04 | 2020-03-31 | 意法半导体股份有限公司 | Detection circuit, related active discharge circuit, integrated circuit and method |
| US11750010B2 (en) | 2014-11-04 | 2023-09-05 | Stmicroelectronics S.R.L. | Detection circuit for an active discharge circuit of an X-capacitor, related active discharge circuit, integrated circuit and method |
| CN107179433A (en) * | 2017-06-07 | 2017-09-19 | 上海乐野网络科技有限公司 | A kind of electric voltage observation circuit |
| CN108020793A (en) * | 2017-12-19 | 2018-05-11 | 湖南大学 | Special power supply exports pulse-detecting circuit and special power supply dead electricity detection method |
| CN108429443A (en) * | 2018-03-08 | 2018-08-21 | 青岛海信电器股份有限公司 | Switching Power Supply power-off protection apparatus, Switching Power Supply and electronic equipment |
| CN117155101A (en) * | 2023-10-31 | 2023-12-01 | 茂睿芯（深圳）科技有限公司 | Discharge control circuit and method for X capacitor and switching power supply |
| CN117155101B (en) * | 2023-10-31 | 2024-03-01 | 茂睿芯（深圳）科技有限公司 | Discharge control circuit and method for X capacitor and switching power supply |
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