CN117811578A

CN117811578A - Method, device, equipment and medium for adjusting clock frequency of GPU (graphics processing Unit)

Info

Publication number: CN117811578A
Application number: CN202311843732.2A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Thread Intelligent Technology Chengdu Co ltd
Current assignee: Moore Thread Intelligent Technology Chengdu Co ltd
Priority date: 2023-12-27
Filing date: 2023-12-27
Publication date: 2024-04-02

Abstract

The present disclosure relates to a method, apparatus, device and medium for adjusting clock frequency of a GPU. The method comprises the following steps: in response to a change in the target clock frequency of the GPU, calculating a target parameter value of a frequency divider and a target parameter value of a pulse controller according to the target clock frequency after/before the change, wherein the frequency divider is used for dividing the clock frequency output by the phase-locked loop, and the pulse controller is used for adjusting the clock frequency output by the frequency divider; configuring parameters of the frequency divider according to target parameter values of the frequency divider; and configuring parameters of the pulse controller according to the target parameter values of the pulse controller.

Description

Method, device, equipment and medium for adjusting clock frequency of GPU (graphics processing Unit)

Technical Field

The disclosure relates to the field of computer technology, and in particular, to a method for adjusting a clock frequency of a GPU, an apparatus for adjusting a clock frequency of a GPU, an electronic device, and a storage medium.

Background

The clock frequency of the GPU (Graphics Processing Unit, graphics processor) determines the speed at which the GPU performs graphics computations and rendering tasks in units of time. Higher clock frequencies generally lead to better graphics processing performance while also yielding higher power consumption.

Disclosure of Invention

The disclosure provides a clock frequency adjustment technical scheme for a GPU.

According to an aspect of the present disclosure, there is provided a method for adjusting a clock frequency of a GPU, including:

in response to a change in the target clock frequency of the GPU, calculating a target parameter value of a frequency divider and a target parameter value of a pulse controller according to the target clock frequency after/before the change, wherein the frequency divider is used for dividing the clock frequency output by the phase-locked loop, and the pulse controller is used for adjusting the clock frequency output by the frequency divider;

configuring parameters of the frequency divider according to target parameter values of the frequency divider;

and configuring parameters of the pulse controller according to the target parameter values of the pulse controller.

In one possible implementation, the parameter values of the phase-locked loop remain fixed after the phase-locked loop is initialized.

In one possible implementation, the parameters of the pulse controller include a frequency division coefficient and an output coefficient; the frequency division coefficient of the pulse controller represents the number of divided clock frequencies output by the frequency divider; the output coefficient represents the number of parts output by the pulse controller in the number of parts obtained by dividing the clock frequency output by the frequency divider;

The clock frequency output by the pulse controller is the product of a first ratio and the output coefficient, wherein the first ratio is the ratio of the clock frequency output by the frequency divider to the frequency division coefficient of the pulse controller.

In one possible implementation, the phase-locked loop initialization process includes:

acquiring a preset maximum clock frequency and a preset minimum clock frequency;

calculating a target parameter value of the phase-locked loop according to the preset maximum clock frequency and the preset minimum clock frequency;

and configuring parameters of the phase-locked loop according to the target parameter values of the phase-locked loop.

In one possible implementation, the calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the target clock frequency after/before the change includes:

calculating a target parameter value of a frequency divider and a target parameter value of a pulse controller according to the changed target clock frequency in response to the changed target clock frequency being between a preset maximum clock frequency and a preset minimum clock frequency;

or,

calculating a target parameter value of a frequency divider and a target parameter value of a pulse controller according to a preset maximum clock frequency in response to the changed target clock frequency being greater than the preset maximum clock frequency;

Or,

and in response to the changed target clock frequency being smaller than a preset minimum clock frequency, calculating a target parameter value of the frequency divider and a target parameter value of the pulse controller according to the preset minimum clock frequency.

In one possible implementation of the present invention,

after calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the preset maximum clock frequency, the method further comprises: updating the preset maximum clock frequency according to the changed target clock frequency;

or,

after the calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the preset minimum clock frequency, the method further comprises: and updating the preset minimum clock frequency according to the changed target clock frequency.

In one possible implementation, the initializing process of the frequency divider and the pulse controller includes:

obtaining an initialization parameter value of the frequency divider and an initialization parameter value of the pulse controller;

configuring parameters of the frequency divider according to the initialized parameter values of the frequency divider;

And configuring parameters of the pulse controller according to the initialized parameter values of the pulse controller.

In one possible implementation, the obtaining the initialization parameter value of the frequency divider and the initialization parameter value of the pulse controller includes:

acquiring an initial value of a clock frequency;

and calculating the initialization parameter value of the frequency divider and the initialization parameter value of the pulse controller according to the clock frequency output by the phase-locked loop and the initial value of the clock frequency.

According to an aspect of the present disclosure, there is provided an adjusting apparatus for a clock frequency of a GPU, including:

the computing module is used for responding to the change of the target clock frequency of the GPU, and computing a target parameter value of a frequency divider and a target parameter value of a pulse controller according to the target clock frequency after the change/before the change, wherein the frequency divider is used for dividing the clock frequency output by the phase-locked loop, and the pulse controller is used for adjusting the clock frequency output by the frequency divider;

the first configuration module is used for configuring parameters of the frequency divider according to target parameter values of the frequency divider;

and the second configuration module is used for configuring parameters of the pulse controller according to the target parameter values of the pulse controller.

In one possible implementation manner, the apparatus further includes a first initialization module configured to:

In one possible implementation, the computing module is configured to:

or,

In one possible implementation manner, the apparatus further includes an updating module configured to:

updating the preset maximum clock frequency according to the changed target clock frequency;

or,

and updating the preset minimum clock frequency according to the changed target clock frequency.

In a possible implementation manner, the apparatus further includes a second initialization module, configured to:

In one possible implementation manner, the second initialization module is configured to:

acquiring an initial value of a clock frequency;

According to an aspect of the present disclosure, there is provided an electronic apparatus including: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to invoke the executable instructions stored by the memory to perform the above-described method.

According to an aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method.

According to an aspect of the present disclosure, there is provided a computer program product comprising a computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in an electronic device, a processor in the electronic device performs the above method.

In the embodiment of the disclosure, in response to a change of a target clock frequency of a GPU, a target parameter value of a frequency divider and a target parameter value of a pulse controller are calculated according to the target clock frequency after/before the change, wherein the frequency divider is used for dividing a clock frequency output by a phase-locked loop, the pulse controller is used for adjusting the clock frequency output by the frequency divider, parameters of the frequency divider are configured according to the target parameter value of the frequency divider, and parameters of the pulse controller are configured according to the target parameter value of the pulse controller, so that in the process of operating the GPU, the clock frequency of the GPU is adjusted through the frequency divider and the pulse controller, and the adjusting speed and the adjusting precision of the clock frequency of the GPU can be improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.

Fig. 1 shows a flowchart of a method for adjusting a clock frequency of a GPU according to an embodiment of the present disclosure.

Fig. 2 illustrates an application scenario of a method for adjusting a clock frequency of a GPU according to an embodiment of the present disclosure.

Fig. 3 shows a block diagram of an adjustment apparatus for a clock frequency of a GPU provided by an embodiment of the present disclosure.

Fig. 4 shows a block diagram of an electronic device 1900 provided by an embodiment of the disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.

In the related art, the clock frequency of the GPU is mainly adjusted in the following three ways.

The first way is to switch to the backup phase-locked loop (Phase Locked Loop, PLL) when the GPU clock frequency needs to be adjusted, adjust the parameters of the main phase-locked loop during the operation of the backup phase-locked loop, and switch back to the main phase-locked loop after the parameter adjustment of the main phase-locked loop is completed. In this way, a backup phase locked loop needs to be provided and the adjustment time is long.

The second way is to continuously adjust the parameters of the phase-locked loop several times with small amplitude when the clock frequency of the GPU needs to be adjusted. In this way, a backup phase-locked loop is not required, but the adjustment times are more, and the adjustment time is still longer.

The third way is to adjust the clock frequency of the GPU by means of a divider (frequency divider). The frequency divider is not fine enough in frequency division, so that the adjustment amplitude is large, and the accuracy of clock frequency adjustment is low.

In order to solve the technical problem similar to the above, the embodiments of the present disclosure provide a method for adjusting a clock frequency of a GPU, which is configured to calculate, in response to a change in a target clock frequency of the GPU, a target parameter value of a frequency divider and a target parameter value of a pulse controller according to the target clock frequency after/before the change, wherein the frequency divider is configured to divide a clock frequency output by a phase-locked loop, the pulse controller is configured to adjust the clock frequency output by the frequency divider, configure a parameter of the frequency divider according to the target parameter value of the frequency divider, and configure a parameter of the pulse controller according to the target parameter value of the pulse controller, thereby adjusting the clock frequency of the GPU through the frequency divider and the pulse controller during operation of the GPU, and improving an adjustment speed and an adjustment accuracy of the clock frequency of the GPU.

In the related art, the clock frequency of the GPU is adjusted through the phase-locked loop, so that the reliability of clock output can be ensured only by waiting for hardware locking, and the adjustment time is in the microsecond level and is about 5 mu s. According to the embodiment of the disclosure, the clock frequency of the GPU is adjusted through the frequency divider and the pulse controller without hardware locking, and the adjustment time length is nanosecond and is about 4ns. Therefore, compared with the scheme of adjusting the clock frequency of the GPU based on the backup phase-locked loop in the related art, the embodiment of the disclosure can improve the adjusting precision of the clock frequency of the GPU. In addition, compared with the scheme of adjusting the clock frequency of the GPU based on the backup phase-locked loop in the related art, the embodiment of the disclosure does not need the participation of the backup phase-locked loop in the process of adjusting the clock frequency of the GPU, so that the hardware cost can be saved.

Compared with the scheme of adjusting the parameters of the phase-locked loop to adjust the clock frequency of the GPU by continuously adjusting the parameters of the phase-locked loop for a plurality of times with small amplitude in the related art, the embodiment of the disclosure does not need to adjust for a plurality of times, so that the adjusting speed of the clock frequency of the GPU can be improved.

In addition, compared with the scheme that the clock frequency of the GPU is adjusted only through the frequency divider in the related art, in the embodiment of the disclosure, the clock frequency of the GPU is adjusted through combining the frequency divider and the pulse controller, and therefore the adjusting precision of the clock frequency of the GPU can be greatly improved.

The following describes in detail a method for adjusting a clock frequency of a GPU according to an embodiment of the present disclosure with reference to the accompanying drawings.

Fig. 1 shows a flowchart of a method for adjusting a clock frequency of a GPU according to an embodiment of the present disclosure. In one possible implementation manner, the execution subject of the method for adjusting the clock frequency of the GPU may be an adjusting device for adjusting the clock frequency of the GPU, for example, the method for adjusting the clock frequency of the GPU may be executed by a terminal device or a server or other electronic devices. The terminal device may be a User Equipment (UE), a mobile device, a User terminal, a cellular phone, a cordless phone, a personal digital assistant (Personal Digital Assistant, PDA), a handheld device, a computing device, a vehicle mounted device, a wearable device, or the like. In some possible implementations, the method for adjusting the clock frequency of the GPU may be implemented by a processor invoking computer readable instructions stored in a memory. As shown in fig. 1, the method for adjusting the clock frequency of the GPU includes steps S11 to S13.

In step S11, in response to the change of the target clock frequency of the GPU, a target parameter value of a frequency divider for dividing the clock frequency output by the phase-locked loop and a target parameter value of a pulse controller for adjusting the clock frequency output by the frequency divider are calculated according to the target clock frequency after/before the change.

In step S12, parameters of the frequency divider are configured according to target parameter values of the frequency divider.

In step S13, parameters of the pulse controller are configured according to target parameter values of the pulse controller.

In the embodiment of the disclosure, the method for adjusting the clock frequency of the GPU may be adopted for at least part of clock domains in the GPU. For example, the method for adjusting the clock frequency of the GPU provided by the embodiments of the present disclosure may be respectively adopted for each clock domain in the GPU.

In one possible implementation, the phase-locked loop initialization process includes: acquiring a preset maximum clock frequency and a preset minimum clock frequency; calculating a target parameter value of the phase-locked loop according to the preset maximum clock frequency and the preset minimum clock frequency; and configuring parameters of the phase-locked loop according to the target parameter values of the phase-locked loop.

In this implementation, the preset maximum clock frequency may be determined according to the historical maximum value of the target clock frequency of the GPU; the preset minimum clock frequency may be determined based on a historical minimum of the target clock frequency of the GPU.

As an example of this implementation, a historical maximum of the target clock frequency of the GPU may be determined as a preset maximum clock frequency; the historical minimum of the target clock frequency of the GPU may be determined as the preset minimum clock frequency.

As another example of this implementation, the historical maximum of the target clock frequency of the GPU may be fine-tuned to obtain a preset maximum clock frequency; the historical minimum value of the target clock frequency of the GPU can be finely adjusted to obtain the preset minimum clock frequency. For example, the sum of the historical maximum value of the target clock frequency of the GPU and the first preset clock frequency may be determined as the preset maximum clock frequency; the difference between the historical minimum of the target clock frequency of the GPU and the second preset clock frequency may be determined as the preset minimum clock frequency. For another example, the product of the historical maximum value of the target clock frequency of the GPU and the first preset proportion may be determined as the preset maximum clock frequency; the product of the historical minimum of the target clock frequency of the GPU and the second preset ratio may be determined as the preset minimum clock frequency.

In this implementation, after the preset maximum clock frequency and the preset minimum clock frequency are acquired, a target parameter value of the phase-locked loop that satisfies the preset maximum clock frequency and the preset minimum clock frequency may be calculated. As an example of this implementation, the target parameter value of the phase locked loop may be calculated by a pre-calculation module from a preset maximum clock frequency and a preset minimum clock frequency. In some application scenarios, the pre-calculation module may also be referred to as a pre-calculator, etc., which is not limited herein.

In this implementation, after the target parameter value of the phase-locked loop is calculated, the parameters of the phase-locked loop may be configured according to the target parameter value of the phase-locked loop to initialize the phase-locked loop.

As an example of this implementation, the phase locked loop may output at least one clock frequency, and the one clock frequency may be equal to a preset maximum clock frequency.

In the implementation mode, the target parameter value of the phase-locked loop is calculated according to the preset maximum clock frequency and the preset minimum clock frequency by acquiring the preset maximum clock frequency and the preset minimum clock frequency, and the parameters of the phase-locked loop are configured according to the target parameter value of the phase-locked loop, so that the phase-locked loop is initialized according to the preset maximum clock frequency and the preset minimum clock frequency, and the clock frequency output by the phase-locked loop can meet the requirement of most scenes on the clock frequency.

As an example of this implementation, the initialization process of the frequency divider and the pulse controller includes: obtaining an initialization parameter value of the frequency divider and an initialization parameter value of the pulse controller; configuring parameters of the frequency divider according to the initialized parameter values of the frequency divider; and configuring parameters of the pulse controller according to the initialized parameter values of the pulse controller.

In one example, the initialization parameter value of the frequency divider may be obtained by calculation.

In another example, the initialization parameter value of the frequency divider may be a preset value.

In one example, the initialization parameter value of the pulse controller may be obtained by calculation.

In this example, after obtaining the initialization parameter value of the frequency divider, the parameters of the frequency divider may be configured to initialize the frequency divider according to the initialization parameter value of the frequency divider. After obtaining the initialization parameter value of the pulse controller, the parameters of the pulse controller may be configured according to the initialization parameter value of the pulse controller to initialize the pulse controller.

In this example, by obtaining the initialization parameter value of the frequency divider and the initialization parameter value of the pulse controller, the parameters of the frequency divider are configured according to the initialization parameter value of the frequency divider, and the parameters of the pulse controller are configured according to the initialization parameter value of the pulse controller, whereby the initialization of the frequency divider and the pulse controller can be achieved.

In one example, the obtaining the initialization parameter value of the frequency divider and the initialization parameter value of the pulse controller includes: acquiring an initial value of a clock frequency; and calculating the initialization parameter value of the frequency divider and the initialization parameter value of the pulse controller according to the clock frequency output by the phase-locked loop and the initial value of the clock frequency. In this example, the initial value of the clock frequency may be a default value, or may be set by the user.

In this example, after the initial value of the clock frequency is acquired, the initialization parameter value of the frequency divider and the initialization parameter value of the pulse controller may be calculated from the clock frequency output by the phase-locked loop and the initial value of the clock frequency so that the clock frequency output by the pulse controller is equal to or close to the initial value of the clock frequency.

In this example, after the frequency divider is configured according to the initialization parameter value of the frequency divider and the pulse controller is configured according to the initialization parameter value of the pulse controller, the absolute value of the difference between the clock frequency output by the pulse controller and the initial value of the clock frequency becomes minimum. That is, the absolute value of the difference between the clock frequency output by the pulse controller and the initial value of the clock frequency after the frequency divider and the pulse controller are configured according to the initialization parameter value of the frequency divider and the initialization parameter value of the pulse controller is smaller than the absolute value of the difference between the clock frequency output by the pulse controller and the initial value of the clock frequency after the frequency divider and the pulse controller are configured according to the other parameter values.

In this example, by acquiring an initial value of the clock frequency and calculating the initialization parameter value of the frequency divider and the initialization parameter value of the pulse controller from the clock frequency output by the phase-locked loop and the initial value of the clock frequency, the clock frequency output by the pulse controller can be made as close to the initial value of the clock frequency as possible.

In one possible implementation, the parameters of the pulse controller include a frequency division coefficient and an output coefficient; the frequency division coefficient of the pulse controller represents the number of divided clock frequencies output by the frequency divider; the output coefficient represents the number of parts output by the pulse controller in the number of parts obtained by dividing the clock frequency output by the frequency divider; the clock frequency output by the pulse controller is the product of a first ratio and the output coefficient, wherein the first ratio is the ratio of the clock frequency output by the frequency divider to the frequency division coefficient of the pulse controller.

In this implementation, the clock frequency output by the pulse controller may be determined from DIV/DENXN. Wherein DIV represents the clock frequency output by the frequency divider, DEN represents the frequency division coefficient of the pulse controller, and N represents the output coefficient of the pulse controller.

By adopting the implementation mode, the clock frequency output by the frequency divider can be finely adjusted.

In another possible implementation, the clock frequency output by the pulse controller may be determined from DIV-STEP× (DEN-N). Wherein DIV represents the clock frequency output by the frequency divider, DEN represents the frequency division coefficient of the pulse controller, N represents the output coefficient of the pulse controller, STEP represents the STEP, and STEP is equal to the ratio of DIV to DEN.

In another possible implementation, the parameter of the pulse controller includes a scaling factor, and the clock frequency output by the pulse controller is a product of the clock frequency output by the frequency divider and the scaling factor.

In one possible implementation, the parameter values of the phase-locked loop remain fixed after the phase-locked loop is initialized. In this implementation, the parameter values of the phase-locked loop may be kept unchanged after the phase-locked loop is initialized, whereby the time-consuming phase-locked loop parameter configuration only needs to be performed once at initialization.

In the embodiment of the disclosure, during the operation of the GPU, the target clock frequency of the GPU may be determined according to the workload (workload) of the host side. The workload may also be referred to as an application load, and the like, and is not limited herein. The target clock frequency of the GPU may represent a target value of the clock frequency of the GPU. In the disclosed embodiment, the actual clock frequency of the GPU is the clock frequency of the pulse controller output. The clock frequency of the pulse controller output may be equal to or close to the target clock frequency of the GPU but not equal to the target clock frequency of the GPU.

In one possible implementation, the target clock frequency of the GPU may be determined by a dynamic voltage frequency scaling (Dynamic Voltage and Frequency Scaling, DVFS) module at the GPU side from the workload at the host side.

In one possible implementation, the target voltage of the GPU may also be determined according to the workload at the host side. After the target voltage is determined, the operating voltage of the GPU may be adjusted by a voltage adjustment module at the GPU side.

As one example of this implementation, the target voltage may be determined from the workload at the host side by dynamic voltage frequency adjustment at the GPU side.

In the embodiment of the disclosure, during the operation of the GPU, the target parameter value of the frequency divider and the target parameter value of the pulse controller may be calculated according to the changed target clock frequency or according to the changed target clock frequency and the target clock frequency before the change in response to the change of the target clock frequency of the GPU.

In one possible implementation, during operation of the GPU, the target parameter value of the frequency divider and the target parameter value of the pulse controller may be calculated in response to a change in the target clock frequency of the GPU, based on the changed target clock frequency.

In another possible implementation manner, during the operation of the GPU, the target clock frequency of the GPU may be changed in response to the target clock frequency of the GPU, and the absolute value of the difference between the target clock frequency after the change and the target clock frequency before the change is greater than or equal to a preset threshold value, and the target parameter value of the frequency divider and the target parameter value of the pulse controller are calculated according to the target clock frequency after the change. In this implementation, if the absolute value of the difference between the target clock frequency after the change and the target clock frequency before the change is smaller than a preset threshold, the parameter values of the frequency divider and the pulse controller may not be adjusted.

In one possible implementation, the calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the target clock frequency after/before the change includes: calculating a target parameter value of a frequency divider and a target parameter value of a pulse controller according to the changed target clock frequency in response to the changed target clock frequency being between a preset maximum clock frequency and a preset minimum clock frequency; or, in response to the changed target clock frequency being greater than a preset maximum clock frequency, calculating a target parameter value of the frequency divider and a target parameter value of the pulse controller according to the preset maximum clock frequency; or in response to the changed target clock frequency being less than a preset minimum clock frequency, calculating a target parameter value of the frequency divider and a target parameter value of the pulse controller according to the preset minimum clock frequency.

In this implementation, when the changed target clock frequency of the GPU is less than or equal to the preset maximum clock frequency and greater than or equal to the preset minimum clock frequency, the target parameter value of the frequency divider and the target parameter value of the pulse controller may be calculated according to the changed target clock frequency, so that the clock frequency output by the pulse controller is closest to the changed target clock frequency. The target parameter value of the frequency divider and the target parameter value of the pulse controller enable the clock frequency output by the pulse controller to be closest to the changed target clock frequency, which may mean that the clock frequency output by the pulse controller corresponding to the target parameter value combination is closer to the changed target clock frequency than the clock frequency output by the pulse controller corresponding to other parameter value combinations in all parameter value combinations of the frequency divider and the pulse controller. The parameter value combination may represent a combination of a parameter value of the frequency divider and a parameter value of the pulse controller, for example, the parameter value combination may represent a combination of a value of a frequency division coefficient of the frequency divider, a value of a frequency division coefficient of the pulse controller, and a value of an output coefficient of the pulse controller. The target parameter combination may represent a combination of a target parameter value of the frequency divider and a target parameter value of the pulse controller. In the implementation manner, the target parameter value of the frequency divider and the target parameter value of the pulse controller are calculated according to the changed target clock frequency by responding to the changed target clock frequency between the preset maximum clock frequency and the preset minimum clock frequency, so that the requirement of the current scene on the clock frequency can be better met, and the performance and the power consumption of the GPU can be better balanced.

In this implementation, the target parameter value of the frequency divider and the target parameter value of the pulse controller may be calculated according to the preset maximum clock frequency in response to the changed target clock frequency of the GPU being greater than the preset maximum clock frequency, so that the clock frequency output by the pulse controller is closest to the preset maximum clock frequency. For example, the frequency division coefficient of the frequency divider may be calculated to be 1, the frequency division coefficient of the pulse controller is 255, and the output coefficient of the pulse controller is 255, so that the clock frequency output by the pulse controller is equal to the preset maximum clock frequency. By responding to the fact that the changed target clock frequency is larger than the preset maximum clock frequency, according to the preset maximum clock frequency, the target parameter value of the frequency divider and the target parameter value of the pulse controller are calculated, and therefore the requirement of a current scene on the clock frequency can be better met on the premise that the clock frequency output by the pulse controller is smaller than or equal to the preset maximum clock frequency.

In this implementation, the target parameter value of the frequency divider and the target parameter value of the pulse controller may be calculated according to the preset minimum clock frequency in response to the changed target clock frequency of the GPU being less than the preset minimum clock frequency, so that the clock frequency output by the pulse controller is closest to the preset minimum clock frequency. And calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the preset minimum clock frequency by responding to the fact that the changed target clock frequency is smaller than the preset minimum clock frequency, so that the requirement of the current scene on the clock frequency can be better met on the premise that the clock frequency output by the pulse controller is larger than or equal to the preset minimum clock frequency.

As an example of this implementation, after said calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to said preset maximum clock frequency, the method further comprises: updating the preset maximum clock frequency according to the changed target clock frequency; alternatively, after calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the preset minimum clock frequency, the method further includes: and updating the preset minimum clock frequency according to the changed target clock frequency.

In one example, in a case where the changed target clock frequency of the GPU is greater than the preset maximum clock frequency, after calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the preset maximum clock frequency, the preset maximum clock frequency may be updated to the changed target clock frequency, that is, the changed target clock frequency may be regarded as the updated preset maximum clock frequency.

In one example, in a case where the changed target clock frequency of the GPU is smaller than the preset minimum clock frequency, after calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the preset minimum clock frequency, the preset minimum clock frequency may be updated to the changed target clock frequency, that is, the changed target clock frequency may be regarded as the updated preset minimum clock frequency.

In this example, when the changed target clock frequency of the GPU is greater than a preset maximum clock frequency, after calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the preset maximum clock frequency, the preset maximum clock frequency is updated according to the changed target clock frequency, or when the target clock frequency of the GPU is less than a preset minimum clock frequency, after calculating the target parameter value of the frequency divider and the target parameter value of the pulse controller according to the preset minimum clock frequency, the preset minimum clock frequency is updated according to the changed target clock frequency, so that the optimized maximum value of the clock frequency output by the phase-locked loop can meet the requirements of more scenes by running iteration.

The method for adjusting the clock frequency of the GPU provided by the embodiment of the present disclosure may be applied to the technical fields of frequency adjustment, power consumption control, and the like, and is not limited herein.

The method for adjusting the clock frequency of the GPU according to the embodiments of the present disclosure is described below with reference to a specific application scenario. Fig. 2 illustrates an application scenario of a method for adjusting a clock frequency of a GPU according to an embodiment of the present disclosure. As shown in fig. 2, the dynamic voltage frequency adjustment module at the GPU side may determine the target clock frequency and the target working voltage of the GPU according to the workload at the host side. The pre-calculation module may calculate a target parameter value of the frequency divider and a target parameter value of the pulse controller based on the target clock frequency of the GPU. The frequency divider can be used for dividing the clock frequency output by the phase-locked loop, and the pulse controller can be used for adjusting the clock frequency output by the frequency divider. The voltage adjusting module can adjust the working voltage of the GPU according to the target working voltage of the GPU.

The following describes the flow of adjusting the clock frequency of the GPU.

1. During GPU initialization

Step 1: the historical maximum value of the target clock frequency of the GPU may be determined as a preset maximum clock frequency, and the historical minimum value of the target clock frequency of the GPU may be determined as a preset minimum clock frequency.

Step 2: the target parameter values of the phase-locked loop meeting the preset maximum clock frequency and the preset minimum clock frequency can be calculated through the pre-calculation module, and parameters of the phase-locked loop can be configured according to the target parameter values of the phase-locked loop so as to initialize the phase-locked loop. The parameters of the phase-locked loop only need to be initialized once at power-up, and then can be kept unchanged.

Step 3: an initial value of the clock frequency may be obtained, and an initialization parameter value of the frequency divider and an initialization parameter value of the pulse controller may be calculated from the clock frequency output by the phase locked loop and the initial value of the clock frequency. Parameters of the frequency divider may be configured to initialize the frequency divider based on initialization parameter values of the frequency divider. Parameters of the pulse controller may be configured to initialize the pulse controller based on initialization parameter values of the pulse controller.

2. During the operation of the GPU

Step 1: and (2) judging whether the changed target clock frequency is between the preset maximum clock frequency and the preset minimum clock frequency or not in response to the change of the target clock frequency of the GPU, if so, entering the step (2 a), otherwise, entering the step (2 b).

Step 2a: the target parameter value of the frequency divider and the target parameter value of the pulse controller can be calculated by a pre-calculation module according to the changed target clock frequency.

Step 2b: the target parameter value of the frequency divider and the target parameter value of the pulse controller can be calculated according to the preset maximum clock frequency through a pre-calculation module in response to the changed target clock frequency being larger than the preset maximum clock frequency, and the target clock frequency can be used as the updated preset maximum clock frequency; alternatively, the target parameter value of the frequency divider and the target parameter value of the pulse controller may be calculated by the pre-calculation module according to the preset minimum clock frequency in response to the changed target clock frequency being smaller than the preset minimum clock frequency, and the target clock frequency may be used as the updated preset minimum clock frequency.

Step 3: parameters of the frequency divider may be configured according to target parameter values of the frequency divider, and parameters of the pulse controller may be configured according to target parameter values of the pulse controller.

Table 1 shows a schematic table of clock frequencies output by the pulse controller in the method for adjusting clock frequencies of the GPU according to the embodiment of the present disclosure.

TABLE 1

In table 1, the PLL is listed as the clock frequency output by the phase-locked loop, the postiv is listed as the frequency division coefficient of the frequency divider, the DIV is listed as the clock frequency output by the frequency divider, the DEN is listed as the frequency division coefficient of the pulse controller, and the STEP is listed as the STEP (i.e., the ratio of the clock frequency output by the frequency divider to the frequency division coefficient of the pulse controller); 254 is listed as the clock frequency output by the pulse controller if N equals 254; 253 is the clock frequency output by the pulse controller with N equal to 253.

In the example shown in table 1, the frequency division coefficient of the pulse controller may be set to 255 at maximum. Of course, the frequency division coefficient of the pulse controller can be set to be smaller than 255 according to the actual application scene requirement.

As shown in table 1, in the case where the clock frequency of the phase locked loop output is 9000, the clock frequency of the frequency divider output may be 3000, 2250, 1800, or the like. The span between the adjacent clock frequencies of the frequency divider output is larger, and the requirements of different scenes are difficult to meet.

The clock frequency of the pulse controller output may be 3000, 2988.24, 2976.47, etc. From this, the pulse controller can output finer clock frequency than the frequency divider, so that the requirements of most scenes can be satisfied.

It will be appreciated that the above-mentioned method embodiments of the present disclosure may be combined with each other to form a combined embodiment without departing from the principle logic, and are limited to the description of the present disclosure. It will be appreciated by those skilled in the art that in the above-described methods of the embodiments, the particular order of execution of the steps should be determined by their function and possible inherent logic.

In addition, the disclosure further provides an adjusting device, an electronic device, a computer readable storage medium and a computer program product for the clock frequency of the GPU, which can be used to implement any of the adjusting methods for the clock frequency of the GPU provided in the disclosure, and the corresponding technical schemes and technical effects can be referred to the corresponding records of the method parts and are not repeated.

Fig. 3 shows a block diagram of an adjustment apparatus for a clock frequency of a GPU provided by an embodiment of the present disclosure. As shown in fig. 3, the adjusting device for the clock frequency of the GPU includes:

A calculating module 31, configured to calculate, in response to a change in a target clock frequency of the GPU, a target parameter value of a frequency divider and a target parameter value of a pulse controller according to the target clock frequency after/before the change, where the frequency divider is configured to divide a clock frequency output by the phase-locked loop, and the pulse controller is configured to adjust the clock frequency output by the frequency divider;

a first configuration module 32, configured to configure parameters of the frequency divider according to target parameter values of the frequency divider;

a second configuration module 33, configured to configure parameters of the pulse controller according to target parameter values of the pulse controller.

In one possible implementation, the computing module 31 is configured to:

or,

Or,

or,

acquiring an initial value of a clock frequency;

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementation and technical effects of the functions or modules may refer to the descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described method. Wherein the computer readable storage medium may be a non-volatile computer readable storage medium or may be a volatile computer readable storage medium.

The disclosed embodiments also propose a computer program comprising computer readable code which, when run in an electronic device, causes a processor in the electronic device to carry out the above method.

Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in an electronic device, causes a processor in the electronic device to perform the above method.

The embodiment of the disclosure also provides an electronic device, including: one or more processors; a memory for storing executable instructions; wherein the one or more processors are configured to invoke the executable instructions stored by the memory to perform the above-described method.

The electronic device may be provided as a terminal, server or other form of device.

Fig. 4 shows a block diagram of an electronic device 1900 provided by an embodiment of the disclosure. For example, electronic device 1900 may be provided as a server or a terminal. Referring to FIG. 4, electronic device 1900 includes a processing component 1922 that further includes one or more processors and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by processing component 1922. The application programs stored in memory 1932 may include one or more modules each corresponding to a set of instructions. Further, processing component 1922 is configured to execute instructions to perform the methods described above.

The electronic device 1900 may also include a power component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input/output interface 1958 (I/O interface). Electronic device 1900 may operate an operating system based on memory 1932, such as the Microsoft Server operating system (Windows Server) ^TM ) Apple Inc. developed graphical user interface based operating System (Mac OS X ^TM ) Multi-user multi-process computer operationWorking system (Unix) ^TM ) Unix-like operating system (Linux) of free and open source code ^TM ) Unix-like operating system (FreeBSD) with open source code ^TM ) Or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 1932, including computer program instructions executable by processing component 1922 of electronic device 1900 to perform the methods described above.

The present disclosure may be a system, method, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for causing a processor to implement aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.

The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.

Computer program instructions for performing the operations of the present disclosure can be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, c++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present disclosure are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information of computer readable program instructions, which can execute the computer readable program instructions.

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The computer program product may be realized in particular by means of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.

The foregoing description of various embodiments is intended to highlight differences between the various embodiments, which may be the same or similar to each other by reference, and is not repeated herein for the sake of brevity.

If the technical scheme of the embodiment of the disclosure relates to personal information, the product applying the technical scheme of the embodiment of the disclosure clearly informs the personal information processing rule and obtains personal independent consent before processing the personal information. If the technical solution of the embodiment of the present disclosure relates to sensitive personal information, the product applying the technical solution of the embodiment of the present disclosure obtains individual consent before processing the sensitive personal information, and simultaneously meets the requirement of "explicit consent". For example, a clear and remarkable mark is set at a personal information acquisition device such as a camera to inform that the personal information acquisition range is entered, personal information is acquired, and if the personal voluntarily enters the acquisition range, the personal information is considered as consent to be acquired; or on the device for processing the personal information, under the condition that obvious identification/information is utilized to inform the personal information processing rule, personal authorization is obtained by popup information or a person is requested to upload personal information and the like; the personal information processing rule may include information such as a personal information processor, a personal information processing purpose, a processing mode, and a type of personal information to be processed.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for adjusting a clock frequency of a GPU, comprising:

2. The method of claim 1, wherein the parameter values of the phase-locked loop remain fixed after the phase-locked loop is initialized.

3. A method according to claim 1 or 2, wherein the parameters of the pulse controller include a division factor and an output factor; the frequency division coefficient of the pulse controller represents the number of divided clock frequencies output by the frequency divider; the output coefficient represents the number of parts output by the pulse controller in the number of parts obtained by dividing the clock frequency output by the frequency divider;

4. The method according to claim 1 or 2, wherein the phase locked loop initialization procedure comprises:

5. The method according to claim 1 or 2, wherein said calculating a target parameter value of a frequency divider and a target parameter value of a pulse controller from said target clock frequency after/before a change comprises:

or,

6. The method of claim 5, wherein the step of determining the position of the probe is performed,

Or,

7. The method of claim 4, wherein the initializing process of the frequency divider and the pulse controller comprises:

8. The method of claim 7, wherein the obtaining the initialization parameter values of the frequency divider and the initialization parameter values of the pulse controller comprises:

acquiring an initial value of a clock frequency;

9. An adjustment device for a clock frequency of a GPU, comprising:

10. An electronic device, comprising:

one or more processors;

a memory for storing executable instructions;

wherein the one or more processors are configured to invoke the memory-stored executable instructions to perform the method of any of claims 1 to 8.

11. A computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1 to 8.