CN117559760A - Control method for inhibiting direct-current voltage fluctuation of three-level inverter - Google Patents

Control method for inhibiting direct-current voltage fluctuation of three-level inverter Download PDF

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Publication number
CN117559760A
CN117559760A CN202311525256.XA CN202311525256A CN117559760A CN 117559760 A CN117559760 A CN 117559760A CN 202311525256 A CN202311525256 A CN 202311525256A CN 117559760 A CN117559760 A CN 117559760A
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axis component
voltage
current
pwm
level inverter
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Inventor
刘翼肇
王金浩
温敏敏
王春斌
秦亚斌
杨超颖
王磊
李胜文
吴佳
杨洋
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State Grid Electric Power Research Institute Of Sepc
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State Grid Electric Power Research Institute Of Sepc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention relates to a control method for inhibiting direct-current voltage fluctuation of a three-level inverter, and belongs to the technical field of three-level inverters. The invention comprises the following steps: outputting a PWM reference voltage d-axis component based on a DC error and an AC error of the three-level inverter; outputting a PWM reference voltage q-axis component based on a difference between the output voltage and the output voltage reactive voltage; outputting a PWM reference voltage 0-axis component based on a difference between the upper DC bus voltage and the lower DC bus voltage; and modulating the PWM reference voltage, the first side inductance current, the upper direct current bus voltage and the lower direct current bus voltage by using a midpoint balance modulation algorithm to obtain PWM control signals so as to control the switch of the three-level inverter. The method directly reflects the difference value of the upper and lower DC bus voltages on the control of the zero sequence current, effectively eliminates the zero sequence current in the circuit, obviously reduces the fundamental frequency power exchange between the upper and lower buses of the DC capacitor, and effectively inhibits the DC voltage fluctuation of the three-level inverter.

Description

Control method for inhibiting direct-current voltage fluctuation of three-level inverter
Technical Field
The invention relates to the technical field of three-level inverters, in particular to a control method for inhibiting direct-current voltage fluctuation of a three-level inverter.
Background
In the three-level inverter, the fluctuation of the direct current voltage is mainly caused by the voltage difference between the upper bus and the lower bus, and when the voltage difference between the upper bus and the lower bus is large, the capacitance current is unbalanced, so that zero sequence current is generated, and the fluctuation of the direct current voltage is further aggravated. The direct-current voltage fluctuation can cause the harmonic content of the output voltage of the inverter to be increased, so that the energy loss is increased, and even the normal operation of devices is affected, so that the problem that how to control the direct-current voltage fluctuation of the three-level inverter is needed to be solved at present.
The current method for restraining the DC voltage fluctuation of the three-level inverter is to eliminate zero sequence current by using a PWM modulation control algorithm so as to restrain the DC voltage fluctuation, but the current control method only obtains PWM reference voltage through the DC voltage, the AC voltage and the output voltage of the three-level inverter, modulates the PWM reference voltage to obtain control signals so as to eliminate the zero sequence current of the inverter, in the process, the neutral point of the DC voltage is always supposed to be stable and unchanged, namely, the pressure difference change between the upper DC bus voltage and the lower DC bus voltage is ignored, but the pressure difference change between the upper DC bus voltage and the lower DC bus voltage not only influences the magnitude of the zero sequence current, but also influences the fluctuation of the DC voltage, so that the current control method for the fluctuation of the DC voltage cannot effectively eliminate the zero sequence current, and cannot effectively restrain the fluctuation of the DC voltage, thereby causing serious threat to the safe operation of an electrolytic capacitor for maintaining the DC voltage under the condition of insufficient DC energy storage capacity, not only reducing the service life of the capacitor and increasing the system loss, but also increasing the control error.
In summary, the existing control method for suppressing the dc voltage fluctuation of the three-level inverter can not effectively eliminate the zero sequence current due to neglecting the control of the upper and lower dc bus voltage differences, and the effect of suppressing the dc voltage fluctuation is not obvious.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to solve the problems that the zero sequence current cannot be effectively eliminated and the effect of inhibiting the direct-current voltage fluctuation is not obvious in the control method for inhibiting the direct-current voltage fluctuation of the three-level inverter in the prior art.
In order to solve the technical problems, the invention provides a control method for inhibiting direct-current voltage fluctuation of a three-level inverter, which comprises the following steps:
collecting an upper direct current bus voltage, a lower direct current bus voltage, an output voltage d-axis component, an output voltage q-axis component, an output voltage 0-axis component, a first side inductor current d-axis component, a first side inductor current q-axis component and a first side inductor current 0-axis component of a three-level inverter;
outputting a PWM reference voltage d-axis component based on a preset reference DC voltage, the upper DC bus voltage, the lower DC bus voltage, a preset reference AC voltage, the output voltage d-axis component and the first side inductor current d-axis component;
outputting a PWM reference voltage q-axis component based on a reactive voltage of an output voltage, the output voltage q-axis component, and the first side inductor current q-axis component;
inputting the difference value of the upper DC bus voltage and the lower DC bus voltage into a first PI controller, outputting a zero sequence current reference value, inputting the difference value of the zero sequence current reference value and the first side inductance current 0 axis component into a second PI controller, and outputting a PWM reference voltage 0 axis component;
and PWM modulating the PWM reference voltage d-axis component, the PWM reference voltage q-axis component, the PWM reference voltage 0-axis component, the first side inductive current d-axis component, the first side inductive current q-axis component, the first side inductive current 0-axis component, the upper direct current bus voltage and the lower direct current bus voltage by using a midpoint balance modulation algorithm to obtain PWM control signals, and controlling a three-level inverter switch based on the PWM control signals.
In one embodiment of the present invention, the outputting the PWM reference voltage d-axis component based on the preset reference dc voltage, the upper dc bus voltage, the lower dc bus voltage, the preset reference ac voltage, the output voltage d-axis component, and the first side inductor current d-axis component includes:
calculating a direct current error based on the preset reference direct current voltage, the upper direct current bus voltage and the lower direct current bus voltage, inputting the direct current error into a third PI controller, and outputting an input inner loop current reference value of an inverter;
inputting a difference value between a preset reference alternating voltage and the d-axis component of the output voltage into a fourth PI controller, and outputting an output inner loop current reference value of the inverter;
and calculating an inner loop current reference d-axis component based on the input inner loop current reference value of the inverter, the output inner loop current reference value of the inverter and the first side inductance current d-axis component, inputting the inner loop current reference d-axis component into a fifth PI controller, and outputting a PWM reference voltage d-axis component.
In one embodiment of the present invention, the calculation formula of the dc error is:
V 1 ＝V ref,DC -V DC,up -V DC,dn ，
wherein V is 1 Is a direct current error, V ref,DC To preset the DC reference voltage, V DC,up For the upper DC bus voltage, V DC,dn The lower DC bus voltage;
the calculation formula of the d-axis component of the inner loop current reference is as follows:
I ref_d ＝I ref_in +I ref_out -I L1,d ，
wherein I is ref_d For the inner loop current reference d-axis component, I ref_in Is the input inner loop current reference value of the inverter, I ref_out I is the output inner loop current reference value of the inverter L1,d Is the d-axis component of the first side inductor current.
In one embodiment of the present invention, the output PWM reference voltage d-axis component further includes:
and acquiring a new PWM reference voltage d-axis component based on the PWM reference voltage d-axis component, the output voltage 0-axis component, the first side inductor current q-axis component and the inductance value of the first side inductor.
In one embodiment of the present invention, the new calculation formula of the d-axis component of the PWM reference voltage is:
V′ ref_PWM,d ＝V ref_PWM,d +V o,d -I L1,q *ωL 1 ，
wherein V 'is' ref_PWM,d For a new PWM reference voltage d-axis component, V ref_PWM,d For the d-axis component of the PWM reference voltage, V o,d To output the d-axis component of the voltage, I L1,q For the q-axis component of the first side inductor current, ω is a predetermined frequency, L 1 Is the inductance of the first side inductance.
In one embodiment of the present invention, the output PWM reference voltage q-axis component based on the reactive voltage of the output voltage, the output voltage q-axis component, and the first side inductor current q-axis component includes:
inputting the difference value between the reactive voltage of the output voltage and the q-axis component of the output voltage into a sixth PI controller, and outputting a reactive current reference value;
and inputting the difference value between the reactive current reference value and the q-axis component of the first side inductor current into a seventh PI controller, and outputting the q-axis component of the PWM reference voltage.
In one embodiment of the present invention, the output PWM reference voltage q-axis component further includes:
and acquiring a new PWM reference voltage q-axis component based on the PWM reference voltage q-axis component, the first side inductor current d-axis component and the inductance value of the first side inductor.
In one embodiment of the present invention, the new PWM reference voltage q-axis component is calculated as:
V′ ref_PWM,q ＝V ref_PWM,q +I L1,d *ωL 1 ，
wherein V 'is' ref_PWM,q For the new PWM reference voltage q-axis component, V ref_PWM,q For the PWM reference voltage q-axis component, I L1,d For the d-axis component of the first side inductor current, omega is a preset frequency, L 1 Is the inductance of the first side inductance.
In one embodiment of the present invention, the obtaining the output voltage d-axis component, the output voltage q-axis component, the output voltage 0-axis component, the first side inductor current d-axis component, the first side inductor current q-axis component, and the first side inductor current 0-axis component includes:
collecting output voltage of a three-level inverter, and performing park conversion on the output voltage to obtain an output voltage d-axis component, an output voltage q-axis component and an output voltage 0-axis component;
and collecting a first side inductive current of the three-level inverter, and performing park conversion on the first side inductive current to obtain a d-axis component of the first side inductive current, a q-axis component of the first side inductive current and a 0-axis component of the first side inductive current.
In one embodiment of the present invention, PWM modulation using a midpoint balanced modulation algorithm to obtain a PWM control signal, controlling a three-level inverter switch based on the PWM control signal comprises:
performing inverse pi conversion on the d-axis component of the PWM reference voltage, the q-axis component of the PWM reference voltage and the 0-axis component of the PWM reference voltage to obtain a PWM reference voltage;
performing inverse Peak conversion on the d-axis component of the first side inductor current, the q-axis component of the first side inductor current and the 0-axis component of the first side inductor current to obtain a first side inductor current;
and PWM modulation is carried out on the PWM reference voltage, the first side inductance current, the upper direct current bus voltage and the lower direct current bus voltage by using a midpoint balance modulation algorithm to obtain PWM control signals.
The control method for restraining the direct current voltage fluctuation of the three-level inverter outputs the d-axis component of the PWM reference voltage through the direct current error and the alternating current error of the three-level inverter, and outputs the q-axis component of the PWM reference voltage through the difference value between the output voltage and the reactive voltage of the output voltage, so that the direct current voltage and the alternating current voltage of the three-level inverter are controlled, the stability of the direct current voltage is improved to a certain extent, and the fluctuation and the deviation of the direct current voltage are reduced; in addition, in the application, the difference value of the upper direct current bus voltage and the lower direct current bus voltage is used as the 0-axis component of the reference output PWM reference voltage of the current inner loop, and as the difference value of the upper direct current bus voltage and the lower direct current bus voltage is a transient component capable of obviously influencing the zero sequence current and the direct current voltage fluctuation of the three-level inverter, the control of the difference value of the upper direct current bus voltage and the lower direct current bus voltage is directly reflected on the control of the zero sequence current, the zero sequence current in a circuit is effectively eliminated, the fundamental frequency power exchange between the upper bus and the lower bus of a direct current capacitor is obviously reduced, and the direct current voltage fluctuation of the three-level inverter is effectively restrained.
Drawings
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings, in which
FIG. 1 is a flow chart of a control method for suppressing DC voltage fluctuation of a three-level inverter;
fig. 2 is a schematic circuit diagram of a three-level inverter according to the present invention;
fig. 3 is a schematic diagram of a control principle for suppressing dc voltage fluctuation of a three-level inverter according to the present invention;
fig. 4 is a schematic diagram of output voltage and output current waveforms of a three-level inverter under control using a conventional method according to an embodiment of the present invention; fig. 4 (a) is a schematic diagram of an output voltage waveform of the three-level inverter, and fig. 4 (b) is a schematic diagram of an output current waveform of the three-level inverter;
FIG. 5 is a waveform spectrum diagram of the output voltage and output current of a three-level inverter under control using a conventional method according to an embodiment of the present invention; fig. 5 (a) is a waveform spectrum diagram of an output voltage of the three-level inverter, and fig. 5 (b) is a waveform spectrum diagram of an output current of the three-level inverter;
fig. 6 is a schematic diagram of output voltage and output current waveforms of a three-level inverter under control using the method according to an embodiment of the present invention; fig. 6 (a) is a schematic diagram of an output voltage waveform of the three-level inverter, and fig. 6 (b) is a schematic diagram of an output current waveform of the three-level inverter;
FIG. 7 is a waveform spectrum diagram of the output voltage and output current of a three-level inverter under control using the method of the present application according to an embodiment of the present invention; fig. 7 (a) is a waveform spectrum diagram of an output voltage of the three-level inverter, and fig. 7 (b) is a waveform spectrum diagram of an output current of the three-level inverter;
fig. 8 is a schematic diagram of a measured waveform of a dc voltage ripple of a three-level inverter controlled by a conventional method according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a waveform of a dc voltage ripple actually measured of a three-level inverter controlled by the method according to an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the invention and practice it.
The existing control method for restraining the direct-current voltage fluctuation assumes that the neutral point of the direct-current voltage is stable and unchanged when the zero-sequence current is controlled, but the direct-current ripple can change the voltage values of the upper bus and the lower bus so as to directly influence the zero-sequence current and exacerbate the direct-current voltage fluctuation, so that the difference value of the voltages of the upper bus and the lower bus is a transient component capable of obviously influencing the zero-sequence current and the direct-current voltage fluctuation of the three-level inverter, and the control on the differential pressure of the upper bus and the lower bus is often ignored in the existing control method. Based on the above, the voltage difference value of the upper and lower direct current bus voltages is directly used as a reference value of a current inner loop, and the control of the upper and lower direct current bus voltage difference is reflected on the control of zero sequence current to form a proportional zero sequence current negative feedback controller.
Referring to fig. 1, fig. 1 is a flowchart of a control method for suppressing dc voltage fluctuation of a three-level inverter, which specifically includes:
s10: collecting an upper direct current bus voltage, a lower direct current bus voltage, an output voltage d-axis component, an output voltage q-axis component, an output voltage 0-axis component, a first side inductor current d-axis component, a first side inductor current q-axis component and a first side inductor current 0-axis component of a three-level inverter;
s20: outputting a PWM reference voltage d-axis component based on a preset reference DC voltage, an upper DC bus voltage, a lower DC bus voltage, a preset reference AC voltage, an output voltage d-axis component and a first side inductor current d-axis component;
s30: outputting a PWM reference voltage q-axis component based on the reactive voltage of the output voltage, the output voltage q-axis component, and the first side inductor current q-axis component;
s40: inputting the difference value between the upper DC bus voltage and the lower DC bus voltage into a first PI controller, outputting a zero sequence current reference value, inputting the difference value between the zero sequence current reference value and the first side inductance current 0-axis component into a second PI controller, and outputting a PWM reference voltage 0-axis component;
s50: and PWM modulating the d-axis component of the PWM reference voltage, the q-axis component of the PWM reference voltage, the 0-axis component of the PWM reference voltage, the d-axis component of the first side inductive current, the q-axis component of the first side inductive current, the 0-axis component of the first side inductive current, the upper direct current bus voltage and the lower direct current bus voltage by using a midpoint balance modulation algorithm to obtain PWM control signals, and controlling the three-level inverter switch based on the PWM control signals.
The method outputs the d-axis component of the PWM reference voltage through the direct current error and the alternating current error of the three-level inverter, and outputs the q-axis component of the PWM reference voltage through the difference between the output voltage and the reactive voltage of the output voltage, so that the direct current voltage and the alternating current voltage of the three-level inverter are controlled, the stability of the direct current voltage is improved to a certain extent, and the fluctuation and the deviation of the direct current voltage are reduced; in addition, in the method, the difference value of the upper direct current bus voltage and the lower direct current bus voltage is used as the 0-axis component of the reference output PWM reference voltage of the current inner loop, and the difference value of the upper direct current bus voltage and the lower direct current bus voltage is a transient component capable of obviously influencing the zero sequence current and the fluctuation of the direct current voltage of the three-level inverter, so that the control of the difference value of the upper direct current bus voltage and the lower direct current bus voltage is directly reflected on the control of the zero sequence current, the zero sequence current in a circuit is effectively eliminated, the fundamental frequency power exchange between the upper bus and the lower bus of a direct current capacitor is obviously reduced, the fluctuation of the direct current voltage of the three-level inverter is effectively restrained, the safe operation of an electrolytic capacitor for maintaining the direct current voltage is better realized, and the service life of the capacitor is prolonged.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of a three-level inverter according to an embodiment of the present application, in which V DC,up For the upper DC bus voltage, V DC,dn For the lower DC bus voltage, L 1 For the first side inductance, I L1 (abc) represents the first side inductance L 1 Three-phase current of I L1 (dq 0) is a pair I L1 (abc) first side inductor current obtained by park transformation, V o (abc) three-phase voltage as output voltage, V o (dq 0) is V o (abc) an output voltage obtained by performing a park transformation.
Specifically, the process of obtaining the output voltage d-axis component, the output voltage q-axis component, the output voltage 0-axis component, the first side inductor current d-axis component, the first side inductor current q-axis component, and the first side inductor current 0-axis component in step S10 includes:
s100: collecting output voltage V of three-level inverter o (abc) for output voltage V o (abc) performing park transformation to obtain d-axis component V of output voltage o,d Q-axis component V of output voltage o,q And output voltage 0 axis component V o,0 ；
S101: collecting first side inductance current I of three-level inverter L1 (abc) for the first side inductor current I L1 (abc) performing a park transformation to obtain a d-axis component I of the first side inductor current L1,d Q-axis component I of first side inductor current L1,q And a first side inductor current 0 axis component I L1,0 。
Referring to fig. 3, fig. 3 is a schematic diagram of a control principle for suppressing dc voltage fluctuation of a three-level inverter according to an embodiment of the present application, where V ref,DC To preset reference DC voltage, V ref,AC For a preset reference ac voltage, 0 represents the reactive voltage of the output voltage, V ref_PWM (dq 0) is the d-axis component V of the output PWM reference voltage ref_PWM,d Q-axis component V ref_PWM,q And 0 axis component V ref_PWM,0 ，V PWM And the PWM control signal is output after PWM modulation.
Specifically, outputting the PWM reference voltage d-axis component in step S20 includes:
s200: based on preset reference DC voltage V ref,DC Upper dc bus voltage V DC,up And a lower DC bus voltage V DC,dn Calculating a direct current error, inputting the direct current error into a third PI controller, and outputting an input inner loop current reference value of the inverter;
specifically, the calculation formula of the dc error is:
V 1 ＝V ref,DC -V DC,up -V DC,dn ，
wherein V is 1 Is a direct current error, V ref,DC To preset the DC reference voltage, V DC,up For the upper DC bus voltage, V DC,dn The lower DC bus voltage;
the calculation formula of the d-axis component of the reference inner loop current is as follows:
I ref_d ＝I ref_in +I ref_out -I L1,d ，
wherein I is ref_d For the inner loop current reference d-axis component, I ref_in Is the input inner loop current reference value of the inverter, I ref_out I is the output inner loop current reference value of the inverter L1,d Is the d-axis component of the first side inductor current.
S201: will preset reference AC voltage V ref,AC And an output voltage d-axis component V o,d The difference value of the current is input into a fourth PI controller, and an output inner loop current reference value of the inverter is output;
s202: based on the input inner loop current reference value of the inverter, the output inner loop current reference value of the inverter and the d-axis component I of the first side inductor current L1,d And calculating an inner loop current reference d-axis component, inputting the inner loop current reference d-axis component into a fifth PI controller, and outputting a PWM reference voltage d-axis component.
As a specific example of the present application, a reference dc voltage V is preset ref,DC The value of (2) is 1700V, and reference alternating voltage V is preset ref,AC Is 690V.
Optionally, in some embodiments of the present application, in order to make the dc voltage of the three-level inverter reach the steady state more quickly, after outputting the d-axis component of the PWM reference voltage, the method further includes:
acquiring a new PWM reference voltage d-axis component based on the PWM reference voltage d-axis component, the output voltage 0-axis component, the first side inductor current q-axis component and the inductance value of the first side inductor;
specifically, the new calculation formula of the d-axis component of the PWM reference voltage is:
V′ ref_PWM,d ＝V ref_PWM,d +V o,d -I L1,q *ωL 1 ，
wherein V 'is' ref_PWM,d For a new PWM reference voltage d-axis component, V ref_PWM,d For the d-axis component of the PWM reference voltage, V o,d To output the d-axis component of the voltage, I L1,q For the q-axis component of the first side inductor current, ω is a predetermined frequency, L 1 Is the inductance of the first side inductance.
Further, outputting the PWM reference voltage q-axis component in step S30 includes:
s301: inputting the difference value between the reactive voltage of the output voltage and the q-axis component of the output voltage into a sixth PI controller, and outputting a reactive current reference value;
s302: the difference between the reactive current reference value and the q-axis component of the first side inductor current is input into a seventh PI controller, and the q-axis component of the PWM reference voltage is output.
Optionally, in some embodiments of the present application, in order to make the dc voltage of the three-level inverter reach the steady state more quickly, after outputting the q-axis component of the PWM reference voltage, the method further includes:
a new PWM reference voltage q-axis component is obtained based on the PWM reference voltage q-axis component, the first side inductor current d-axis component, and the inductance value of the first side inductor.
Specifically, the new calculation formula of the q-axis component of the PWM reference voltage is:
V′ ref_PWM,q ＝V ref_PWM,q +I L1,d *ωL 1 ，
wherein V is r ′ ef_PWM,q For the new PWM reference voltage q-axis component, V ref_PWM,q For the PWM reference voltage q-axis component, I L1,d For the d-axis component of the first side inductor current, omega is a preset frequency, L 1 Is the inductance of the first side inductance.
Specifically, in step S40, PWM modulation is performed by using a midpoint balanced modulation algorithm to obtain a PWM control signal, and controlling the three-level inverter switch based on the PWM control signal includes:
performing inverse Peak conversion on the d-axis component of the PWM reference voltage, the q-axis component of the PWM reference voltage and the 0-axis component of the PWM reference voltage to obtain PWM reference voltage;
performing inverse Peak transformation on the d-axis component of the first side inductor current, the q-axis component of the first side inductor current and the 0-axis component of the first side inductor current to obtain a first side inductor current;
and PWM modulating the PWM reference voltage, the first side inductance current, the upper direct current bus voltage and the lower direct current bus voltage by using a midpoint balance modulation algorithm to obtain PWM control signals.
Compared with the existing control method, the control method for restraining the direct-current voltage fluctuation of the three-level inverter can remarkably reduce the fundamental frequency power exchange between the upper bus and the lower bus of the direct-current capacitor on the low-frequency harmonic frequency.
Referring to fig. 4 and 5, fig. 4 (a) is a waveform diagram of an output voltage of the three-level inverter under control of the conventional method, fig. 4 (b) is a waveform diagram of an output current of the three-level inverter under control of the conventional method, wherein an abscissa indicates time, an ordinate indicates voltage, and three curves respectively indicate a-phase, b-phase and c-phase voltages of the output voltage; fig. 5 (a) is a waveform spectrum diagram of an output voltage of the three-level inverter under control of the conventional method, and fig. 5 (b) is a waveform spectrum diagram of an output current of the three-level inverter under control of the conventional method.
Referring to fig. 6 and 7, fig. 6 (a) is a waveform diagram of an output voltage of the three-level inverter under control of the method provided by the present application, fig. 6 (b) is a waveform diagram of an output current of the three-level inverter under control of the method provided by the present application, in which an abscissa indicates time, an ordinate indicates voltage, and three curves respectively indicate voltages of a phase, b phase and c phase of the output voltage; fig. 7 (a) is a waveform spectrum diagram of an output voltage of the three-level inverter under control of the method provided in the present application, and fig. 7 (b) is a waveform spectrum diagram of an output current of the three-level inverter under control of the method provided in the present application;
as can be seen from the graph, the fluctuation of the output voltage and the output current of the three-level inverter under the control of the method provided by the application is smaller than that of the three-level inverter under the control of the existing method; moreover, as can be seen by comparing the Total Harmonic Distortion (THD) values in fig. 5 and 7, regardless of the waveform spectrum distribution of the output voltage or the output current, the THD value under the control of the method provided by the present application is significantly smaller than the THD value under the control of the existing method, which indicates that the harmonic content of the output voltage and the output current waveform under the control of the method provided by the present application is lower, and the harmonic content of the output voltage and the output current waveform under the control of the existing method is higher, and the waveform distortion is serious.
Referring to fig. 8 and 9, fig. 8 is a schematic diagram of a waveform of a dc voltage ripple actually measured by controlling a lower three-level inverter using a conventional method; fig. 9 is a schematic diagram of a measured waveform of a dc voltage ripple of a three-level inverter under control of the method provided in the present application.
As can be seen by comparing fig. 8 and fig. 9, the dc voltage fluctuation of the three-level inverter under control by using the method provided by the present application is significantly smaller than that of the three-level inverter under control by the existing method, which indicates that the method provided by the present application can more effectively eliminate zero sequence current and inhibit dc voltage fluctuation, thereby better realizing safe operation of the electrolytic capacitor for maintaining dc voltage and prolonging the service life of the capacitor.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.

Claims (10)

1. A control method for suppressing dc voltage fluctuation of a three-level inverter, comprising:
collecting an upper direct current bus voltage, a lower direct current bus voltage, an output voltage d-axis component, an output voltage q-axis component, an output voltage 0-axis component, a first side inductor current d-axis component, a first side inductor current q-axis component and a first side inductor current 0-axis component of a three-level inverter;
outputting a PWM reference voltage d-axis component based on a preset reference DC voltage, the upper DC bus voltage, the lower DC bus voltage, a preset reference AC voltage, the output voltage d-axis component and the first side inductor current d-axis component;
outputting a PWM reference voltage q-axis component based on a reactive voltage of an output voltage, the output voltage q-axis component, and the first side inductor current q-axis component;
inputting the difference value of the upper DC bus voltage and the lower DC bus voltage into a first PI controller, outputting a zero sequence current reference value, inputting the difference value of the zero sequence current reference value and the first side inductance current 0 axis component into a second PI controller, and outputting a PWM reference voltage 0 axis component;
and PWM modulating the PWM reference voltage d-axis component, the PWM reference voltage q-axis component, the PWM reference voltage 0-axis component, the first side inductive current d-axis component, the first side inductive current q-axis component, the first side inductive current 0-axis component, the upper direct current bus voltage and the lower direct current bus voltage by using a midpoint balance modulation algorithm to obtain PWM control signals, and controlling a three-level inverter switch based on the PWM control signals.
2. The control method for suppressing a dc voltage fluctuation of a three-level inverter according to claim 1, wherein the outputting the PWM reference voltage d-axis component based on a preset reference dc voltage, the upper dc bus voltage, the lower dc bus voltage, a preset reference ac voltage, the output voltage d-axis component, and the first side inductor current d-axis component comprises:
calculating a direct current error based on the preset reference direct current voltage, the upper direct current bus voltage and the lower direct current bus voltage, inputting the direct current error into a third PI controller, and outputting an input inner loop current reference value of an inverter;
inputting a difference value between a preset reference alternating voltage and the d-axis component of the output voltage into a fourth PI controller, and outputting an output inner loop current reference value of the inverter;
and calculating an inner loop current reference d-axis component based on the input inner loop current reference value of the inverter, the output inner loop current reference value of the inverter and the first side inductance current d-axis component, inputting the inner loop current reference d-axis component into a fifth PI controller, and outputting a PWM reference voltage d-axis component.
3. The control method for suppressing dc voltage fluctuation of a three-level inverter according to claim 2, wherein the calculation formula of the dc error is:
V 1 ＝V ref,DC -V DC,up -V DC,dn ，
wherein V is 1 Is a direct current error, V ref,DC To preset the DC reference voltage, V DC,up For the upper DC bus voltage, V DC,dn The lower DC bus voltage;
the calculation formula of the d-axis component of the inner loop current reference is as follows:
I ref_d ＝I ref_in +I ref_out -I L1,d ，
wherein I is ref_d For the inner loop current reference d-axis component, I ref_in Is the input inner loop current reference value of the inverter, I ref_out I is the output inner loop current reference value of the inverter L1,d Is the d-axis component of the first side inductor current.
4. The control method for suppressing dc voltage fluctuation of a three-level inverter according to claim 2, wherein the outputting of the PWM reference voltage d-axis component further comprises:
and acquiring a new PWM reference voltage d-axis component based on the PWM reference voltage d-axis component, the output voltage 0-axis component, the first side inductor current q-axis component and the inductance value of the first side inductor.
5. The control method for suppressing three-level inverter dc voltage fluctuations according to claim 4, wherein the calculation formula of the new PWM reference voltage d-axis component is:
V′ ref_PWM,d ＝V ref_PWM,d +V o,d -I L1,q *ωL 1 ，
wherein V 'is' ref_PWM,d For a new PWM reference voltage d-axis component, V ref_PWM,d For the d-axis component of the PWM reference voltage, V o,d To output the d-axis component of the voltage, I L1,q For the q-axis component of the first side inductor current, ω is a predetermined frequency, L 1 Is the inductance of the first side inductance.
6. The control method for suppressing a dc voltage fluctuation of a three-level inverter according to claim 1, wherein the outputting the PWM reference voltage q-axis component based on the reactive voltage of the output voltage, the output voltage q-axis component, and the first side inductor current q-axis component comprises:
inputting the difference value between the reactive voltage of the output voltage and the q-axis component of the output voltage into a sixth PI controller, and outputting a reactive current reference value;
and inputting the difference value between the reactive current reference value and the q-axis component of the first side inductor current into a seventh PI controller, and outputting the q-axis component of the PWM reference voltage.
7. The control method for suppressing dc voltage fluctuations in a three-level inverter according to claim 6, wherein said outputting the q-axis component of the PWM reference voltage further comprises:
and acquiring a new PWM reference voltage q-axis component based on the PWM reference voltage q-axis component, the first side inductor current d-axis component and the inductance value of the first side inductor.
8. The control method for suppressing three-level inverter dc voltage fluctuations according to claim 7, wherein the new PWM reference voltage q-axis component is calculated by the formula:
V′ ref_PWM,q ＝V ref_PWM,q +I L1,d *ωL 1 ，
wherein V 'is' ref_PWM,q For the new PWM reference voltage q-axis component, V ref_PWM,q For the PWM reference voltage q-axis component, I L1,d For the d-axis component of the first side inductor current, omega is a preset frequency, L 1 Is the inductance of the first side inductance.
9. The control method for suppressing dc voltage fluctuation of a three-level inverter according to claim 1, wherein the obtaining of the output voltage d-axis component, the output voltage q-axis component, the output voltage 0-axis component, the first side inductor current d-axis component, the first side inductor current q-axis component, and the first side inductor current 0-axis component includes:
collecting output voltage of a three-level inverter, and performing park conversion on the output voltage to obtain an output voltage d-axis component, an output voltage q-axis component and an output voltage 0-axis component;
and collecting a first side inductive current of the three-level inverter, and performing park conversion on the first side inductive current to obtain a d-axis component of the first side inductive current, a q-axis component of the first side inductive current and a 0-axis component of the first side inductive current.
10. The control method for suppressing dc voltage fluctuation of a three-level inverter according to claim 1, wherein PWM modulating with a midpoint balanced modulation algorithm to obtain a PWM control signal, controlling the three-level inverter switch based on the PWM control signal comprises:
performing inverse pi conversion on the d-axis component of the PWM reference voltage, the q-axis component of the PWM reference voltage and the 0-axis component of the PWM reference voltage to obtain a PWM reference voltage;
performing inverse Peak conversion on the d-axis component of the first side inductor current, the q-axis component of the first side inductor current and the 0-axis component of the first side inductor current to obtain a first side inductor current;
and PWM modulation is carried out on the PWM reference voltage, the first side inductance current, the upper direct current bus voltage and the lower direct current bus voltage by using a midpoint balance modulation algorithm to obtain PWM control signals.
CN202311525256.XA 2023-11-15 2023-11-15 Control method for inhibiting direct-current voltage fluctuation of three-level inverter Pending CN117559760A (en)

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