CN116846365A - Signal latch circuit, battery management system, battery system and electric equipment - Google Patents
Signal latch circuit, battery management system, battery system and electric equipment Download PDFInfo
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- CN116846365A CN116846365A CN202310799299.0A CN202310799299A CN116846365A CN 116846365 A CN116846365 A CN 116846365A CN 202310799299 A CN202310799299 A CN 202310799299A CN 116846365 A CN116846365 A CN 116846365A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/35—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar semiconductor devices with more than two PN junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M2010/4271—Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing
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- General Chemical & Material Sciences (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The application relates to a signal latch circuit, a battery management system, a battery system and electric equipment, and belongs to the field of electronic circuits. The signal latch circuit includes: the output pin of the latch is connected with the self-locking circuit. The latch includes a clear pin that is pulled up high. The self-locking circuit comprises a control unit, an output end and a self-locking unit, wherein the control unit is connected with the self-locking unit, and the self-locking unit is connected with the output end and an output pin of the latch. The self-locking circuit is configured to respond to the control unit receiving a control signal and the output pin outputting a high level, the self-locking circuit being turned on and outputting a first signal at the output terminal.
Description
Technical Field
The application belongs to the field of electronic circuits, and particularly relates to a signal latch circuit, a battery management system, a battery system and electric equipment.
Background
When electromagnetic compatibility (Electro Magnetic Compatibility, EMC) tests are carried out on a battery management system (Battery Management System, BMS), a zero clearing pin (such as a CLR pin) of a latch, when the CLR pin of the latch is at a high level, an input level of the latch can be mapped into an output level of the latch by a CLK (clock signal) rising edge, when the CLR pin is at a low level, the output end of the latch is always at the low level), the latch is sensitive, misoperation is easy, and the abrupt change of the working state of a rear-end circuit (such as a switch) is caused, so that the normal operation of the system can be influenced, the reliability and the stability of the system can be reduced, and the customer experience can be influenced.
Disclosure of Invention
In view of the above, the present application is directed to a signal latch circuit, a battery management system, a battery system and an electric device, so as to solve the problem that the reset pin (for example, CLR pin) of the latch is sensitive and is prone to malfunction.
Embodiments of the present application are implemented as follows:
in a first aspect, an embodiment of the present application provides a signal latch circuit including: the output pin of the latch is connected with the self-locking circuit; the latch comprises a zero clearing pin which is pulled up to be in a high level; the self-locking circuit comprises a control unit, an output end and a self-locking unit, wherein the control unit is connected with the self-locking unit, and the self-locking unit is connected with the output end and an output pin of the latch; the self-locking circuit is configured to respond to the control unit to receive a control signal and the output pin to output a high level, and is conducted and outputs a first signal at the output end.
In the embodiment of the application, the zero clearing pin of the latch is pulled up to be at the high level, so that the zero clearing pin of the latch cannot malfunction due to signal interference, and the high level is always maintained and cannot jump to be at the low level. Meanwhile, the self-locking circuit is introduced to replace the function that the zero clearing pin of the latch is at a low level, so that the integrity of the function is ensured. Meanwhile, the self-locking circuit is controlled by the control signal to realize control as required, so that the anti-interference capability of the circuit is improved, and the reliability of the circuit is improved.
With reference to an implementation manner of the first aspect embodiment, the control unit includes: the first resistor, the first switch and the control end; the control terminal is configured to receive the control signal; a first end of the first switch is connected with the control end, a second end of the first switch is configured to be connected with a power supply, and a third end of the first switch is connected with the self-locking unit; the first resistor is connected between a first end of the first switch and a second end of the first switch.
In the embodiment of the application, the control unit can be adopted to realize the required functions, reduce the complexity of the circuit and utilize the circuit design and reproduction.
With reference to an implementation manner of the first aspect embodiment, the control unit further includes: the second resistor is connected between the control end and the first end of the first switch, and the second resistor and the first resistor are connected to one side close to the control end.
In the embodiment of the application, the voltage of the first end of the first switch can be increased by additionally arranging the second resistor between the control end and the first end of the first switch, so that the current when the first switch is conducted is increased, and the response speed of the circuit is further improved.
With reference to an implementation manner of the first aspect, the self-locking unit includes: the second switch, the third resistor, the fourth resistor and the fifth resistor; the second end of the second switch is grounded, the third end of the second switch is respectively connected with the first end and the output end of the third switch, and the third end of the second switch and the output pin of the latch are also connected with a first node; the second end of the third switch and the output pin of the latch are connected to the first node, and the third end of the third switch and the first end of the second switch are connected to the second node; the third resistor is connected between the first node and the first end of the third switch; the fourth resistor is connected between the first node and the output end of the self-locking circuit; the fifth resistor is connected between the second node and a second end of the second switch.
In the embodiment of the application, the self-locking unit is adopted, when the control unit receives the control signal and the output pin of the latch outputs a high level, the second switch is automatically conducted, the voltage of the output end is pulled down to a low level after the second switch is conducted, meanwhile, the third resistor has voltage drop, so that the third switch is conducted, the fifth resistor has voltage drop after the third switch is conducted, the second switch and the third switch form self-locking, so that even if the control end does not receive the control signal any more, the second switch and the third switch can be kept conducting, the output end of the self-locking circuit always outputs a low level, the function that the pin of the latch is in a low level is realized, signal interference is not received, and the stability of the system is improved.
With reference to an implementation manner of the first aspect, the second switch is one of a triode, a FET and an IGBT, and the third switch is one of a triode, a FET and an IGBT.
In the embodiment of the application, one of the triode, the FET and the IGBT is selected as the second switch and the third switch, so that different switch types can be selected according to the application scene of the signal latch circuit, and the design freedom degree of the signal latch circuit is improved.
With reference to an implementation manner of the first aspect embodiment, the self-locking unit further includes: at least one of the sixth resistor, the seventh resistor, and the eighth resistor; the sixth resistor is connected between the first end of the third switch and a third node, wherein the third end of the second switch and the output end of the self-locking circuit are connected to the third node; the seventh resistor is connected between the control unit and the second node; the eighth resistor is connected between the second node and a third terminal of the third switch.
In the embodiment of the application, at least one resistor of the sixth resistor, the seventh resistor and the eighth resistor is further arranged at the position, so that the resistor can be used as a current limiting resistor, and external surge voltage is prevented, and the switch is prevented from being broken down to be damaged.
With reference to an implementation manner of the first aspect embodiment, the self-locking circuit is further configured to: in response to the control unit not receiving the control signal, the self-locking circuit is disconnected; alternatively, the latching circuit is opened in response to the output pin of the latch outputting a low level.
In the embodiment of the application, the self-locking circuit is configured to be disconnected in response to the control unit not receiving the control signal; or, in response to the output pin of the latch outputting a low level, the self-locking circuit is disconnected, so that the self-locking state of the self-locking circuit can be released, and the output level of the self-locking circuit is ensured to be the output level of the latch.
In a second aspect, an embodiment of the present application further provides a battery management system, including the signal latch circuit described above, where the battery management system further includes: the device comprises a controller, a watchdog circuit, a logic gate circuit, a power supply, a charging switch and a discharging switch; the power supply is connected to the self-locking circuit, the controller is connected to the logic gate circuit and the latch, the logic gate circuit is connected to the watchdog circuit and the control end of the self-locking circuit, and the output end of the self-locking circuit is connected to the charging switch and/or the discharging switch.
In combination with an implementation of the second aspect embodiment, the logic gate is configured to satisfy at least one of the following conditions: i) The logic gate circuit receives a controller reset signal transmitted by the watchdog circuit and transmits the control signal to a control end of the self-locking circuit; ii) the logic gate circuit receives the controller latch signal transmitted by the controller and transmits the control signal to the control end of the self-locking circuit.
In a third aspect, an embodiment of the present application further provides a battery system, including a battery module and a battery management system as described above, where the battery module is connected to the battery management system.
In a fourth aspect, an embodiment of the present application further provides an electrical apparatus, including a load and a battery system as described above, where the battery system supplies power to the load.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments are briefly introduced below, and the drawings in the following description are only some embodiments of the present application and are not limiting of the present application. The above and other objects, features and advantages of the present application will become more apparent from the accompanying drawings.
Fig. 1 shows a schematic diagram of a signal latch circuit according to an embodiment of the present application.
Fig. 2 shows a schematic circuit diagram of a control unit connected to a self-locking unit according to an embodiment of the present application.
Fig. 3 shows a schematic circuit diagram of a latch and a control unit respectively connected with a self-locking unit according to an embodiment of the present application.
Fig. 4 is a schematic circuit diagram of a latch circuit connected to a latch according to an embodiment of the present application.
Fig. 5 shows a schematic circuit diagram of a signal latch circuit according to an embodiment of the present application.
Fig. 6 is a schematic diagram showing a structure of a battery management system connected to a battery according to an embodiment of the present application.
Detailed Description
The technical scheme in the embodiment of the application will be described below with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The following examples are given by way of illustration for more clearly illustrating the technical solution of the present application, and are not to be construed as limiting the scope of the application. Those skilled in the art will appreciate that the embodiments described below and features of the embodiments can be combined with one another without conflict.
The term "and/or" in the present application is merely an association relation describing the association object, and indicates that three kinds of relations may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone.
In the description of the embodiments of the present application, unless explicitly specified and limited otherwise, the term "connected" may be either directly or indirectly through intermediaries. The specific meaning of the above terms in the embodiments of the present application will be understood by those of ordinary skill in the art according to specific circumstances.
In view of the fact that the zero clearing pin (such as CLR pin) of the latch is sensitive, the latch is easy to malfunction, for example, the zero clearing pin of the latch is required to be at high level currently, but in practice, the zero clearing pin of the latch jumps to be at low level due to signal interference, or the zero clearing pin of the latch is required to be at low level currently, but in practice, the zero clearing pin of the latch jumps to be at high level due to signal interference. Thus, abrupt change of the working state of the back-end circuit (such as a switch) can be caused, and the reliability, stability and customer experience of the back-end circuit are affected. In order to solve the problem, the embodiment of the application provides a signal latch circuit, a battery management system, a battery system and electric equipment, which can improve the problems caused by the fact that a zero clearing pin of a latch is sensitive and is easy to malfunction, and can provide anti-interference capability and reliability of a circuit or a system where the circuit is located.
For a better understanding of the present solution, the following description will be given with reference to the signal latch circuit shown in fig. 1. The signal latch circuit includes: the device comprises a latch and a self-locking circuit, wherein an output pin of the latch is connected with the self-locking circuit.
The latch includes a clear pin that is pulled up high. The latch may be a device having a signal latch function, and may be an SR (Set Reset) latch, a D (Data) latch, or the like, for example.
The self-locking circuit comprises a control unit, an output end and a self-locking unit. The control unit is connected with the self-locking unit, and the self-locking unit is connected with the output end and the output pin of the latch. The self-locking circuit is configured to respond to the control unit receiving the control signal and the output pin outputting a high level, the self-locking circuit being turned on and outputting a first signal at an output terminal.
In view of the sensitivity of the zero clearing pin of the latch, the anti-interference capability of the latch needs to be improved, and in order to improve the reliability, in the embodiment of the application, the zero clearing pin of the latch is pulled up to be at a high level, so that the zero clearing pin of the latch cannot malfunction due to signal interference, and the high level is always maintained and cannot jump to be at a low level. Meanwhile, the self-locking circuit is introduced to replace the function that the zero clearing pin of the latch is at a low level, so that the integrity of the function is ensured.
In some embodiments, the first signal may be a control signal for controlling the opening of a switch (e.g., a charge switch and/or a discharge switch) on the charge-discharge main loop. In some embodiments, the first signal may be a low level signal, which may control the switch on the charge-discharge main loop to open. In this embodiment, the high level signal output from the latch output pin is changed into the low level signal output after passing through the latch circuit. Namely, a high-level signal is input into the self-locking circuit, and a low-level signal is output from the self-locking circuit.
In some embodiments, the control signal is a low level signal, which may be used to control the latch circuit to conduct.
In some embodiments, the self-locking circuit is further configured to open in response to the control unit not receiving the control signal; alternatively, the latching circuit is opened in response to the output pin of the latch outputting a low level. After the self-locking circuit is disconnected, the signals output by the output pins of the latch are not converted and the converted signals are not latched, namely, when the self-locking circuit does not receive a control signal or the output pins of the latch output low level, the signals output by the output pins of the latch are consistent with the output signals of the self-locking circuit.
In some embodiments, as shown in fig. 2, the control unit includes: a first resistor (as represented by R1), a first switch (as represented by Q1), and a control terminal. The control terminal is configured to receive a control signal. The first end of the first switch is connected with the control end, the second end of the first switch is configured to be connected with a power supply, and the third end of the first switch is connected with the self-locking unit. The first resistor is connected between a first end of the first switch and a second end of the first switch. When the control signal is received by the control unit, the first switch is turned on, and then the self-locking unit is started to be turned on. In this embodiment, the control signal is a low level signal.
In some embodiments, the control unit further comprises: and the second resistor (as represented by R2) is connected between the control end and the first end of the first switch and is connected with the first resistor on one side close to the control end. Through add the second resistance between the first end of control end and first switch, the second resistance can be regarded as current-limiting resistance, prevents outside surge voltage, prevents that first switch from being broken down and damaging.
In one embodiment, the resistance of the second resistor is smaller than the resistance of the first resistor, for example, the resistance of the first resistor is 10k, and the resistance of the second resistor is 1k.
The first switch may be one of a transistor switch, a FET, and an IGBT.
In one embodiment, the first switch may be a P-type transistor switch, the principle of which is shown in fig. 2. At this time, the first end of the first switch is a gate, the second end of the first switch is a source, and the third end of the first switch is a drain.
In some embodiments, as shown in fig. 3, the self-locking unit includes: a second switch (e.g., represented by Q2), a third switch (e.g., represented by Q3), a third resistor (e.g., represented by R3), a fourth resistor (e.g., represented by R4), and a fifth resistor (e.g., represented by R5). The second end of the second switch is grounded, the third end of the second switch is connected to the first end and the output end of the third switch respectively, and the third end of the second switch and the output pin of the latch are also connected to the first node (as represented by N1). The second end of the third switch and the output pin of the latch are connected to the first node, and the third end of the third switch and the first end of the second switch are connected to the second node (as denoted by N2). The third resistor is connected between the first node and the first end of the third switch. The fourth resistor is connected between the first node and the output end of the self-locking circuit. The fifth resistor is connected between the second node and the second end of the second switch. Wherein the second node is also connected with the control unit.
The control unit receives the control signal and then controls the second switch to be conducted, the signal at the output end of the self-locking circuit is pulled down to be a low-level signal after the second switch is conducted, meanwhile, the output of the trigger is high-level, the third resistor has voltage drop, so that the third switch is conducted, the fifth resistor has voltage drop after the third switch is conducted, the second switch and the third switch form self-locking, and therefore even if an interference signal exists, the output signal of the signal latch circuit is not affected, and the low-level signal is always output.
In one embodiment, the second switch may be one of a triode, a FET, and an IGBT, and the third switch may be one of a triode, a FET, and an IGBT. In one embodiment, the second switch may be an N-type transistor switch and the third switch may be a P-type transistor switch.
In one embodiment, the self-locking unit further comprises: at least one of a sixth resistance (as represented by R6), a seventh resistance (as represented by R7), and an eighth resistance (as represented by R8). The sixth resistor is connected between the first end of the third switch and the third node (as denoted by N3), the third end of the second switch and the output end of the self-locking circuit are connected to the third node, the seventh resistor is connected between the control unit and the second node, specifically, the seventh resistor is connected between the third end of the first switch and the second node, and the eighth resistor is connected between the second node and the third end of the third switch.
In one embodiment, the resistance of the sixth resistor, the seventh resistor, and the eighth resistor is smaller than the resistance of the third resistor, the fourth resistor, and the fifth resistor, for example, the resistance of the sixth resistor, the seventh resistor, and the eighth resistor is 1k, and the resistance of the third resistor, the fourth resistor, and the fifth resistor is 10k.
In an alternative embodiment, a schematic diagram of the self-locking circuit is shown in fig. 4, and it is understood that the schematic diagram of fig. 4 is only one of many examples of the present application. For a better understanding, the principle of the self-locking circuit is described below in connection with fig. 4. When the output pin of the latch outputs high level, if the control end of the self-locking circuit does not receive a control signal, at this time, the first switch Q1, the second switch Q2 and the third switch Q3 are not conducted, and the high level output by the latch is directly output through the resistor R4. When the output pin of the latch outputs a high level and the control end receives a control signal (low level signal), the 3.3V power supply and the resistor R1 enable the first switch Q1 to be conducted so as to control the second switch Q2 to be conducted, after the second switch Q2 is conducted, a signal at the output end of the self-locking circuit is pulled down to be a low level signal, meanwhile, as the output of the trigger is high level, the resistor R3 has voltage drop, so that the third switch Q3 is conducted, after the third switch Q3 is conducted, the resistor R5 has voltage drop, so that the second switch Q2 and the third switch Q3 form self-locking, and therefore, even if the control end does not receive the control signal any more, after the first switch Q1 is turned off, the Q2 and the Q3 are kept conducting, and the output end of the self-locking circuit always outputs the low level.
When the output pin of the latch outputs a low level, the output end of the latch circuit outputs the low level no matter whether the control end receives a control signal or not, namely the latch circuit needs to be released. In the embodiment where the latch is a D latch, the CLR pin of the latch is required to be high and the input signal of the D pin of the latch is required to be low, and when the CLK rising edge arrives, the low level of the D pin of the latch is mapped to the Q pin of the latch, and at this time, Q2 and Q3 are released from the latch state.
In an alternative embodiment, a schematic diagram of a signal latch circuit is shown in fig. 5. When the rising edge of CLK (input clock) arrives, the input level of the latch D end is mapped to the output level of the latch Q end, and the output level of the latch Q end remains unchanged until the next rising edge of CLK arrives. For example, when the CLK (input clock) rising edge comes, the input level of the D terminal is low, and the output level of the Q terminal is also low. When CLK (input clock) comes, the input level of the D terminal is high, and the output level of the Q terminal is also high.
The resistance of R11, R12 in fig. 5 is larger than the resistance of R13, R14, for example, the resistance of R11, R12 is 10k, and the resistance of R13, R14 is 0.1k. The input signal in fig. 5, i.e. the input signal at the D-terminal of the latch, may come from the controller.
It will be appreciated that in one embodiment, R11-R14, and C1-C6 in FIG. 5 may be eliminated.
The embodiment of the application also provides a power management system (Battery Management System, BMS) which comprises the signal latch circuit.
In a specific implementation manner, the battery management system of the present application may be embodied in a form of a printed circuit board, on which the signal latch circuit is disposed, and other electronic components may be disposed on the battery management system, for example, the battery management system further includes: a controller, a watchdog circuit, a logic gate, a power supply, a charge switch, and a discharge switch, as shown in fig. 6. The power supply is connected with the self-locking circuit and outputs 3.3V or 5V voltage to supply power for the self-locking circuit, the controller is connected with the logic gate circuit and the latch, the logic gate circuit is connected with the watchdog circuit and the control end of the self-locking circuit, and the output end of the self-locking circuit is connected with the charging switch and/or the discharging switch.
Wherein the logic gate is configured to satisfy at least one of the following conditions: i) The logic gate circuit receives a controller reset signal transmitted by the watchdog circuit and transmits a control signal to a control end of the self-locking circuit; ii) the logic gate circuit receives the controller latch signal transmitted by the controller and transmits a control signal to the control terminal of the latch circuit.
In some embodiments, when at least one of the controller reset signal and the controller latch signal is a low level signal, the logic gate circuit includes an and gate circuit, and accordingly, the control signal is a low level signal.
In still other embodiments, the controller reset signal and the controller latch signal are both low signals, and the logic gate circuit includes an or gate, and accordingly the control signal is a low signal.
The watchdog circuit is used for transmitting a controller reset signal, for example, the watchdog circuit is turned on when being powered on, the controller can realize a watchdog feeding function through level change of an Input Output (IO) pin, once the controller is abnormal and the watchdog feeding is overtime, the watchdog circuit sends the controller reset signal to the controller to control the controller to reset, and meanwhile, the watchdog circuit also sends the controller reset signal to the logic gate circuit.
The controller may be an integrated circuit chip with signal processing capabilities. The controller may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but also digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. A general purpose processor may be a microprocessor (Micro Controller Unit, MCU) or the processor may be any conventional processor or the like.
The self-locking circuit is connected with the charging switch and/or the discharging switch, and controls the on/off of the charging switch and/or the discharging switch to manage the charging and discharging of the battery module. For example, the battery module may be charged when the charge switch is closed, and the battery module may be discharged to the outside when the discharge switch is closed. The charge switch and/or the discharge switch may be controllable switches capable of receiving a control signal to turn on or off, and may be, for example, various relays, transistor switches, IGBTs, and the like. It can be understood that a driving module can be arranged between the output end of the self-locking circuit and the charging switch and/or the discharging switch, the output signal of the self-locking circuit is transmitted to the driving module, and the driving module outputs the driving signal again, so that the on-off of the charging switch and the discharging switch is controlled.
It will be appreciated that in the case where only one switch is shown in fig. 5 as a charge switch or a discharge switch, in other embodiments the charge switch is disposed on the charge path and the discharge switch is disposed on the discharge path.
Battery energy storage system and other consumer (provide electric energy by the battery), be provided with BMS, BMS and battery module constitution battery system, this BMS is used for managing battery module's each item parameter (voltage, electric current, temperature etc.).
The principle and the technical effects of the signal latch circuit provided by the embodiment of the battery management system are the same as those of the embodiment of the signal latch circuit, and for the sake of brevity, reference is made to the corresponding contents of the embodiment of the signal latch circuit.
The embodiment of the application also provides a battery system which comprises the battery module and the battery management system, wherein the battery management system is connected with the battery module and is used for controlling the charging and/or discharging of the battery module. The battery module may include at least one battery.
The principles and technical effects of the battery management system provided by the battery system embodiment are the same as those of the battery management system embodiment, and for brevity, reference may be made to the corresponding content of the battery management system embodiment.
The embodiment of the application also provides electric equipment, which comprises a load and the battery system, wherein the battery system is used for supplying power to the load. The electric equipment is different, and the corresponding load is also different.
The powered device may be a battery energy storage system, including a household energy storage system, a portable energy storage system, and the like. The electric equipment can be an electric vehicle, and comprises an electric train, an electric automobile, a ship, an electric two-wheel vehicle (such as a battery car, an electric bicycle and the like), an electric motorcycle, an electric tricycle and the like. The powered device may be an electric tool, including an electric drill, an electric wrench, an electric hammer, and a garden electric tool, such as a mower. The powered device may be a cleaning tool, including a sweeping robot, a dust collector, or the like.
The principle and the technical effects of the battery system provided by the electric equipment embodiment are the same as those of the battery system embodiment, and for the sake of brief description, reference may be made to the corresponding content in the battery system embodiment.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A signal latch circuit comprising: the output pin of the latch is connected with the self-locking circuit;
the latch comprises a zero clearing pin which is pulled up to be in a high level;
the self-locking circuit comprises a control unit, an output end and a self-locking unit, wherein the control unit is connected with the self-locking unit, and the self-locking unit is connected with the output end and an output pin of the latch;
the self-locking circuit is configured to respond to the control unit to receive a control signal and the output pin to output a high level, and is conducted and outputs a first signal at the output end.
2. The signal latch circuit of claim 1, the control unit comprising: the first resistor, the first switch and the control end;
the control terminal is configured to receive the control signal;
a first end of the first switch is connected with the control end, a second end of the first switch is configured to be connected with a power supply, and a third end of the first switch is connected with the self-locking unit;
the first resistor is connected between a first end of the first switch and a second end of the first switch.
3. The signal latch circuit of claim 2, the control unit further comprising: the second resistor is connected between the control end and the first end of the first switch, and is connected with the first resistor at one side close to the control end.
4. A signal latching circuit according to any one of claims 1-3, the self-locking unit comprising: the second switch, the third resistor, the fourth resistor and the fifth resistor;
the second end of the second switch is grounded, the third end of the second switch is respectively connected with the first end and the output end of the third switch, and the third end of the second switch and the output pin of the latch are also connected with a first node;
the second end of the third switch and the output pin of the latch are connected to the first node, and the third end of the third switch and the first end of the second switch are connected to the second node;
the third resistor is connected between the first node and the first end of the third switch;
the fourth resistor is connected between the first node and the output end of the self-locking circuit;
the fifth resistor is connected between the second node and a second end of the second switch.
5. The signal latching circuit of claim 4 wherein the second switch is one of a transistor, FET and IGBT and the third switch is one of a transistor, FET and IGBT.
6. The signal latch circuit of claim 4 or 5, the self-latching unit further comprising: at least one of the sixth resistor, the seventh resistor, and the eighth resistor;
the sixth resistor is connected between the first end of the third switch and a third node, wherein the third end of the second switch and the output end of the self-locking circuit are connected to the third node;
the seventh resistor is connected between the control unit and the second node;
the eighth resistor is connected between the second node and a third terminal of the third switch.
7. The signal latching circuit of any of claims 1-6, the latching circuit further configured to:
in response to the control unit not receiving the control signal, the self-locking circuit is disconnected;
or alternatively, the process may be performed,
the latching circuit is opened in response to an output pin of the latch outputting a low level.
8. A battery management system comprising the signal latch circuit of any one of claims 1 to 7, the battery management system further comprising: the device comprises a controller, a watchdog circuit, a logic gate circuit, a power supply, a charging switch and a discharging switch;
the power supply is connected to the self-locking circuit, the controller is connected to the logic gate circuit and the latch, the logic gate circuit is connected to the watchdog circuit and the control end of the self-locking circuit, and the output end of the self-locking circuit is connected to the charging switch and/or the discharging switch.
9. The battery management system of claim 8, the logic gate circuit configured to satisfy at least one of the following conditions:
i) The logic gate circuit receives a controller reset signal transmitted by the watchdog circuit and transmits the control signal to a control end of the self-locking circuit;
ii) the logic gate circuit receives the controller latch signal transmitted by the controller and transmits the control signal to the control end of the self-locking circuit.
10. A battery system comprising a battery module and the battery management system according to claim 8 or 9, the battery module being connected to the battery management system.
11. A powered device comprising a load and the battery system of claim 10, the battery system powering the load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310799299.0A CN116846365A (en) | 2023-06-30 | 2023-06-30 | Signal latch circuit, battery management system, battery system and electric equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310799299.0A CN116846365A (en) | 2023-06-30 | 2023-06-30 | Signal latch circuit, battery management system, battery system and electric equipment |
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| Publication Number | Publication Date |
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| CN116846365A true CN116846365A (en) | 2023-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310799299.0A Pending CN116846365A (en) | 2023-06-30 | 2023-06-30 | Signal latch circuit, battery management system, battery system and electric equipment |
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| CN (1) | CN116846365A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117360536A (en) * | 2023-11-07 | 2024-01-09 | 吉咖智能机器人有限公司 | Circuit system for protecting vehicle from faults and vehicle |
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2023
- 2023-06-30 CN CN202310799299.0A patent/CN116846365A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117360536A (en) * | 2023-11-07 | 2024-01-09 | 吉咖智能机器人有限公司 | Circuit system for protecting vehicle from faults and vehicle |
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