CN116683896B

CN116683896B - Duty cycle adjustable circuit, chip and electronic equipment

Info

Publication number: CN116683896B
Application number: CN202211690436.9A
Authority: CN
Inventors: 张伟
Original assignee: Haiguang Integrated Circuit Design Beijing Co ltd
Current assignee: Haiguang Integrated Circuit Design Beijing Co ltd
Priority date: 2022-12-27
Filing date: 2022-12-27
Publication date: 2024-04-02
Anticipated expiration: 2042-12-27
Also published as: CN116683896A

Abstract

The application provides a duty cycle adjustable circuit, chip and electronic equipment, duty cycle adjustable circuit includes: a delay phase-locked loop circuit configured to receive an original clock signal and delay the original clock signal to generate N first clock signals having equal differences in phase; and the duty ratio regulating circuit is electrically connected with the delay phase-locked loop circuit and is configured to receive a duty ratio selection signal and select two target first clock signals from N first clock signals according to the duty ratio selection signal so as to generate a second clock signal according to the two target first clock signals. Based on the duty ratio adjustable circuit provided by the embodiment of the application, the duty ratio adjustable circuit can generate a second clock signal with the required duty ratio only by outputting the corresponding duty ratio selection signal to the duty ratio adjustable circuit according to the requirement, so that the clock signal is accurately controlled to be adjusted.

Description

Duty cycle adjustable circuit, chip and electronic equipment

Technical Field

The application relates to the field of chips, in particular to a duty cycle adjustable circuit, a chip and electronic equipment.

Background

In large scale integrated circuits, a clock signal drives all sequential logic devices, determining the operating frequency of the chip. With the increasing frequency of chip operation, the quality requirement of clock signals is also increasing, and high-speed, low-jitter and high-precision clock signals are generally required. In some circuit designs, it is also necessary to adjust the duty cycle of the clock signal according to specific design requirements, so as to generate a clock signal with a specific duty cycle.

With the transmission of the clock signal, power supply noise or signal noise in the circuit may deviate the duty cycle of the clock signal by 50%. The longer the distance of signal transmission, the higher the degree of deviation, and when reaching the sequential logic device, the duty cycle of the clock signal may have deviated by 50%, and this clock signal may greatly affect the performance of the whole chip, so the clock signal needs to be corrected before reaching the sequential logic device, so that when the clock signal is transmitted at a long distance, the duty cycle is returned to 50%.

In some digital circuit designs, a clock signal with a specific duty cycle is used, and this duty cycle is not equal to 50%, and may be equal to 20% or 80%, and how to generate this high-precision clock signal is also a problem in chip design.

Furthermore, in circuit design, there may be a case where the duty ratio of the clock signal needs to be dynamically adjusted according to the function of the design. For example, if it is found in the test that some duty cycles fail to meet the design requirements, a fast switch to the clock signal of another duty cycle is required to meet the chip's functionality.

In view of the above, it would be desirable to provide a circuit that enables accurate controlled adjustment of the signal duty cycle.

Disclosure of Invention

The embodiment of the application aims to provide a duty ratio adjustable circuit, a chip, an electronic component and electronic equipment, wherein the duty ratio adjustable circuit, the chip and the electronic component can realize accurate and controlled adjustment of a signal duty ratio.

The embodiment of the application provides a duty ratio adjustable circuit, which comprises: a delay phase-locked loop circuit configured to receive an original clock signal and delay the original clock signal to generate N first clock signals having equal differences in phase; n is a positive integer greater than or equal to 2; a duty cycle adjustment circuit electrically connected to the delay phase locked loop circuit and configured to receive a duty cycle selection signal and select two target first clock signals from the N first clock signals according to the duty cycle selection signal to generate a second clock signal according to the two target first clock signals; the second clock signal has a set duty cycle.

In the above implementation structure, the delay phase-locked loop circuit can stably generate N first clock signals with equal phase differences, and then the duty cycle adjusting circuit selects two target first clock signals from the N first clock signals according to the duty cycle selection signal, and generates a second clock signal based on the target first clock signals. It will be appreciated that in the case where the duty cycle adjustment circuit determines that the direct phase difference of the two target first clock signals is determined, then the duty cycle of the corresponding generable second clock signal is determined, and with the difference in the direct phase difference of the two target first clock signals, the generable second clock signal may also differ, for example, a second clock signal having a duty cycle of 50 may be generated based on the target first clock signal having a phase difference of (N-1/2) clock cycles, and a second clock signal having a duty cycle of (1/(N-1)) may be generated based on the target first clock signal having a phase difference of (1/(N-1)). Therefore, based on the duty cycle adjustable circuit provided by the embodiment of the application, only the corresponding duty cycle selection signal is output to the duty cycle adjustable circuit according to the requirement, so that the duty cycle adjustable circuit can generate the second clock signal with the required duty cycle, the accurate and controlled adjustment of the clock signal is realized, the clock signal with the specific duty cycle is generated according to the specific design requirement, the clock signal with the specific duty cycle is corrected according to the clock signal during long-distance transmission, the clock signal with the high precision and the specific duty cycle is generated, or the clock signal with the multiple duty cycles is rapidly switched according to the implementation mode of the application, and the implementation mode of the application has very strong universality.

Further, the delay locked loop circuit includes: an original clock signal input for receiving the original clock signal; the delay chain comprises a plurality of delay unit circuits which are sequentially connected with the input end of the original clock signal in series; and the state machine is respectively connected with each delay unit circuit to adjust the delay value of each delay unit circuit.

In the implementation process, the delay value of each delay unit circuit is adjusted through a plurality of delay unit circuits which are sequentially connected with the input end of the original clock signal in series, so that the phase difference between the first clock signals is fixed on a designed phase difference through the setting of the state machine, and the subsequent generation of the second clock signal with the required duty ratio based on the selection of the first clock signals is ensured.

Further, the delay locked loop circuit further includes: the phase detector is respectively connected with the signal input end of the delay unit circuit of the first stage, the signal output end of the delay unit circuit of the last stage and the state machine and is used for outputting a locking signal to the state machine when the phase difference between the signal input into the delay unit circuit of the first stage in the delay chain and the first clock signal output by the delay unit circuit of the last stage in the delay chain is one clock period; the state machine is used for gradually increasing the delay value of each delay unit circuit and maintaining the delay value of each delay unit circuit when the locking signal is received.

In the above implementation manner, the phase difference between the adjacent first clock signals can be controlled to be (1/(N-1)) clock cycles through the action of the phase detector, so that the selection of the target first clock signal is facilitated.

Further, the delay unit circuit includes: and the adjustable capacitor is connected with the state machine.

In the implementation manner, the state machine can effectively adjust the delay value of the whole delay unit circuit by controlling the value of the adjustable capacitor, so that the controlled adjustment of the delay unit circuit is realized, and the implementation structure is simple.

Further, the duty cycle adjustment circuit includes: the signal input end of the first multiplexer is respectively connected with the signal output end of each first clock signal in the delay phase-locked loop circuit, and the enabling end of the first multiplexer is configured to receive the duty ratio selection signal so that the first multiplexer can select two target first clock signals to output according to the duty ratio selection signal; and the clock signal generating circuit is connected with the signal output end of the first multiplexer so as to generate the second clock signal according to the two target first clock signals.

In the implementation manner, the selection of the target first clock signal based on the duty ratio selection signal can be realized through the action of the first multiplexer, and the second clock signal can be generated through the clock signal generating circuit, so that the simple and reliable structure is realized.

Further, the clock signal generation circuit includes: the signal input ends of the second multiplexer are respectively connected with the two signal output ends of the first multiplexer; the clock signal input end of the trigger is connected with the signal output end of the second multiplexer, and the data output end of the trigger is connected with the data input end of the trigger through an inverter; the enabling end of the second multiplexer is connected with the data input end of the trigger.

In the above implementation, the signal output by the data output terminal is at a low level at the beginning of the flip-flop, and after passing through the inverter, a high level is output, so that the signal Din of the data input terminal of the flip-flop is equal to 1, and the second multiplexer sends the first target first clock signal to the clock signal input terminal of the flip-flop. When the clock signal transmission circuit works, the first target first clock signal rising edge triggers the trigger to transmit Din to the data output end, the Gclk signal output by the data output end is turned from low level to high level, and after the high level passes through the phase inverter, the low level is output, so that Din is equal to 0, and the second multiplexer transmits the second target first clock signal to the clock signal input port of the trigger.

Over time, the second target first clock signal rising edge triggers the flip-flop to transmit the Din signal to the data output, and the Gclk signal toggles from high to low. After the Gclk signal passes through the inverter, a high level is output so that Din is equal to 1, and the first target first clock signal is transmitted to the clock signal input port of the flip-flop. Then, after delaying the rising edge of the first target first clock signal, the rising edge of the first target first clock signal triggers the flip-flop to transmit the Din signal to the data output terminal, and the Gclk signal is inverted from the low level to the high level. This process is repeated continuously, so that the Gclk signal has a specific duty cycle. Therefore, the structure can effectively realize the generation of the second clock signal, is simple to realize and is beneficial to implementation in a chip.

Further, the duty cycle adjustment circuit further includes: a third multiplexer, one signal input of the third multiplexer being connected to the data output of the flip-flop, the other signal input of the third multiplexer being configured to receive the original clock signal; the enable terminal of the third multiplexer is configured to receive an enable signal and the enable terminal of the flip-flop is also configured to receive the enable signal.

In the above implementation manner, through the action of the third multiplexer and the enable signal, the original clock signal can be output when the trigger is not enabled, so as to ensure the correct transmission of the clock signal.

Further, the clock signal generation circuit includes: the signal input end of the first pulse generating circuit is connected with one signal output end of the first multiplexer; the signal input end of the second pulse generating circuit is connected with the other signal output end of the first multiplexer; and the set port of the latch is connected with the signal output end of the first pulse generating circuit, and the reset port of the latch is connected with the signal output end of the second pulse generating circuit.

In the above implementation manner, the pulse clock signal may be generated through the first pulse generating circuit and the second pulse generating circuit, and since the first pulse generating circuit and the second pulse generating circuit are pulse clock signals respectively generated based on the first target first clock signal and the second target first clock signal, a rising edge interval between the two pulse clock signals is equal to a phase difference between the two target first clock signals, so that the clock signal of a specific duty ratio related to the phase difference between the two target first clock signals may be generated after the latch is driven. Therefore, the structure can effectively realize the generation of the second clock signal, is simple to realize and is beneficial to implementation in a chip.

Further, the duty cycle adjustment circuit further includes: a fourth multiplexer, one signal input terminal of the fourth multiplexer being connected to the signal output terminal of the flip-flop, the other signal input terminal of the fourth multiplexer being configured to receive the original clock signal, the enable terminal of the fourth multiplexer being configured to receive an enable signal; the set and reset ports of the latch are configured to receive the enable signal through an inverter.

In the above implementation manner, through the action of the fourth multiplexer and the enable signal, the original clock signal can be output when the latch is not enabled, so as to ensure the correct transmission of the clock signal.

The embodiment of the application also provides a chip which comprises the duty ratio adjustable circuit of any one of the above.

The embodiment of the application also provides electronic equipment, which comprises the chip.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a basic structure of a duty cycle adjustable circuit according to an embodiment of the present application;

fig. 2 is a schematic diagram of a basic structure of a delay locked loop circuit according to an embodiment of the present application;

fig. 3 is a schematic diagram of a basic structure of a duty cycle adjusting circuit according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a specific duty cycle adjusting circuit according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of another specific duty cycle adjustment circuit according to an embodiment of the present disclosure;

fig. 6 is a waveform diagram of a lock state signal of a delay locked loop circuit according to an embodiment of the present application;

FIG. 7 is a signal waveform diagram of a 50% duty cycle clock signal generated by the circuit of FIG. 4 according to one embodiment of the present disclosure;

FIG. 8 is a signal waveform diagram of a case of generating a 1/n duty cycle clock signal using the circuit of FIG. 4 according to an embodiment of the present application;

fig. 9 is a signal waveform diagram of a 50% duty cycle clock signal generated by the circuit of fig. 5 according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

In order to realize accurate and controlled adjustment of the signal duty ratio, the embodiment of the application provides a duty ratio adjustable circuit. Referring to fig. 1, fig. 1 is a schematic diagram of a basic structure of a duty cycle adjustable circuit provided in an embodiment of the present application, including a Delay Lock Loop (DLL) circuit and a duty cycle adjustment (duty cycle adjustment, DCA) circuit.

The delay phase-locked loop circuit is configured to receive an original clock signal, delay the original clock signal to generate N first clock signals with equal differences in phase, and sequentially record PH [0] to PH [ N ], wherein PH [0] to PH [ N ] can also be written as PH [ n:0]. Wherein N is a positive integer greater than or equal to 2, and N is equal to N-1.

And the duty ratio adjusting circuit is electrically connected with the delay phase-locked loop circuit and is configured to receive a duty ratio selection signal Sel [ i:0] and select two target first clock signals from N first clock signals according to the duty ratio selection signal so as to generate a second clock signal Clkuut according to the two target first clock signals.

It will be appreciated that in the case of a determined duty cycle adjustment circuit, since the direct phase difference of the two target first clock signals is also determined, the duty cycle of the second clock signal that the duty cycle adjustment circuit can correspondingly generate is determined, i.e. the second clock signal is a clock signal with a set duty cycle. Therefore, the second clock signal with the required duty ratio can be generated by the duty ratio adjustable circuit only by outputting the corresponding duty ratio selection signal to the duty ratio adjustable circuit according to the requirement, and the accurate controlled adjustment of the clock signal is realized.

In an embodiment of the present application, as shown in fig. 2, the delay locked loop circuit may include an original clock signal input, a delay chain, and a state machine (i.e., the DLL FSM in fig. 2). The original clock signal input end is used for receiving an original clock signal; the delay chain comprises a plurality of delay unit circuits which are sequentially connected with the input end of the original clock signal in series; the state machine is connected with each delay unit circuit respectively to adjust the delay value of each delay unit circuit.

It will be appreciated that in the embodiment of the present application, the original clock signal input terminal may include only a signal line to directly receive the original clock signal clk, and input the clk as the initial first clock signal PH [0] into the subsequent delay cell circuits. That is, in the embodiment of the present application, the initial first clock signal PH [0] may be a clock signal obtained by delaying the original clock signal Clkin by zero clock cycles.

In addition, in this embodiment of the present application, as shown in fig. 2, the input end of the original clock signal may also include a buffer B0, so that the buffer B0 shapes the original clock signal clk, thereby improving the driving capability of the original clock signal clk, reducing the driving force of the signal, which is caused by long-time transmission, of the original clock signal clk, and affecting the subsequent processing. The clock signal output through the buffer B0 is the initial first clock signal PH 0.

It is understood that in the embodiment of the present application, the delay chain may include n delay unit circuits, so as to sequentially generate the first clock signal PH [1] to the first clock signal PH [ n ]. It will also be appreciated that the configuration of each delay cell circuit may be uniform to ensure that the first clock signals output by adjacent two delay cell circuits have the same phase difference.

In the embodiment of the present application, each delay unit circuit is a circuit with a controllable delay value. To this end, in a possible implementation manner of the embodiment of the present application, as shown in fig. 2, each delay unit circuit may include a buffer (i.e., B1 to Bn in the drawing) and an adjustable capacitor (i.e., C1 to Cn in the drawing) connected in parallel, and the adjustable capacitor is connected to the state machine, so that the adjustable capacitor continuously adjusts its own size under the control of a configuration signal (i.e., D1 to Dn in the drawing) issued by the state machine to change the delay value of the whole delay unit circuit.

It will be appreciated that in the embodiment of the present application, each delay unit circuit may be implemented by adopting other structures besides the buffer based on parallel connection and the adjustable capacitor, for example, a buffer based on series connection and an adjustable resistor, and the embodiment of the present application is not limited to the above-exemplified structure for the specific implementation structure of the delay unit circuit.

In an embodiment of the present application, as shown in fig. 2, the delay locked loop circuit may further include a Phase Detector (PD). The phase detector is respectively connected with the signal input end of the first-stage delay unit circuit, the signal output end of the last-stage delay unit circuit and the state machine, and is used for outputting a locking signal to the state machine when the phase of the signal (PH 0) input into the first-stage delay unit circuit in the delay chain is different from the phase of the first clock signal (PH n) output by the last-stage delay unit circuit in the delay chain by one clock period.

The state machine is used for gradually increasing the delay value of each delay unit circuit and maintaining the delay value of each delay unit circuit when the locking signal is received.

In this way, the delay value of each delay unit circuit is continuously increased through the state machine, and the delay value at the moment is maintained when the phase difference between PH [0] and PH [ N ] is just different by one clock cycle, so that the phase difference between adjacent first clock signals can be controlled to be (1/(N-1)) clock cycles, and the selection of the target first clock signals is facilitated.

It will be appreciated that in an alternative implementation of the embodiment of the present application, the phase detector may not be provided, and each delay cell circuit may have a specified delay value by configuring the magnitude of the configuration signal D generated by the state machine.

It should also be understood that the foregoing is merely a few alternative delay locked loop circuit implementation structures provided in the embodiments of the present application, but the embodiments of the present application are not limited to implementation using only these structures. In fact, various delay locked loop circuits may be implemented in the embodiments of the present application, so long as they can generate a plurality of first clock signals with the same phase difference.

In an embodiment of the present application, referring to fig. 3, the duty cycle adjustment circuit may include a first multiplexer CLOCK MUX and a CLOCK signal generation circuit. Wherein:

the signal input ends of the first multiplexer CLOCK MUXs are respectively connected with the signal output ends of the first CLOCK signals in the delay phase-locked loop circuit, and the enabling ends of the first multiplexer CLOCK MUXs are configured to receive the duty ratio selection signals Sel [ i:0], so that the first multiplexer CLOCK MUXs select two target first CLOCK signals to output according to the duty ratio selection signals Sel [ i:0 ].

The CLOCK signal generating circuit is connected with the signal output end of the first multiplexer CLOCK MUX to generate a second CLOCK signal according to the two target first CLOCK signals.

It will be appreciated that the duty cycle selection signal Sel [ i:0] may be configured according to the desired duty cycle. The duty cycle selection signals Sel [ i:0] are different, and the combination of the selected target first clock signals is different, so that the waveforms and the duty cycles of the generated second clock signals may be different.

It will also be appreciated that the clock signal generation circuit may be implemented in at least the following two ways, but is not limited thereto:

mode one: as shown in fig. 4, the clock signal generating circuit may include a second multiplexer K2 and a flip-flop (a case of using a data flip-flop (DFF) is shown in the figure, but not as a limitation). Wherein:

the signal input terminal of the second multiplexer K2 is connected to the two signal output terminals of the first multiplexer CLOCK MUX, respectively.

The clock signal input end of the trigger is connected with the signal output end of the second multiplexer K2, and the data output end of the trigger is connected with the data input end of the trigger through the inverter.

The enable terminal of the second multiplexer K2 is connected to the data input terminal of the flip-flop.

Thus, the signal output from the data output terminal is at a low level at the beginning of the flip-flop, and after passing through the inverter, a high level is output so that the signal Din of the data input terminal of the flip-flop is equal to 1, and the second multiplexer K2 transmits the first target first clock signal to the clock signal input terminal of the flip-flop. When the clock signal switching circuit works, the first target first clock signal rising edge triggers the trigger to transmit Din to the data output end, the Gclk signal output by the data output end is turned from low level to high level, and after the high level passes through the phase inverter, the low level is output, so that Din is equal to 0, and the second target first clock signal is transmitted to the clock signal input port of the trigger by the second multiplexer K2.

Over time, the second target first clock signal rising edge triggers the flip-flop to transmit the Din signal to the data output, and the Gclk signal toggles from high to low. After the Gclk signal passes through the inverter, a high level is output so that Din is equal to 1, and the first target first clock signal is transmitted to the clock signal input port of the flip-flop. Then, after delaying the rising edge of the first target first clock signal, the rising edge of the first target first clock signal triggers the flip-flop to transmit the Din signal to the data output terminal, and the Gclk signal is inverted from the low level to the high level. This process is repeated continuously, so that the Gclk signal has a specific duty cycle.

In the above manner, please continue to refer to fig. 4, the duty cycle adjustment circuit may further include: and a third multiplexer. One signal input of the third multiplexer K3 is connected to the data output of the flip-flop, and the other signal input of the third multiplexer K3 is configured to receive the original clock signal.

The enable terminal of the third multiplexer K3 is configured to receive the enable signal, and the enable terminal of the flip-flop is also configured to receive the enable signal.

In this way, through the action of the third multiplexer and the enabling signal, the original clock signal can be output when the trigger is not enabled, so that the correct transmission of the clock signal is ensured.

It will be appreciated that to ensure that the driving capability of the original clock signal being output is sufficient, the other signal input of the third multiplexer K3 may be connected to the input of the first delay cell circuit of the delay chain to output PH 0 when the flip-flop is not enabled.

Mode two: as shown in fig. 5, the clock signal generation circuit may include a first pulse generation circuit (i.e., PG1 in fig. 5), a second pulse generation circuit (i.e., PG2 in fig. 5), and a latch. The signal input end of the first pulse generating circuit is connected with one signal output end of the first multiplexer CLOCK MUX.

The signal input end of the second pulse generating circuit is connected with the other signal output end of the first multiplexer CLOCK MUX.

The set port of the latch is connected with the signal output end of the first pulse generating circuit, and the reset port of the latch is connected with the signal output end of the second pulse generating circuit.

In this way, the pulse clock signal can be generated through the first pulse generating circuit and the second pulse generating circuit, and since the first pulse generating circuit and the second pulse generating circuit are pulse clock signals respectively generated based on the first target first clock signal and the second target first clock signal, the rising edge interval between the two pulse clock signals is equal to the phase difference between the two target first clock signals, so that the clock signal with a specific duty ratio related to the phase difference between the two target first clock signals can be generated after the latch is driven.

Similarly, in the above implementation, the duty cycle adjustment circuit may further include a fourth multiplexer K4.

One signal input of the fourth multiplexer K4 is connected to the signal output of the flip-flop, and the other signal input of the fourth multiplexer K4 is configured to receive the original clock signal.

The enable terminal of the fourth multiplexer K4 is configured to receive the enable signal En. And the set and reset ports of the latch are configured to receive the enable signal En through the inverter.

Similarly, by the action of the fourth multiplexer K4 and the enable signal En, the original clock signal can be output when the latch is not enabled, ensuring the correct transmission of the clock signal.

Similarly, to ensure that the driving capability of the output original clock signal is sufficient, the other signal input terminal of the fourth multiplexer K4 may be connected to the input terminal of the first delay cell circuit of the delay chain, thereby outputting PH [0] when the flip-flop is not enabled.

It will be appreciated that in the embodiment of the present application, the second multiplexer K2, the third multiplexer K3 and the fourth multiplexer K4 may be implemented by using two or one selectors. The first multiplexer may then be implemented using a 2-N selector.

It will also be appreciated that the above are just a few of the alternative duty cycle adjustment circuit configurations illustrated in the embodiments of the present application, but not limiting. For example, the first multiplexer in the duty cycle adjustment circuit may also be implemented using other more complex circuits that enable signal selection.

In the following, in order to facilitate understanding of the solution of the embodiment of the present application, the delay locked loop circuit is taken as an example with the structure shown in fig. 2, and the duty cycle adjusting circuit is taken as an example with the structures shown in fig. 4 and 5, respectively, to describe the embodiment of the present application as an example.

For the delay locked loop circuit, when the original clock signal Clkin is input, the first clock signal PH [ n:0] is generated through the buffer B0 and each delay unit circuit.

Specifically, the input clock signal ClkIn passes through the primary buffer B0 to generate a PH 0 signal, and the PH 0 signal is a reference clock signal of the whole delay chain. The delay unit circuit is composed of a buffer and an adjustable capacitor. The adjustable load capacitor receives configuration signals D1 to Dn generated by the state machine, each of which is a set of bus signals. Taking the first stage delay cell circuit as an example, when D1 is equal to 0, the buffer does not drive the adjustable capacitor, the delay of the circuit is minimum, and as the value of D1 becomes larger, the value C1 of the load capacitor synchronously increases, and the delay of the buffer synchronously increases. By adjusting the value of D1, the delay value of the delay cell circuit can be adjusted.

The PH 0 signal drives the first stage delay unit circuit to generate PH 1, and PH 1 and PH 0 have the same frequency and phase difference by one stage delay unit value. The PH 1 signal drives the second stage delay cell circuit to generate PH 2, the PH 2 and PH 1 being out of phase by one stage delay cell value. Similarly, PH 3, …, PH n-1 and PH n signals are continuously generated. All PH [ n:0] signals have the same frequency and differ in phase by one delay unit value.

The phase detector monitors the phase difference between PH 0 and PH n and sends the difference to the state machine. The phase detector may be implemented with a flip-flop (DFF), PH 0 being used as a sampling clock, connected to a clock port of the DFF, PH n being used as a sampling signal, connected to a data port of the DFF. The value of PH [ n ] is sampled using PH [0] and then sent to the state machine.

In the embodiment of the application, the state machine receives the sampling signal sent by the phase detector, and dynamically adjusts the configuration signals D1, D2, … and Dn of the delay chain according to the sampling value. In the initial state, all the configuration signals are equal to 0, then the values of the configuration signals are continuously increased, so that the delay of the delay unit circuit is continuously increased, then the configuration signals are continuously and dynamically adjusted according to the sampling values, and finally the obtained signal waveforms are shown in fig. 6.

A waveform diagram of the lock state signal of the delay locked loop circuit is shown in fig. 6, where Tcyc represents the clock period of the input original clock signal. When the delay phase-locked loop circuit is locked, PH 0 is used as a reference clock signal, the phase difference between PH n and PH 0 is exactly one clock cycle, the phase difference between PH 1 and PH 0 is 1/n clock cycle, the phase difference between PH 2 and PH 0 is 2/n clock cycle, the phase difference between PH n/2 and PH 0 is 1/2 clock cycle, and the phase difference between PH n-1 and PH 0 is (1-1/n) clock cycle.

When the delay phase-locked loop circuit is locked, the phase difference between PH [ n:1] and PH [0] is generated as shown in the following table:

signal signal	Phase difference	Signal signal	Phase difference
				PH[1]	1/n	PH[n/2+1]	1/2+1/n
PH[2]	2/n	PH[n/2+2]	1/2+2/n
				PH[3]	3/n	PH[n/2+3]	1/2+3/n
…	…	…	…
				PH[n/2-2]	1/2-2/n	PH[n-2]	1-2/n
PH[n/2-1]	1/2-1/n	PH[n-1]	1-1/n
				PH[n/2]	1/2	PH[n]	1

At this time, the delay phase-locked loop circuit can generate a flag bit signal of DLL_lock, which indicates that the delay phase-locked loop circuit is already in a locked state, and the PH [ n:0] clock signals are all generated, so that an output signal with adjustable duty ratio can be generated. The dllock signal may be sent to a control module to generate a high level enable signal to enable the duty cycle adjustment circuit to operate.

The following describes the duty cycle adjusting circuit shown in fig. 4 in detail:

the duty cycle adjusting circuit receives the PH [ n:0] CLOCK signal sent by the delay phase-locked loop circuit and transmits the PH [ n:0] CLOCK signal to the first multiplexer CLOCK MUX, and the selection signal of the CLOCK MUX is a duty cycle selection signal Sel [ i:0]. The value of Sel [ i:0] is configured to transfer the particular two-way clock signal in PH [ n:0] to the CLK0 and CLK1 ports. CLK0 and CLK1 are transmitted to the clock port of the flip-flop (DFF) through the second multiplexer K2, the input signal En is an asynchronous reset signal (i.e., the enable signal described above) of the DFF, when En is equal to 0, the DFF is reset to zero, and when En is equal to 1, the DFF is enabled to operate normally, generating the Gclk signal. The En signal is used as a selection signal of a third multiplexer K3 of the PH [0] and the Gclk signals, when the En is equal to 0, the PH [0] is sent to the Clkuut port, the duty ratio of the output signal cannot be adjusted, and when the En is equal to 1, the Gclk signal is sent to the Clkuut port.

The output signal Gclk of the DFF flip-flop is connected to the data port Din (data input) of the DFF through an inverter while being connected to the selection port of the first multiplexer. CLK1 is transferred to the CLK port (clock signal input) when Din is equal to 1, and CLK0 is transferred to the CLK port when Din is equal to 0.

The following description will be given for the case of generating a 50% duty cycle clock signal using the above-described circuit as an example:

the Sel [ i:0] signal is configured to send PH [0] to the CLK1 port and PH [ n/2] to the CLK0 port, PH [ n/2] being out of phase with PH [0] by 1/2 clock cycles. The waveform of each signal at this time is shown in fig. 7.

When En is equal to 0, the DFF is in a reset and zero state, the Gclk signal is in a low level, and after passing through the inverter, the high level is output, so that Din is equal to 1, and Din sends PH [0] to a clock input port of the DFF, and the DFF is initialized. And loading high level on En port, normal operation of DFF, triggering DFF to transmit Din to Q port (data output end) by PH 0 rising edge, turning Gclk signal from low level to high level, and outputting low level after high level passes through inverter to make Din equal to 0, and transmitting PH n/2 to CK port of DFF.

After a delay of 0.5 tcyc time, the rising edge of PH n/2 triggers the DFF to transmit Din to the Q port, the Gclk signal toggles from high to low, and the Gclk high lasts for 0.5 tcyc time. After the Gclk low signal passes through the inverter, a high signal is output such that Din is equal to 1, transmitting PH 0 to the CK port of the DFF. Then, after a delay of 0.5 tcyc time, the rising edge of PH [0] triggers the DFF to transmit Din to the Q port, the Gclk signal toggles from low to high, and the Gclk low lasts for 0.5 tcyc time. The Gclk signal outputs a low level through an inverter such that Din is equal to 0, transmitting PH n/2 to the CK port of the DFF.

In this way, the Gclk high level has a duration exactly equal to 0.5 times the clock period and the low level has a duration exactly equal to 0.5 times the clock period. The output Gclk signal has a duty cycle exactly equal to 50% no matter how much the duty cycle of the input clock Clkin is equal.

The following description will be made with respect to a case of generating a 1/n duty cycle clock signal using the above-described circuit as an example:

the Sel [ i:0] signal is configured to send PH [0] to the CLK1 port and PH [1] to the CLK0 port, PH [1] and PH [0] being out of phase by 1/n clock cycles. The waveform of each signal at this time is shown in fig. 8.

When En is equal to 0, the DFF is in a reset and zero state, the Gclk signal is in a low level, din is equal to 1 after the signal passes through an inverter, PH [0] is sent to a clock input CK port of the DFF, and the DFF is initialized. And loading high level on En port, normal operation of DFF, and transmitting Din to Q port by PH 0 rising edge triggering DFF, turning Gclk signal from low level to high level, and after high level passes through inverter, making Din equal to 0, and transmitting PH 1 to CK port of DFF.

After a delay of 1/n Tcyc, the rising edge of PH [1] triggers the DFF to transmit Din to the Q port, the Gclk signal toggles from high to low, and the Gclk high lasts for 1/n Tcyc time. After the Gclk low-level signal passes through the inverter, a high level is output, so that Din is equal to 1, PH [0] is transmitted to a CK port of the DFF, then after (1-1/n) Tcyc time is delayed, the rising edge of PH [0] triggers the DFF to transmit Din to a Q port, the Gclk signal is turned from the low level to the high level, and the Gclk low level lasts (1-1/n) Tcyc time. The Gclk signal goes through an inverter, outputting a low level such that Din is equal to 0, transmitting PH [1] to the CK port of the DFF.

In this way, gclk has a high level of duration exactly equal to 1/n Tcyc and a low level of duration exactly equal to (1-1/n) Tcyc. The duty cycle of the output Gclk signal is exactly equal to 1/n, no matter how much the duty cycle of the input clock Clkin is equal.

The following specifically describes the duty cycle adjustment circuit shown in fig. 5:

the circuit of fig. 5 employs a two-way pulse generating circuit (i.e., a first pulse generating circuit and a second pulse generating circuit) and a latch instead of the second multiplexer K2 and DFF flip-flop of fig. 4. By configuring the Sel [ i:0] signal, two specific clock signals are sent to the CLK0 and CLK1 ports, and CLK0 and CLK1 drive the two pulse generating circuits to generate two pulse clock signals, respectively.

The two pulse clock signals are connected to the Set (Set) and Reset (Reset) ports of the latch, respectively, the Set signal sets Gclk high, and the Reset signal sets Gclk low.

Illustratively, for the case of generating a 50% duty cycle clock signal: PH 0 is transferred to the CLK1 port and PH n/2 is transferred to the CLK0 port by configuring the Sel [ i:0] signal, PH n/2 being out of phase with PH 0 by 0.5 clock cycles. The signal waveform at this time is shown in fig. 9.

When the En signal is equal to 0, gclk is maintained at a low level. After En signal is enabled, PH [0] driving Pulse Generator (PG) generates Set pulse signal, PH [ n/2] driving pulse generator generates Reset pulse signal, and high level of Set signal makes Gclk turn to high level. After a delay of 0.5 clock cycles, the Reset signal goes high causing Gclk to flip low, with the Gclk high lasting 0.5 clock cycles. After a further delay of 0.5 clock cycles, the Set signal high causes Gclk to flip high and Gclk low for 0.5 clock cycles. In this way a 50% duty cycle clock signal can be generated.

It will be appreciated that the process is completely identical for the case of generating clock signals of other duty cycles, except that the two pHs selected are different and will not be described again.

It will be appreciated that by configuring the Sel i 0 signal to transmit 2 specific PH signals to the CLK0 and CLK1 ports and then using DFF flip-flops, a clock signal having a multiple duty cycle of 1/n can be generated as desired using the circuit configurations shown in fig. 4 and 5. Theoretically, when n is equal to 10, the minimum duty cycle is equal to 10%, the maximum duty cycle is equal to 90%, and the adjustment step (i.e., the difference between adjacent adjustable duty cycles) is equal to 10%. When n is equal to 20, the minimum duty cycle is equal to 5%, the maximum duty cycle is equal to 95%, and the adjustment step size is equal to 5%. When n is equal to 40, the minimum duty cycle is equal to 2.5%, the maximum duty cycle is equal to 97.5%, and the adjustment step size is equal to 2.5%.

In summary, by adopting the scheme provided by the embodiment of the application, only by changing the value of Sel [ i:0], one duty cycle signal can be quickly switched to another duty cycle signal according to the design requirement, the DCA circuit can generate a clock signal with the duty cycle precisely equal to the set value, the adjustment range is very wide, the number of stages of N is larger, the adjustment step length is smaller, and the adjustment range is finer.

Based on the same inventive concept, the embodiment of the application also provides a chip, wherein the chip comprises the duty ratio adjustable circuit.

It should be noted that, the chip provided in the embodiment of the present application may be a computing chip such as a GPU (Graphic Processing Unit, graphics processor) chip, a CPU (Central Processing Unit ) chip, an AI processor chip, or a communication chip such as bluetooth, or a memory management chip, or a video processing chip, which is not limited in this embodiment of the present application.

Based on the same inventive concept, the embodiment of the application also provides electronic equipment, which comprises the chip.

Alternatively, the electronic device may be a module or a component that may be independently produced, such as a board card, a controller, etc. having the chip, or may be a device that directly provides services, such as a computer, a mobile phone, a server, etc., but is not limited thereto.

It can be further understood that the scheme provided by the embodiment of the application has very strong universality, and the scheme based on the embodiment of the application can be satisfied whether the scheme aims at a scene of generating a clock signal with a specific duty ratio by adjusting the duty ratio of the clock signal according to specific design requirements, a scene of correcting the clock signal when the clock signal is transmitted in a long distance, a scene of generating a clock signal with a high-precision specific duty ratio or a scene of fast switching for the clock signal with multiple duty ratios.

In the embodiments provided herein, it should be understood that the disclosed circuit may be implemented in other ways. The embodiments described above are merely illustrative, as some features may be omitted, or not employed.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity from another entity without necessarily requiring or implying any actual such relationship or order between such entities.

Herein, a plurality refers to two or more.

The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A duty cycle adjustable circuit, comprising:

a delay phase-locked loop circuit configured to receive an original clock signal and delay the original clock signal to generate N first clock signals having equal differences in phase; n is a positive integer greater than or equal to 2;

a duty cycle adjustment circuit electrically connected to the delay phase locked loop circuit and configured to receive a duty cycle selection signal and select two target first clock signals from the N first clock signals according to the duty cycle selection signal to generate a second clock signal according to the two target first clock signals; the second clock signal has a set duty cycle;

the delay locked loop circuit includes: an original clock signal input for receiving the original clock signal; the delay chain comprises a plurality of delay unit circuits which are sequentially connected with the input end of the original clock signal in series; the state machine is respectively connected with each delay unit circuit to adjust the delay value of each delay unit circuit; the phase detector is respectively connected with the signal input end of the delay unit circuit of the first stage, the signal output end of the delay unit circuit of the last stage and the state machine and is used for outputting a locking signal to the state machine when the phase difference between the signal input into the delay unit circuit of the first stage in the delay chain and the first clock signal output by the delay unit circuit of the last stage in the delay chain is one clock period;

2. The duty cycle adjustable circuit of claim 1, wherein the delay cell circuit comprises:

and the adjustable capacitor is connected with the state machine.

3. The duty cycle adjustable circuit of any one of claims 1-2, wherein the duty cycle adjustment circuit comprises:

the signal input end of the first multiplexer is respectively connected with the signal output end of each first clock signal in the delay phase-locked loop circuit, and the enabling end of the first multiplexer is configured to receive the duty ratio selection signal so that the first multiplexer can select two target first clock signals to output according to the duty ratio selection signal;

and the clock signal generating circuit is connected with the signal output end of the first multiplexer so as to generate the second clock signal according to the two target first clock signals.

4. A duty cycle adjustable circuit as claimed in claim 3, wherein the clock signal generation circuit comprises:

The signal input ends of the second multiplexer are respectively connected with the two signal output ends of the first multiplexer;

the clock signal input end of the trigger is connected with the signal output end of the second multiplexer, and the data output end of the trigger is connected with the data input end of the trigger through an inverter;

the enabling end of the second multiplexer is connected with the data input end of the trigger.

5. The duty cycle adjustable circuit of claim 4, wherein the duty cycle adjustment circuit further comprises:

a third multiplexer, one signal input of the third multiplexer being connected to the data output of the flip-flop, the other signal input of the third multiplexer being configured to receive the original clock signal;

the enable terminal of the third multiplexer is configured to receive an enable signal and the enable terminal of the flip-flop is also configured to receive the enable signal.

6. A duty cycle adjustable circuit as claimed in claim 3, wherein the clock signal generation circuit comprises:

the signal input end of the first pulse generating circuit is connected with one signal output end of the first multiplexer;

The signal input end of the second pulse generating circuit is connected with the other signal output end of the first multiplexer;

and the set port of the latch is connected with the signal output end of the first pulse generating circuit, and the reset port of the latch is connected with the signal output end of the second pulse generating circuit.

7. The duty cycle adjustable circuit of claim 6, wherein the duty cycle adjustment circuit further comprises:

a fourth multiplexer, one signal input of the fourth multiplexer being connected to the signal output of the latch, the other signal input of the fourth multiplexer being configured to receive the original clock signal, the enable of the fourth multiplexer being configured to receive an enable signal;

the set and reset ports of the latch are configured to receive the enable signal through an inverter.

8. A chip comprising a duty cycle adjustable circuit as claimed in any one of claims 1 to 7.

9. An electronic device comprising the chip of claim 8.