CN116566198A - Direct connection and power conversion dual-mode power optimization device and integrated control circuit - Google Patents
Direct connection and power conversion dual-mode power optimization device and integrated control circuit Download PDFInfo
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- CN116566198A CN116566198A CN202310827133.5A CN202310827133A CN116566198A CN 116566198 A CN116566198 A CN 116566198A CN 202310827133 A CN202310827133 A CN 202310827133A CN 116566198 A CN116566198 A CN 116566198A
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 124
- 238000005457 optimization Methods 0.000 title claims abstract description 18
- 238000001514 detection method Methods 0.000 claims description 33
- 238000009966 trimming Methods 0.000 claims description 15
- 230000000295 complement effect Effects 0.000 claims description 11
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
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- 230000008859 change Effects 0.000 claims description 7
- 238000004891 communication Methods 0.000 claims description 5
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 4
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- 230000001360 synchronised effect Effects 0.000 claims description 4
- 230000006872 improvement Effects 0.000 abstract description 2
- 238000012423 maintenance Methods 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 230000008439 repair process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000010248 power generation Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/66—Regulating electric power
- G05F1/67—Regulating electric power to the maximum power available from a generator, e.g. from solar cell
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/56—Power conversion systems, e.g. maximum power point trackers
Abstract
The invention discloses a direct connection and power conversion dual-mode power optimization device and an integrated control circuit, and relates to the technical field of photovoltaic power optimization and control circuits thereof. On one hand, the power circuit is provided with the direct current conversion circuit and the direct current switching circuit, so that the maximum power point tracking efficiency during power conversion is high and the power loss during direct current is low, on the other hand, the ASIC chip is provided with the mode control circuit and the logic control and driving circuit on the basis of a special power conversion control function, so that the power circuit is controlled by combining a pulse width modulation signal and a received mode signal, the power circuit is operated between a power conversion mode and a direct current mode, and when in use, the corresponding mode signal can be sent to the ASIC chip to realize mode maintenance and switching, thereby realizing the simplification of a control architecture and the improvement of control resolution.
Description
Technical Field
The disclosure relates to the technical field of photovoltaic power optimization and control circuits thereof, in particular to a direct-connection and power conversion dual-mode power optimization device and an integrated control circuit.
Background
Module-Level Power Electronics (MLPE) refers to Power Electronics devices that enable fine control of a single or several photovoltaic modules. Generally, the MLPE component is configured with a power optimizer that enables power conversion and Maximum Power Point Tracking (MPPT) of the individual photovoltaic components.
In the photovoltaic grid-connected power generation system, a plurality of MLPE components are mutually output and connected in series to form an MLPE photovoltaic group string, and the MLPE photovoltaic group string is connected into the inverter equipment of the later stage for further conversion and then is connected into a grid. In the traditional system, the inverter equipment at the later stage also bears the MPPT function of the photovoltaic string, and each component can operate at the maximum power point under the condition of good consistency of irradiation, temperature and performance. In fact, in more cases, the irradiation, temperature, performance, etc. of each component in the string of photovoltaic groups are not uniform, so that the independent MPPT of the MLPE components will promote the efficiency of photovoltaic power harvesting. However, the inductance, switches, etc. provided in the MLPE components will also increase power losses. Therefore, in the MLPE photovoltaic string, according to different conditions such as irradiation, temperature and performance, if part of the MLPE components can directly communicate the photovoltaic panel with the MLPE photovoltaic string, and the other MLPE components perform power conversion and MPPT, the efficiency of the system is further increased.
In the MLPE component, judging and confirming whether to operate in the through mode or the power conversion mode requires that the control chip can perform complex logic operation and accurate program control. The control chip of the traditional power optimizer carries out logic operation on the detected parameter signals to track the maximum power, but does not have the functions of parameter monitoring, complex logic judgment, communication and the like, and two modes of maintenance and switching judgment are difficult to realize. However, the control chip of the power optimizer adopts a digital architecture, and although parameter monitoring, complex logic judgment and communication can be realized, the resolution and performance of executing maximum power point tracking are difficult to meet the requirements.
Disclosure of Invention
In view of the problems existing in the prior art, the present invention aims to provide a power optimizing device and an integrated control circuit with two modes of direct connection and power conversion, which can realize the high resolution and high performance of the power optimizing device in the power conversion mode and low power loss in the direct connection mode, and the control circuit has the characteristics of simple structure, low cost, high performance and the like.
To achieve the above object, in a first aspect, the present invention provides a power optimizing apparatus comprising: the power circuit comprises a direct current conversion circuit and a direct current switching circuit; the direct current conversion circuit comprises an input port coupled to the photovoltaic module, an output port coupled to the MLPE photovoltaic string, a first switch, and a second switch; the first end of the first switch is connected to the positive electrode of the input port, the second end of the first switch is connected to the first end of the second switch, the second end of the second switch is connected to the negative electrode of the input port, and the intermediate port between the first switch and the second switch is directly or indirectly connected to the positive electrode of the output port; the through switch circuit comprises a third switch, a first end of the third switch is connected with the positive electrode of the input port, and a second end of the third switch is connected with the positive electrode of the output port; the ASIC chip comprises a current and voltage detection circuit, a multiplier, a maximum power point tracking circuit, a mode control circuit and a logic control and driving circuit, wherein the current and voltage detection circuit is used for collecting the voltage and the current of an input port or collecting the voltage and the current of an output port; the multiplier is used for multiplying the voltage and the current of the input port to obtain the input power of the direct current conversion circuit, or the multiplier is used for multiplying the voltage and the current of the output port to obtain the output power of the direct current conversion circuit; the maximum power point tracking circuit is used for tracking and determining the current maximum power according to the input power or the output power, determining a pulse width modulation signal according to the current maximum power and outputting the pulse width modulation signal to the logic control and driving circuit; the mode control circuit is used for generating corresponding signal states according to the received first mode signal and the received second mode signal and outputting the corresponding signal states to the logic control and driving circuit; the logic control and drive circuit is used for controlling the high-frequency on-off of the first switch and the second switch by utilizing the pulse width modulation signal when the first mode signal is input so as to enable the power circuit to operate in a power conversion mode, and is used for controlling at least the second switch to be disconnected when the second mode signal is input so as to enable the power circuit to operate in a direct-through mode.
The power optimizing device is optional, the logic control and driving circuit comprises a logic control circuit, a first driving unit, a second driving unit and a third driving unit, wherein the first driving unit is in driving connection with the first switch, the second driving unit is in driving connection with the second switch, and the third driving unit is in driving connection with the third switch; when the logic control circuit receives a first mode signal, the power circuit operates in a power conversion mode, the logic control circuit controls the high-frequency on-off of the first switch through the first driving unit by utilizing the pulse width modulation signal, controls the high-frequency on-off of the second switch through the second driving unit by utilizing a complementary signal of the pulse width modulation signal, and controls the disconnection of the third switch through the third driving unit; when the logic control circuit receives the second mode signal, the power circuit operates in a through mode, the logic control circuit controls the second switch to be disconnected through the second driving unit, and controls the third switch to be connected through the third driving unit.
The power optimizing device is optional, the logic control and driving circuit comprises a logic control circuit, a first driving unit and a second driving unit, the first driving unit is in driving connection with the first switch, and the second driving unit is in driving connection with the second switch; when the logic control circuit receives a first mode signal, the power circuit operates in a power conversion mode, the logic control circuit controls the high-frequency on-off of the first switch through the first driving unit by utilizing the pulse width modulation signal, and controls the high-frequency on-off of the second switch through the second driving unit by utilizing a complementary signal of the pulse width modulation signal; when the logic control circuit receives the second mode signal, the power circuit operates in a pass-through mode, and the logic control circuit controls the second switch to be disconnected through the second driving unit.
The power optimizing device is optional, the power circuit further comprises a signal generating circuit, the output end of the signal generating circuit is connected with the input end of the mode control circuit, and the signal generating circuit is provided with a trimming switch; and the signal generating circuit is correspondingly driven to generate a first mode signal or a second mode signal at the input end of the mode control circuit by controlling the turning-on or turning-off of the trimming switch.
The above power optimizing device may be further configured such that the on-resistance of the third switch is lower than the on-resistance of the first switch.
The power optimizing device is optional, and the current and voltage detecting circuit is used for collecting the voltage of the positive electrode of the input port, the voltage of the negative electrode of the input port and the voltage of the middle port; the current and voltage detection circuit is used for determining the current of the first switch according to the voltage of the positive electrode of the input port and the voltage of the middle port, determining the current of the second switch according to the voltage of the middle port and the voltage of the negative electrode of the input port, and adding the current of the first switch and the current of the second switch to determine the current of the output port; and the current-voltage detection circuit is used for determining the voltage of the output port according to the voltage of the positive electrode of the output port and the voltage of the negative electrode of the input port.
The power optimizing device is optional, and further comprises a local manager, wherein the local manager is used for acquiring a local current duty ratio during a power conversion mode, judging whether the current duty ratio exceeds a preset duty ratio threshold, if so, changing the input state of the mode control circuit to generate a second mode signal by the local manager, and if not, maintaining the input state of the mode control circuit to continuously generate a first mode signal by the local manager; the local manager is used for acquiring the duration time of the through mode and judging whether the duration time exceeds a time threshold value or not when the through mode is in the through mode, if so, the local manager changes the input loading of the mode control circuit to generate a first mode signal, and if not, the local manager maintains the input state of the mode control circuit to continuously generate a second mode signal; or the local manager is used for judging whether to acquire the signal or the instruction sent by the upper equipment through communication in the direct mode, if yes, the local manager changes the input loading of the mode control circuit to generate the first mode signal, and if no, the local manager maintains the input state of the mode control circuit to continuously generate the second mode signal.
To achieve the above object, in a second aspect, the present invention provides an integrated control circuit comprising an ASIC chip dedicated to controlling a power circuit including an input port for coupling to a photovoltaic cell, an output port for coupling to an MLPE string of photovoltaic groups, a first switch for coupling between the input port and the output port for power conversion, a second switch for coupling between the positive and negative of the output port for synchronous freewheeling, a third switch for shorting the input port and the output port when turned on, the ASIC chip including a current-voltage detection circuit for collecting the voltage and current of the input port, or collecting the voltage and current of the output port, a multiplier, a maximum power point tracking circuit, a mode control circuit, a logic control and drive circuit; the multiplier is used for multiplying the voltage and the current of the input port to obtain the input power of the direct current conversion circuit, or the multiplier is used for multiplying the voltage and the current of the output port to obtain the output power of the direct current conversion circuit; the maximum power point tracking circuit is used for tracking and determining the current maximum power according to the input power or the output power, determining a pulse width modulation signal according to the current maximum power and outputting the pulse width modulation signal to the logic control and driving circuit; the mode control circuit is used for generating corresponding signal states according to the received first mode signal and the received second mode signal and outputting the corresponding signal states to the logic control and driving circuit; the logic control and drive circuit is used for controlling the high-frequency on-off of the first switch and the second switch by utilizing the pulse width modulation signal when the first mode signal is input so as to enable the power circuit to operate in a power conversion mode, and is used for stopping controlling the first switch and the second switch by utilizing the pulse width modulation signal when the second mode signal is input so as to enable the power circuit to operate in a direct-through mode.
The integrated control circuit is optional, the logic control and driving circuit comprises a logic control circuit, a first driving unit, a second driving unit and a third driving unit, the first driving unit is in driving connection with the first switch, the second driving unit is in driving connection with the second switch, and the third driving unit is in driving connection with the third switch; when the logic control circuit receives a first mode signal, the power circuit operates in a power conversion mode, the logic control circuit controls the high-frequency on-off of the first switch through the first driving unit by utilizing the pulse width modulation signal, controls the high-frequency on-off of the second switch through the second driving unit by utilizing a complementary signal of the pulse width modulation signal, and controls the disconnection of the third switch through the third driving unit; when the logic control circuit receives the second mode signal, the power circuit operates in a through mode, the logic control circuit controls the second switch to be disconnected through the second driving unit, and controls the third switch to be connected through the third driving unit.
The integrated control circuit is optional, the logic control and driving circuit comprises a logic control circuit, a first driving unit and a second driving unit, the first driving unit is in driving connection with the first switch, and the second driving unit is in driving connection with the second switch; when the logic control circuit receives a first mode signal, the power circuit operates in a power conversion mode, the logic control circuit controls the high-frequency on-off of the first switch through the first driving unit by utilizing the pulse width modulation signal, and controls the high-frequency on-off of the second switch through the second driving unit by utilizing a complementary signal of the pulse width modulation signal; when the logic control circuit receives the second mode signal, the power circuit operates in a pass-through mode, and the logic control circuit controls the second switch to be disconnected through the second driving unit.
Compared with the prior art, the invention has the following beneficial effects:
(1) The power optimizing device of the invention, on one hand, the power circuit is provided with the direct current conversion circuit and the through switch circuit, the power optimizing device can independently operate in the power conversion mode or the through mode by controlling the operation of the direct current conversion circuit and the through switch circuit, the maximum power point tracking efficiency during power conversion is high, and the power loss during through is low. On the whole, be favorable to the cost reduction of photovoltaic power generation system to increase efficiency, can realize green energy-conservation, be convenient for photovoltaic power generation's popularization.
(2) The integrated control circuit is specially used for a photovoltaic power circuit, not only is provided with a current-voltage detection circuit, a multiplier and a maximum power point tracking circuit, but also can generate a pulse width modulation signal which is used for controlling the power circuit and can track the maximum power by utilizing detected electric parameters, and simultaneously is provided with a mode control circuit and a logic control and driving circuit, so that the power circuit is controlled to operate between a power conversion mode and a direct-connection mode by combining the pulse width modulation signal and a received mode signal.
(3) The integrated control circuit can collect voltage and current signals of the photovoltaic unit and the power circuit, obtain the power signal through the analog multiplier, and adjust the duty ratio of the pulse width modulation signal to realize the tracking of the maximum power point of the power generation assembly, avoid the analog-to-digital conversion and the subsequent operational amplification process, simplify peripheral devices, effectively reduce the cost and facilitate the improvement of the circuit integration level in the power optimization device; compared with the power optimization control of digital signals, the analog loop of the integrated control circuit omits the calculation time of a microprocessor and improves the response speed and the processing precision.
The invention is further described below with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic circuit diagram of a power optimizing apparatus according to a first embodiment of the present invention;
fig. 2 is a schematic circuit diagram of an integrated control circuit according to a first embodiment of the present invention.
FIG. 3 is a schematic circuit diagram of a power optimizing apparatus according to a second embodiment of the present invention;
fig. 4 is a schematic circuit diagram of an integrated control circuit according to a second embodiment of the present invention.
Detailed Description
For a better illustration of the objects, technical solutions and advantages of the present invention, the following detailed description of the present invention will be given with reference to the accompanying drawings and examples. The following examples illustrate the invention but are not intended to limit the scope thereof.
As shown in fig. 1 to 4, a power optimizing apparatus for a through and power conversion dual mode according to an embodiment of the present invention is provided. The power optimization device mainly comprises a power circuit 10 and an ASIC chip 20. The power circuit 10 performs a function of performing power conversion on the received photovoltaic unit, and provides the converted power to the MLPE photovoltaic string. ASIC chip 20 functions to control the operation of power circuit 10. It should be noted that the MLPE photovoltaic string refers to a plurality of photovoltaic modules connected in series, and each photovoltaic module is configured with the power optimizing device, that is, the MLPE photovoltaic string has the characteristics of power electronics of module level.
To achieve the object of the present invention, the power circuit 10 of the present embodiment is composed of two parts, namely, a dc conversion circuit 11 and a through switch circuit 12. The dc conversion circuit 11 plays a role in converting the input photovoltaic unit power to output to the MLPE photovoltaic string, and the through switch circuit 12 plays a role in bypassing the dc conversion circuit 11 and directly connecting the input photovoltaic unit power to the MLPE photovoltaic string. In detail, the dc conversion circuit 11 mainly includes an input port Vi, an output port Vo, a first switch M1, and a second switch M2. The input port Vi is for connection to the output of a photovoltaic unit, i.e. a photovoltaic power input as a power optimizing means. The output port Vo is for connection to an MLPE photovoltaic string, i.e. a photovoltaic power output as a power optimizing device. The first end of the first switch M1 is connected to the positive electrode of the input port Vi, the second end of the first switch M1 is connected to the first end of the second switch M2, the second end of the second switch M2 is connected to the negative electrode of the input port Vi, and the intermediate port between the first switch M1 and the second switch M2 is directly or indirectly connected to the positive electrode of the output port Vo. In other words, the dc conversion circuit 11 adopts a BUCK-type conversion topology structure, and performs BUCK power conversion by controlling the high frequency on/off of the first switch M1, and performs synchronous freewheeling in the conversion process by controlling the high frequency on/off of the second switch M2. The pass-through switch circuit 12 includes a third switch M3, a first end of the third switch M3 is connected to the positive electrode of the input port Vi, and a second end of the third switch M3 is connected to the positive electrode of the output port Vo. In other words, the third switch M3 is controlled to be turned on, so that the positive electrode of the input port Vi and the positive electrode of the output port Vo are shorted, i.e. the photovoltaic unit is directly connected to the MLPE photovoltaic string, and the power of the input port Vi is output at the output port Vo after the power of the first switch M1 and the second switch M2 is converted by controlling the third switch M3 to be turned off.
To control the power circuit 10, the asic chip 20 includes an internal power supply circuit 201, a reference voltage generation circuit 202, a current-voltage detection circuit 203, a multiplier 204, a maximum power point tracking circuit 205, a mode control circuit 206, and a logic control and drive circuit 210. In detail, the internal power supply circuit 201 is configured to supply power to the ASIC chip 20 by using the photovoltaic power of the input port Vi. The reference voltage generation circuit 202 is configured to generate a reference voltage and supply the reference voltage to the maximum power point tracking circuit 205 to determine the reference voltage of the pulse modulation signal. The current-voltage detection circuit 203 is configured to collect a voltage signal u_out and a current signal i_out that pass through the output port Vo of the conversion circuit. The multiplier 204 is configured to multiply the voltage signal u_out of the output port Vo collected by the current-voltage detection circuit 203 with the current signal i_out to obtain the input power of the dc conversion circuit 11. The maximum power point tracking circuit 205 is configured to determine a current maximum power according to the output power tracking, determine a pulse width modulation signal according to the current maximum power, and output the pulse width modulation signal to the logic control and driving circuit 210. The mode control circuit 206 is configured to generate corresponding signal states according to the received first mode signal and the received second mode signal, and input the generated signal states to the logic control and driving circuit 210. Logic control and drive circuit 210 combines the input pulse width modulated signal and the mode signal states to control power circuit 10 to operate between a power conversion mode and a pass-through mode. When the mode control circuit 206 receives the first mode signal, the logic control and driving circuit 210 controls the first switch M1 and the second switch M2 by using the pulse width modulation signal, and when the mode control circuit 206 receives the second mode signal, the logic control and driving circuit 210 directly controls the second switch M2 to be turned off.
It should be noted that, when the power optimizing device is determined to be in the power conversion mode, the input mode signal of the mode control circuit 206 of the ASIC chip 20 may be set to the first mode signal, and the third switch M3 is turned off, so that the ASIC chip 20 will control the power circuit 10 to perform power conversion and maximum power point tracking, and the logic control and driving circuit 210 will control the first switch M1 and the second switch M2 to be turned on and off at high frequency by using the pulse width modulation signal. When the power optimization device is determined to be in the pass-through mode, the input mode signal of the mode control circuit 206 of the ASIC chip 20 may be set to the second mode signal, and the third switch M3 is turned on, so that the logic control and driving circuit 210 will not control the first switch M1 and the second switch M2 to be turned on or off at high frequency, but control the second switch M2 of the dc conversion circuit 11 to be turned off.
Therefore, the ASIC chip 20 can generate the pulse width modulation signal capable of tracking the maximum power point and control the first switch M1 and the second switch M2 by using the detected electrical parameter, and the second switch M2 can be switched from the control state of high-frequency on-off to the off state by the set mode control circuit 206 and the logic control and driving circuit 210 during the pass-through mode of the ASIC chip 20, so that the electric leakage of the output port Vo of the dc conversion circuit 11 during the high-frequency on-off is avoided, and the pass-through switch circuit 12 can normally operate and switch to the pass-through mode.
It will be appreciated that in other embodiments according to the invention, the current-voltage detection circuit 203 may also be used to detect the voltage signal u_in and the current signal i_in of the input port Vi of the dc conversion circuit 11. Accordingly, the multiplier 204 is connected to the current-voltage detection circuit 203, and multiplies the voltage signal u_in of the input port Vi by the current signal i_in to obtain the output power of the power circuit 10. Accordingly, the maximum power point tracking circuit 205 will determine the current maximum power from the input power tracking.
In this embodiment, the local manager 30 is configured to confirm whether it is currently operating in the power conversion mode or the pass-through mode. Wherein the local manager 30 may send the first mode signal and the second mode signal to the mode control circuit 206 of the ASIC chip 20. When the local manager 30 confirms that it should currently operate in the power conversion mode according to the judgment condition, a first mode signal is transmitted to the mode control circuit 206 of the ASIC chip 20. When the local manager 30 confirms that it should currently operate in the pass-through mode according to the judgment condition, a second mode signal is transmitted to the mode control circuit 206 of the ASIC chip 20. The local manager 30 adopts a digital architecture, has multiple functions of logic operation, program judgment, communication and the like, can complete dual-mode confirmation of the embodiment, and can expand other management functions.
It can be seen that the power optimizing apparatus of the present embodiment can realize not only the dual modes of power conversion and pass-through by using the simple control structure of the ASIC chip 20, but also the dual mode confirmation and the judgment and management of other complicated situations such as the rapid disconnection at the component level by using the local manager 30.
In this embodiment, in order to acquire the current signal i_out of the output port Vo, on one hand, the current-voltage detection circuit 203 is connected to the positive electrode of the input port Vi and detects the voltage V1 of the positive electrode of the input port Vi; meanwhile, the current-voltage detection circuit 203 is connected to the intermediate port between the first switch M1 and the second switch M2, and detects the voltage V2 of the intermediate port; the current-voltage detection circuit 203 divides the voltage difference between the positive voltage V1 of the output port Vo and the intermediate port voltage V2 by the on-resistance value of the first switch M1. The current I1 of the first switch M1 can be calculated. On the other hand, the current-voltage detection circuit 203 is also connected to the ground terminal, that is, the negative electrodes of the input port Vi and the output port Vo, and detects the voltage V3 at the ground terminal; the current/voltage detection circuit 203 divides the voltage difference between the intermediate port voltage V2 and the ground voltage V3 by the on-resistance of the second switch M2, so as to calculate the current I2 of the second switch M2. Further, the current-voltage detection circuit 203 adds the current I1 of the first switch M1 and the current I2 of the second switch M2 to obtain the current signal i_out of the output port Vo. In order to obtain the voltage signal u_out of the output port Vo, the current-voltage detection circuit 203 is further connected to the positive electrode of the output port Vo, and outputs the voltage V4 of the positive electrode of the output port Vo, and calculates the voltage difference between the voltage V4 of the positive electrode of the output port Vo and the voltage V3 of the ground terminal (i.e., the negative electrode of the output port Vo), so as to obtain the current signal u_out of the output port Vo. The current-voltage detection circuit 203 may collect the electrical parameter signal of the dc conversion circuit 11, and obtain the processed signal by using an analog operation method, without performing processing such as analog-to-digital conversion and subsequent signal amplification, so as to implement the power conversion and maximum power point tracking functions with simple structure and high stability.
In the present embodiment, regarding the structure of the power circuit 10, in detail, the dc conversion circuit 11 is a buck type, and has an input port Vi, an output port Vo, a first switch M1, a second switch M2, an inductance L, an input capacitor C1, an output capacitor C2, and a bypass diode D1. The input port Vi of the dc conversion circuit 11 may be used to couple to an output terminal of the photovoltaic unit, and the output port Vo of the dc conversion circuit 11 may be used to couple to the MLPE photovoltaic string. The first end of the first switch M1 is connected to the positive electrode of the input port Vi, the second end of the first switch M1 is connected to the first end of the second switch M2, the second end of the second switch M2 is connected to the negative electrode of the output port Vo, the negative electrode of the input port Vi and the negative electrode of the output port Vo of the direct current conversion circuit 11 are respectively connected to the grounding end, an intermediate port between the first switch M1 and the second switch M2 is connected to the first end of the inductor L, and the second end of the inductor L is connected to the positive electrode of the output port Vo. Two ends of the input capacitor C1 are respectively connected between the positive electrode and the negative electrode of the input port Vi, and two ends of the output capacitor C2 are respectively connected between the positive electrode and the negative electrode of the output port Vo. The anode of the bypass diode D1 is connected to the cathode of the output port Vo, and the cathode of the bypass diode D1 is connected to the output port Vo. The first switch M1 can be controlled by using a pulse modulation signal, so that the first switch M1 can be switched on and off at high frequency, and the inductor L can be charged and discharged at high frequency, thereby realizing power conversion and maximum power point tracking. The second switch M2 may be controlled by a complementary signal of the pulse modulation signal, and the second switch M2 may also be turned on and off at a high frequency. The second switch M2 is maintained to be turned off during the on period of the first switch M1, and conversely, the second switch M2 is maintained to be turned on during the off period of the first switch M1, thereby achieving the effect of synchronous freewheel.
In one embodiment, the power optimization device includes three parts, namely a power circuit 10, an ASIC chip 20 and a local manager 30. The local manager 30 is configured to determine what mode signal is to be transmitted to the ASIC chip 20, and specifically, the duty ratio threshold d_ref, the through mode duration t_ref, and the mode change command are preset in the local manager 30. The local manager 30 may obtain an electrical parameter related to the current duty cycle of the dc link circuit 11, obtain the duration t of the power circuit 10 in the pass-through mode, and communicatively obtain a signal or instruction related to a change in the mode setting sent by a subsequent stage inverter device, such as a photovoltaic inverter.
At initial start-up, the local manager 30 defaults to sending a first mode signal to the ASIC chip 20 and the power circuit 10 operates in a power conversion mode.
When the power circuit 10 is operating in the power conversion mode, the local manager 30 determines whether to switch from transmitting the first mode signal to the ASIC chip 20 to transmitting the second mode signal to the ASIC chip 20. Specifically, the local manager 30 detects the voltage u_in and the output voltage u_out of the input port Vi of the dc conversion circuit 11, and calculates the current duty ratio D of the dc conversion circuit 11 from u_out/u_in based on the characteristics of the BUCK dc conversion circuit 11. The local manager 30 compares the current duty cycle D with a preset duty cycle threshold d_ref, and if the current duty cycle D is smaller than the duty cycle threshold d_ref, the local manager 30 transmits a first mode signal to the ASIC chip 20 (i.e., maintains the power circuit 10 in the power conversion mode), and if the current duty cycle D is equal to or greater than the duty cycle threshold d_ref, the local manager 30 transmits a second mode signal to the ASIC chip 20 (i.e., switches the power circuit 10 to the pass-through mode).
When the power circuit 10 is operating in the pass-through mode, the local manager 30 determines whether to switch from sending the second mode signal to the ASIC chip 20 to sending the first mode signal to the ASIC chip 20. The condition of the judgment may be based on whether the duration t of the through mode exceeds a preset time threshold t_ref or whether a mode change instruction of the subsequent-stage conversion apparatus is received. One specific way may be: if the pass-through mode duration t is less than the time threshold t_ref and no mode change instruction is received, then the local manager 30 sends a second mode signal to the ASIC chip 20 (i.e., maintains the power circuit 10 in pass-through mode); if the pass-through mode duration t is less than the time threshold t_ref and a mode change instruction is received, or if the mode change instruction is not received and the pass-through mode duration t is equal to or greater than the time threshold t_ref, the local manager 30 sends a first mode signal (i.e., switches the power circuit 10 to a power conversion mode) to the ASIC chip 20.
For ease of understanding, the MLPE photovoltaic string described in this embodiment is connected to the DC/DC conversion front stage of the photovoltaic inverter, by way of illustration and not limitation. The photovoltaic inverter can control the voltage of the input side of the DC/DC conversion front stage to rise, and the voltage of the MLPE photovoltaic group string also rises, so that the voltage signal U_out of the output port Vo of the direct current conversion circuit 11 in each MLPE component rises. Due to differences in irradiation, ambient temperature, photovoltaic efficiency, etc., there is a 3% operational variability of each MLPE component 100 in the MLPB photovoltaic string. In other words, the current maximum power of each MLPE component has a range variance of about 3%. The power optimization device of the embodiment is configured in a photovoltaic panel to form an MLPE component. 30 MLPE components are arranged in the MLPE photovoltaic group string.
The above table is an example, and in state a, the MLPE photovoltaic string is set at 1200V. Each MLPE component in the group string sets the output voltage u_out of the dc conversion circuit 11 to be within a range of 40±0.6v according to the local maximum power point. Meanwhile, the environmental difference has less influence on the output voltage of the photovoltaic panel, and thus the input voltage u_in of the dc conversion circuit 11 in each MLPE component will be set at approximately 45V quite. Further, the dc conversion circuit 11 in each MLPE component has an operating duty ratio D within a range of 0.889±0.03, each local manager 30 will send a first mode signal according to D < d_ref, and the power circuit 10 is set in the power conversion mode. Thus, by controlling the input side voltage rise of the DC/DC conversion pre-stage, the output voltage u_out and the duty cycle D can be caused to rise, thereby operating part of the MLPE component in the pass-through mode. In state b, the MLPE string is set at 1290V in an ascending fashion. The input voltage U_in of each MLPE device is still set at 45V, while each MLPE device rises to a range of 43+ -0.6V with the MLPE photovoltaic string. Further, the operation duty ratio D of the dc conversion circuit 11 in each MLPE component is distributed within a range of 0.956±0.03. Thus, the local manager 30 will determine that D < d_ref changes the mode signal and send the first mode signal for the MLPE component having a duty cycle in the range of [0.941,0.97), and then the ASIC chip 20 of this part of the MLPE component controls the power circuit 10 to remain in the power conversion mode; the local manager 30 will determine that D.gtoreq.D_ref changes the mode signal and send the second mode signal for the MLPE component having a duty cycle in the range of [0.97,0.985], and then the ASIC chip 20 of this portion of the MLPE component controls the power circuit 10 to switch to pass-through mode.
It follows that with the regulation of the input side voltage by the subsequent stage of the conversion device, a preset target number of MLPE components can be made to operate in the pass-through mode. As can be seen from the above, in the pass-through mode, the first switch M1 and the inductor L will not consume photovoltaic power any more, thereby achieving low power consumption. In the power conversion mode, the pulse width modulation signal is directly calculated and determined by an electric parameter signal of the direct conversion circuit, so that high efficiency is realized. It should be noted that the present invention utilizes the ASIC chip 20 with simple structure, low cost and high control resolution to achieve the above-mentioned purposes of low power consumption and high efficiency.
Regarding the generation of the first mode signal and the second mode signal at the mode control circuit 206, in the present embodiment, the power circuit 10 further includes the signal generation circuit 13. Specifically, the signal generating circuit 13 includes an R1 resistor and a trimming switch M4. The ASIC chip 20 is provided with a Mode terminal and a VDD terminal. The second end of the trimming switch M4 is connected to the grounding end of the direct current conversion circuit, and the first end of the trimming switch M4 is connected to one end of the R1 resistor. The other end of the R1 resistor is used as an output terminal of the signal generating circuit and is connected to an input terminal of the Mode control circuit 206, i.e., a Mode terminal of the ASIC chip 20. Meanwhile, the other end of the R1 resistor is connected to the VDD terminal through the R2 resistor. The R2 resistor is connected to the ground terminal through a capacitor so that the VDD terminal has a high level voltage. When the trimming switch M4 is turned off, the VDD terminal, the R2 resistor, the R1 resistor and the Mode terminal are connected, and the R1 resistor and the ground terminal are not connected, the Mode control circuit 206 obtains the high level input of the VDD terminal, i.e. receives the first Mode signal. When the trimming switch M4 is turned on, the resistor R1 and the ground terminal are connected, and the mode control circuit 206 obtains a low-level input of the ground terminal, i.e. receives the second mode signal. Further, the local manager 30 is connected to the control end of the repair switch M4, and if the local manager 30 determines that the power conversion mode is currently supposed to be the power conversion mode, the repair switch M4 is controlled to be turned off, and if the local manager 30 determines that the power conversion mode is currently supposed to be the pass-through mode, the repair switch M4 is controlled to be turned on.
First embodiment
As shown in fig. 1, there is illustrated a power optimizing apparatus according to a first embodiment of the present invention, which includes three parts of a power circuit 10, an ASIC chip 20, and a local manager 30. As shown in fig. 2, an integrated control circuit according to a first embodiment of the present invention is configured as the ASIC chip 20 described above.
In detail, the power circuit 10 is composed of a dc conversion circuit 11 and a through switch circuit 12. The dc conversion circuit 11 includes an input port Vi, an output port Vo, a first switch M1, a second switch M2, an inductance L, an input capacitance C1, an output capacitance C2, and a bypass diode D1. The pass-through switch circuit 12 includes a third switch M3. The first end of the first switch M1 is connected to the positive electrode of the input port Vi, the second end of the first switch M1 is connected to the first end of the second switch M2, the second end of the second switch M2 is connected to the negative electrode of the output port Vo, the negative electrode of the input port Vi and the negative electrode of the output port Vo of the dc conversion circuit 11 are respectively connected to the ground terminal, an intermediate port between the first switch M1 and the second switch M2 is connected to one end of the inductor L, and the other end of the inductor L is connected to the positive electrode of the output port Vo. The first end of the third switch M3 is connected to the positive electrode of the input port Vi, and the second end of the third switch M3 is connected to the positive electrode of the output port Vo.
In detail, the ASIC chip 20 includes an internal power supply circuit 201, a reference voltage generation circuit 202, a current-voltage detection circuit 203, a multiplier 204, a maximum power point tracking circuit 205, a mode control circuit 206, a logic control circuit 214, a first driving unit 211, a second driving unit 212, and a third driving unit 213. The ASIC chip 20 is provided with a VCC terminal, a VDD terminal, a Switch-H terminal, a Switch-L terminal, a Vout terminal, an AGND terminal, a DR-driver terminal, an HD-driver terminal, an LD-driver terminal, and a Mode terminal. The VCC terminal is externally connected to the input port Vi of the dc converter circuit 11, and the VCC terminal is internally connected to the internal power supply circuit 201, the reference voltage generating circuit 202, and the VDD terminal. The VDD terminal is externally connected to the ground terminal via the R2 resistor and capacitor to generate the reference voltage u_ref in the reference voltage generating circuit 202. Meanwhile, the reference voltage generating circuit 202 is connected to the maximum power point tracking circuit 205 to determine a reference voltage u_ref required for the generated pulse width modulated signal.
Specifically, the Switch-H terminal is externally used for connecting to the positive electrode of the input port Vi of the dc conversion circuit 11, the Switch-L terminal is externally used for connecting to the intermediate port between the first Switch M1 and the second Switch M2, the Vout terminal is externally used for connecting to the positive electrode of the output port Vo of the dc conversion circuit 11, and the AGND terminal is externally connected to the ground terminal of the dc conversion circuit 11. The Switch-H terminal, switch-L terminal, vout terminal and AGND terminal are connected to the current/voltage detection circuit 203 in pairs, respectively. On the other hand, the current/voltage detection circuit 203 determines the voltage difference of the first Switch M1 according to the Switch-H terminal voltage V1 and the Switch-L terminal voltage V2, and calculates the current I1 of the first Switch M1 according to the voltage difference of the first Switch M1 and the on-resistance value (preset constant value) of the first Switch M1. Meanwhile, the current-voltage detection circuit 203 determines the voltage difference of the second Switch M2 according to the Switch-L terminal voltage V2 and the ground terminal voltage V3, and then calculates the second Switch M2 current I2 according to the voltage difference of the second Switch M2 and the on-resistance value (preset constant value) of the second Switch M2. Finally, the current I1 of the first switch M1 and the current I2 of the second switch M2 of the current-voltage detection circuit 203 are summed to obtain an output current i_out of the dc conversion circuit 11, and are provided to the multiplier 204. On the other hand, the current-voltage detection circuit 203 determines the output voltage u_out of the dc conversion circuit 11 from the difference between the Vout terminal voltage V4 and the ground terminal voltage V3, and supplies the determined output voltage u_out to the multiplier 204. The multiplier 204 calculates an output power p_out from the output current i_out and the output voltage u_out of the dc conversion circuit 11, and supplies the output power p_out to the maximum power point tracking circuit 205. The maximum power point tracking circuit 205 determines the pulse width modulation signal from the output power p_out and supplies the pulse width modulation signal to the logic control circuit 214, and determines the output power p_out required for the generated pulse width modulation signal.
The Mode end is connected to the ground end of the dc conversion circuit 11 through the resistor of the external diameter R1 and the trimming switch M4. The Mode terminal pair is connected to the Mode control circuit 206 to send the first Mode signal or the second Mode signal to the Mode control circuit 206. The mode control circuit 206 is coupled to the logic control circuit 214 to output a corresponding signal state thereto.
The maximum power point tracking circuit 205 and the mode control circuit 206 are connected to the input side of the logic control circuit 214, and the first driving unit 211, the second driving unit 212 and the third driving unit 213 are connected to the output side of the logic control circuit 214. The first driving unit 211 is connected to the external first switch M1 through the HD-driver terminal, the second driving unit 212 is connected to the external second switch M2 through the LD-driver terminal, and the third driving unit 213 is connected to the external third switch M3 through the DR-driver terminal. In other words, the ASIC chip 20 controls not only the dc conversion circuit 11 but also the through switch circuit 12.
When the trimming switch M4 is in an off state, the Mode end of the ASIC chip 20 is connected to the VDD end, the Mode control circuit 206 receives the high-level signal (i.e., the first Mode signal) and sends a corresponding signal state to the logic control circuit 214, the logic control circuit 214 controls the high-frequency on-off of the first switch M1 through the first driving unit 211 by using the pulse width modulation signal, controls the high-frequency on-off of the second switch M2 through the second driving unit 212 by using a signal complementary to the pulse width modulation signal, and controls the third switch M3 to maintain on through the third driving unit 213, so that the power circuit 10 operates in the power conversion Mode.
When the trimming switch M4 is in a conducting state, the Mode end of the ASIC chip 20 is connected to the ground, the Mode control circuit 206 receives the low-level signal (i.e., the second Mode signal) and sends a corresponding signal state to the logic control circuit 214, and the logic control circuit 214 controls the third switch M3 to be turned on via the third driving unit 213 and controls the second switch M2 to be turned off via the second driving unit 212 and controls the first switch M1 to be turned on or off via the first driving unit 211 according to the signal state and the pulse width modulation signal, so that the power circuit 10 operates in the pass-through Mode.
It can be seen that the integrated control circuit of the present embodiment can control the power circuit 10 to operate in both power conversion and pass-through modes by combining the pwm signal and the mode signal.
Second embodiment
As shown in fig. 3, a power optimizing apparatus according to a second embodiment of the present invention is illustrated, and includes three parts of a power circuit 10, an ASIC chip 20, and a local manager 30. As shown in fig. 4, an integrated control circuit according to a second embodiment of the present invention is configured as the ASIC chip 20 described above. In the second embodiment, the power circuit 10 is composed of the dc conversion circuit 11 and the through switch circuit 12 of each of the above embodiments. The direct current conversion circuit 11 includes an input port Vi, a first switch M1, a second switch M2, and an output port Vo. The ASIC chip 20 includes an internal power supply circuit 201, a reference voltage generation circuit 202, a current-voltage detection circuit 203, a multiplier 204, a maximum power point tracking circuit 205, a mode control circuit 206, a logic control circuit 214, a first driving unit 211, and a second driving unit 212. The ASIC chip 20 is provided with a VCC terminal, a VDD terminal, a Switch-H terminal, a Switch-L terminal, a Vout terminal, an AGND terminal, an HD-driver terminal, an LD-driver terminal, and a Mode terminal. The Mode terminal of the ASIC chip 20 is connected to the ground terminal of the dc conversion circuit 11 via the R1 resistor and the trimming switch.
In the second embodiment, the ASIC chip 20 does not include the third driving unit 213 and the HD-driver side, as compared to the first embodiment. The ASIC chip 20, in use, no longer controls the third switch M3 of the power circuit 10. The output terminal of the local manager 30 is connected to the control terminal of the trimming switch M4, and the output terminal of the local manager 30 is also connected to the control terminal of the third switch M3. In the power conversion mode, the local manager 30 will control the repair switch M4 to be turned off, the ASIC chip 20 will receive the first mode signal, the logic control and driving circuit 210 will control the first switch M1 to be turned on and off at high frequency by using the pulse width modulation signal, and the second switch M2 to be turned on and off at high frequency by using the signal complementary to the pulse width modulation signal; at the same time, the local manager 30 will also control the third switch M3 to be turned off, thereby controlling the power circuit 10 to perform power conversion and maximum power point tracking. In the pass-through mode, the local manager 30 will control the repair switch M4 to be turned on, the ASIC chip 20 will receive the second mode signal, the logic control and driving circuit 210 will control the first switch M1 to be turned on and off, and the second switch M2 to be turned off; at the same time, the local manager 30 will also control the third switch M3 to be turned on, so as to control the power circuit 10 to directly connect the photovoltaic unit and the MLPE photovoltaic string.
It can be seen that the integrated control circuit of the present embodiment can be further simplified and is only used for controlling the dc conversion circuit 11 of the power circuit 10. The through switch circuit 12 of the power circuit 10 is controlled along with the local manager 30 controlling the trimming switch M4. It should be noted that, when the integrated control circuit receives the second mode signal, it controls the disconnection of the second switch M2, so as to avoid the electric leakage of the output port Vo of the dc conversion circuit 11 caused by the high-frequency conduction of the second switch M2, which is a key ring for realizing the through mode.
In the above embodiments, it can be understood that, in one scheme, the ASIC chip 20 can control the first switch M1 to be turned on in the through mode, and then the first switch M1 and the third switch M3 are connected in parallel, so as to further reduce the loss of the photovoltaic power in the through mode. In a corresponding further variant, the ASIC chip 20 can control the first switch M1 to be switched off in the pass-through mode, and the input port Vi and the output port Vo are connected only by the third switch M3. This will allow the first switch M1 to be able to pause operation in the pass-through mode. For the former scheme, the logic control and driving circuit 210 may set and fix the pwm signal at 100% in the pass mode, so that the first switch M1 will be continuously turned on and the second switch M2 will be continuously turned off.
In the above embodiments, regarding the power conversion mode and the pass-through mode, in detail, the first switch M1, the second switch M2, and the third switch M3 are all MOSFET switching transistors. The third switch M3 of the power circuit 10 may be a resistor with a lower on-resistance, and the first switch M1 may be a resistor with a higher on-resistance. Generally, to meet the requirements of turning off and high frequency on-off, the on-resistance of the first switch M1 will be limited to a high level. The third switch M3 does not need to operate in a high-frequency on-off state, and the loss of power conversion can be further reduced by adopting a lower on-resistance value.
Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
The foregoing embodiments have described primarily the basic principles, principal features and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present invention, and various changes and modifications may be made without departing from the spirit and scope of the invention, which is defined in the appended claims.
Claims (10)
1. A power optimization apparatus, comprising: an ASIC chip (20) and a power circuit (10), the power circuit (10) comprising a DC conversion circuit (11) and a DC switch circuit (12);
the direct current conversion circuit (11) comprises an input port (Vi) coupled to a photovoltaic module, an output port (Vo) coupled to an MLPE photovoltaic string, a first switch (M1), and a second switch (M2); the first end of the first switch (M1) is connected to the positive electrode of the input port (Vi), the second end of the first switch (M1) is connected to the first end of the second switch (M2), the second end of the second switch (M2) is connected to the negative electrode of the input port (Vi), and the intermediate port between the first switch (M1) and the second switch (M2) is directly or indirectly connected to the positive electrode of the output port (Vo);
the through switch circuit (12) comprises a third switch (M3), a first end of the third switch (M3) is connected with the positive electrode of the input port (Vi), and a second end of the third switch (M3) is connected with the positive electrode of the output port (Vo);
the ASIC chip (20) comprises a current-voltage detection circuit (203), a multiplier (204), a maximum power point tracking circuit (205), a mode control circuit (206), a logic control and drive circuit (210),
The current and voltage detection circuit (203) is used for collecting the voltage and the current of the input port (Vi) or collecting the voltage and the current of the output port (Vo);
the multiplier (204) is used for multiplying the voltage and the current of the input port (Vi) to obtain the input power of the direct current conversion circuit (11), or the multiplier (204) is used for multiplying the voltage and the current of the output port (Vo) to obtain the output power of the direct current conversion circuit (11);
the maximum power point tracking circuit (205) is used for tracking and determining the current maximum power according to the input power or the output power, determining a pulse width modulation signal according to the current maximum power and outputting the pulse width modulation signal to the logic control and driving circuit (210);
the mode control circuit (206) is used for generating corresponding signal states according to the received first mode signal and the received second mode signal and outputting the corresponding signal states to the logic control and driving circuit (210);
the logic control and driving circuit (210) is used for controlling the high-frequency on-off of the first switch (M1) and the second switch (M2) by utilizing the pulse width modulation signal when the first mode signal is input so as to enable the power circuit (10) to operate in a power conversion mode, and is used for controlling at least the second switch (M2) to be turned off when the second mode signal is input so as to enable the power circuit (10) to operate in a through mode.
2. A power optimization device according to claim 1, characterized in that the logic control and driving circuit (210) comprises a logic control circuit (214), a first driving unit (211), a second driving unit (212) and a third driving unit (213), the first driving unit (211) being drivingly connected to the first switch (M1), the second driving unit (212) being drivingly connected to the second switch (M2), the third driving unit (213) being drivingly connected to the third switch (M3);
when the logic control circuit (214) receives the first mode signal, the power circuit (10) operates in a power conversion mode, the logic control circuit (214) controls the high-frequency on-off of the first switch (M1) through the first driving unit (211) by utilizing the pulse width modulation signal, controls the high-frequency on-off of the second switch (M2) through the second driving unit (212) by utilizing the complementary signal of the pulse width modulation signal, and controls the disconnection of the third switch (M3) through the third driving unit (213);
when the logic control circuit (214) receives the second mode signal, the power circuit (10) operates in the pass-through mode, the logic control circuit (214) controls the second switch (M2) to be turned off through the second driving unit (212), and controls the third switch (M3) to be turned on through the third driving unit (213).
3. A power optimization device according to claim 1, characterized in that the logic control and driving circuit (210) comprises a logic control circuit (214), a first driving unit (211) and a second driving unit (212), the first driving unit (211) being drivingly connected to the first switch (M1), the second driving unit (212) being drivingly connected to the second switch (M2);
when the logic control circuit (214) receives the first mode signal, the power circuit (10) operates in a power conversion mode, the logic control circuit (214) controls the high-frequency on-off of the first switch (M1) through the first driving unit (211) by utilizing the pulse width modulation signal, and controls the high-frequency on-off of the second switch (M2) through the second driving unit (212) by utilizing the complementary signal of the pulse width modulation signal;
when the logic control circuit (214) receives the second mode signal, the power circuit (10) operates in the pass-through mode, and the logic control circuit (214) controls the second switch (M2) to be turned off through the second driving unit (212).
4. A power optimization device according to claim 1, characterized in that the power circuit (10) further comprises a signal generation circuit (13), the output of the signal generation circuit (13) being connected to the input of the mode control circuit (206), the signal generation circuit (13) being provided with a trimming switch (M4); and the signal generating circuit (13) is correspondingly driven to generate a first mode signal or a second mode signal at the input end of the mode control circuit by controlling the on or off of the trimming switch (M4).
5. A power optimizing device according to claim 1, characterized in that the on-resistance of the third switch (M3) is configured to be lower than the on-resistance of the first switch (M1).
6. A power optimization device according to claim 1, characterized in that the current-voltage detection circuit (203) is configured to collect the voltage at the positive pole of the input port (Vi), the voltage at the negative pole of the input port (Vi) and the voltage at the intermediate port;
the current-voltage detection circuit (203) is configured to determine a current of the first switch (M1) according to a voltage of a positive electrode of the input port (Vi) and a voltage of a middle port, determine a current of the second switch (M2) according to the voltage of the middle port and the voltage of a negative electrode of the input port (Vi), and add the current of the first switch (M1) and the current of the second switch (M2) to determine a current of the output port (Vo); the method comprises the steps of,
the current-voltage detection circuit (203) is configured to determine a voltage of the output port (Vo) according to a voltage of the positive electrode of the output port (Vo) and a voltage of the negative electrode of the input port (Vi).
7. The power optimization apparatus of claim 1, further comprising a local manager (30), wherein the local manager (30) is configured to obtain a local current duty cycle during the power conversion mode, determine whether the current duty cycle exceeds a preset duty cycle threshold, if so, change an input state of the mode control circuit (206) to generate the second mode signal, and if not, maintain the input state of the mode control circuit (206) to generate the first mode signal continuously by the local manager (30);
The local manager (30) is used for acquiring the duration of the through mode and judging whether the duration exceeds a time threshold value or not when the through mode is adopted, if yes, the local manager (30) changes the input loading of the mode control circuit (206) to generate a first mode signal, and if no, the local manager (30) maintains the input state of the mode control circuit (206) to continuously generate a second mode signal; or, the local manager (30) is configured to determine whether to acquire a signal or an instruction sent by the upper device via communication during the pass-through mode, if so, the local manager (30) changes the input loading of the mode control circuit (206) to generate the first mode signal, and if not, the local manager (30) maintains the input state of the mode control circuit (206) to continuously generate the second mode signal.
8. An integrated control circuit comprising an ASIC chip (20) dedicated to controlling a power circuit (10), the power circuit (10) comprising an input port (Vi) for coupling to a photovoltaic cell, an output port (Vo) for coupling to a string of MLPE photovoltaic groups, a first switch (M1) for coupling between the input port (Vi) and the output port (Vo) for power conversion, a second switch (M2) for coupling between the positive and negative of the output port (Vo) for synchronous freewheeling, a third switch (M3) for shorting the input port (Vi) and the output port (Vo) when conducting, characterized in that the ASIC chip (20) comprises a current-voltage detection circuit (203), a multiplier (204), a maximum power point tracking circuit (205), a mode control circuit (206), a logic control and drive circuit (210),
The current and voltage detection circuit (203) is used for collecting the voltage and the current of the input port (Vi) or collecting the voltage and the current of the output port (Vo);
the multiplier (204) is used for multiplying the voltage and the current of the input port (Vi) to obtain the input power of the direct current conversion circuit (11), or the multiplier (204) is used for multiplying the voltage and the current of the output port (Vo) to obtain the output power of the direct current conversion circuit (11);
the maximum power point tracking circuit (205) is used for tracking and determining the current maximum power according to the input power or the output power, determining a pulse width modulation signal according to the current maximum power and outputting the pulse width modulation signal to the logic control and driving circuit (210);
the mode control circuit (206) is used for generating corresponding signal states according to the received first mode signal and the received second mode signal and outputting the corresponding signal states to the logic control and driving circuit (210);
the logic control and driving circuit (210) is used for controlling the high-frequency on-off of the first switch (M1) and the second switch (M2) by utilizing the pulse width modulation signal when the first mode signal is input so as to enable the power circuit (10) to operate in a power conversion mode, and is used for stopping controlling the first switch (M1) and the second switch (M2) by utilizing the pulse width modulation signal when the second mode signal is input so as to enable the power circuit (10) to operate in a direct-through mode.
9. The integrated control circuit of claim 8, wherein the logic control and drive circuit (210) comprises a logic control circuit (214), a first drive unit (211), a second drive unit (212), and a third drive unit (213),
the first driving unit (211) is in driving connection with the first switch (M1), the second driving unit (212) is in driving connection with the second switch (M2), and the third driving unit (213) is in driving connection with the third switch (M3);
when the logic control circuit (214) receives the first mode signal, the power circuit (10) operates in a power conversion mode, the logic control circuit (214) controls the high-frequency on-off of the first switch (M1) through the first driving unit (211) by utilizing the pulse width modulation signal, controls the high-frequency on-off of the second switch (M2) through the second driving unit (212) by utilizing the complementary signal of the pulse width modulation signal, and controls the disconnection of the third switch (M3) through the third driving unit (213);
when the logic control circuit (214) receives the second mode signal, the power circuit (10) operates in the pass-through mode, the logic control circuit (214) controls the second switch (M2) to be turned off through the second driving unit (212), and controls the third switch (M3) to be turned on through the third driving unit (213).
10. The integrated control circuit of claim 8, wherein the logic control and drive circuit (210) comprises a logic control circuit (214), a first drive unit (211), and a second drive unit (212),
the first driving unit (211) is in driving connection with the first switch (M1), and the second driving unit (212) is in driving connection with the second switch (M2);
when the logic control circuit (214) receives the first mode signal, the power circuit (10) operates in a power conversion mode, the logic control circuit (214) controls the high-frequency on-off of the first switch (M1) through the first driving unit (211) by utilizing the pulse width modulation signal, and controls the high-frequency on-off of the second switch (M2) through the second driving unit (212) by utilizing the complementary signal of the pulse width modulation signal;
when the logic control circuit (214) receives the second mode signal, the power circuit (10) operates in the pass-through mode, and the logic control circuit (214) controls the second switch (M2) to be turned off through the second driving unit (212).
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| CN202310827133.5A CN116566198A (en) | 2023-07-07 | 2023-07-07 | Direct connection and power conversion dual-mode power optimization device and integrated control circuit |
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| CN202310827133.5A CN116566198A (en) | 2023-07-07 | 2023-07-07 | Direct connection and power conversion dual-mode power optimization device and integrated control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116800096A (en) * | 2023-08-24 | 2023-09-22 | 杭州禾迈电力电子股份有限公司 | Control method of power converter, power converter and photovoltaic system |
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| CN116154861A (en) * | 2023-04-21 | 2023-05-23 | 深圳市中旭新能源有限公司 | Photovoltaic system based on direct connection and power conversion dual-mode MLPE component |
| CN116247733A (en) * | 2022-12-29 | 2023-06-09 | 深圳市中旭新能源有限公司 | Photovoltaic device and power generation system based on dual-operation mode ASIC chip control safety |
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| CN115663769A (en) * | 2022-12-29 | 2023-01-31 | 深圳市中旭新能源有限公司 | Photovoltaic power generation system direct-current parallel arc protection and positioning system and method |
| CN116247733A (en) * | 2022-12-29 | 2023-06-09 | 深圳市中旭新能源有限公司 | Photovoltaic device and power generation system based on dual-operation mode ASIC chip control safety |
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| CN116800096A (en) * | 2023-08-24 | 2023-09-22 | 杭州禾迈电力电子股份有限公司 | Control method of power converter, power converter and photovoltaic system |
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