CN116339478A - Dual-power priority selection circuit - Google Patents

Dual-power priority selection circuit Download PDF

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Publication number
CN116339478A
CN116339478A CN202211592473.6A CN202211592473A CN116339478A CN 116339478 A CN116339478 A CN 116339478A CN 202211592473 A CN202211592473 A CN 202211592473A CN 116339478 A CN116339478 A CN 116339478A
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China
Prior art keywords
power
input
nand gate
output
inverter
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CN202211592473.6A
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Chinese (zh)
Inventor
陈致志
胡辰凯
李喜
宋三年
宋志棠
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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Priority to CN202211592473.6A priority Critical patent/CN116339478A/en
Publication of CN116339478A publication Critical patent/CN116339478A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/30—Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S20/00—Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
    • Y04S20/20—End-user application control systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The invention relates to a dual power priority selection circuit, comprising: the dual-power supply power-on reset synthesis circuit is used for monitoring the condition of dual power supplies, generating a power-on reset signal and a synthesized output signal according to the condition of the dual power supplies, and comprises two input ends and two output ends, wherein the two input ends are respectively connected with the two power supply ends of the dual power supplies, and the two output ends are used for outputting the generated power-on reset signal; the two-phase non-overlapping RS trigger circuit is used for generating a corresponding level signal according to the power-on reset signal by taking the synthesized output signal as a power supply; and the level shifter is used for converting the level signal into a power supply control signal. The invention enables the system to automatically select among different input power supplies so as to avoid power supply conflict.

Description

Dual-power priority selection circuit
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a dual-power priority selection circuit.
Background
As the system functionality of the system on chip (SoC, systemonChip) increases, the power supply modules therein employ multiple power supply systems, requiring the use of a power priority selection circuit when the system is to select between different input power supplies. For example, when one charger is connected with two electronic products to be charged at the same time, the charger can charge the electronic products connected first preferentially, and shield the electronic products connected later, so that collision is avoided.
Disclosure of Invention
The invention aims to provide a dual-power priority selection circuit, which enables a system to automatically select among different input power supplies so as to avoid power supply conflict.
The technical scheme adopted for solving the technical problems is as follows: there is provided a dual power priority selection circuit including:
the dual-power supply power-on reset synthesis circuit is used for monitoring the condition of dual power supplies, generating a power-on reset signal and a synthesized output signal according to the condition of the dual power supplies, and comprises two input ends and two output ends, wherein the two input ends are respectively connected with the two power supply ends of the dual power supplies, and the two output ends are used for outputting the generated power-on reset signal;
the two-phase non-overlapping RS trigger circuit is used for generating a corresponding level signal according to the power-on reset signal by taking the synthesized output signal as a power supply;
and the level shifter is used for converting the level signal into a power supply control signal.
The dual-power-supply power-on reset synthesis circuit comprises a first power-on reset circuit and a second power-on reset circuit, wherein the input end of the first power-on reset circuit is connected with one power supply end in the dual power supply, and the output end of the first power-on reset circuit is connected with the input end of the first switching device; the input end of the second power-on reset circuit is connected with the other power end of the dual power supply, and the output end of the second power-on reset circuit is connected with the input end of the second switching device; the output ends of the first switching device and the second switching device are connected with the power end of the two-phase non-overlapping RS trigger circuit.
The first switching device and the second switching device are NMOS transistors.
The two-phase non-overlapping RS trigger circuit comprises a first RS trigger and a second RS trigger, wherein a first input end of the first RS trigger is connected with one of two output ends of the dual-power-supply power-on reset synthesis circuit, and a second input end of the first RS trigger is connected with the other one of the two output ends of the dual-power-supply power-on reset synthesis circuit; the first output end of the first RS trigger is connected with the first input end of the second RS trigger through a first inverter, and the second output end of the first RS trigger is connected with the second input end of the second RS trigger through a fourth inverter; the first output end of the second RS trigger is connected with the first input end of the level shifter, and the second output end of the second RS trigger is connected with the second input end of the level shifter.
The first input end and the second input end of the first RS trigger are grounded through a resistor.
The first RS trigger comprises a first NAND gate and a third NAND gate, wherein a first input end of the first NAND gate is connected with one of two output ends of the dual-power-supply power-on reset synthesis circuit, and a second input end of the first NAND gate is connected with an output end of the third NAND gate; the first input end of the third NAND gate is connected with the other one of the two output ends of the dual-power-supply power-on reset synthesis circuit, and the second input end of the third NAND gate is connected with the output end of the first NAND gate; the output end of the first NAND gate is used as a first output end of the first RS trigger, and the output end of the third NAND gate is used as a second output end of the first RS trigger.
The second RS trigger comprises a second NAND gate, a fourth NAND gate, a second inverter, a third inverter, a fifth inverter and a sixth inverter, wherein the first input end of the second NAND gate is connected with the output end of the first inverter, the second input end of the second NAND gate is connected with the output end of the sixth inverter, and the output end of the second NAND gate is connected with the input end of the second inverter; the first input end of the fourth NAND gate is connected with the output end of the fourth inverter, the second input end of the fourth NAND gate is connected with the output end of the third inverter, the output end of the fourth NAND gate is connected with the input end of a fifth NAND gate, the output end of the second NAND gate is connected with the input end of the third inverter, and the output end of the fifth NAND gate is connected with the input end of the sixth NAND gate; the output end of the second inverter is used as the first output end of the second RS trigger, and the output end of the fifth inverter is used as the second output end of the second RS trigger.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the invention has the advantages of automatic selection of the system among different input power supplies, avoiding conflict among the power supplies, having certain industrial utilization value, and being easy to integrate because most of the circuits adopt digital circuits which can be reduced along with the progress of the process.
Drawings
Fig. 1 is a schematic diagram of a dual power priority selection circuit according to an embodiment of the invention.
FIG. 2 is a waveform diagram showing the output signal of the power-on reset circuit with time according to the embodiment of the present invention.
Fig. 3 is a schematic diagram of a truth table of a two-phase non-overlapping RS flip-flop circuit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of an output waveform of a level shifter according to an embodiment of the present invention.
Detailed Description
The invention will be further illustrated with reference to specific examples. It is to be understood that these examples are illustrative of the present invention and are not intended to limit the scope of the present invention. Further, it is understood that various changes and modifications may be made by those skilled in the art after reading the teachings of the present invention, and such equivalents are intended to fall within the scope of the claims appended hereto.
Embodiments of the present invention relate to a dual power priority selection circuit, as shown in fig. 1, including: the dual-power-supply power-on reset synthesis circuit 100 is used for monitoring the condition of dual power supplies, generating a power-on reset signal and a synthesized output signal according to the condition of the dual power supplies, and comprises two input ends and two output ends, wherein the two input ends are respectively connected with the two power supply ends of the dual power supplies, and the two output ends are used for outputting the generated power-on reset signal; the two-phase non-overlapping RS flip-flop circuit 200 is configured to generate a corresponding level signal according to the power-on reset signal by using the synthesized output signal as a power source; a level shifter 300 for converting the level signal into a power control signal.
The dual-power-supply power-on reset synthesis circuit 100 in this embodiment includes a first power-on reset circuit and a second power-on reset circuit, where an input end of the first power-on reset circuit is connected to one power supply end VDD1 in the dual power supply, and an output end of the first power-on reset circuit is connected to an input end of the first switching device NMOS 1; the input end of the second power-on reset circuit is connected with the other power supply end VDD2 in the dual power supply, and the output end of the second power-on reset circuit is connected with the input end of the second switching device NMOS 2; the output ends of the first switching device NMOS1 and the second switching device NMOS2 are connected and then connected with the power supply end of the two-phase non-overlapping RS trigger circuit. The first switching device NMOS1 and the second switching device NMOS2 are NMOS transistors.
The dual power supply power-on reset synthesis circuit of the embodiment is composed of two power-on reset circuits and two NMOS transistor switches. The input ends of the two power-on reset circuits are respectively connected with a power supply end VDD1 and a power supply end VDD2 to monitor the level of the dual power supply, when the power supply end VDD1 or the power supply end VDD2 starts to be powered on, the corresponding power-on reset circuits can generate power-on reset signals POR1 or POR2, the generated power-on reset signals POR1 or POR2 are output to the two-phase non-overlapping RS trigger circuits through the two output ends of the dual power-on reset synthesis circuit, and meanwhile, the power-on reset signals POR1 and POR2 also respectively control the on-off of the first switching device NMOS1 and the second switching device NMOS2, and the power-on reset signals which pass through the first switching device NMOS1 and the second switching device NMOS2 are synthesized into synthesized output signals to serve as power supplies of the two-phase non-overlapping RS trigger. When the power supply terminals VDD1 and VDD2 are not powered on, the power-on reset signals POR1 and POR2 are both in a low level state (Gnd), and the entire network is in a zero state, so that no combination effect is exerted on the power supply. Specifically:
when the power supply terminal VDD1 gradually rises to a high enough level and the power supply terminal VDD2 is kept at a low level all the time, the signal passes through the power-on reset circuit to generate a power-on reset signal POR1, the waveform is as shown in fig. 2, the power-on reset signal POR1 is input to the VDD1/POR1 port of the two-phase non-overlapping RS flip-flop, the high level of the power-on reset signal POR1 enables the first switching device NMOS1 to be turned on and the second switching device NMOS2 at the low level to be turned off, and the synthesized output signal is connected to the power supply of the two-phase non-overlapping RS flip-flop. When the power supply terminal VDD2 gradually rises to a high enough level and the power supply terminal VDD1 is kept at a low level all the time, the signal passes through the power-on reset circuit to generate a power-on reset signal POR2, and the power-on reset signal POR2 is input to the VDD2/POR2 port of the two-phase non-overlapping RS flip-flop, the high level of the power-on reset signal POR2 enables the second switching device NMOS2 to be turned on and the first switching device NMOS1 at the low level to be turned off, and the synthesized output signal is connected to the power supply of the two-phase non-overlapping RS flip-flop circuit.
The two-phase non-overlapping RS trigger circuit of the embodiment comprises a first RS trigger and a second RS trigger, wherein a first input end of the first RS trigger is connected with one of two output ends of the dual-power-supply power-on reset synthesis circuit, and a second input end of the first RS trigger is connected with the other one of the two output ends of the dual-power-supply power-on reset synthesis circuit; the first output end of the first RS trigger is connected with the first input end of the second RS trigger through a first inverter INV1, and the second output end of the first RS trigger is connected with the second input end of the second RS trigger through a fourth inverter INV 4; the first output end of the second RS trigger is connected with the first input end of the level shifter, and the second output end of the second RS trigger is connected with the second input end of the level shifter. The first input end and the second input end of the first RS trigger are grounded through a resistor.
The first RS trigger comprises a first NAND gate NAND1 and a third NAND gate NAND3, wherein a first input end of the first NAND gate NAND1 is connected with a power-on reset signal POR1 output by the dual-power-on reset synthesis circuit, and a second input end of the first NAND gate NAND1 is connected with an output end of the third NAND gate NAND 3; the first input end of the third NAND gate NAND3 is connected with a power-on reset signal POR2 output by the dual-power-supply power-on reset synthesis circuit, and the second input end of the third NAND gate NAND3 is connected with the output end of the first NAND gate NAND 1; the output end of the first NAND gate NAND1 is used as a first output end of the first RS trigger, and the output end of the third NAND gate is used as a second output end of the first RS trigger.
The second RS trigger comprises a second NAND gate NAND2, a fourth NAND gate NAND4, a second inverter INV2, a third inverter INV3, a fifth inverter INV5 and a sixth inverter INV6, wherein the first input end of the second NAND gate NAND2 is connected with the output end of the first inverter INV1, the second input end is connected with the output end of the sixth inverter INV6, and the output end is connected with the input end of the second inverter INV 2; the first input end of the fourth NAND gate NAND4 is connected with the output end of the fourth inverter INV4, the second input end is connected with the output end of the third inverter INV3, the output end is connected with the input end of the fifth inverter INV5, the output end of the second inverter INV2 is connected with the input end of the third inverter INV3, and the output end of the fifth inverter INV5 is connected with the input end of the sixth inverter INV 6; the output end of the second inverter INV2 is used as the first output end of the second RS flip-flop, and the output end of the fifth inverter INV5 is used as the second output end of the second RS flip-flop.
The level shifter of the present embodiment includes a first level shifter portion level shifter1 and a second level shifter portion level shifter2 arranged in parallel, wherein an input terminal of the first level shifter portion level shifter1 is connected to an output terminal of the second inverter INV2, and an input terminal of the second level shifter portion level shifter2 is connected to an output terminal of the fifth inverter.
In the two-phase non-overlapping RS flip-flop circuit of this embodiment, each of the two input ports has a resistor R1 and a resistor R2 connected to ground, and the logic values of the two ports are all low level under the condition that no power is connected, so that the whole network is in a zero state, the outputs of the second inverter INV2 and the fifth inverter INV5 are all low level "0", and the whole circuit has no selective effect on the power.
When the input port VDD1/POR1 is high and VDD2/POR2 is low, the first NAND gate NAND1 outputs a low level of "0", the third NAND gate NAND3 outputs a high level of "1", the first inverter INV1 outputs a high level of "1", the second NAND gate NAND2 outputs a low level of "0", the second inverter INV2 outputs a high level of "1", the third inverter INV3 outputs a low level of "0", while the fourth inverter INV4 outputs a low level of "0", the fourth NAND gate NAND4 outputs a high level of "1", the fifth inverter INV5 outputs a low level of "0", the sixth inverter INV6 outputs a high level of "1", and the truth table of the two-phase non-overlapping RS flip-flop circuit is shown in fig. 3. The high level output of the second inverter INV2 is converted into the Control signal VDD1Control with the high level of VDD1 to output the high level "1" and VDD2Control to output the low level "0" by the level conversion of the level converter, so that the selection of the VDD1 power supply is realized, and the waveform is shown in fig. 4.
When the input port VDD2/POR2 is high and VDD1/POR1 is low, the first NAND gate NAND1 outputs a high level "1", the third NAND gate NAND3 outputs a low level "0", the first inverter INV1 outputs a low level "0", the second NAND gate NAND2 outputs a high level "1", the second inverter INV2 outputs a low level "0", the third inverter INV3 outputs a high level "1", while the fourth inverter INV4 outputs a high level "1", the fourth NAND gate NAND4 outputs a low level "0", the fifth inverter INV5 outputs a high level "1", and the sixth inverter INV6 outputs a low level "0". The high level output of the fifth inverter INV5 is converted into the Control signal VDD2Control with the high level of VDD2 to output the high level "1" through the level conversion of the level converter, and VDD1Control outputs the low level "0", so that the selection of the VDD2 power supply is realized, and the circuit maintains the current level state by the output of the third inverter INV3 and the sixth inverter INV 6.
When the input ports VDD1/POR1 and VDD2/POR2 become high at the same time, the whole circuit maintains the level state at the previous time, if the port VDD1/POR1 has a high level input before the port VDD2/POR2, the power supply is selected as POR1, if the port VDD2/POR2 has a high level input before the port VDD1/POR1, the power supply is selected as POR2.
It is easy to find that the invention has the advantages of automatic selection of the system between different input power supplies, avoiding conflict between the power supplies, having certain industrial utilization value, and the majority of the circuits adopt digital circuits, being capable of being reduced along with the progress of the process, and being easy to integrate.

Claims (7)

1. A dual power priority selection circuit comprising:
the dual-power supply power-on reset synthesis circuit is used for monitoring the condition of dual power supplies, generating a power-on reset signal and a synthesized output signal according to the condition of the dual power supplies, and comprises two input ends and two output ends, wherein the two input ends are respectively connected with the two power supply ends of the dual power supplies, and the two output ends are used for outputting the generated power-on reset signal;
the two-phase non-overlapping RS trigger circuit is used for generating a corresponding level signal according to the power-on reset signal by taking the synthesized output signal as a power supply;
and the level shifter is used for converting the level signal into a power supply control signal.
2. The dual power priority selection circuit as recited in claim 1 wherein the dual power supply power-on-reset combining circuit comprises a first power-on-reset circuit and a second power-on-reset circuit, an input of the first power-on-reset circuit being connected to one of the power supply terminals of the dual power supply, an output being connected to an input of the first switching device; the input end of the second power-on reset circuit is connected with the other power end of the dual power supply, and the output end of the second power-on reset circuit is connected with the input end of the second switching device; the output ends of the first switching device and the second switching device are connected with the power end of the two-phase non-overlapping RS trigger circuit.
3. The dual power priority selection circuit of claim 2 wherein the first switching device and the second switching device are NMOS transistors.
4. The dual power priority selection circuit of claim 1 wherein the two-phase non-overlapping RS flip-flop circuit comprises a first RS flip-flop having a first input connected to one of the two outputs of the dual power up reset combining circuit and a second RS flip-flop having a second input connected to the other of the two outputs of the dual power up reset combining circuit; the first output end of the first RS trigger is connected with the first input end of the second RS trigger through a first inverter, and the second output end of the first RS trigger is connected with the second input end of the second RS trigger through a fourth inverter; the first output end of the second RS trigger is connected with the first input end of the level shifter, and the second output end of the second RS trigger is connected with the second input end of the level shifter.
5. The dual power priority selection circuit as recited in claim 4 wherein the first input and the second input of the first RS flip-flop are both grounded through a resistor.
6. The dual power priority selection circuit as recited in claim 4 wherein the first RS flip-flop comprises a first nand gate and a third nand gate, a first input of the first nand gate being coupled to one of two outputs of the dual power on reset combining circuit, a second input being coupled to an output of the third nand gate; the first input end of the third NAND gate is connected with the other one of the two output ends of the dual-power-supply power-on reset synthesis circuit, and the second input end of the third NAND gate is connected with the output end of the first NAND gate; the output end of the first NAND gate is used as a first output end of the first RS trigger, and the output end of the third NAND gate is used as a second output end of the first RS trigger.
7. The dual power priority selection circuit as recited in claim 4 wherein the second RS flip-flop comprises a second nand gate, a fourth nand gate, a second inverter, a third inverter, a fifth inverter and a sixth inverter, a first input of the second nand gate being connected to an output of the first inverter, a second input being connected to an output of the sixth inverter, an output being connected to an input of the second inverter; the first input end of the fourth NAND gate is connected with the output end of the fourth inverter, the second input end of the fourth NAND gate is connected with the output end of the third inverter, the output end of the fourth NAND gate is connected with the input end of a fifth NAND gate, the output end of the second NAND gate is connected with the input end of the third inverter, and the output end of the fifth NAND gate is connected with the input end of the sixth NAND gate; the output end of the second inverter is used as the first output end of the second RS trigger, and the output end of the fifth inverter is used as the second output end of the second RS trigger.
CN202211592473.6A 2022-12-13 2022-12-13 Dual-power priority selection circuit Pending CN116339478A (en)

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CN202211592473.6A CN116339478A (en) 2022-12-13 2022-12-13 Dual-power priority selection circuit

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Application Number Priority Date Filing Date Title
CN202211592473.6A CN116339478A (en) 2022-12-13 2022-12-13 Dual-power priority selection circuit

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CN116339478A true CN116339478A (en) 2023-06-27

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