CN116227507B - Arithmetic device for performing bilinear interpolation processing - Google Patents
Arithmetic device for performing bilinear interpolation processing Download PDFInfo
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Abstract
The present disclosure relates to the field of data processing, and discloses an arithmetic device for performing bilinear interpolation processing, including: the weight input module is used for determining weight input data corresponding to each multiplier by utilizing the first low-level data u and the second low-level data v, and inputting the weight input data into the corresponding multiplier; the multiplexer is used for respectively determining data to be operated corresponding to at least one multiplier according to the first interpolation weight U and the second interpolation weight V, and inputting the data to be operated into the corresponding multiplier; the multiplier is used for carrying out corresponding multiplication according to the data to be calculated and the weight input data and determining multiplication results; and the adder is used for carrying out summation operation on multiplication operation results corresponding to the multipliers and determining bilinear interpolation processing results corresponding to the data to be interpolated. According to the embodiment of the disclosure, the input bit width of the multiplier can be reduced, the circuit area of the device is reduced, and the hardware resource consumption for bilinear interpolation processing is saved.
Description
Technical Field
The present disclosure relates to the field of data processing, and in particular, to an arithmetic device for performing bilinear interpolation processing.
Background
Bilinear interpolation is a linear interpolation extension of an interpolation function with two variables, the principle of which is to perform linear interpolation once in two directions, respectively. Bilinear interpolation is used as an interpolation algorithm in numerical analysis, and is widely applied to the technical fields of signal processing, digital image and video processing and the like.
Disclosure of Invention
In view of this, the present disclosure proposes an arithmetic device for performing bilinear interpolation processing.
According to an aspect of the present disclosure, there is provided an arithmetic device for performing bilinear interpolation processing, including: the system comprises a weight input module, a multiplexer, a plurality of multipliers and an adder, wherein the input bit width of the multipliers is m-1 bit; the weight input module is configured to determine weight input data corresponding to each multiplier by using first low-level data U and second low-level data V, and input the weight input data to the corresponding multiplier, where the first low-level data U is a low-level m-1 bit of a first interpolation weight U, the second low-level data V is a low-level m-1 bit of a second interpolation weight V, the first interpolation weight U and the second interpolation weight V are m bits, and are greater than or equal to 0 and less than or equal to 1, and m is a bit number of a binary number corresponding to the first interpolation weight U and the second interpolation weight V; the multiplexer is configured to determine data to be operated corresponding to at least one multiplier according to the first interpolation weight U and the second interpolation weight V, and input the data to be operated into the corresponding multiplier, where the data to be operated corresponding to each multiplier is one of a plurality of data to be interpolated that need to be subjected to the bilinear interpolation processing; the multiplier is used for carrying out corresponding multiplication according to the data to be calculated and the weight input data, and determining a multiplication result; and the adder is used for carrying out summation operation on the multiplication operation results corresponding to the multipliers and determining bilinear interpolation processing results corresponding to the plurality of data to be interpolated.
In one possible implementation, the plurality of multipliers comprises: a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier, the weight input data comprising: the first weight input data, the second weight input data, the third weight input data and the fourth weight input data; the weight input module inputs the first weight input data of the first multiplier as 1-u and 1-v; the weight input module inputs the second weight input data of the second multiplier as u and 1-v; the weight input module inputs the third weight input data of the third multiplier as 1-u and v; the weight input module inputs the fourth weight input data of the fourth multiplier as u and v.
In a possible implementation manner, the multiplexer is configured to determine, according to the most significant bits of the first interpolation weight U and the second interpolation weight V, a value change of the first low-order data U with respect to the first interpolation weight U, and a value change of the second low-order data V with respect to the second interpolation weight V; the multiplexer is configured to determine the data to be operated corresponding to at least one multiplier according to a value change of the first low-order data U relative to the first interpolation weight U, a value change of the second low-order data V relative to the second interpolation weight V, and the plurality of data to be interpolated, where the plurality of data to be interpolated includes: the first data to be interpolated, the second data to be interpolated, the third data to be interpolated and the fourth data to be interpolated.
In one possible implementation manner, the multiplexer is configured to determine that the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U and the value of the second low-order data V is unchanged relative to the value of the second interpolation weight V when the most significant bits of the first interpolation weight U and the second interpolation weight V are both 0.
In one possible implementation manner, the multiplexer is configured to determine that the data to be operated corresponding to the first multiplier is the first data to be interpolated, the data to be operated corresponding to the second multiplier is the second data to be interpolated, and the data to be operated corresponding to the third multiplier is the third data to be interpolated when the value of the first low data U is unchanged relative to the value of the first interpolation weight U and the value of the second low data V is unchanged relative to the value of the second interpolation weight V.
In one possible implementation manner, the multiplexer is configured to determine that the value of the first low-order data U changes with respect to the value of the first interpolation weight U and that the value of the second low-order data V does not change with respect to the value of the second interpolation weight V when the most significant bit of the first interpolation weight U is 1 and the most significant bit of the second interpolation weight V is 0.
In one possible implementation manner, the multiplexer is configured to determine that the data to be operated corresponding to the first multiplier is the second data to be interpolated and the data to be operated corresponding to the third multiplier is the fourth data to be interpolated when the value of the first low-order data U changes relative to the value of the first interpolation weight U and the value of the second low-order data V does not change relative to the value of the second interpolation weight V.
In one possible implementation manner, the multiplexer is configured to determine that the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U and that the value of the second low-order data V is changed relative to the value of the second interpolation weight V when the most significant bit of the first interpolation weight U is 0 and the most significant bit of the second interpolation weight V is 1.
In one possible implementation manner, the multiplexer is configured to determine that the data to be operated corresponding to the first multiplier is the third data to be interpolated, and the data to be operated corresponding to the second multiplier is the fourth data to be interpolated when the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U and the value of the second low-order data V is changed relative to the value of the second interpolation weight V.
In one possible implementation manner, the multiplexer is configured to determine that the value of the first low-order data U changes relative to the value of the first interpolation weight U and the value of the second low-order data V changes relative to the value of the second interpolation weight V when the most significant bits of the first interpolation weight U and the second interpolation weight V are both 1.
In one possible implementation manner, the multiplexer is configured to determine that the data to be operated corresponding to the first multiplier is the fourth data to be interpolated when the value of the first low-order data U changes relative to the value of the first interpolation weight U and the value of the second low-order data V changes relative to the value of the second interpolation weight V.
In one possible implementation, the plurality of data to be interpolated are four pixel data of a 2×2 structure requiring bilinear interpolation processing in the target image.
The computing device for performing bilinear interpolation processing in the embodiment of the disclosure determines weight input data corresponding to each multiplier by using first low-order data U and second low-order data V through a weight input module, and inputs the weight input data into the corresponding multiplier, wherein the first low-order data U is low-order m-1 bit of a first interpolation weight U, the second low-order data V is low-order m-1 bit of a second interpolation weight V, and the first interpolation weight U and the second interpolation weight V are m bits, and are greater than or equal to 0 and less than or equal to 1; the weight input data determined according to the first low-bit data u and the second low-bit data v of m-1 bit has the number of bits of m-1 bit, so that the input bit width of the multiplier can be reduced from m bit to m-1 bit. The multiplexer is utilized to respectively determine the data to be operated corresponding to at least one multiplier according to the values of the first interpolation weight U and the second interpolation weight V, wherein the data to be operated corresponding to each multiplier is one of a plurality of data to be interpolated which need bilinear interpolation processing, and the data to be operated is input into the corresponding multiplier, so that the multiplication result corresponding to the multiplier can be adjusted, and the accuracy of the bilinear interpolation processing result is further ensured. Through the multipliers, corresponding multiplication operation can be performed according to the data to be operated and the weight input data, multiplication operation results are determined, and then through the adders, summation operation can be performed on the multiplication operation results corresponding to the multipliers, and bilinear interpolation processing results are determined. By reducing the input bit width of the multiplier and adjusting the logic of the data to be interpolated input into the multiplier through the multiplexer, the circuit area of the whole device can be reduced, and the hardware resource consumption for bilinear interpolation processing is saved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.
Fig. 1 shows a schematic diagram of an arithmetic device for performing bilinear interpolation processing in the related art.
Fig. 2 shows a block diagram of an arithmetic device for performing bilinear interpolation processing according to an embodiment of the present disclosure.
Fig. 3 shows a schematic diagram of an arithmetic device for performing bilinear interpolation processing according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
Bilinear interpolation is a linear interpolation extension of an interpolation function with two variables, the principle of which is to perform linear interpolation once in two directions, respectively. Bilinear interpolation is used as an interpolation algorithm in numerical analysis, and is widely applied to the technical fields of signal processing, digital image and video processing and the like.
One expression of bilinear interpolation can be expressed as the following formulas (1) to (3):
result_ab=a×(1-U)+b×U （1）
result_cd=c×(1-U)+d×U （2）
result_abcd=result_ab×(1-V)+result_cd×V （3）
wherein a, b, c, d represents four data to be interpolated requiring bilinear interpolation; result_ab represents an output result of linear interpolation in the first direction; result_cd represents the output result of linear interpolation in the first direction; result_abcd represents an output result of linear interpolation in the second direction, that is, an output result of bilinear interpolation; u represents a first interpolation weight corresponding to linear interpolation in a first direction, V represents a second interpolation weight corresponding to linear interpolation in a second direction, and the value ranges of U and V are more than or equal to 0 and less than or equal to 1.
In one mode of the related art, according to the above formulas (1) and (2), the output results result_ab and result_cd of linear interpolation in the first direction are calculated respectively, and then according to the above formula (3), the two output results are subjected to linear interpolation in the second direction, so as to determine the output result result_abcd of bilinear interpolation.
In another related art, according to the above formulas (1), (2) and (3), the output result result_abcd of the bilinear interpolation is expressed as the following formula (4):
result_abcd= a×(1-U)(1-V)+b×U(1-V)+c×(1-U)V+d×UV （4）
According to the above formula (4), the output result result_abcd of the bilinear interpolation can be directly determined.
According to the two technical schemes, bilinear interpolation processing is directly carried out according to the first interpolation weight U and the second interpolation weight V, and optimization processing is not carried out on the first interpolation weight U and the second interpolation weight V. In the prior art, when bilinear interpolation processing is performed, a first interpolation weight U and a second interpolation weight V need to be input to a multiplier to perform multiplication operation. The first interpolation weight U and the second interpolation weight V may be represented as binary numbers of m bits, where m is the number of bits of the binary numbers corresponding to the first interpolation weight U and the second interpolation weight V, and correspondingly, the input bit width of the multiplier is also m bits. Because the value ranges of the first interpolation weight U and the second interpolation weight V are more than or equal to 0 and less than or equal to 1, when the precision of the first interpolation weight U and the second interpolation weight V is higher, namely m is larger, the input bit width corresponding to the multiplier is larger, and the consumed hardware resources are also larger.
Fig. 1 shows a schematic diagram of an arithmetic device for performing bilinear interpolation processing in the related art. As shown in fig. 1, the apparatus 100 may be used to perform bilinear interpolation, where the apparatus 100 includes a multiplier 101, a multiplier 102, a multiplier 103, and a multiplier 104, and an adder 105.
Based on the above formula (4), the multiplier 101 may be used to determine a multiplication result corresponding to a× (1-U) (1-V), the multiplier 102 may be used to determine a multiplication result corresponding to b× (1-V), the multiplier 103 may be used to determine a multiplication result corresponding to c× (1-U) V, the multiplier 104 may be used to determine a multiplication result corresponding to d× (UV), and the adder 105 may be used to sum the multiplication results corresponding to the respective multipliers, thereby determining the bilinear interpolation result.
Wherein the first interpolation weight U and the second interpolation weight V may be represented by a binary number of m bits. Correspondingly, the input bit width of the multiplier also needs to be m bits. Because the value ranges of the first interpolation weight U and the second interpolation weight V are greater than or equal to 0 and less than or equal to 1, when the accuracy of U and V is higher, that is, m is larger, the input bit width of the multiplier is larger, and larger hardware resource consumption is required.
The present disclosure provides an arithmetic device for performing bilinear interpolation processing, which can save consumption of hardware resources. The operation device for bilinear interpolation processing provided by the present disclosure is described in detail below.
Fig. 2 shows a block diagram of an arithmetic device for performing bilinear interpolation processing according to an embodiment of the present disclosure. As shown in fig. 2, the apparatus 200 includes: the device comprises a weight input module 201, a multiplexer 202, a plurality of multipliers 203 and an adder 204, wherein the input bit width of the multipliers 203 is m-1 bit.
The weight input module 201 is configured to determine weight input data corresponding to each multiplier 203 by using first low-order data U and second low-order data V, and input the weight input data to the corresponding multiplier 203, where the first low-order data U is a low order m-1 bit of the first interpolation weight U, the second low-order data V is a low order m-1 bit of the second interpolation weight V, the first interpolation weight U and the second interpolation weight V are m bits, and are greater than or equal to 0 and less than or equal to 1, and m is a bit of a binary number corresponding to the first interpolation weight U and the second interpolation weight V.
The multiplexer 202 is configured to determine data to be operated corresponding to each multiplier 203 according to the values of the first interpolation weight U and the second interpolation weight V, and input the data to be operated to the corresponding multiplier 203, where the data to be operated corresponding to each multiplier 203 is one of a plurality of data to be interpolated that need bilinear interpolation processing.
Multiplier 203 is configured to perform corresponding multiplication according to the data to be calculated and the weight input data, and determine a multiplication result.
And an adder 204, configured to perform a summation operation on multiplication results corresponding to the multipliers 203, and determine bilinear interpolation processing results corresponding to the plurality of data to be interpolated.
The first interpolation weight U and the second interpolation weight V corresponding to the bilinear interpolation process may be represented as binary numbers of m bits, where the value ranges of U and V are greater than or equal to 0 and less than or equal to 1.
Through the weight input module 201, weight input data corresponding to each multiplier 203 can be determined according to the first low-order data U and the second low-order data V, that is, the low-order m-1 bit of the first interpolation weight U and the low-order m-1 bit of the second interpolation weight V, and the weight input data is input to each multiplier 203 respectively. The specific structure of the weight input module 201 may be set according to actual use requirements, which is not specifically limited in this disclosure.
In an example, a binary number of 9 bits is used to represent the first interpolation weight U and the second interpolation weight V that are equal to or greater than 0 and equal to or less than 1. For example, the first interpolation weight U is expressed as: 011000000, the second interpolation weight V is expressed as: 001110011, accordingly, it can be determined that the first low-order data u is expressed as: 11000000, the second low order data v is expressed as: 01110011.
in an example, a 9-bit binary number is used to represent a first interpolation weight U that is greater than or equal to 0 and less than or equal to 1. When the value of the first interpolation weight U is equal to 0, the value can be expressed as 000000000; the first low-order data u is 00000000, and the value of the first low-order data u is 0; at this time, the value of the first low bit data U is unchanged from the value of the first interpolation weight U. When the value of the first interpolation weight U is equal to 1, the value may be denoted 100000000; the first low-order data u is 00000000, and the value of the first low-order data u is 0; at this time, the value of the first low bit data U is changed with respect to the value of the first interpolation weight U. And so on, the second interpolation weight V is equally applicable, and will not be described here.
Since 0 and 1 are represented by m bit binary numbers, the corresponding low order m-1 bit is the same. When the value of the first interpolation weight U and/or the second interpolation weight V is equal to 1, that is, when the highest bit of the first interpolation weight U and/or the second interpolation weight V is 1, the value of the corresponding first low-bit data U and/or the second low-bit data V is 0, that is, the value of the first low-bit data U is changed relative to the value of the first interpolation weight U, and/or the value of the second low-bit data V is changed relative to the value of the second interpolation weight V. At this time, the weight input data corresponding to each multiplier 203 is determined according to the first low-order data U and the second low-order data V, and the value of the weight input data is changed relative to the weight input data determined directly according to the first interpolation weight U and the second interpolation weight V, which may cause a corresponding multiplication result to be changed, and may further affect the output result of the device 200, that is, affect the accuracy of the bilinear interpolation result.
In an example, a binary number of 9 bits is used to represent the first interpolation weight U and the second interpolation weight V that are equal to or greater than 0 and equal to or less than 1. For example, when the value of the first interpolation weight U is equal to 1 and the value of the second interpolation weight V is greater than 0 and less than 1, the bilinear interpolation processing result is b× (1-V) +d×v based on the above formula (4). As can be seen from the above description, at this time, the value of the first low-level data U changes relative to the value of the first interpolation weight U, the value of the second low-level data V does not change relative to the value of the second interpolation weight V, and if the weight input data corresponding to each multiplier 203 is determined according to the first low-level data U and the second low-level data V, the operation is performed based on the above formula (4), and the corresponding operation result is a× (1-V) +c×v=a× (1-V) +c×v. That is, determining the weight input data corresponding to each multiplier 203 according to the first low-order data u and the second low-order data v may result in a change in the corresponding multiplication result, thereby affecting the accuracy of the bilinear interpolation result.
Therefore, in order to ensure the accuracy of the bilinear interpolation processing result, the multiplexer 202 may determine, according to the values of the first interpolation weight U and the second interpolation weight V, the data to be operated corresponding to the at least one multiplier 203 from the plurality of data to be interpolated, so as to adjust the multiplication result corresponding to the at least one multiplier 203.
The process of determining the data to be operated corresponding to the at least one multiplier 203 by the multiplexer 202 according to the values of the first interpolation weight U and the second interpolation weight V will be described in detail later in connection with a possible implementation manner of the present disclosure, and will not be described in detail here.
The specific configuration and number of multiplexers 202 may be set according to the actual use requirements, which is not specifically limited in this disclosure.
According to the data to be operated and the weight input data corresponding to each multiplier 203, corresponding multiplication operation can be performed, so as to determine the multiplication operation result corresponding to each multiplier 203. The multiplier 203 and the corresponding multiplication operation will be described in detail in connection with possible implementations of the present disclosure, which will not be described here.
The specific structure and number of multipliers 203 may be set according to actual usage requirements, which is not specifically limited in this disclosure.
The adder 204 may perform a summation operation on the multiplication results output from the multipliers 203, determine the summation result, and determine the summation result as bilinear interpolation processing results corresponding to the plurality of data to be interpolated.
The specific structure of the adder 204 may be set according to actual usage requirements, which is not specifically limited in this disclosure.
The computing device for performing bilinear interpolation processing in the embodiment of the disclosure determines weight input data corresponding to each multiplier by using first low-order data U and second low-order data V through a weight input module, and inputs the weight input data into the corresponding multiplier, wherein the first low-order data U is low-order m-1 bit of a first interpolation weight U, the second low-order data V is low-order m-1 bit of a second interpolation weight V, and the first interpolation weight U and the second interpolation weight V are m bits, and are greater than or equal to 0 and less than or equal to 1; the weight input data determined according to the first low-bit data u and the second low-bit data v of m-1 bit has the number of bits of m-1 bit, so that the input bit width of the multiplier can be reduced from m bit to m-1 bit. The multiplexer is utilized to respectively determine the data to be operated corresponding to at least one multiplier according to the values of the first interpolation weight U and the second interpolation weight V, wherein the data to be operated corresponding to each multiplier is one of a plurality of data to be interpolated which need bilinear interpolation processing, and the data to be operated is input into the corresponding multiplier, so that the multiplication result corresponding to the multiplier can be adjusted, and the accuracy of the bilinear interpolation processing result is further ensured. Through the multipliers, corresponding multiplication operation can be performed according to the data to be operated and the weight input data, multiplication operation results are determined, and then through the adders, summation operation can be performed on the multiplication operation results corresponding to the multipliers, and bilinear interpolation processing results are determined. By reducing the input bit width of the multiplier and adjusting the logic of the data to be interpolated input into the multiplier through the multiplexer, the circuit area of the whole device can be reduced, and the hardware resource consumption for bilinear interpolation processing is saved.
In one possible implementation, the plurality of multipliers 203 includes: the first multiplier, the second multiplier, the third multiplier and the fourth multiplier, the weight input data includes: the first weight input data, the second weight input data, the third weight input book and the fourth weight input data; the weight input module inputs the first weight input data of the first multiplier into 1-u and 1-v; the weight input module inputs the second weight input data of the second multiplier as u and 1-v; the weight input module inputs the third weight input data of the third multiplier into 1-u and v; the weight input module inputs the fourth weight input data of the fourth multiplier as u and v.
Fig. 3 shows a schematic diagram of an arithmetic device for performing bilinear interpolation processing according to an embodiment of the present disclosure. As shown in fig. 3, the multiplier 203 includes: a first multiplier 2031, a second multiplier 2032, a third multiplier 2033, and a fourth multiplier 2034.
It can be determined from the above formula (4): the multiplication term of the first multiplier 2031 for multiplying the data to be calculated is (1-U) (1-V), and thus it can be determined that the first weight input data input to the first multiplier by the weight input module is 1-U and 1-V; the multiplication term of the second multiplier 2032 for multiplying the data to be multiplied is U (1-V), so that it can be determined that the second weight input data input to the second multiplier by the weight input module is U and 1-V; the multiplication term of the third multiplier 2033 for multiplying the data to be calculated is (1-U) V, and thus, it can be determined that the third weight input data input to the third multiplier by the weight input module is 1-U and V; the multiplication term of the fourth multiplier 2034 for multiplying the data to be calculated is UV, and thus, it can be determined that the fourth weight input data input to the fourth multiplier by the weight input module is u and v.
After determining the data to be operated corresponding to each multiplier 203 in the plurality of data to be interpolated respectively through the multiplexer 202, the data to be operated is input to the corresponding multiplier 203. The multiplier 203 may determine a corresponding multiplication result according to the data to be calculated and a multiplication term corresponding to the multiplier 203.
In one possible implementation, the multiplexer 202 is configured to determine, according to the most significant bits of the first interpolation weight U and the second interpolation weight V, a value change of the first low-order data U with respect to the first interpolation weight U, and a value change of the second low-order data V with respect to the second interpolation weight V; the multiplexer is configured to determine data to be operated corresponding to the at least one multiplier according to a change in a value of the first low-order data U relative to the first interpolation weight U, a change in a value of the second low-order data V relative to the second interpolation weight V, and a plurality of data to be interpolated, where the plurality of data to be interpolated includes: the first data to be interpolated, the second data to be interpolated, the third data to be interpolated and the fourth data to be interpolated.
The change of the value of the first low-level data U relative to the first interpolation weight U refers to whether the value indicated by the first low-level data U of m-1 bit and the value indicated by the first interpolation weight U of m bit are changed or not; the change of the value of the second low-order data V relative to the second interpolation weight V refers to whether the value indicated by the second low-order data V of m-1 bit and the value indicated by the second interpolation weight V of m bit change or not.
As can be seen from the foregoing, when the value of the first interpolation weight U and/or the second interpolation weight V is equal to 1, the value of the first low-order data U and/or the second low-order data V is changed relative to the value of the first interpolation weight U and/or the second interpolation weight V. When the first interpolation weight U and/or the second interpolation weight V is greater than or equal to 0 and less than 1, the value of the first low-order data U and/or the second low-order data V is unchanged relative to the value of the first interpolation weight U and/or the second interpolation weight V.
Because the first interpolation weight U and the second interpolation weight V are binary numbers of m bits, and the value range is more than or equal to 0 and less than or equal to 1. Therefore, it is possible to quickly determine whether or not the values of the first interpolation weight U and the second interpolation weight V are equal to 1 by the most significant bits of the first interpolation weight U and the first interpolation weight V, thereby determining the value change of the first low-order data U with respect to the first interpolation weight U and the value change of the second low-order data V with respect to the second interpolation weight V.
In order to ensure that the multiplication result corresponding to each multiplier 203 is correct, the multiplexer 202 may determine the value change of the first low-order data U with respect to the first interpolation weight U and the value change of the second low-order data V with respect to the second interpolation weight V according to the highest bit of the first interpolation weight U and the second interpolation weight V.
The multiplexer 202 may determine the data to be operated corresponding to the at least one multiplier according to the change in the value of the first low-order data U with respect to the first interpolation weight U, the change in the value of the second low-order data V with respect to the second interpolation weight V, and the plurality of data to be interpolated.
Wherein the plurality of data to be interpolated includes: the first data to be interpolated a, the second data to be interpolated b, the third data to be interpolated c and the fourth data to be interpolated d. The multiplexer 202 may determine the data to be operated corresponding to the first multiplier 2031, the second multiplier 2032, and the third multiplier 2033 from among the first data to be interpolated a, the second data to be interpolated b, the third data to be interpolated c, and the fourth data to be interpolated d, respectively.
Based on the above formula (4), when the value of the first low-order data U changes relative to the value of the first interpolation weight U and/or the value of the second low-order data V changes relative to the value of the second interpolation weight V, the weight input data determined according to the first low-order data U and the second low-order data V is input to the fourth multiplier 2034, and the corresponding multiplication results are all 0. Therefore, when the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U and the value of the second low-order data V is unchanged relative to the value of the second interpolation weight V, the fourth data d to be interpolated is normally input to the fourth multiplier 2034; when the value of the first low-order data U changes relative to the value of the first interpolation weight U and/or the value of the second low-order data V changes relative to the value of the second interpolation weight V, the weight input data determined according to the first low-order data U and the second low-order data V is input into the fourth multiplier 2034, and the multiplication result corresponding to the fourth multiplier 2034 is necessarily 0, so that a multiplexer does not need to be set to select the corresponding data to be calculated.
In one possible implementation, the multiplexer 202 is configured to determine that the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U and the value of the second low-order data V is unchanged relative to the value of the second interpolation weight V when the highest bits of the first interpolation weight U and the second interpolation weight V are both 0.
When the highest bits of the first interpolation weight U and the second interpolation weight V are 0, namely the values of the first interpolation weight U and the second interpolation weight V are more than or equal to 0 and less than 1. At this time, the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data V is unchanged relative to the value of the second interpolation weight V.
In an example, a binary number of 9 bits is used to represent the first interpolation weight U and the second interpolation weight V that are equal to or greater than 0 and equal to or less than 1. For example, when the value of the first interpolation weight U is equal to 0.75, it may be denoted as 011000000; the value of the second interpolation weight V is equal to 0.45, which may be denoted as 001110011. The highest bits of the first interpolation weight U and the second interpolation weight V are 0, namely the values of the first interpolation weight U and the second interpolation weight V are more than or equal to 0 and less than 1. Correspondingly, the first low-order data u is 11000000, and the value of the first low-order data u is equal to 0.75; the second low order data v is 01110011, and the value of the second low order data v is equal to 0.45. At this time, the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data V is unchanged relative to the value of the second interpolation weight V.
In a possible implementation manner, the multiplexer 202 is configured to determine that the data to be operated corresponding to the first multiplier 2031 is the first data to be interpolated, the data to be operated corresponding to the second multiplier 2032 is the second data to be interpolated, the data to be operated corresponding to the third multiplier 2033 is the third data to be interpolated, and the data to be operated corresponding to the fourth multiplier 2034 is the fourth data to be interpolated when the value of the first low data U is unchanged relative to the value of the first interpolation weight U and the value of the second low data V is unchanged relative to the value of the second interpolation weight V.
Taking the above fig. 3 as an example, as shown in fig. 3, the multiplexer 202 includes: a first multiplexer 2021, a second multiplexer 2022, and a third multiplexer 2023.
The value of the first low-order data U is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data V is unchanged relative to the value of the second interpolation weight V, that is, the values of the first low-order data U and the second low-order data V may represent the true values of the first interpolation weight U and the second interpolation weight V. Therefore, the weight input data determined according to the first low-bit data U and the second low-bit data V of m-1 bit are multiplied with the data to be operated, and the corresponding multiplication result is unchanged relative to the weight input data determined according to the first interpolation weight U and the second interpolation weight V of m bit.
When the values of the first interpolation weight U and the second interpolation weight V are equal to or greater than 0 and less than 1, according to the above formula (4), the bilinear interpolation processing result result_abcd=a× (1-U) (1-V) +bχu (1-V) +c× (1-U) v+d×uv can be determined. Because the values of the first interpolation weight U and the second interpolation weight V are greater than or equal to 0 and less than 1, the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data V is unchanged relative to the value of the second interpolation weight V. Therefore, the first multiplexer 2021 may determine that the data to be operated corresponding to the first multiplier 2031 is the first data to be interpolated a, the second multiplexer 2022 may determine that the data to be operated corresponding to the second multiplier 2032 is the second data to be interpolated b, the third multiplexer 2023 may determine that the data to be operated corresponding to the third multiplier 2033 is the third data to be interpolated c, and the fourth multiplier 2034 may determine that the data to be operated corresponding to the fourth multiplier 2034 is the fourth data to be interpolated d. At this time, it is possible to secure the bilinear interpolation processing result result_abcd=a× (1-U) (1-V) +b×u (1-V) +c× (1-U) v+d×uv=a× (1-U) (1-V) +b×u (1-V) +c× (1-U) v+d×uv.
In one possible implementation, the multiplexer 202 is configured to determine that the value of the first low-order data U changes with respect to the value of the first interpolation weight U and the value of the second low-order data V does not change with respect to the value of the second interpolation weight V when the most significant bit of the first interpolation weight U is 1 and the most significant bit of the second interpolation weight V is 0.
When the highest bit of the first interpolation weight U is 1 and the highest bit of the second interpolation weight V is 0, namely the value of the first interpolation weight U is equal to 1, the value of the second interpolation weight V is more than or equal to 0 and less than 1. At this time, the value of the first low-order data U is changed relative to the value of the first interpolation weight U, and the value of the second low-order data V is unchanged relative to the value of the second interpolation weight V.
In an example, a binary number of 9 bits is used to represent the first interpolation weight U and the second interpolation weight V that are equal to or greater than 0 and equal to or less than 1. The value of the first interpolation weight U is equal to 1 and may be expressed as 00000000, and the value of the second interpolation weight V is equal to 0.45 and may be expressed as 001110011. The highest bit of the first interpolation weight U is 1, the highest bit of the second interpolation weight V is 0, namely the value of the first interpolation weight U is equal to 1, and the value of the second interpolation weight V is more than or equal to 0 and less than 1. Correspondingly, the first low-order data u is expressed as 00000000, and the value of the first low-order data u is equal to 0; the second low order data v is 01110011, and the value of the second low order data v is equal to 0.45. At this time, the value of the first low-order data U is changed with respect to the value of the first interpolation weight U, and the value of the second low-order data V is unchanged with respect to the value of the second interpolation weight V.
In a possible implementation manner, the multiplexer 202 is configured to determine that the data to be calculated corresponding to the first multiplier 2031 is the second data to be interpolated and the data to be calculated corresponding to the third multiplier 2033 is the fourth data to be interpolated when the value of the first low-order data U changes relative to the value of the first interpolation weight U and the value of the second low-order data V does not change relative to the value of the second interpolation weight V.
The value of the first low-order data U changes relative to the value of the first interpolation weight U, and the value of the second low-order data V does not change relative to the value of the second interpolation weight V, that is, the value of the first low-order data U cannot represent the true value of the first interpolation weight U; the value of the second low-order data V may represent the true value of the second interpolation weight V. Therefore, the weight input data determined according to the first low-bit data U of m-1 bit is multiplied with the data to be operated, and the corresponding multiplication result may be changed with respect to the weight input data determined according to the first interpolation weight U of m bit.
When the value of the first interpolation weight U is equal to 1 and the value of the second interpolation weight V is equal to or greater than 0 and less than 1, the bilinear interpolation processing result result_abcd=b× (1-V) +d×v can be determined according to the above formula (4). Because the value of the first interpolation weight U is equal to 1, the value of the first low-order data U is equal to 0, and the value of the first low-order data U is changed relative to the value of the first interpolation weight U; the value of the second interpolation weight V is larger than or equal to 0 and smaller than 1, and the value of the second low-order data V is unchanged relative to the value of the second interpolation weight V. Therefore, in order to ensure the accuracy of the bilinear interpolation processing performed by the apparatus 200, the first multiplexer 2021 determines that the data to be operated corresponding to the first multiplier 2031 is the second data to be interpolated b, and the third multiplexer 2023 determines that the data to be operated corresponding to the third multiplier 2033 is the fourth data to be interpolated d. At this time, the bilinear interpolation processing result result_abcd=b× (1-V) +d×v=b× (1-V) +d×v can be ensured.
In one possible implementation, the multiplexer 202 is configured to determine that the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U, and that the value of the second low-order data V is changed relative to the value of the second interpolation weight V when the most significant bit of the first interpolation weight U is 0 and the most significant bit of the second interpolation weight V is 1.
When the highest bit of the first interpolation weight U is 0 and the highest bit of the second interpolation weight V is 1, namely the value of the first interpolation weight U is more than or equal to 0 and less than 1, the value of the second interpolation weight V is equal to 1. At this time, the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data V is changed relative to the value of the second interpolation weight V.
In an example, a binary number of 9 bits is used to represent the first interpolation weight U and the second interpolation weight V that are equal to or greater than 0 and equal to or less than 1. The value of the first interpolation weight U is equal to 0.75, which can be expressed as 011000000, and the value of the second interpolation weight V is equal to 1, which can be expressed as: 100000000. the highest bit of the first interpolation weight U is 0, the highest bit of the second interpolation weight V is 1, namely the value of the first interpolation weight U is more than or equal to 0 and less than 1, and the value of the second interpolation weight V is equal to 1. Correspondingly, the first low-order data u is 11000000, and the value of the first low-order data u is equal to 0.75; the second low-order data v is represented as 00000000, and the value of the second low-order data v is equal to 0. Therefore, the value of the first low-order data U is unchanged from the value of the first interpolation weight U, and the value of the second low-order data V is changed from the value of the second interpolation weight V.
In a possible implementation manner, the multiplexer 202 is configured to determine that the data to be calculated corresponding to the first multiplier 2031 is the third data to be interpolated and the data to be calculated corresponding to the second multiplier 2032 is the fourth data to be interpolated when the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U and the value of the second low-order data V is changed relative to the value of the second interpolation weight V.
The value of the first low-order data U is unchanged relative to the value of the first interpolation weight U, and the value of the second low-order data V is changed relative to the value of the second interpolation weight V, that is, the value of the first low-order data U may represent the true value of the first interpolation weight U; the value of the second low-order data V cannot represent the true value of the second interpolation weight V. Therefore, the weight input data determined according to the second low-bit data V of m-1 bit is multiplied with the data to be operated, and the corresponding multiplication result may be changed with respect to the weight input data determined according to the second interpolation weight V of m bit.
When the value of the first interpolation weight U is equal to or greater than 0 and less than 1 and the value of the second interpolation weight V is equal to 1, according to the above formula (4), the bilinear interpolation processing result result_abcd=c× (1-U) +d×u can be determined. Because the value of the first interpolation weight U is greater than or equal to 0 and smaller than 1, the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U; the value of the second interpolation weight V is equal to 1, the value of the second low-order data V is equal to 0, and the value of the second interpolation weight V is changed. Therefore, in order to ensure the accuracy of the bilinear interpolation processing performed by the apparatus 200, the first multiplexer 2021 determines that the data to be operated corresponding to the first multiplier 2031 is the third data to be interpolated c, and the second multiplexer 2022 determines that the data to be operated corresponding to the second multiplier 2032 is the fourth data to be interpolated d. At this time, the bilinear interpolation processing result result_abcd=c× (1-U) +d×u=c× (1-U) +d×u can be ensured.
In one possible implementation, the multiplexer 202 is configured to determine that the value of the first low-order data U changes with respect to the value of the first interpolation weight U and the value of the second low-order data V changes with respect to the value of the second interpolation weight V when the most significant bits of the first interpolation weight U and the second interpolation weight V are both 1.
When the highest bit of the first interpolation weight U and the second interpolation weight V is 1, namely the values of the first interpolation weight U and the second interpolation weight V are equal to 1. At this time, the value of the first low-order data U changes with respect to the value of the first interpolation weight U, and the value of the second low-order data V changes with respect to the value of the second interpolation weight V.
In an example, a binary number of 9 bits is used to represent the first interpolation weight U and the second interpolation weight V that are equal to or greater than 0 and equal to or less than 1. The value of the first interpolation weight U is equal to 1 and can be expressed as 100000000; the value of the second interpolation weight V is equal to 1 and may be represented as 100000000. The highest bit of the first interpolation weight U and the second interpolation weight V is 1, namely the values of the first interpolation weight U and the second interpolation weight V are equal to 1. Correspondingly, the first low-order data u is expressed as 00000000, and the value of the first low-order data u is equal to 0; the second low-order data v is represented as 00000000, and the value of the second low-order data v is equal to 0. At this time, the values of the first low-order data U and the second low-order data V are changed with respect to the values of the first interpolation weight U and the second interpolation weight V.
In one possible implementation, the multiplexer 202 is configured to determine that the data to be operated corresponding to the first multiplier 2031 is fourth data to be interpolated when the value of the first low-order data U changes relative to the value of the first interpolation weight U and the value of the second low-order data V changes relative to the value of the second interpolation weight V.
The value of the first low-order data U changes relative to the value of the first interpolation weight U, and the value of the second low-order data V changes relative to the value of the second interpolation weight V, that is, the values of the first low-order data U and the second low-order data V cannot represent the true values of the first interpolation weight U and the second interpolation weight V. Therefore, the weight input data determined according to the first low-bit data U and the second low-bit data V of m-1 bit are multiplied with the data to be operated, and the multiplication result corresponding to the weight input data determined according to the first interpolation weight U and the second interpolation weight V of m bit is multiplied with the data to be operated, and may change.
When the values of the first interpolation weight and the second interpolation weight are both equal to 1, according to the above formula (4), the bilinear interpolation processing result result_abcd=d can be determined. Because the values of the first interpolation weight and the second interpolation weight are equal to 1, the values of the first low-order data U and the second low-order data V are equal to 0, the value of the first low-order data U changes relative to the value of the first interpolation weight U, and the value of the second low-order data V changes relative to the value of the second interpolation weight V. Therefore, in order to ensure the accuracy of the bilinear interpolation processing performed by the apparatus 200, the data to be operated corresponding to the first multiplier 2031 is determined to be the fourth data to be interpolated d by the first multiplexer 2021. At this time, the bilinear interpolation processing result result_abcd=d can be ensured.
In one possible implementation, the plurality of data to be interpolated are four pixel data of a 2×2 structure requiring bilinear interpolation processing in the target image.
The apparatus 200 for bilinear difference may be applied to data filtering processing in a high performance processor, such as a texture unit in a graphics processor (graphics processing unit, GPU) or an arithmetic logic unit requiring filtering. Accordingly, the plurality of data to be interpolated may be four pixel data of a 2×2 structure requiring bilinear interpolation processing in the target image.
In one example, when a target image needs to be enlarged, each pixel on the target image needs to be moved in a particular direction according to a corresponding scaling factor. When amplified by a non-integer scaling factor, there will be some pixel locations where there are not appropriate pixel values, thus creating a hole defect. At this time, the holes need to be allocated with appropriate RGB or gray values so that the amplified target image to be output does not include pixels having no pixel value. The pixel data corresponding to four pixel points of a 2×2 structure around the hole can be obtained with the hole as the center, and then the pixel data is input into the multiplier 203 as the data to be interpolated, and the bilinear interpolation processing is performed, so as to determine the corresponding bilinear interpolation processing result, that is, the pixel data corresponding to the hole, thereby distributing corresponding RGB or gray values for the hole.
The computing device for performing bilinear interpolation processing in the embodiment of the disclosure determines weight input data corresponding to each multiplier by using first low-order data U and second low-order data V through a weight input module, and inputs the weight input data into the corresponding multiplier, wherein the first low-order data U is low-order m-1 bit of a first interpolation weight U, the second low-order data V is low-order m-1 bit of a second interpolation weight V, and the first interpolation weight U and the second interpolation weight V are m bits, and are greater than or equal to 0 and less than or equal to 1; the weight input data determined according to the first low-bit data u and the second low-bit data v of m-1 bit has the number of bits of m-1 bit, so that the input bit width of the multiplier can be reduced from m bit to m-1 bit. The multiplexer is utilized to respectively determine the data to be operated corresponding to at least one multiplier according to the values of the first interpolation weight U and the second interpolation weight V, wherein the data to be operated corresponding to each multiplier is one of a plurality of data to be interpolated which need bilinear interpolation processing, and the data to be operated is input into the corresponding multiplier, so that the multiplication result corresponding to the multiplier can be adjusted, and the accuracy of the bilinear interpolation processing result is further ensured. Through the multipliers, corresponding multiplication operation can be performed according to the data to be operated and the weight input data, multiplication operation results are determined, and then through the adders, summation operation can be performed on the multiplication operation results corresponding to the multipliers, and bilinear interpolation processing results are determined. By reducing the input bit width of the multiplier and adjusting the logic of the data to be interpolated input into the multiplier through the multiplexer, the circuit area of the whole device can be reduced, and the hardware resource consumption for bilinear interpolation processing is saved.
It should be noted that, although the circuit configuration of the arithmetic device for performing bilinear interpolation processing is described above by taking fig. 2 and 3 as examples, those skilled in the art will understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set the specific structure of the computing device for performing bilinear interpolation processing according to personal preference and/or practical application scene, and the circuits and the electrical elements in the computing device can be adaptively increased, decreased and replaced, so long as bilinear interpolation processing can be performed based on the above-mentioned process.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (12)
1. An arithmetic device for performing bilinear interpolation processing, comprising: the system comprises a weight input module, a multiplexer, a plurality of multipliers and an adder, wherein the input bit width of the multipliers is m-1 bit;
The weight input module is configured to determine weight input data corresponding to each multiplier by using first low-level data U and second low-level data V, and input the weight input data to the corresponding multiplier, where the first low-level data U is a low-level m-1 bit of a first interpolation weight U, the second low-level data V is a low-level m-1 bit of a second interpolation weight V, the first interpolation weight U and the second interpolation weight V are m bits, and are greater than or equal to 0 and less than or equal to 1, and m is a bit number of a binary number corresponding to the first interpolation weight U and the second interpolation weight V;
the multiplexer is configured to determine data to be operated corresponding to at least one multiplier according to the first interpolation weight U and the second interpolation weight V, and input the data to be operated into the corresponding multiplier, where the data to be operated corresponding to each multiplier is one of a plurality of data to be interpolated that need to be subjected to the bilinear interpolation processing;
the multiplier is used for carrying out corresponding multiplication according to the data to be calculated and the weight input data, and determining a multiplication result;
The adder is used for carrying out summation operation on the multiplication operation results corresponding to the multipliers and determining bilinear interpolation processing results corresponding to the plurality of data to be interpolated;
wherein the multiplexer is specifically for: determining the value change of the first low-order data U relative to the first interpolation weight U and the value change of the second low-order data V relative to the second interpolation weight V according to the highest bit of the first interpolation weight U and the highest bit of the second interpolation weight V; and determining the data to be operated corresponding to at least one multiplier according to the value change of the first low-order data U relative to the first interpolation weight U, the value change of the second low-order data V relative to the second interpolation weight V and the plurality of data to be interpolated.
2. The apparatus of claim 1, wherein the plurality of multipliers comprises: a first multiplier, a second multiplier, a third multiplier, and a fourth multiplier, the weight input data comprising: the first weight input data, the second weight input data, the third weight input data and the fourth weight input data;
the weight input module inputs the first weight input data of the first multiplier as 1-u and 1-v;
The weight input module inputs the second weight input data of the second multiplier as u and 1-v;
the weight input module inputs the third weight input data of the third multiplier as 1-u and v;
the weight input module inputs the fourth weight input data of the fourth multiplier as u and v.
3. The apparatus of claim 2, wherein the plurality of data to be interpolated comprises: the first data to be interpolated, the second data to be interpolated, the third data to be interpolated and the fourth data to be interpolated.
4. The apparatus of claim 3, wherein the multiplexer is configured to determine that the value of the first low order data U is unchanged relative to the value of the first interpolation weight U and the value of the second low order data V is unchanged relative to the value of the second interpolation weight V when the most significant bits of the first interpolation weight U and the second interpolation weight V are both 0.
5. The apparatus of claim 4, wherein the multiplexer is configured to determine that the data to be operated corresponding to the first multiplier is the first data to be interpolated, the data to be operated corresponding to the second multiplier is the second data to be interpolated, and the data to be operated corresponding to the third multiplier is the third data to be interpolated when the value of the first low data U is unchanged relative to the value of the first interpolation weight U and the value of the second low data V is unchanged relative to the value of the second interpolation weight V.
6. The apparatus of claim 3, wherein the multiplexer is configured to determine that the value of the first low-order data U changes relative to the value of the first interpolation weight U and that the value of the second low-order data V does not change relative to the value of the second interpolation weight V when the most significant bit of the first interpolation weight U is 1 and the most significant bit of the second interpolation weight V is 0.
7. The apparatus of claim 6, wherein the multiplexer is configured to determine the data to be calculated corresponding to the first multiplier as the second data to be interpolated and the data to be calculated corresponding to the third multiplier as the fourth data to be interpolated when the value of the first low data U changes relative to the value of the first interpolation weight U and the value of the second low data V does not change relative to the value of the second interpolation weight V.
8. The apparatus of claim 3, wherein the multiplexer is configured to determine that the value of the first low-order data U is unchanged relative to the value of the first interpolation weight U and that the value of the second low-order data V is changed relative to the value of the second interpolation weight V when the most significant bit of the first interpolation weight U is 0 and the most significant bit of the second interpolation weight V is 1.
9. The apparatus of claim 8, wherein the multiplexer is configured to determine the data to be calculated corresponding to the first multiplier as the third data to be interpolated and the data to be calculated corresponding to the second multiplier as the fourth data to be interpolated when the value of the first low data U is unchanged relative to the value of the first interpolation weight U and the value of the second low data V is changed relative to the value of the second interpolation weight V.
10. The apparatus of claim 3, wherein the multiplexer is configured to determine that the value of the first low order data U changes relative to the value of the first interpolation weight U and that the value of the second low order data V changes relative to the value of the second interpolation weight V when the most significant bits of the first interpolation weight U and the second interpolation weight V are each 1.
11. The apparatus of claim 10, wherein the multiplexer is configured to determine the data to be calculated corresponding to the first multiplier as the fourth data to be interpolated when the value of the first low-order data U changes relative to the value of the first interpolation weight U and the value of the second low-order data V changes relative to the value of the second interpolation weight V.
12. The apparatus according to any one of claims 1 to 11, wherein the plurality of data to be interpolated are four pixel data of a 2 x 2 structure requiring bilinear interpolation processing in the target image.
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