CN115622017A - Reverse protection circuit and load switch - Google Patents

Abstract

The invention provides a reverse protection circuit and a load switch, which relate to the technical field of reverse protection circuits and comprise the following components: the reverse voltage detection circuit, the power tube P4 and the power tube turn-off circuit; the power tube P4 is used for outputting power from the voltage input terminal VIN to the voltage output terminal VOUT; the reverse voltage detection and selection circuit is used for comparing the voltage of the voltage input end VIN with the voltage of the voltage output end VOUT, and when the difference value between the voltage of the voltage output end VOUT and the voltage of the voltage input end VIN is larger than the reverse voltage detection threshold value, the reverse protection can be completed by adjusting the switch of the power tube turn-off circuit to be switched off and only arranging one power tube, so that the integration cost of the reverse protection circuit is reduced.

Description

Reverse protection circuit and load switch

Technical Field

The present invention relates to the field of reverse protection circuits, and in particular, to a reverse protection circuit and a load switch.

Background

The reverse protection circuit is a very important module of the load switch, for example, the reverse protection circuit can prevent current from flowing from the voltage output terminal VOUT to the voltage input terminal VIN to prevent the power tube from being damaged. Existing reverse protection circuits include several types: the first type is a reverse protection circuit based on a diode, and the diode is low in cost, easy to integrate and suitable for application scenes of small current. However, in high current applications, a small voltage drop from the input to the output of the load switch is required, and the large forward voltage of the diode reduces the power efficiency. Compared with a diode, the reverse protection circuit based on two power tubes connected back to back reduces the voltage drop from the voltage input end VIN to the voltage output end VOUT, but the two power tubes occupy a large area, and the integration cost is increased. The third is a reverse protection circuit based on reverse voltage detection, which takes the starting voltage VTH _ P of the PMOS transistor as a reverse voltage detection threshold, and turns off the power transistor when the voltage difference between the voltage output terminal VOUT and the voltage input terminal VIN is greater than | VTH _ P |. However, in the reverse protection circuit, the threshold of the reverse voltage detection is the threshold voltage VTH _ P with a larger value, and the on-resistance of the power tube is small, so that the reverse current of the load switch of the power tube is larger, and the power tube is easily burnt by the larger reverse current. Therefore, a reverse protection circuit which is easy to integrate and can timely turn off the power transistor is needed.

Disclosure of Invention

The invention aims to provide a reverse protection circuit and a load switch, wherein the reverse protection circuit is applied to the load switch, reverse protection can be completed by only arranging one power tube, and the integration cost of the reverse protection circuit is reduced.

In order to achieve the purpose, the invention provides the following scheme:

a reverse protection circuit comprising: the reverse voltage detection circuit, the power tube P4 and the power tube turn-off circuit;

the drain electrode of the power tube P4 and the first port of the reverse voltage selecting circuit are both connected with a voltage input end VIN;

the source electrode of the power tube P4 and the second port of the reverse voltage detection circuit are both connected with a voltage output end VOUT;

the grid electrode of the power tube P4 is connected with the first port of the power tube turn-off circuit;

the back gate of the power tube P4 is connected to the third port of the reverse voltage selection circuit and the second port of the power tube turn-off circuit respectively;

a fourth port of the reverse voltage selection circuit is connected with a third port of the power tube turn-off circuit;

the fifth port of the reverse voltage selection circuit is used for controlling the on-off state of a switch S in the power tube turn-off circuit;

the fourth port of the power tube turn-off circuit is connected with the output end of the driving circuit;

the power tube P4 is used for outputting power from a voltage input terminal VIN to a voltage output terminal VOUT;

the reverse voltage detection circuit is used for comparing the voltage of the voltage input end VIN with the voltage of the voltage output end VOUT, and adjusting the switch of the power tube turn-off circuit to be switched off when the difference value between the voltage of the voltage output end VOUT and the voltage of the voltage input end VIN is larger than a reverse voltage detection threshold value.

Optionally, the power tube turn-off circuit further includes: a PMOS tube P3;

a connection point obtained after the drain electrode of the PMOS tube P3 is connected with the first end of the switch S is a first port of the power tube turn-off circuit;

the source electrode of the PMOS tube P3 is a second port of the power tube turn-off circuit;

the grid electrode of the PMOS tube P3 is a third port of the power tube turn-off circuit;

and the second end of the switch S is a fourth port of the power tube turn-off circuit.

Optionally, the reverse voltage selecting circuit includes: a reverse voltage detection circuit and a back gate potential selection circuit of the power tube;

a connection point obtained after the forward input end of the reverse voltage detection circuit is connected with the first port of the back gate potential selection circuit of the power tube is the first port of the reverse voltage detection circuit;

a connection point obtained after the negative input end of the reverse voltage detection circuit is connected with the second port of the back gate potential selection circuit of the power tube is the second port of the reverse voltage detection circuit;

a connection point obtained after the forward output end of the reverse voltage detection circuit is connected with the third port of the back gate potential selection circuit of the power tube is a fourth port of the reverse voltage detection circuit;

a connection point obtained after the reverse output end of the reverse voltage detection circuit is connected with the fourth port of the back gate potential selection circuit of the power tube is a fifth port of the reverse voltage detection circuit;

a fifth port of the back gate potential selection circuit of the power tube is a third port of the reverse voltage detection circuit;

the reverse voltage detection circuit is used for comparing the voltage of the voltage input end VIN with the voltage of the voltage output end VOUT;

the back gate potential selection circuit of the power tube is used for selecting the maximum voltage of the voltage at the voltage input end VIN and the voltage at the voltage output end VOUT as the back gate voltage of the power tube P4.

Optionally, the back gate potential selection circuit of the power transistor includes: PMOS pipe P1 and PMOS pipe P2;

the drain electrode of the PMOS tube P1 is a first port of a back gate potential selection circuit of the power tube;

a connection point obtained by connecting the source electrode of the PMOS transistor P1 and the source electrode of the PMOS transistor P2 is a fifth port of the back gate potential selection circuit of the power transistor;

the grid electrode of the PMOS tube P1 is a fourth port of the back gate potential selection circuit of the power tube;

the drain electrode of the PMOS tube P2 is a second port of the back gate potential selection circuit of the power tube;

the gate of the PMOS transistor P2 is a third port of the back gate potential selection circuit of the power transistor.

Optionally, the reverse voltage detection circuit includes: a PMOS tube P5, a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, a PMOS tube P10, a PMOS tube P11, a PMOS tube P12, a PMOS tube P13, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, an NMOS tube N6, an NMOS tube N7, an NMOS tube N8, an NMOS tube N9 and a bias current unit;

a connection point obtained by connecting the source electrode of the PMOS tube P5 with the source electrode of the PMOS tube P6 is a negative input end of the reverse voltage detection circuit;

the back gate of the PMOS transistor P5, the back gate of the PMOS transistor P6, the back gate of the PMOS transistor P7, the back gate of the PMOS transistor P8, the back gate of the PMOS transistor P11, the source of the PMOS transistor P11, the back gate of the PMOS transistor P12, the source of the PMOS transistor P12, the back gate of the PMOS transistor P13, and the source of the PMOS transistor P13 are all connected to the back gate of the power transistor P4;

a connection point obtained by connecting the source electrode of the PMOS transistor P7, the source electrode of the PMOS transistor P8, the source electrode of the PMOS transistor P9, the back gate of the PMOS transistor P9, the source electrode of the PMOS transistor P10 and the back gate of the PMOS transistor P10 is a forward input end of the reverse voltage detection circuit;

the grid electrode of the PMOS tube P5, the grid electrode of the PMOS tube P6, the drain electrode of the PMOS tube P6, the grid electrode of the PMOS tube P7, the drain electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P8 are connected with one end of the bias current unit;

the other end of the bias current unit, the source of the NMOS transistor N1, the source of the NMOS transistor N2, the source of the NMOS transistor N3, the source of the NMOS transistor N4, the source of the NMOS transistor N5, the source of the NMOS transistor N6, the source of the NMOS transistor N7, the source of the NMOS transistor N8, the source of the NMOS transistor N9, the back gate of the NMOS transistor N1, the back gate of the NMOS transistor N2, the back gate of the NMOS transistor N3, the back gate of the NMOS transistor N4, the back gate of the NMOS transistor N5, the back gate of the NMOS transistor N6, the back gate of the NMOS transistor N7, the back gate of the NMOS transistor N8, and the back gate of the NMOS transistor N9 are all grounded;

the drain electrode of the PMOS tube P5, the drain electrode of the NMOS tube N1, the grid electrode of the NMOS tube N2, the drain electrode of the NMOS tube N3 and the grid electrode of the NMOS tube N6 are connected;

the drain electrode of the PMOS tube P8, the drain electrode of the NMOS tube N2, the grid electrode of the NMOS tube N3, the grid electrode of the NMOS tube N4, the drain electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N5 are connected;

the drain electrode of the PMOS tube P9, the grid electrode of the PMOS tube P10 and the drain electrode of the NMOS tube N5 are connected;

the drain electrode of the PMOS tube P10, the drain electrode of the NMOS tube N6, the grid electrode of the PMOS tube P11 and the grid electrode of the NMOS tube N7 are connected;

the drain electrode of the PMOS tube P11, the drain electrode of the NMOS tube N7, the grid electrode of the PMOS tube P12 and the grid electrode of the NMOS tube N8 are connected;

a connection point obtained after the drain electrode of the PMOS tube P12, the drain electrode of the NMOS tube N8, the grid electrode of the PMOS tube P13 and the grid electrode of the NMOS tube N9 are connected is a forward output end of the reverse voltage detection circuit;

and a connection point obtained by connecting the drain electrode of the PMOS tube P13 with the drain electrode of the NMOS tube N9 is a reverse output end of the reverse voltage detection circuit.

Optionally, the ratio of the width-to-length ratio of the PMOS transistor P5 to the width-to-length ratio of the PMOS transistor P6 is 1:1;

the ratio of the width-length ratio of the PMOS pipe P7 to the width-length ratio of the PMOS pipe P8 is 1:1;

the ratio of the width-length ratio of the PMOS pipe P9 to the width-length ratio of the PMOS pipe P10 is 1:6;

the ratio of the width-length ratio of the NMOS tube N1 to the width-length ratio of the NMOS tube N2 is 1:1;

the ratio of the width-length ratio of the NMOS tube N3 to the width-length ratio of the NMOS tube N4 is 1:1;

the ratio of the width-length ratio of the NMOS tube N5 to the width-length ratio of the NMOS tube N6 is 1:6.

A load switch employs the reverse protection circuit.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

the invention provides a reverse protection circuit and a load switch, comprising: the reverse voltage detection circuit, the power tube P4 and the power tube turn-off circuit; reverse protection can be completed by only arranging one power tube, and the integration cost of the reverse protection circuit is reduced.

In addition, in the reverse protection circuit provided by the invention, the width-to-length ratio of the PMOS tube in the reverse voltage detection circuit is adjusted, so that the reverse voltage detection threshold can be adjusted, and the situation that the reverse current of the power tube turn-off load switch is already large and the power tube is easily burnt by the large reverse current because the starting voltage VTH _ P of the PMOS tube is used as the reverse voltage detection threshold in the prior art is avoided.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

Fig. 1 is a diagram of a reverse protection circuit in embodiment 1 of the present invention;

fig. 2 is a reverse voltage detection circuit diagram in embodiment 1 of the present invention;

FIG. 3 is a graph of VOUT and VIN as a function of time for example 1;

FIG. 4 is a graph of the REV _ L signal over time in accordance with embodiment 1 of the present invention;

FIG. 5 is a graph of the REV _ H signal over time in example 1 of the present invention;

FIG. 6 is a graph showing the time-dependent variation of the SUB signal in embodiment 1 of the present invention;

FIG. 7 is a graph showing the time-dependent change of the GATE signal in example 1 of the present invention;

FIG. 8 is a graph of reverse current IRVERSE versus time in example 1 of the present invention;

fig. 9 is a circuit layout diagram of a back gate potential selection circuit PMOS transistor of a power transistor in embodiment 1 of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention aims to provide a reverse protection circuit and a load switch, wherein the reverse protection circuit is applied to the load switch, reverse protection can be completed only by arranging one power tube, and the integration cost of the reverse protection circuit is reduced.

In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description thereof.

Example 1

As shown in fig. 1, the present embodiment provides a reverse protection circuit, including: the reverse voltage detection circuit, the power tube P4 and the power tube turn-off circuit; the drain electrode of the power tube P4 and the first port of the reverse voltage selection circuit are both connected with a voltage input end VIN; the source electrode of the power tube P4 and the second port of the reverse voltage detection circuit are both connected with the voltage output end VOUT; the grid electrode of the power tube P4 is connected with the first port of the power tube turn-off circuit; the back gate of the power tube P4 is respectively connected with the third port of the reverse voltage detection circuit and the second port of the power tube turn-off circuit; a fourth port of the reverse voltage selection circuit is connected with a third port of the power tube turn-off circuit; the fifth port of the reverse voltage selection circuit is used for controlling the on-off state of a switch S in the power tube turn-off circuit; the fourth port of the power tube turn-off circuit is connected with the output end of the driving circuit; the power tube P4 is used for outputting power from the voltage input terminal VIN to the voltage output terminal VOUT; the reverse voltage detection circuit is used for comparing the voltage of the voltage input end VIN with the voltage of the voltage output end VOUT, and when the difference value between the voltage of the voltage output end VOUT and the voltage of the voltage input end VIN is larger than a reverse voltage detection threshold value, the switch S of the power tube turn-off circuit is adjusted to be disconnected.

Specifically, the switch S is controlled to be opened and closed by the reverse terminal REV _ L of the reverse voltage detection circuit, and the switch S controls whether the output DRV of the driving circuit I2 is connected to the GATE of the power transistor P4. The reverse voltage detection circuit (RCP) is a comparator I1, compares the VIN signal with the signal of VOUT, and outputs logic control signals REV _ L and REV _ H. When the REV _ L is low and the REV _ H is high in the logic control signal, the back gate potential selection circuit of the power tube switches on the power tube P1 and switches off the power tube P2, and the back gate potential SUB of the power tube P4 is equal to VIN, that is, the highest potential is selected; on the contrary, the power transistor P1 is turned off, the power transistor P2 is turned on, and the back gate potential SUB of the power transistor P4 is equal to the potential of the voltage output terminal VOUT, that is, the highest potential is selected. The power transistor P4 is a high power PMOS, and is responsible for outputting power from the voltage input terminal VIN to the voltage output terminal VOUT. When the voltage of the voltage output end VOUT is higher than the voltage of the voltage input end VIN by a reverse voltage detection threshold value, the PMOS tube P3 pulls the grid GATE potential of the power tube P4 high, and meanwhile, the switch S disconnects the output DRV of the driving circuit I2 from the grid GATE of the power tube P4.

Wherein, the power tube turn-off circuit still includes: a PMOS tube P3; a connection point obtained after the drain electrode of the PMOS tube P3 is connected with the first end of the switch S is a first port of the power tube turn-off circuit; the source electrode of the PMOS tube P3 is a second port of the power tube turn-off circuit; the grid electrode of the PMOS tube P3 is a third port of the power tube turn-off circuit; the second end of the switch S is the fourth port of the power tube turn-off circuit.

Specifically, the reverse voltage selection circuit includes: a reverse voltage detection circuit and a back gate potential selection circuit of the power tube; a connection point obtained after a forward input end of the reverse voltage detection circuit is connected with a first port of a back gate potential selection circuit of the power tube is a first port of the reverse voltage detection circuit; a connection point obtained after the negative input end of the reverse voltage detection circuit is connected with the second port of the back gate potential selection circuit of the power tube is the second port of the reverse voltage detection circuit; a connection point after the forward output end of the reverse voltage detection circuit is connected with the third port of the back gate potential selection circuit of the power tube is a fourth port of the reverse voltage detection circuit; a connecting point obtained after the reverse output end of the reverse voltage detection circuit is connected with the fourth port of the back gate potential selection circuit of the power tube is a fifth port of the reverse voltage detection circuit; a fifth port of the back gate potential selection circuit of the power tube is a third port of the reverse voltage detection circuit; the reverse voltage detection circuit is used for comparing the voltage of a voltage input end VIN with the voltage of a voltage output end VOUT; the back gate potential selection circuit of the power tube is used for selecting the maximum voltage of the voltage input end VIN and the voltage output end VOUT as the back gate voltage of the power tube P4.

Specifically, the back gate potential selection circuit of the power tube comprises: PMOS pipe P1 and PMOS pipe P2; the drain electrode of the PMOS tube P1 is used as a first port of a back gate potential selection circuit of the power tube; a connection point obtained by connecting the source electrode of the PMOS tube P1 and the source electrode of the PMOS tube P2 is a fifth port of the back gate potential selection circuit of the power tube; the grid electrode of the PMOS tube P1 is a fourth port of the back gate potential selection circuit of the power tube; the drain electrode of the PMOS pipe P2 is a second port of the back gate potential selection circuit of the power pipe; the grid electrode of the PMOS pipe P2 is a third port of the back gate potential selection circuit of the power pipe.

As shown in fig. 2, the reverse voltage detection circuit includes: PMOS pipe P5, PMOS pipe P6, PMOS pipe P7, PMOS pipe P8, PMOS pipe P9, PMOS pipe P10, PMOS pipe P11, PMOS pipe P12, PMOS pipe P13, NMOS pipe N1, NMOS pipe N2, NMOS pipe N3, NMOS pipe N4, NMOS pipe N5, NMOS pipe N6, NMOS pipe N7, NMOS pipe N8, NMOS pipe N9 and bias current unit.

And a connection point obtained by connecting the source electrode of the PMOS pipe P5 and the source electrode of the PMOS pipe P6 is a negative input end of the reverse voltage detection circuit.

The back gate of the PMOS transistor P5, the back gate of the PMOS transistor P6, the back gate of the PMOS transistor P7, the back gate of the PMOS transistor P8, the back gate of the PMOS transistor P11, the source of the PMOS transistor P11, the back gate of the PMOS transistor P12, the source of the PMOS transistor P12, the back gate of the PMOS transistor P13 and the source of the PMOS transistor P13 are all connected with the back gate of the power transistor P4.

And a connection point obtained by connecting the source electrode of the PMOS tube P7, the source electrode of the PMOS tube P8, the source electrode of the PMOS tube P9, the back gate of the PMOS tube P9, the source electrode of the PMOS tube P10 and the back gate of the PMOS tube P10 is a forward input end of the reverse voltage detection circuit.

The grid electrode of the PMOS tube P5, the grid electrode of the PMOS tube P6, the drain electrode of the PMOS tube P6, the grid electrode of the PMOS tube P7, the drain electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P8 are connected with one end of the bias current unit.

The other end of the bias current unit, the source electrode of the NMOS transistor N1, the source electrode of the NMOS transistor N2, the source electrode of the NMOS transistor N3, the source electrode of the NMOS transistor N4, the source electrode of the NMOS transistor N5, the source electrode of the NMOS transistor N6, the source electrode of the NMOS transistor N7, the source electrode of the NMOS transistor N8, the source electrode of the NMOS transistor N9, the back gate of the NMOS transistor N1, the back gate of the NMOS transistor N2, the back gate of the NMOS transistor N3, the back gate of the NMOS transistor N4, the back gate of the NMOS transistor N5, the back gate of the NMOS transistor N6, the back gate of the NMOS transistor N7, the back gate of the NMOS transistor N8, and the back gate of the NMOS transistor N9 are all grounded.

The drain electrode of the PMOS tube P5, the drain electrode of the NMOS tube N1, the grid electrode of the NMOS tube N2, the drain electrode of the NMOS tube N3 and the grid electrode of the NMOS tube N6 are connected.

The drain electrode of the PMOS tube P8, the drain electrode of the NMOS tube N2, the grid electrode of the NMOS tube N3, the grid electrode of the NMOS tube N4, the drain electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N5 are connected.

The drain electrode of the PMOS tube P9, the grid electrode of the PMOS tube P10 and the drain electrode of the NMOS tube N5 are connected.

The drain electrode of the PMOS tube P10, the drain electrode of the NMOS tube N6, the grid electrode of the PMOS tube P11 and the grid electrode of the NMOS tube N7 are connected.

The drain electrode of the PMOS tube P11, the drain electrode of the NMOS tube N7, the grid electrode of the PMOS tube P12 and the grid electrode of the NMOS tube N8 are connected.

And a connection point obtained after the drain electrode of the PMOS tube P12, the drain electrode of the NMOS tube N8, the grid electrode of the PMOS tube P13 and the grid electrode of the NMOS tube N9 are connected is a forward output end of the reverse voltage detection circuit.

And a connection point obtained after the drain electrode of the PMOS pipe P13 is connected with the drain electrode of the NMOS pipe N9 is the reverse output end of the reverse voltage detection circuit.

Specifically, the ratio of the width-to-length ratio of the PMOS transistor P5 to the width-to-length ratio of the PMOS transistor P6 is 1:1; the ratio of the width-length ratio of the PMOS pipe P7 to the width-length ratio of the PMOS pipe P8 is 1:1; the ratio of the width-length ratio of the PMOS tube P9 to the width-length ratio of the PMOS tube P10 is 1:6; the ratio of the width-length ratio of the NMOS tube N1 to the width-length ratio of the NMOS tube N2 is 1:1; the ratio of the width-length ratio of the NMOS tube N3 to the width-length ratio of the NMOS tube N4 is 1:1; the ratio of the width-length ratio of the NMOS tube N5 to the width-length ratio of the NMOS tube N6 is 1:6.

In this embodiment, the PMOS transistor P5 and the PMOS transistor P6 form a current mirror unit, and the M ratio is 1:1. The PMOS tube P7 and the PMOS tube P7 form a current mirror unit, and the M proportion of the current mirror unit is 1:1.NMOS tube N1, NMOS tube N2 and NMOS tube N6 constitute the current mirror unit, and M proportion is 1. The NMOS tube N4, the NMOS tube N3 and the NMOS tube N5 form a current mirror unit, and the proportion of M (the number of devices) is 1.PMOS pipe P9 and PMOS pipe P10 constitute the current mirror unit, and its M proportion is 1:6. The PMOS tube P11 and the NMOS tube N7 form an inverter unit. The PMOS pipe P12 and the NMOS pipe N8 form an inverter unit. The PMOS tube P13 and the NMOS tube N9 form an inverter unit. IBIAS is a bias current unit.

The operation curves of the nodes in the reverse protection circuit in this embodiment are shown in fig. 3-8, and as shown in fig. 3-8, the initial state of the signal at the voltage output terminal VOUT is not higher than the signal at the voltage input terminal VIN, and the circuit is in the normal operation state of non-reverse protection. At this time, the logic control signal REV _ L is L, the logic control signal REV _ H is H, the back GATE potential SUB signal of the logic control signal REV _ H selects the voltage input terminal VIN signal, the GATE signal is L, and there is no reverse current I _REVERSE . Then the voltage input VIN is kept unchanged, the voltage signal of the voltage output end VOUT gradually rises, and the reverse current I is generated along with the rise of the voltage signal of the voltage output end VOUT _REVERSE And also gradually increases. When the voltage signal of the voltage output end VOUT rises to VOUT-VIN>In VRCP, the back GATE potential SUB signal of the logic control signal REV _ L is H, the logic control signal REV _ H is L, VOUT is selected, the GATE GATE signal is H, and the reverse current I is _REVERSE And closing the circuit and entering a reverse protection state.

The reverse voltage detection threshold is defined as V _RCP From fig. 2, it is possible to obtain:

V _RCP ＝V _{GS_P6} -V _{GS_P7} (1)

wherein, V _{GS_P6} The grid source voltage of a PMOS pipe P6 is represented; v _{GS_P7} The gate-source voltage of the PMOS transistor P7 is shown.

If the PMOS transistor P6 and the PMOS transistor P7 operate in the saturation region, neglecting the channel length modulation effect, according to the formula (1), it can be obtained:

in the formula (2), μ _P Is the surface mobility (cm) of a P-channel device ² /V·s)，C _OX Is the capacitance (F/cm) of the gate oxide per unit area ² )。I _{DS_P6} The source-drain current of the PMOS pipe P6 is shown; i is _{DS_P7} Representing the source-drain current of the PMOS pipe P7; v _{TH_P6} Represents the turn-on threshold voltage of the PMOS pipe P6; v _{TH_P7} Indicating the turn-on threshold voltage of PMOS transistor P7.

I _BIAS ＝I _{DS_P6} +I _{DS_P7} (3)

The condition that the output REV _ L or REV _ H level of the reverse voltage detection circuit (RCP) is inverted is I _{DS_P6} ＝I _{DS_P7} I.e. by

V _{TH_P6} ≈V _{TH_P7} (4)

Then, equation (2) can be converted to:

from the formula (5), it can be seen that the desired reverse voltage detection threshold V can be obtained by adjusting the current of the bias current unit, the width/length ratio of the PMOS transistor P6, or the width/length ratio of the PMOS transistor P7 _RCP 。

According to the inventionThe reverse voltage detection circuit (RCP) has simple structure and small size; good device matching can be easily achieved in layout design; the resulting reverse voltage detection threshold (VRCP) can also be designed to be small. In addition, the back gate potential selection circuit of the power tube is very simple, and only two PMOS tubes are needed. Through the outputs REV _ L and REV _ H of the reverse voltage detection circuit (RCP), the PMOS transistor P1 and the PMOS transistor P2 can control the back gate of the power transistor to select the highest potential. If VOUT-VIN>V _RCP If yes, SUB selects VOUT; otherwise, SUB selects VIN. In layout design, as shown in fig. 4, P1 and P2 in a back gate potential selection circuit of a power tube are respectively placed at two sides of the power tube P4 to form a symmetrical structure.

Example 2

This embodiment provides a load switch to which a reverse protection circuit as described in embodiment 1 is applied.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. Meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (7)

1. A reverse protection circuit, comprising:

the reverse voltage detection circuit, the power tube P4 and the power tube turn-off circuit;

the drain electrode of the power tube P4 and the first port of the reverse voltage selection circuit are both connected with a voltage input end VIN;

the source electrode of the power tube P4 and the second port of the reverse voltage detection circuit are both connected with a voltage output end VOUT;

the grid electrode of the power tube P4 is connected with the first port of the power tube turn-off circuit;

the back gate of the power tube P4 is connected to the third port of the reverse voltage selection circuit and the second port of the power tube turn-off circuit respectively;

a fourth port of the reverse voltage selecting circuit is connected with a third port of the power tube turn-off circuit;

a fifth port of the reverse voltage detection and selection circuit is used for controlling the on-off state of a switch S in the power tube turn-off circuit;

the fourth port of the power tube turn-off circuit is connected with the output end of the driving circuit;

the power tube P4 is used for outputting power from a voltage input end VIN to a voltage output end VOUT;

the reverse voltage detection circuit is used for comparing the voltage of the voltage input end VIN with the voltage of the voltage output end VOUT, and adjusting the switch of the power tube turn-off circuit to be switched off when the difference value between the voltage of the voltage output end VOUT and the voltage of the voltage input end VIN is larger than a reverse voltage detection threshold value.

2. The reverse protection circuit of claim 1, wherein the power tube turn-off circuit further comprises:

a PMOS tube P3;

a connection point obtained after the drain electrode of the PMOS tube P3 is connected with the first end of the switch S is a first port of the power tube turn-off circuit;

the source electrode of the PMOS tube P3 is a second port of the power tube turn-off circuit;

the grid electrode of the PMOS tube P3 is a third port of the power tube turn-off circuit;

and the second end of the switch S is a fourth port of the power tube turn-off circuit.

3. The reverse protection circuit of claim 1, wherein the reverse voltage selection circuit comprises:

a reverse voltage detection circuit and a back gate potential selection circuit of the power tube;

a connection point obtained after the forward input end of the reverse voltage detection circuit is connected with the first port of the back gate potential selection circuit of the power tube is the first port of the reverse voltage detection circuit;

a connection point obtained after the negative input end of the reverse voltage detection circuit is connected with the second port of the back gate potential selection circuit of the power tube is the second port of the reverse voltage detection circuit;

a connection point obtained after the forward output end of the reverse voltage detection circuit is connected with the third port of the back gate potential selection circuit of the power tube is a fourth port of the reverse voltage detection circuit;

a connection point obtained after the reverse output end of the reverse voltage detection circuit is connected with the fourth port of the back gate potential selection circuit of the power tube is a fifth port of the reverse voltage detection circuit;

a fifth port of the back gate potential selection circuit of the power tube is a third port of the reverse voltage detection circuit;

the reverse voltage detection circuit is used for comparing the voltage of the voltage input end VIN with the voltage of the voltage output end VOUT;

the back gate potential selection circuit of the power tube is used for selecting the maximum voltage of the voltage at the voltage input end VIN and the voltage at the voltage output end VOUT as the back gate voltage of the power tube P4.

4. The reverse protection circuit according to claim 3, wherein the back gate potential selection circuit of the power transistor comprises:

PMOS pipe P1 and PMOS pipe P2;

the drain electrode of the PMOS tube P1 is a first port of a back gate potential selection circuit of the power tube;

a connection point obtained by connecting the source electrode of the PMOS transistor P1 and the source electrode of the PMOS transistor P2 is a fifth port of the back gate potential selection circuit of the power transistor;

the grid electrode of the PMOS tube P1 is a fourth port of the back gate potential selection circuit of the power tube;

the drain electrode of the PMOS tube P2 is a second port of the back gate potential selection circuit of the power tube;

the gate of the PMOS transistor P2 is a third port of the back gate potential selection circuit of the power transistor.

5. The reverse protection circuit of claim 1, wherein the reverse voltage detection circuit comprises:

a PMOS tube P5, a PMOS tube P6, a PMOS tube P7, a PMOS tube P8, a PMOS tube P9, a PMOS tube P10, a PMOS tube P11, a PMOS tube P12, a PMOS tube P13, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, an NMOS tube N6, an NMOS tube N7, an NMOS tube N8, an NMOS tube N9 and a bias current unit;

a connection point obtained by connecting the source electrode of the PMOS tube P5 and the source electrode of the PMOS tube P6 is a negative input end of the reverse voltage detection circuit;

the back gate of the PMOS transistor P5, the back gate of the PMOS transistor P6, the back gate of the PMOS transistor P7, the back gate of the PMOS transistor P8, the back gate of the PMOS transistor P11, the source of the PMOS transistor P11, the back gate of the PMOS transistor P12, the source of the PMOS transistor P12, the back gate of the PMOS transistor P13, and the source of the PMOS transistor P13 are all connected to the back gate of the power transistor P4;

a connection point obtained by connecting the source electrode of the PMOS transistor P7, the source electrode of the PMOS transistor P8, the source electrode of the PMOS transistor P9, the back gate of the PMOS transistor P9, the source electrode of the PMOS transistor P10 and the back gate of the PMOS transistor P10 is a forward input end of the reverse voltage detection circuit;

the grid electrode of the PMOS tube P5, the grid electrode of the PMOS tube P6, the drain electrode of the PMOS tube P6, the grid electrode of the PMOS tube P7, the drain electrode of the PMOS tube P7 and the grid electrode of the PMOS tube P8 are connected with one end of the bias current unit;

the other end of the bias current unit, the source of the NMOS transistor N1, the source of the NMOS transistor N2, the source of the NMOS transistor N3, the source of the NMOS transistor N4, the source of the NMOS transistor N5, the source of the NMOS transistor N6, the source of the NMOS transistor N7, the source of the NMOS transistor N8, the source of the NMOS transistor N9, the back gate of the NMOS transistor N1, the back gate of the NMOS transistor N2, the back gate of the NMOS transistor N3, the back gate of the NMOS transistor N4, the back gate of the NMOS transistor N5, the back gate of the NMOS transistor N6, the back gate of the NMOS transistor N7, the back gate of the NMOS transistor N8, and the back gate of the NMOS transistor N9 are all grounded;

the drain electrode of the PMOS tube P5, the drain electrode of the NMOS tube N1, the grid electrode of the NMOS tube N2, the drain electrode of the NMOS tube N3 and the grid electrode of the NMOS tube N6 are connected;

the drain electrode of the PMOS tube P8, the drain electrode of the NMOS tube N2, the grid electrode of the NMOS tube N3, the grid electrode of the NMOS tube N4, the drain electrode of the NMOS tube N4 and the grid electrode of the NMOS tube N5 are connected;

the drain electrode of the PMOS tube P9, the grid electrode of the PMOS tube P10 and the drain electrode of the NMOS tube N5 are connected;

the drain electrode of the PMOS tube P10, the drain electrode of the NMOS tube N6, the grid electrode of the PMOS tube P11 and the grid electrode of the NMOS tube N7 are connected;

the drain electrode of the PMOS tube P11, the drain electrode of the NMOS tube N7, the grid electrode of the PMOS tube P12 and the grid electrode of the NMOS tube N8 are connected;

a connection point obtained after the drain electrode of the PMOS tube P12, the drain electrode of the NMOS tube N8, the grid electrode of the PMOS tube P13 and the grid electrode of the NMOS tube N9 are connected is a forward output end of the reverse voltage detection circuit;

and a connection point obtained by connecting the drain electrode of the PMOS tube P13 and the drain electrode of the NMOS tube N9 is a reverse output end of the reverse voltage detection circuit.

6. The reverse protection circuit of claim 5, wherein the ratio of the width-to-length ratio of the PMOS transistor P5 to the width-to-length ratio of the PMOS transistor P6 is 1:1;

the ratio of the width-length ratio of the PMOS tube P7 to the width-length ratio of the PMOS tube P8 is 1:1;

the ratio of the width-length ratio of the PMOS pipe P9 to the width-length ratio of the PMOS pipe P10 is 1:6;

the ratio of the width-length ratio of the NMOS tube N1 to the width-length ratio of the NMOS tube N2 is 1:1;

the ratio of the width-length ratio of the NMOS tube N3 to the width-length ratio of the NMOS tube N4 is 1:1;

the ratio of the width-length ratio of the NMOS tube N5 to the width-length ratio of the NMOS tube N6 is 1:6.

7. A load switch, characterized in that the load switch is applied with a reverse protection circuit according to any of claims 1-6.

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