CN115586921A - Method, circuit, chip and electronic device for realizing multi-bit register atomic operation - Google Patents
Method, circuit, chip and electronic device for realizing multi-bit register atomic operation Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
A method, circuit, chip, electronic device for realizing multi-bit register atomic operation, the said multi-bit register includes writing port, setting operation interface, clear operation interface; the method comprises the following steps: writing data to the multi-bit register through a write port; when the data in the multi-bit register needs to be modified, the data modification operation is directly completed once through the setting operation interface or the zero clearing operation interface. By using the scheme of the invention, the atomic access to the multi-bit register can be realized, and the influence on the normal operation of the system is avoided.
Description
Technical Field
The invention relates to the technical field of digital circuits, in particular to a method, a circuit, a chip and electronic equipment for realizing multi-bit register atomic operation.
Background
The register is a small storage area used for storing data in the CPU, and is used for temporarily storing the data participating in the operation and the operation result. The storage circuit of the register is formed by latches or flip-flops, and since one latch or flip-flop can store 1-bit binary number, an N-bit (bit) register can be formed by N latches or flip-flops. Registers are functionally divided, typically by: general purpose registers, special purpose registers, and control registers.
The number of general register bits is equal to the number of bits of the machine word length, 16 bits, and also 32 bits. Currently, in a System-On-a-Chip (SOC) or an integrated circuit, registers are mostly assembled into a group according to 32 bits. In the prior art, in order to avoid an error caused by invalidation of a previous operation due to contention access in an operation on a register in a multi-core system, a set-clear register is proposed, that is, a register implementing a set (set) and clear (clear) operation interface is provided, a bit in the register is modified through the set operation interface, and a bit in the register is cleared through the clear operation interface.
In the prior art, set and clear operation interfaces are generally provided only for single-bit registers, and corresponding operation interfaces are not provided for multi-bit registers, so that the implementation mode still cannot avoid errors introduced by multi-core contention access. For this reason, there are also products that implement the above functions for multi-bit registers, that is, the same implementation scheme as a single-bit register is adopted for each bit register in the multi-bit register, but the modification operation for the multi-bit register that provides set and clear operation interfaces not only complicates the operation of modifying the register, but also introduces a problem of larger or smaller size to the system due to different meanings represented by the multi-bit register.
Disclosure of Invention
The embodiment of the invention provides a method, a circuit, a chip and electronic equipment for realizing multi-bit register atomic operation, so as to realize atomic access to a multi-bit register and avoid influencing the normal operation of a system.
Therefore, the embodiment of the invention provides the following technical scheme:
on one hand, the embodiment of the invention provides a method for realizing multi-bit register atomic operation, wherein the multi-bit register comprises a write port, a set operation interface and a clear operation interface; the method comprises the following steps:
writing data to the multi-bit register through a write port;
when the data in the multi-bit register needs to be modified, the data modification operation is directly completed once through the setting operation interface or the zero clearing operation interface.
Optionally, the completing the data modification operation directly through the set operation interface or the clear operation interface at one time includes:
if a non-0 value needs to be given to the multi-bit register, directly writing a non-0 target value into the multi-bit register through the setting operation interface;
and if a 0 value needs to be assigned to the multi-bit register, directly writing a non-0 value through the zero clearing operation interface.
Optionally, the method further comprises:
generating a control signal according to all bit data of the multi-bit register;
generating a multi-path selection signal according to the control signal and a current operation signal, wherein the operation signal comprises: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface;
the writing of the target value other than 0 to the multi-bit register directly through the set operation interface includes:
enabling the setting operation interface and transmitting the target value which is not 0 to a data bus;
controlling the target value of the non-0 on the data bus to be written into the multi-bit register through the multi-path selection signal;
the writing of a non-0 value directly through the clear operation interface comprises:
enabling the zero clearing operation interface and transmitting non-0 data to the data bus;
and controlling to input all 0 data values to the multi-bit register through the multi-path selection signal.
In another aspect, an embodiment of the present invention further provides a circuit for implementing an atomic operation of a multi-bit register, where the circuit includes: the multi-bit register comprises a write port, a setting operation interface and a zero clearing operation interface;
the write operation module is used for outputting a write operation signal to control the write port to write data into the multi-bit register;
and the modification operation module is used for outputting a setting operation signal or a zero clearing operation signal when the data in the multi-bit register needs to be modified so as to control the setting operation interface or the zero clearing operation interface to finish data modification operation once.
Optionally, the modify operation module is specifically configured to output the set operation signal when a value other than 0 needs to be assigned to the multi-bit register, so as to control the set operation interface to write a target value other than 0 into the multi-bit register; and when a 0 value needs to be given to the multi-bit register, outputting the set operation signal to control the zero clearing operation interface to write a non-0 value into the multi-bit register.
Optionally, the circuit further comprises:
a control signal generating module, configured to generate a selection control signal according to all bit data of the multi-bit register and a current operation signal, where the operation signal includes: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface;
and the selection module is used for outputting the data on the data bus corresponding to each operation signal according to the selection control signal.
Optionally, the control signal generating module includes: the first OR gate, the first AND gate and the second AND gate;
the first OR gate inputs a plurality of paths of data input signals of the multi-bit register and outputs a judgment signal;
the first AND gate inputs the setting operation signal and the judgment signal and outputs a setting selection signal;
the second AND gate inputs the zero clearing operation signal and the judgment signal and outputs a zero clearing selection signal;
the selection module inputs the write operation signal, the setting selection signal and the zero clearing operation signal; when the write operation signal is effective, writing data into the multi-bit register through the write port; when the setting selection signal is effective, writing a target value which is not 0 into the multi-bit register through the setting operation interface; and when the zero clearing selection signal is effective, writing a non-0 value into the multi-bit register through the zero clearing operation interface.
Optionally, the selection module comprises: the third selector, the second selector and the first selector are connected in sequence;
the control end of the third selector inputs the write operation signal, and the first input end and the second input end of the third selector respectively input the multi-channel data input signal of the multi-bit register and the multi-channel data output signal of the multi-bit register and output a first data signal;
the control end of the second selector inputs the zero clearing selection signal, and the first input end and the second input end of the second selector respectively input the first data signal and all 0 data values required to be written by the zero clearing operation and output a second data signal;
the control end of the first selector inputs the setting selection signal, the first input end and the second input end of the first selector respectively input the second data signal and the multi-path data input signals of the multi-bit register, and the output end of the first selector is connected with the data input end of the multi-bit register.
Optionally, the second selector comprises: a first inverter and a third and gate;
the first inverter inputs the zero clearing selection signal;
one input end of the third AND gate is connected with the output end of the first inverter, the other input end of the third AND gate inputs the first data signal, and the output end of the third AND gate outputs the second data signal.
Optionally, the selection module comprises: the three control ends of the one-out-of-three selector respectively input the write operation signal, the setting selection signal and the zero clearing selection signal; and three input ends of the one-out-of-three selector are respectively input with a multi-path data input signal of the multi-bit register, a multi-path data output signal of the multi-bit register and an all-0 data value required to be written by the zero clearing operation, and an output end of the one-out-of-three selector is connected with a data input end of the multi-bit register.
Optionally, the selection module comprises: the second OR gate, the alternative selector, the second inverter and the fourth AND gate;
the second or gate inputs the write operation signal and the set selection signal respectively;
the control end of the alternative selector is connected with the output end of the second or gate, and the first input end and the second input end of the alternative selector are respectively input with the multi-channel data input signals of the multi-bit register and the multi-channel data output signals of the multi-bit register;
the second inverter inputs the zero clearing selection signal;
and two input ends of the fourth AND gate are respectively connected with the output end of the second phase inverter and the output end of the two-selection one selector, and the output end of the fourth AND gate is connected with the data input end of the multi-bit register.
On the other hand, the embodiment of the present invention further provides a chip, which includes the foregoing circuit for implementing the multi-bit register atomic operation.
In another aspect, an embodiment of the present invention further provides an electronic device, which includes the foregoing circuit for implementing the multi-bit register atomic operation.
According to the method, the circuit, the chip and the electronic device for realizing the multi-bit register atomic operation, aiming at the multi-bit register with the setting operation interface and the zero clearing operation interface, when data in the multi-bit register needs to be modified, the data modification operation is directly finished at one time through the setting operation interface or the zero clearing operation interface, the modification of any bit or multiple bits in the multi-bit register can be finished through one-step operation, and the real atomic operation is realized, so that errors caused by multi-core competition access are effectively avoided, and the problem of stability cannot be caused to a processor.
Drawings
FIG. 1 is a flow diagram of a method of implementing a multi-bit register atomic operation according to an embodiment of the invention;
FIG. 2 is a flow chart of a method of controlling a set operation interface and a clear operation interface in an embodiment of the present invention;
FIG. 3 is a functional block diagram of a circuit implementing an atomic operation of a multi-bit register according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating the control principle of operations in a circuit for implementing multi-bit register atomic operations according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing a detailed structure of a part of the modules and the control signal generation module in FIG. 4;
FIG. 6 is a diagram illustrating a specific structure of a circuit for implementing an atomic operation of a multi-bit register according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of an alternate construction of a second selector in the circuit of FIG. 6;
fig. 8 is a schematic diagram of another specific structure of a circuit for implementing the multi-bit register atomic operation according to the embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
An atomic operation is defined as an operation that is not split into actual operations that must be executed and completed without interruption by another task or event, i.e., it is the smallest unit of execution. For a single bit register, an atomic operation is implemented by setting a set and clear operation interface thereto.
Setting a set and clear operation interface for a multi-bit register, that is, adopting the same set and clear operation as a single-bit register for each bit in the multi-bit register, there are generally the following three implementations in the prior art:
(1) And performing three steps of reading-modifying-writing through a standard interface.
Although the set and clear operation interfaces are set in the multi-bit register, the three-step operation mode cannot guarantee atomic operation, and therefore errors caused by multi-core contention access cannot be avoided.
(2) Firstly, the operation is carried out through a set operation interface and then through a clear operation interface.
For example, register y _ reg [3:0] needs to be changed from 4'b0111 to 4' b1100. Firstly, changing a register value from 4'b0111 to 4' b1111 through a set operation interface; and changing the register value from 4'b1111 to 4' b1100 through a clear operation interface. If the multi-bit register value represents the frequency at which the processor is running, then the frequency corresponding to the middle value of 4' b1111 would exceed the frequency allowed by the voltage corresponding to the values of 4' b0111 and 4' b1100, which would introduce stability problems to the processor.
(3) Firstly, the operation is carried out through the clear operation interface and then through the set operation interface.
For example, register y _ reg [3:0] needs to be changed from 4'b0111 to 4' b1100. Firstly, changing a register value from 4'b0111 to 4' b0100 through a clear operation interface; then, the register value is changed from 4'b0100 to 4' b1100 through a set operation interface. If the multi-bit register value represents the voltage at which the processor is running, then the voltage corresponding to the intermediate value of 4' b0100 will be lower than the voltage allowed by the frequency corresponding to the values of 4' b0111 and 4' b1100, again introducing stability issues to the processor.
Obviously, the existing operation of the multi-bit register with set and clear operation interfaces is not only troublesome, but also has the problems.
For a multi-bit register having a set operation interface and a clear operation interface, when data in the multi-bit register needs to be modified, the method and circuit directly complete data modification operation through the set operation interface or the clear operation interface at one time, so as to implement real atomic operation.
Fig. 1 is a flowchart of a method for implementing an atomic operation of a multi-bit register according to an embodiment of the present invention, including the following steps:
The read-write operation of the multi-bit register with the setting operation interface and the clearing operation interface is the same as the read-write operation of the multi-bit register without the setting operation interface and the clearing operation interface, namely the read-write operation is completed through a standard read-write interface, and the description is omitted.
And 102, when the data in the multi-bit register needs to be modified, completing the data modification operation once directly through a setting operation interface or a zero clearing operation interface.
And if a non-0 value needs to be given to the multi-bit register, directly writing a non-0 target value into the multi-bit register through the setting operation interface. For example, the multi-bit register y _ reg [3:0] needs to be changed from 4'b0111 to 4' b1100, and the register is directly written into 1100 through the set operation interface, so that the data stored by the register is modified to 1100.
If a 0 value needs to be assigned to the multi-bit register, namely the multi-bit register is cleared, a non-0 value is directly written in through the clear operation interface. It should be noted that, the specific value is not required, and any bit is 1, as long as the value is not 0 written through the clear operation interface.
As shown in fig. 2, it is a flowchart of a control method for setting operation interfaces and clearing operation interfaces in the embodiment of the present invention, and includes the following steps:
And 204, enabling the zero clearing operation interface when a 0 value needs to be assigned to the multi-bit register, transmitting a non-0 data to the data bus, and controlling to input all 0 data values to the multi-bit register through the multi-path selection signal.
It should be understood that, in various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The method for realizing the atomic operation of the multi-bit register provided by the embodiment of the invention is directed at the multi-bit register with a setting operation interface and a zero clearing operation interface, when the data in the multi-bit register needs to be modified, the data modification operation is directly finished once through the setting operation interface or the zero clearing operation interface, the modification of any bit or multiple bits in the multi-bit register can be finished through one-step operation, and the real atomic operation is realized, so that the error introduced by multi-core competition access is effectively avoided, and the stability problem cannot be introduced to a processor.
Correspondingly, the invention also provides a circuit for realizing the multi-bit register atomic operation, and the circuit is a schematic block diagram of the circuit as shown in fig. 3.
The circuit includes: a multi-bit register 301, which includes a write port (write), a set operation interface (set), and a clear operation interface (clear).
The circuit further comprises: a write operation module 302 and a modify operation module 303. Wherein:
the write operation module 302 is configured to output a write operation signal to control the write port to write data into the multi-bit register;
the modification operation module 303 is configured to output a set operation signal or a clear operation signal when data in the multi-bit register needs to be modified, so as to control the set operation interface or the clear operation interface to complete data modification operation at one time. Specifically, when a non-0 value needs to be assigned to the multi-bit register 301, a set operation signal is output to control the set operation interface to write a non-0 target value to the multi-bit register; when a 0 value needs to be assigned to the multi-bit register 301, a clear operation signal is output to control the clear operation interface to write a non-0 value to the multi-bit register.
In a specific application, the operations of the write operation module 302 on the write port and the operations of the modify operation module 303 on the set operation interface and the clear operation interface may be controlled and completed by corresponding signals.
Fig. 4 is a schematic diagram illustrating a control principle of each operation in a circuit for implementing multi-bit register atomic operation according to an embodiment of the present invention.
In this embodiment, the circuit further comprises: a control signal generation module 401 and a selection module 402. Wherein:
the control signal generating module 401 is configured to generate a selection control signal according to all bit data of the multi-bit register and a current operation signal, where the operation signal includes: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface;
the selection module 402 is configured to output data on the data bus corresponding to each operation signal according to the selection control signal.
It should be noted that the block diagrams shown in fig. 3 and fig. 4 are only schematic illustrations of the principles of the present invention, and in practical applications, the modules shown in the diagrams may be integrated in the same physical entity or may be separate physical entities, which does not limit the embodiment of the present invention.
The circuit and operation of the present invention for implementing the multi-bit register atomic operation are further described in detail by using several embodiments.
Fig. 5 is a schematic diagram illustrating a specific structure of a circuit for implementing multi-bit register atomic operation according to an embodiment of the present invention.
In this embodiment, for clarity of illustration, the writing operation module 302 and the modification operation module 303 are not shown, and only signals output by these two modules, namely, a writing operation signal reg _ wr, a set interface operation signal reg _ set, and a clear interface operation signal reg _ clear, are shown. In addition, PCLK and PRESETn in fig. 5 are a clock signal and a reset signal of the multi-bit register 301, respectively. The multi-way data input signal of the multi-bit register 301 is reg _ update [ N:0], and the multi-way data output signal of the multi-bit register 301 is y _ reg [ N:0].
In this embodiment, the control signal generation module includes: a first or gate 410, a first and gate 411, and a second and gate 412. Wherein:
the first or gate 410 inputs a multi-path data input signal reg _ data [ N:0] of the multi-bit register, and outputs a judgment signal;
the first and gate 411 inputs the set operation signal reg _ set and the determination signal, and outputs a set selection signal;
the second and gate 412 inputs the clear operation signal reg _ clear and the determination signal, and outputs a clear selection signal.
In this embodiment, the selection module 402 inputs the write operation signal reg _ wr, the set selection signal, and the clear operation signal; when the write operation signal is valid, writing data into the multi-bit register 301 through the write port; writing a target value other than 0 to the multi-bit register 301 through the set operation interface when the set selection signal is active; when the clear select signal is active, a non-0 value is written to the multi-bit register 301 through the clear operation interface.
In particular implementations, the selection module 402 can have a variety of implementations, as illustrated below.
For example, in a non-limiting embodiment, the selecting module 402 may be implemented by using a one-out-of-three selector, and three control terminals of the one-out-of-three selector respectively input the write operation signal reg _ wr, the set selection signal, and the clear selection signal; the three input ends of the one-of-three selector respectively input the multi-path data input signals of the multi-bit register, the multi-path data output signals of the multi-bit register and the all 0 data value N +1'b0 (N +1 represents the number of bits of the multi-bit register, from 0 to N,' b0 represents the 0 value represented by binary coding) required to be written in the zero clearing operation, and the output end of the one-of-three selector is connected with the data input end of the multi-bit register.
By using the one-out-of-three selector, when the three control signals are invalid, the multi-path data output signal of the one-out-of-three selector output multi-bit register 301 is y _ reg [ N:0], namely the data in the multi-bit register 301 is kept unchanged; when the write operation signal reg _ wr or the set selection signal is valid, outputting a multi-channel data input signal reg _ byte [ N:0] of the multi-bit register, namely writing data corresponding to a write interface into the multi-bit register 301 or writing non-0 target data corresponding to a set operation interface; and when the clear selection signal is effective, outputting all 0 data values N +1' b0 required to be written by the clear operation. For another example, in another non-limiting embodiment, the selection module 402 may be implemented by three alternative selectors, as shown in fig. 6. The three alternative selectors are a third selector 423, a second selector 422 and a first selector 421 which are connected in sequence in fig. 6. The three alternative selectors function as follows: when the control input of the selector is 0, the selector outputs the value of the first input end, and when the control input of the selector is 1, the selector outputs the value of the second end. Wherein:
a control end of the third selector 423 inputs a write operation signal reg _ wr, and a first input end and a second input end respectively input a multi-path data input signal reg _ white [ N:0] of the multi-bit register 301 and a multi-path data output signal y _ reg [ N:0] of the multi-bit register 301, and output a first data signal;
the control end of the second selector 422 inputs the zero clearing selection signal, and the first input end and the second input end respectively input the first data signal and the all 0 data value required to be written by the zero clearing operation and output a second data signal;
the control terminal of the first selector 421 inputs the set selection signal, the first input terminal and the second input terminal respectively input the second data signal and the multi-channel data input signal reg _ data [ N:0] of the multi-bit register, and the output terminal is connected to the data input terminal of the multi-bit register 301.
The operation of the circuit for implementing the multi-bit register atomic operation according to the present invention is described in detail below with reference to fig. 6.
In the embodiment shown in FIG. 6, OR gate 410 ORs all bits of the multiple data input signals reg _ date [ n:0] of multi-bit register 301 to determine whether the data in the write channel is zero. When the reg _ data [ N:0] of the multi-path data input signals is equal to 0, the output of the OR gate is 0; when the multiple data input signals reg _ white [ N:0] are not equal to 0, the output of the OR gate is 1.
The first and gate 411 is used to determine whether a non-0 value is written through the set operation interface. When a non-0 value is written through the set operation interface, the output of the first and gate 411 is 1; otherwise, the output of the first and gate 411 is 0.
The second and gate 412 is used to determine if a non-0 value was written through the clear operation interface. When a non-0 value is written through the clear operation interface, the output of the second and gate 412 is 1; otherwise, the output of the second and gate 412 is 0.
The first selector 421 writes a target value of not 0 through the set operation interface, the output of the first and gate 411 is 1, the first selector 421 gates the multi-path data input signal reg _ date [ N:0], and the multi-bit register 301 writes the value of the multi-path data input signal reg _ date [ N:0]; otherwise, the multiplexer 301 gates the output of the second selector 422 and writes the output value of the second selector 422 to the multi-bit register 301.
The second selector 422: when a non-0 value is written through the clear operation interface, the output of the second and gate 412 is 1, the second selector 422 gates the N +1' b0 value, and the all 0 values are written into the multi-bit register 301 through the first selector 421; otherwise, the second selector 422 gates the output of the third selector 423 and writes the output to the multi-bit register 301.
The third selector 423: when the multi-bit register 301 is written through the general write port, the write operation signal reg _ wr is 1, the third selector 423 gates the multi-path data input signal reg _ white [ N:0] and writes the value of the signal into the multi-bit register 301 through the first selector 421 and the second selector 422; otherwise, the third selector 423 gates the Q value output from the multi-bit register 301 and writes the value into the multi-bit register 301, i.e., keeps the data in the multi-bit register 301 unchanged.
It should be noted that the three alternative selectors can also adopt other modified structures to achieve the same function, as shown in fig. 7, which is a schematic diagram of a modified structure of the second selector in the circuit shown in fig. 6.
In this embodiment, the second selector 422 includes: a first inverter 4221 and a third and gate 4222. The input end of the first inverter 4221 is connected to the input end of the second and gate 412 in fig. 6, and the clear selection signal is input; one input terminal of the third and gate 4222 is connected to the output terminal of the first inverter 4221, another input terminal of the third and gate 4222 is connected to the output terminal of the third selector in fig. 6, so as to input the first data signal, and the output terminal of the third and gate 4222 is the output terminal of the second selector 422, so as to output the second data signal.
Referring to fig. 6 and 7, when a non-0 value is written through the clear operation interface, the output of the first or gate 410 is 1, the clear operation signal reg _ clear is 1, the output of the second and gate 412 is 1, the output of the first inverter 4221 is 0, and after and operation is performed on the outputs of the third and gate 4222 and the third selector 423, an N + 1-bit all-0 value is generated and written into the multi-bit register 301, so that the clear operation is achieved. When a target value other than 0 is written through the set operation interface, the output of the first or gate 410 is 1, the set operation signal reg _ set is 1, the first and gate 411 outputs a set selection signal, and the first selector 421 gates the multi-path data input signal reg _ date [ N:0] to write the target value other than 0 into the multi-path register 301.
Referring to fig. 8, fig. 8 is a schematic diagram of another specific structure of a circuit for implementing the multi-bit register atomic operation according to the embodiment of the present invention.
In this embodiment, the selection module includes: a second or gate 431, an alternative selector 432, a second inverter 433, and a fourth and gate 434. Wherein:
the second or gate 431 inputs the write operation signal reg _ wr and the set selection signal output by the first and gate 411 respectively;
the control terminal of the one-out selector 432 is connected with the output terminal of the second or gate 431, and the first input terminal and the second input terminal of the one-out selector 432 are respectively inputted with the multi-channel data input signal reg _ data [ N:0] of the multi-bit register 301 and the multi-channel data output signal y _ reg [ N:0] of the multi-bit register 301;
the second inverter 433 inputs the zero clearing selection signal output by the second and gate 422;
two input ends of the fourth and gate 434 are respectively connected to the output end of the second inverter 433 and the output end of the two-select-one selector 432, and an output end of the fourth and gate 434 is connected to a data input end of the multi-bit register 301.
The operation of the circuit of this embodiment will be described in detail below with reference to fig. 8.
When the multi-bit register 301 is written through the general write port, the write operation signal reg _ wr is 1, the set operation signal reg _ set and the clear operation signal reg _ clear are 0, the output of the second and gate 412 is 0, and the output of the second inverter 433 is 1. The one-out selector 432 gates the multiple data input signals reg _ white [ N:0] and outputs the signal to the fourth AND gate 434, and the value of the multiple data input signals reg _ white [ N:0] is written into the multi-bit register 301 through the fourth AND gate 434.
When a target value other than 0 is written through the set operation interface, the set operation signal reg _ set is 1, the write operation signal reg _ wr and the clear operation signal reg _ clear are 0, the output of the second inverter 433 is 1, and after and operation is performed on the outputs of the fourth and gate 434 and the multiplexer 432, the output of the fourth and gate 434 holds the output value of the multiplexer 432, so that the purpose of writing a non-0 value at the time of setting is achieved.
When a non-0 value is written through the clear operation interface, the output of the first or gate 410 is 1, the clear operation signal reg _ clear is 1, the write operation signal reg _ wr and the set operation signal reg _ set are 0, the output of the second inverter 433 is 0, and after performing and operation with the output of the multiplexer 432, a full 0 value of N +1 bits is generated and written into the multi-bit register 301, thereby achieving the purpose of clear.
The circuit for realizing the atomic operation of the multi-bit register provided by the embodiment of the invention is directed at the multi-bit holding register with a setting operation interface and a zero clearing operation interface, when the data in the multi-bit register needs to be modified, the data modification operation is directly finished once through the setting operation interface or the zero clearing operation interface, the modification of any bit or multiple bits in the multi-bit register can be finished through one-step operation, and the real atomic operation is realized, so that the error introduced by multi-core competition access is effectively avoided, and the stability problem cannot be introduced to a processor.
The scheme of the invention can simply and conveniently realize the modification of the data in the multi-bit register, and the circuit has simple structure and low cost.
Correspondingly, the embodiment of the invention also provides a chip which comprises the circuit for realizing the multi-bit register atomic operation.
Correspondingly, the embodiment of the invention also provides an electronic device, which comprises the circuit for realizing the multi-bit register atomic operation.
In a specific implementation, the multiplier digital circuit for memory calculation may correspond to a Chip in a network device, such as a System-On-a-Chip (SoC), a baseband Chip, a Chip module, and the like.
In specific implementation, regarding each module/unit included in each apparatus and product described in the foregoing embodiments, it may be a software module/unit, or may also be a hardware module/unit, or may also be a part of the software module/unit and a part of the hardware module/unit.
For example, for each device or product applied to or integrated into a chip, each module/unit included in the device or product may be implemented by hardware such as a circuit, or at least a part of the module/unit may be implemented by a software program running on a processor integrated within the chip, and the rest (if any) part of the module/unit may be implemented by hardware such as a circuit; for each device or product applied to or integrated with the chip module, each module/unit included in the device or product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules/units may be implemented by using a software program running on a processor integrated within the chip module, and the rest (if any) of the modules/units may be implemented by using hardware such as a circuit; for each device and product applied to or integrated in the terminal, each module/unit included in the device and product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program running on a processor integrated in the terminal, and the rest (if any) part of the modules/units may be implemented by using hardware such as a circuit.
In the embodiments provided in the present invention, it should be understood that the disclosed method, apparatus and system can be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative; for example, the division of the unit is only a logic function division, and there may be another division manner in actual implementation; for example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be physically included alone, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. A method for realizing multi-bit register atomic operation, the said multi-bit register includes writing port, setting operation interface, clear operation interface; characterized in that the method comprises:
writing data to the multi-bit register through a write port;
when the data in the multi-bit register needs to be modified, the data modification operation is directly completed once through the setting operation interface or the zero clearing operation interface.
2. The method of claim 1, wherein the completing the data modification operation directly through the set operation interface or the clear operation interface once comprises:
if a non-0 value needs to be given to the multi-bit register, directly writing a non-0 target value into the multi-bit register through the setting operation interface;
and if a 0 value needs to be given to the multi-bit register, directly writing a non-0 value through the zero clearing operation interface.
3. The method of claim 2, further comprising:
generating a control signal according to all bit data of the multi-bit register;
generating a multi-path selection signal according to the control signal and a current operation signal, wherein the operation signal comprises: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface;
the writing of the target value other than 0 to the multi-bit register directly through the set operation interface includes:
enabling the setting operation interface and transmitting the target value which is not 0 to a data bus;
controlling the target value of the non-0 on the data bus to be written into the multi-bit register through the multi-path selection signal;
the writing of a non-0 value directly through the clear operation interface comprises:
enabling the zero clearing operation interface and transmitting non-0 data to the data bus;
and controlling to input all 0 data values to the multi-bit register through the multi-path selection signal.
4. A circuit for implementing multi-bit register atomic operations, the circuit comprising: the multi-bit register comprises a write port, a setting operation interface and a zero clearing operation interface;
the write operation module is used for outputting a write operation signal so as to control the write port to write data into the multi-bit register;
and the modification operation module is used for outputting a setting operation signal or a zero clearing operation signal when the data in the multi-bit register needs to be modified so as to control the setting operation interface or the zero clearing operation interface to finish data modification operation once.
5. The circuit of claim 4,
the modifying operation module is specifically configured to output the set operation signal when a non-0 value needs to be assigned to the multi-bit register, so as to control the set operation interface to write a non-0 target value into the multi-bit register; and when a 0 value needs to be assigned to the multi-bit register, outputting the set operation signal to control the zero clearing operation interface to write a non-0 value into the multi-bit register.
6. The circuit of claim 5, further comprising:
a control signal generating module, configured to generate a selection control signal according to all bit data of the multi-bit register and a current operation signal, where the operation signal includes: a write operation signal for controlling the write port, a set operation signal for controlling the set operation interface, and a clear operation signal for controlling the clear operation interface;
and the selection module is used for outputting the data on the data bus corresponding to each operation signal according to the selection control signal.
7. The circuit of claim 6, wherein the control signal generation module comprises: the first OR gate, the first AND gate and the second AND gate;
the first OR gate inputs a plurality of paths of data input signals of the multi-bit register and outputs a judgment signal;
the first AND gate inputs the setting operation signal and the judgment signal and outputs a setting selection signal;
the second AND gate inputs the zero clearing operation signal and the judgment signal and outputs a zero clearing selection signal;
the selection module inputs the write operation signal, the setting selection signal and the zero clearing operation signal; when the write operation signal is effective, writing data into the multi-bit register through the write port; writing a target value other than 0 to the multi-bit register through the set operation interface when the set selection signal is active; and when the zero clearing selection signal is effective, writing a non-0 value into the multi-bit register through the zero clearing operation interface.
8. The circuit of claim 7, wherein the selection module comprises: the third selector, the second selector and the first selector are connected in sequence;
the control end of the third selector inputs the write operation signal, and the first input end and the second input end of the third selector respectively input the multi-channel data input signal of the multi-bit register and the multi-channel data output signal of the multi-bit register and output a first data signal;
the control end of the second selector inputs the zero clearing selection signal, and the first input end and the second input end of the second selector respectively input the first data signal and all 0 data values required to be written by the zero clearing operation and output a second data signal;
the control end of the first selector inputs the setting selection signal, the first input end and the second input end of the first selector respectively input the second data signal and the multi-path data input signals of the multi-bit register, and the output end of the first selector is connected with the data input end of the multi-bit register.
9. The circuit of claim 8, wherein the second selector comprises: a first inverter and a third and gate;
the first inverter inputs the zero clearing selection signal;
one input end of the third AND gate is connected with the output end of the first inverter, the other input end of the third AND gate inputs the first data signal, and the output end of the third AND gate outputs the second data signal.
10. The circuit of claim 7, wherein the selection module comprises: the three control ends of the one-out-of-three selector respectively input the write operation signal, the setting selection signal and the zero clearing selection signal; and three input ends of the one-out-of-three selector are respectively input with a multi-path data input signal of the multi-bit register, a multi-path data output signal of the multi-bit register and an all-0 data value required to be written by the zero clearing operation, and an output end of the one-out-of-three selector is connected with a data input end of the multi-bit register.
11. The circuit of claim 7, wherein the selection module comprises: the second OR gate, the alternative selector, the second inverter and the fourth AND gate;
the second or gate inputs the write operation signal and the set selection signal respectively;
the control end of the alternative selector is connected with the output end of the second or gate, and the first input end and the second input end of the alternative selector are respectively input with the multi-channel data input signals of the multi-bit register and the multi-channel data output signals of the multi-bit register;
the second inverter inputs the zero clearing selection signal;
and two input ends of the fourth AND gate are respectively connected with the output end of the second inverter and the output end of the two-selection-one selector, and the output end of the fourth AND gate is connected with the data input end of the multi-bit register.
12. A chip comprising a circuit for implementing multi-bit register atomic operations as claimed in any one of claims 4 to 11.
13. An electronic device comprising a circuit for implementing a multi-bit register atomic operation as claimed in any one of claims 4 to 11.
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| CN202211078925.9A CN115586921A (en) | 2022-09-05 | 2022-09-05 | Method, circuit, chip and electronic device for realizing multi-bit register atomic operation |
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| CN202211078925.9A CN115586921A (en) | 2022-09-05 | 2022-09-05 | Method, circuit, chip and electronic device for realizing multi-bit register atomic operation |
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