CN114884383A - Generalized virtual vector modulation method and system for simplified three-level inverter - Google Patents

Generalized virtual vector modulation method and system for simplified three-level inverter Download PDF

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CN114884383A
CN114884383A CN202210645806.0A CN202210645806A CN114884383A CN 114884383 A CN114884383 A CN 114884383A CN 202210645806 A CN202210645806 A CN 202210645806A CN 114884383 A CN114884383 A CN 114884383A
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vector
reference voltage
virtual
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voltage vector
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秦昌伟
李晓艳
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Shandong Jianzhu University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H02J3/381—Dispersed generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2300/00—Systems for supplying or distributing electric power characterised by decentralized, dispersed, or local generation
    • H02J2300/20—The dispersed energy generation being of renewable origin
    • H02J2300/22—The renewable source being solar energy
    • H02J2300/24—The renewable source being solar energy of photovoltaic origin
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Abstract

The invention belongs to the technical field of power electronic power conversion, and provides a generalized virtual vector modulation method and a generalized virtual vector modulation system for a simplified three-level inverter, wherein the method comprises the following steps: sector and area judgment, virtual vector definition and selection, duty ratio calculation, capacitance voltage independent control, duty ratio updating, switch sequence design and PWM signal generation. The capacitance-voltage independent control strategy can be further divided into the midline current calculation and the optimal distribution factor acquisition. The method is simultaneously suitable for the neutral point voltage balance and unbalance operation working conditions of the direct current side, and ensures high-quality output current; the duty ratio of the basic voltage vector can be obtained only by algebraic operation, so that the complexity of the implementation process is greatly reduced; and meanwhile, flexible control of capacitor voltage can be realized.

Description

Generalized virtual vector modulation method and system for simplified three-level inverter
Technical Field
The invention belongs to the technical field of power electronic power conversion, and particularly relates to a generalized virtual vector modulation method and system of a simplified three-level inverter.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
The Three-Level Inverter (Three-Level Inverter) has the obvious advantages of low voltage stress of a power switch tube, high output waveform quality, small filter volume and the like, and is widely applied to the fields of renewable energy power generation, composite energy storage, electric energy quality control and the like. Diode Clamped (Diode Clamped) and T-Type (T-Type) three-level inverters are the two most commonly used three-level inverter topologies, but both of them need to use a large number of power switching tubes, which inevitably increases the system cost and volume.
In order to further reduce the number of power switching tubes and reduce the system volume and cost, a Simplified-type (SNPC) three-level inverter topology is proposed by Tung Ngo et al, university scholars of auckland, new zealand, which comprises ten power switching tubes, and the number of the topology is further reduced compared with that of a traditional T-type three-level inverter, and no clamping diode is needed.
The inventors have found that the existing modulation methods for a simplified three-level inverter are only suitable for dc-side midpoint voltage balancing conditions. However, when the simplified three-level inverter is used in systems such as centralized photovoltaic power generation, composite energy storage, new energy vehicles and the like, the direct-current side is provided with two independent input power supplies, which is significant for improving the system efficiency, but the current modulation scheme cannot be simultaneously applied to the neutral-point voltage balance and unbalance operation conditions of the direct-current side.
Disclosure of Invention
In order to solve at least one technical problem in the background art, the invention provides a generalized virtual vector modulation method and system of a simplified three-level inverter, which are suitable for neutral point voltage balance and unbalance operation conditions on a direct current side and ensure high-quality output current; the duty ratio of the basic voltage vector can be obtained only by algebraic operation, so that the complexity of the implementation process is greatly reduced; and meanwhile, flexible control of capacitor voltage can be realized.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a generalized virtual vector modulation method of a simplified three-level inverter, which comprises the following steps:
defining a virtual voltage vector according to a space voltage vector expression;
judging a sector and a region where a reference voltage vector is located currently according to the amplitude and phase angle value conditions of the reference voltage vector, if the reference voltage vector is located in the sector 1, synthesizing the reference voltage vector by adopting a corresponding virtual voltage vector selection rule method based on the relative position relationship between the reference voltage and a space vector diagram, establishing a volt-second balance equation, calculating the duty ratio of each virtual voltage vector by utilizing coordinate transformation, and if the reference voltage vector is located in other sectors except the sector 1, converting the phase angle of the reference voltage vector to the sector 1 through a mapping relationship;
the method for selecting the rule by adopting the corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically comprises the following steps:
when the reference voltage vector is positioned in the inner area of the space vector diagram, three virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by solving through a direct method;
when the reference voltage vector is positioned in the outer area of the space vector diagram, four virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by adopting an indirect method;
converting the duty ratio of each virtual vector into the duty ratio of a basic vector, designing a capacitor voltage optimal controller, accurately adjusting neutral current to obtain optimal distribution factors of the P-type and N-type small vector duty ratios, and updating the duty ratios of the basic vectors;
and designing a switching sequence based on the updated duty ratio of the basic vector and the sector and the area where the reference voltage vector is located, and converting the switching sequence into a PWM (pulse-width modulation) driving signal of the power switching tube.
A second aspect of the present invention provides a generalized virtual vector modulation system for a simplified three-level inverter, comprising:
the virtual voltage vector definition module is used for defining a virtual voltage vector according to the space voltage vector expression;
the virtual voltage vector selection and duty ratio calculation module is used for judging the sector and the area where the reference voltage vector is located currently according to the amplitude and phase angle value conditions of the reference voltage vector, if the reference voltage vector is located in the sector 1, synthesizing the reference voltage vector by adopting a corresponding virtual voltage vector selection rule method based on the relative position relation between the reference voltage and a space vector diagram, establishing a volt-second balance equation, calculating the duty ratio of each virtual voltage vector by utilizing coordinate transformation, and if the reference voltage vector is located in other sectors except the sector 1, converting the phase angle of the reference voltage vector to the sector 1 through a mapping relation;
the method for selecting the rule by adopting the corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically comprises the following steps:
when the reference voltage vector is positioned in the inner area of the space vector diagram, three virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by solving through a direct method;
when the reference voltage vector is positioned in the outer area of the space vector diagram, four virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by adopting an indirect method;
the capacitance voltage independent control module is used for converting the duty ratio of each virtual vector into the duty ratio of a basic vector, designing a capacitance voltage optimal controller, accurately adjusting neutral current to obtain optimal distribution factors of the duty ratios of the P-type and N-type small vectors and updating the duty ratios of the basic vectors;
and the driving signal generating module is used for designing a switching sequence based on the updated duty ratio of the basic vector and the sector and area where the reference voltage vector is located, and converting the switching sequence into a PWM driving signal of the power switching tube.
A third aspect of the invention provides a computer-readable storage medium.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the generalized virtual vector modulation method of a simplified three-level inverter as described above.
A fourth aspect of the invention provides a computer apparatus.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the generalized virtual vector modulation method of a simplified three-level inverter as described above when executing the program.
Compared with the prior art, the invention has the beneficial effects that:
(1) the method is simultaneously suitable for the balanced and unbalanced operation working conditions of the capacitor voltage at the direct current side of the simplified three-level inverter, ensures high-quality output current, and generates the PWM signals through sector and region discrimination, virtual vector definition and selection, duty ratio calculation, capacitor voltage independent control, duty ratio updating, switch sequence design and PWM signal generation. The independent control strategy of the capacitor voltage can be further divided into the neutral current calculation and the optimal distribution factor acquisition, the duty ratio of the basic voltage vector can be obtained only by algebraic operation, the complexity of the implementation process is greatly reduced, and the flexible control of the capacitor voltage can be realized.
(2) When the method is adopted, the direct-current side capacitor voltage fluctuation amplitude of the simplified three-level inverter is very small, and a capacitor with small capacity can be used, so that cost reduction and efficiency improvement of a system are facilitated;
(3) the method can flexibly control the difference value of the voltages of the two capacitors at the direct current side, and the adjusting time is obviously shortened compared with that of a traditional Proportional Integral (PI) controller.
Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.
FIG. 1 is a block diagram of the overall control of the system;
FIG. 2 is a circuit topology diagram of a simplified three-level inverter;
FIG. 3 is a space vector diagram of a simplified three-level inverter with a DC-side imbalance factor greater than 0;
FIG. 4 is a space vector diagram of a simplified three-level inverter with a DC-side imbalance factor less than 0;
FIG. 5 is a space vector diagram of the method of the present invention;
FIG. 6 is a schematic diagram of the switching sequence in sector 1, region A;
FIG. 7 is a schematic diagram of the switching sequence in sector 1, region B;
fig. 8(a) -8 (c) are steady-state operating waveform diagrams of the method of the present invention when the modulation degree m is 0.8;
fig. 9(a) -9 (b) are comparison graphs of operating waveforms of the capacitor voltage control using the method of the present invention and the conventional PI control method when the modulation degree m is 0.8;
fig. 10(a) -fig. 10(c) are steady-state operating waveform diagrams of the method of the present invention when the modulation degree m is 0.4;
fig. 11(a) -11 (b) are graphs comparing operating waveforms of the capacitor voltage control using the method of the present invention and the conventional PI control method when the modulation degree m is 0.4.
Detailed Description
The invention is further described with reference to the following figures and examples.
It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Example one
The embodiment provides a generalized virtual vector modulation method for a simplified three-level inverter, as shown in fig. 1, including the following steps:
step 1: defining a virtual vector according to the space voltage vector definition and the expression of the basic voltage vector;
step 2: judging the sector and the area where the reference voltage vector is currently located based on the amplitude value and the phase angle value condition of the reference voltage vector;
and step 3: designing a virtual voltage vector selection rule according to a sector where a reference voltage vector is located at present, synthesizing the reference voltage vector, establishing a volt-second balance equation, and solving the volt-second balance equation by utilizing coordinate transformation to obtain the duty ratio of each virtual vector;
and 4, step 4: designing a capacitor voltage optimal controller, accurately adjusting neutral current to obtain optimal distribution factors of the duty ratios of the P-type and N-type small vectors, and updating the duty ratios of the basic vectors by combining the corresponding relation between the virtual vectors and the basic vectors;
and 5: designing a switching sequence according to the sector and the area where the reference voltage vector is located currently; when the reference voltage vector is located in other sectors except the sector 1, converting the phase angle of the reference voltage vector to the sector 1 through a mapping relation; and converting the switching sequence into a PWM driving signal of the power switch tube.
Fig. 2 is a circuit topology diagram of a simplified three-level inverter system, which includes the following components: two sets of photovoltaic arrays (PV1 and PV2), two DC-side support capacitors (C) 1 And C 2 ) Ten power switch tubes (S) 1 ，S 2 ，…，S 10 )。
Wherein the values of the two DC-side supporting capacitors are equal, i.e. C 1 ＝C 2 ＝C dc (ii) a Two ends of each capacitor are respectively connected with a group of photovoltaic arrays to realize the function of Maximum Power Point Tracking (MPPT) and further improve the generating efficiency of the system.
S 1 、S 2 、S 3 And S 4 Four power switch tubes are connected in series to form a common switch unit S 5 、S 6 Through the clusterConnected to form a first group of individual switch units, S 7 、S 8 By series connection to form a second group of individual switching cells, S 9 、S 10 The third group of independent switch units is formed by series connection.
Will S 2 And S 3 As a neutral point of the inverter, a capacitor C 1 And C 2 The neutral point of the inverter is connected to the neutral point of the dc input power supply. The on and off of each power switch tube is controlled by adopting a Pulse Width Modulation (PWM) mode.
It is understood that the power switch tube in this embodiment may be an insulated-Gate Bipolar Transistor (IGBT), and may also be implemented by using other types of transistors, which may be specifically selected according to actual needs of those skilled in the art.
The switching states of the simplified three-level inverter include three types: [ P ], [ O ] and [ N ].
Selecting a neutral point on the DC side (i.e., point O in FIG. 2) 1 ) For reference. Wherein when the switch state is [ P ]]The output voltage of the bridge arm is + V C1 (ii) a When the switch state is [ O ]]When the voltage is zero, the output voltage of the bridge arm is 0; when the switch state is [ N ]]When the output voltage of the bridge arm is-V C2 。
The basic voltage vector, the switching state and the switched-on switching tube of the simplified three-level inverter are shown in table 1. It can be seen that the basic voltage vectors of the simplified three-level inverter include a large vector, a small vector and a zero vector.
TABLE 1 basic voltage vector, switching state and switching tube for simplified three-level inverter
Figure BDA0003685870300000081
To facilitate the description of the difference between the voltages of the two capacitors on the DC side, the imbalance factor on the DC side is defined as
Figure BDA0003685870300000082
Wherein, V C1 And V C2 Are respectively a capacitor C 1 And C 2 Voltage across, V dc ＝V C1 +V C2 。
When the dc-side imbalance factor is greater than or less than 0, the space vector diagrams of the simplified three-level inverter are shown in fig. 3 and 4, respectively. Therefore, under the working condition of neutral point voltage unbalance on the direct current side, the positions of the large vector and the zero vector are kept unchanged, namely the positions are the same as those under the working condition of neutral point voltage unbalance; the positions of the small vectors are shifted, and the positions of the P-type small vector and the N-type small vector are not overlapped, so that the implementation process of the space vector modulation method is extremely complex.
Therefore, the embodiment provides a generalized virtual vector modulation method and system suitable for a simplified three-level inverter, which can effectively solve the above-mentioned problems. Without loss of generality, the sector 1 is taken as an example to explain the specific implementation process in detail.
Step 1: defining a virtual vector according to a space voltage vector definition expression;
as one or more embodiments, in step 1, according to the definition of the space voltage vector, the expression of the basic voltage vector in sector 1 can be obtained as follows:
Figure BDA0003685870300000091
defining the virtual vector as:
Figure BDA0003685870300000092
wherein alpha is the distribution factor of the P type small vector and the N type small vector.
It can be seen that: the virtual large vector is the same as the large vector; the virtual zero vector is the same as the zero vector; the virtual small vector is a combination of a P-type small vector and an N-type small vector. When α takes different values, the vertices of the virtual small vectors differ.
In this embodiment, for ease of solution, α is taken to be equal to 1/2.
Step 2: judging the sector and the area where the reference voltage vector is currently located based on the amplitude value and the phase angle value condition of the reference voltage vector;
and step 3: designing a virtual voltage vector selection rule according to a sector where a reference voltage vector is located at present, synthesizing the reference voltage vector, establishing a volt-second balance equation, and solving the volt-second balance equation by utilizing coordinate transformation to obtain the duty ratio of each virtual vector;
as one or more embodiments, in step 3, to simplify the calculation process, a 60 ° coordinate system is established, i.e., the g-axis is rotated 60 ° counterclockwise to obtain the h-axis (see fig. 4). The coordinate transformation process can be expressed as:
Figure BDA0003685870300000101
wherein v is rg Representing the g-axis component, v, of the reference voltage vector rh Representing the h-axis component, v, of the reference voltage vector rα Representing the alpha-axis component, v, of the reference voltage vector rβ Representing the beta axis component of the reference voltage vector.
Selecting four virtual voltage vectors with the nearest distance when the reference voltage vector is in a region A (namely, the outer region of the space vector diagram) in the sector 1, wherein the four virtual voltage vectors comprise two virtual large vectors and two virtual small vectors (namely V) L1 、V L2 、V S1 And V S2 ) Synthesizing a reference voltage vector, wherein a volt-second equilibrium equation is as follows:
Figure BDA0003685870300000102
wherein, V r As a vector of reference voltages, d L1 、d L2 、d S1 And d S2 Are each V L1 、V L2 、V S1 And V S2 The duty cycle of (c).
The following indirect calculation method is adopted to solve the duty ratio d L1 、d L2 、d S1 And d S2 ：
Using the coordinate transformation given by equation (4), the volt-second equilibrium equation can be simplified as:
Figure BDA0003685870300000111
wherein, V rg And V rh The g-axis and h-axis components of the reference voltage vector, respectively.
Further obtain d S1 And d S2 Satisfy the requirement of
Figure BDA0003685870300000112
Introduction of partition factor beta (0)<β<1)，d S1 And d S2 Can be expressed as:
Figure BDA0003685870300000113
d L1 and d L2 Can be expressed as:
Figure BDA0003685870300000114
due to d L1 And d L2 For duty cycle, it is clear that: d L1 >0，d L2 >0, further available partition factor β satisfies
Figure BDA0003685870300000115
Bonding 0<β<1, upper limit value beta of obtainable partition factor beta max And a lower limit value beta min Respectively as follows:
Figure BDA0003685870300000116
Figure BDA0003685870300000117
selecting the distribution factor beta as its upper limit value beta max And a lower limit value beta min I.e.:
Figure BDA0003685870300000121
and substituting the distribution factor given by the formula (13) into the expression of the duty ratio to obtain the duty ratio of each virtual vector. It is converted into the duty cycle of the basis vector as shown in equation (14).
Figure BDA0003685870300000122
Wherein d is 1 、d 2 、d 7p 、d 7n 、d 8p And d 8n Are each V 1 [PNN]、V 2 [PPN]、V 7p [POO]、V 7n [ONN]、V 8p [PPO]And V 8n [OON]The duty cycle of (c). Xi is the duty ratio distribution factor of the P type small vector and the N type small vector and can be used for controlling the voltage deviation of the capacitor.
When the reference voltage vector is in the area B (i.e. the inner area of the space vector diagram) in the sector 1, three virtual voltage vectors with the nearest distance are selected to comprise two virtual small vectors and a virtual zero vector (i.e. V) S1 、V S2 And V Z ) Synthesizing a reference voltage vector, wherein a volt-second balance equation is as follows:
Figure BDA0003685870300000123
wherein, V r As a vector of reference voltages, d S1 、d S2 And d Z Are each V S1 、V S2 And V Z The duty cycle of (c). The direct calculation method is adopted to solve the duty ratio d S1 、d S2 And d Z ：
By using the coordinate transformation given by equation (4), the duty ratio of each virtual vector can be obtained as:
Figure BDA0003685870300000131
it is converted into the duty ratio of the basic vector as shown in equation (17).
Figure BDA0003685870300000132
Wherein d is 7p 、d 7n 、d 8p 、d 8n And d 0 Are each V 7p [POO]、V 7n [ONN]、V 8p [PPO]、V 8n [OON]And V 0 [OOO]The duty cycle of (c).
And 4, step 4: designing a capacitor voltage optimal controller, accurately adjusting neutral current to obtain optimal distribution factors of the duty ratios of the P-type and N-type small vectors, and updating the duty ratios of the basic vectors by combining the corresponding relation between the virtual vectors and the basic vectors;
as one or more embodiments, after the duty ratios of the virtual vectors are obtained, the capacitor voltage optimal controller is designed, the neutral line current is accurately adjusted, P-type and N-type small vector duty ratio distribution factors are obtained, and the duty ratios of the basic vectors are updated by combining the corresponding relational expressions of the virtual vectors and the basic vectors, which specifically comprises the following steps:
the mathematical model of the neutral current is:
Figure BDA0003685870300000133
wherein, C dc Supporting the value of the capacitance for the DC side (i.e. C) 1 ＝C 2 ＝C dc )，V diff Is the voltage difference (i.e. V) between two capacitors on the DC side diff ＝V C1 –V C2 )。
The discrete form of the mathematical model of the neutral current is:
Figure BDA0003685870300000141
wherein, T s Is the sampling period of the digital controller, V diff (k) And V diff And (k +1) is the voltage difference of the two capacitors on the direct current side at the moment k and the moment k +1 respectively.
Let V diff (k +1) is given value V of capacitor voltage deviation diff_ref Then the reference value of the neutral current can be expressed as:
Figure BDA0003685870300000142
when the reference voltage vector is located in sector 1 (including region a and region B), the relationship between the actual system neutral current and the three-phase output current, the base vector duty cycle, can be expressed as:
i np ＝i a ·(d 7n +d 8n )+i b ·(d 8n +d 7p )+i c ·(d 7p +d 8p ) (21)
by combining the formula (17), the formula (20) and the formula (21), the optimal distribution factor ξ can be obtained opt Is composed of
Figure BDA0003685870300000143
By adopting similar analysis and solving method, the optimal distribution factor xi in other sectors can be obtained opt . The optimal allocation factor within each sector is as follows:
when the reference voltage vector is located in sector 1, the optimal allocation factor is:
Figure BDA0003685870300000144
when the reference voltage vector is located in sector 2, the optimal allocation factor is:
Figure BDA0003685870300000145
when the reference voltage vector is located in sector 3, the optimal allocation factor is:
Figure BDA0003685870300000151
when the reference voltage vector is located in sector 4, the optimal allocation factor is:
Figure BDA0003685870300000152
when the reference voltage vector is located in sector 5, the optimal allocation factor is:
Figure BDA0003685870300000153
when the reference voltage vector is located in sector 6, the optimal allocation factor is:
Figure BDA0003685870300000154
and 5: designing a switching sequence according to the sector and the area where the reference voltage vector is located currently;
in one or more embodiments, in step 5, the switching sequence is designed in consideration of factors such as low harmonic content of the output waveform of the simplified three-level inverter, and low operation frequency of the power switching tube.
The designed switching sequence is a seven-segment or nine-segment switching sequence, and specifically comprises the following steps:
when the reference voltage vector is located in region a within sector 1, the seven-segment switching sequence is designed as follows: [ PNN ] - [ ONN ] - [ OON ] - [ PPN ] - [ PPO ] - [ POO ] - [ PNN ] (shown in FIG. 5).
When the reference voltage vector is located in region B within sector 1, the nine-segment switching sequence is designed as follows: [ ONN ] - [ OON ] - [ OOO ] - [ POO ] - [ PPO ] - [ POO ] - [ OOO ] - [ OON ] - [ ONN ] (shown in FIG. 6).
Step 6: when the reference voltage vector is located in other sectors except the sector 1, converting the phase angle of the reference voltage vector to the sector 1 through a mapping relation; and converting the switching sequence into a PWM driving signal of the power switch tube.
In one or more embodiments, in step 6, when the reference voltage vector is located in another sector (i.e., sector 2-sector 6), the phase angle of the reference voltage vector is transformed to sector 1, i.e., the phase angle of the reference voltage vector, through the mapping relationship (i.e., equation (14)) in step 6
Figure BDA0003685870300000161
Where θ is the phase angle of the reference voltage vector, N is the sector number, and θ' is the value that the phase angle of the reference voltage vector maps into sector 1.
On the basis, the duty ratio of the corresponding basic voltage vector is calculated by using a duty ratio calculation formula in the sector 1. And then selecting a basic voltage vector in a sector where the reference voltage vector is located, and designing a switching sequence.
The switching sequences in different sectors and regions are designed as follows:
when the reference voltage vector is located in region a within sector 2, the seven-segment switching sequence is designed as follows: [ PPN ] - [ OON ] - [ NON ] - [ NPN ] - [ OPO ] - [ PPO ] - [ PPN ].
When the reference voltage vector is located in region B within sector 2, the nine-segment switching sequence is designed as follows: [ NON ] - [ OON ] - [ OOO ] - [ OPO ] - [ PPO ] - [ OPO ] - [ OOO ] - [ OON ] - [ NON ].
When the reference voltage vector is located in region a within sector 3, the seven-segment switching sequence is designed as follows: [ NPN ] - [ NON ] - [ NOO ] - [ NPP ] - [ OPP ] - [ OPO ] - [ NPN ].
When the reference voltage vector is located in region B within sector 3, the nine-segment switching sequence is designed as follows: [ NON ] - [ NOO ] - [ OOO ] - [ OPO ] - [ OPP ] - [ OPO ] - [ OOO ] - [ NOO ] - [ NON ].
When the reference voltage vector is located in region a within sector 4, the seven-segment switching sequence is designed as follows: [ NPP ] - [ NOO ] - [ NNO ] - [ NNP ] - [ OOP ] - [ OPP ] - [ NPP ].
When the reference voltage vector is located in region B within sector 4, the nine-segment switching sequence is designed as follows: [ NNO ] - [ NOO ] - [ OOO ] - [ OOP ] - [ OPP ] - [ OOP ] - [ OOO ] - [ NOO ] - [ NNO ].
When the reference voltage vector is located in region a within sector 5, the seven-segment switching sequence is designed as follows: [ NNP ] - [ NNO ] - [ ONO ] - [ PNP ] - [ POP ] - [ OOP ] - [ NNP ].
When the reference voltage vector is located in region B within sector 5, the nine-segment switching sequence is designed as follows: [ NNO ] - [ ONO ] - [ OOO ] - [ OOP ] - [ POP ] - [ OOP ] - [ OOO ] - [ ONO ] - [ NNO ].
When the reference voltage vector is located in region a within sector 6, the seven-segment switching sequence is designed as follows: [ PNP ] - [ ONO ] - [ ONN ] - [ PNN ] - [ POO ] - [ POP ] - [ PNP ].
When the reference voltage vector is located in region B within sector 6, the nine-segment switching sequence is designed as follows: [ ONN ] - [ ONO ] - [ OOO ] - [ POO ] - [ POP ] - [ POO ] - [ OOO ] - [ ONO ] - [ ONN ].
FIG. 7 is a control block diagram of the method of the present invention, the basic steps include: sector and area judgment, virtual vector selection, duty ratio calculation, capacitance voltage independent control, duty ratio updating, switch sequence design and PWM generation. The capacitance-voltage independent control strategy can be further divided into parts such as neutral current calculation, optimal distribution factor calculation, amplitude limiting and the like.
When the modulation degree is 0.8, the steady-state operation waveform diagrams of the simplified three-level inverter are shown in fig. 8(a) to 8 (c). When the running time is between 0.15s and 0.2s, the capacitor voltage deviation given value is 0V; when the running time is between 0.25s and 0.3s, the capacitor voltage deviation given value is 100V; when the operation time is between 0.35s and 0.4s, the capacitor voltage deviation is given by-100V. Meanwhile, fig. 8(a) -8 (c) show the output line voltage total harmonic distortion rate (THDv) and the output current total harmonic distortion rate (THDi). It can be seen that: under the working conditions of balance and unbalance of the direct current side capacitor voltage, the method disclosed by the invention can ensure high-quality output current.
When the system modulation degree is equal to 0.8 and the given value of the capacitor voltage deviation has step change, the performance of the method of the invention and the traditional PI control method is shown in figures 9(a) to 9 (b).
It can be seen that: by adopting the method, the voltage regulation time of the direct current side capacitor is obviously shortened compared with the traditional PI control method.
Fig. 10(a) to 10(c) show steady-state operation waveforms of the simplified three-level inverter when the modulation degree is 0.4. When the running time is between 0.15s and 0.2s, the capacitor voltage deviation given value is 0V; when the running time is between 0.25s and 0.3s, the capacitor voltage deviation given value is 100V; when the operation time is between 0.35s and 0.4s, the capacitor voltage deviation is given by-100V. Meanwhile, fig. 10(a) -10 (c) show the output line voltage total harmonic distortion rate (THDv) and the output current total harmonic distortion rate (THDi). Therefore, the method is simultaneously suitable for the working conditions of balanced and unbalanced capacitor voltage on the direct current side, and the stable and reliable operation of the inverter system is ensured.
When the system modulation degree is equal to 0.4 and the given value of the capacitor voltage deviation has a step change, the performance of the method of the invention and the performance of the traditional PI control method are as shown in FIGS. 11(a) to 11 (b).
It can be seen that: the method can realize the fast and accurate tracking control of the capacitor voltage, and has obvious advantages compared with the traditional PI control method.
Example two
The present embodiment provides a generalized virtual vector modulation system of a simplified three-level inverter, including:
the virtual voltage vector definition module is used for defining a virtual voltage vector according to the space voltage vector expression;
the virtual voltage vector selection and duty ratio calculation module is used for judging the sector and the area where the reference voltage vector is located currently according to the amplitude and phase angle value conditions of the reference voltage vector, if the reference voltage vector is located in the sector 1, synthesizing the reference voltage vector by adopting a corresponding virtual voltage vector selection rule method based on the relative position relation between the reference voltage and a space vector diagram, establishing a volt-second balance equation, calculating the duty ratio of each virtual voltage vector by utilizing coordinate transformation, and if the reference voltage vector is located in other sectors except the sector 1, converting the phase angle of the reference voltage vector to the sector 1 through a mapping relation;
the method for selecting the rule by adopting the corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically comprises the following steps:
when the reference voltage vector is positioned in the inner area of the space vector diagram, three virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by solving through a direct method;
when the reference voltage vector is positioned in the outer area of the space vector diagram, four virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by adopting an indirect method;
the capacitance voltage independent control module is used for converting the duty ratio of each virtual vector into the duty ratio of a basic vector, designing a capacitance voltage optimal controller, accurately adjusting neutral current to obtain optimal distribution factors of the duty ratios of the P-type and N-type small vectors and updating the duty ratios of the basic vectors;
and the driving signal generating module is used for designing a switching sequence based on the updated duty ratio of the basic vector and the sector and area where the reference voltage vector is located, and converting the switching sequence into a PWM driving signal of the power switching tube.
EXAMPLE III
The present embodiment provides a computer readable storage medium having stored thereon a computer program which, when being executed by a processor, implements the steps in the generalized virtual vector modulation method of a simplified three-level inverter as described above.
Example four
The present embodiment provides a computer device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the generalized virtual vector modulation method for a simplified three-level inverter as described above.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A generalized virtual vector modulation method of a simplified three-level inverter is characterized by comprising the following steps:
defining a virtual voltage vector according to a space voltage vector expression;
judging a sector and a region where a reference voltage vector is located currently according to the amplitude and phase angle value conditions of the reference voltage vector, if the reference voltage vector is located in the sector 1, synthesizing the reference voltage vector by adopting a corresponding virtual voltage vector selection rule method based on the relative position relationship between the reference voltage and a space vector diagram, establishing a volt-second balance equation, calculating the duty ratio of each virtual voltage vector by utilizing coordinate transformation, and if the reference voltage vector is located in other sectors except the sector 1, converting the phase angle of the reference voltage vector to the sector 1 through a mapping relationship;
the method for selecting the rule by adopting the corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically comprises the following steps:
when the reference voltage vector is positioned in the inner area of the space vector diagram, three virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by solving through a direct method;
when the reference voltage vector is positioned in the outer area of the space vector diagram, four virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by adopting an indirect method;
converting the duty ratio of each virtual vector into the duty ratio of a basic vector, designing a capacitor voltage optimal controller, accurately adjusting neutral current to obtain optimal distribution factors of the P-type and N-type small vector duty ratios, and updating the duty ratios of the basic vectors;
and designing a switching sequence based on the updated duty ratio of the basic vector and the sector and the area where the reference voltage vector is located, and converting the switching sequence into a PWM (pulse-width modulation) driving signal of the power switching tube.
2. The generalized virtual vector modulation method of the simplified three-level inverter according to claim 1, wherein the duty ratio expression of each virtual vector obtained by direct solution is as follows:
Figure FDA0003685870290000021
the duty ratio of each corresponding basic voltage vector is as follows:
Figure FDA0003685870290000022
in the formula (d) S1 、d S2 And d Z The duty ratio of the three virtual voltage vectors is shown, and xi is the duty ratio distribution factor of the P type small vector and the N type small vector; v rg And V rh The g-axis and h-axis components of the reference voltage vector,
Figure FDA0003685870290000025
is a DC side imbalance factor, V dc Alpha is the distribution factor of the P-type small vector and the N-type small vector, which is the sum of the voltages at two ends of the capacitor.
3. The generalized virtual vector modulation method of the simplified three-level inverter according to claim 1, wherein the duty ratio expression of each virtual vector obtained by indirect solution is:
Figure FDA0003685870290000023
wherein the content of the first and second substances,
Figure FDA0003685870290000024
Figure FDA0003685870290000031
Figure FDA0003685870290000032
Figure FDA0003685870290000033
the duty cycle of each basic voltage vector is:
Figure FDA0003685870290000034
in the formula (d) L1 、d L2 、d S1 And d S2 And xi is the duty ratio distribution factor of the P type small vector and the N type small vector.
4. The generalized virtual vector modulation method of a simplified three-level inverter according to claim 1, wherein the optimal distribution factor is specifically:
when the reference voltage vector is located in sector 1, the optimal allocation factor is:
Figure FDA0003685870290000035
when the reference voltage vector is located in sector 2, the optimal allocation factor is:
Figure FDA0003685870290000036
when the reference voltage vector is located in sector 3, the optimal allocation factor is:
Figure FDA0003685870290000037
when the reference voltage vector is located in sector 4, the optimal allocation factor is:
Figure FDA0003685870290000041
when the reference voltage vector is located in sector 5, the optimal allocation factor is:
Figure FDA0003685870290000042
when the reference voltage vector is located in sector 6, the optimal allocation factor is:
Figure FDA0003685870290000043
wherein the reference value of the neutral current is
Figure FDA0003685870290000044
C dc For the value of the DC-side support capacitance, V diff_ref Given value of capacitor voltage deviation, T s Is the sampling period of the digital controller, V diff (k) At time k, two sides of direct currentThe voltage difference of the capacitors.
5. The generalized virtual vector modulation method of a simplified three-level inverter as claimed in claim 1, wherein the designed switching sequence is a seven-segment or nine-segment switching sequence.
6. The generalized virtual vector modulation method of a simplified three-level inverter as claimed in claim 5, wherein the seven-segment or nine-segment switching sequence is specifically:
when the reference voltage vector is located in region a within sector 1, the switching sequence is designed as follows:
[PNN]-[ONN]-[OON]-[PPN]-[PPO]-[POO]-[PNN]；
when the reference voltage vector is located in region B within sector 1, the switching sequence is designed as follows:
[ONN]-[OON]-[OOO]-[POO]-[PPO]-[POO]-[OOO]-[OON]-[ONN]；
when the reference voltage vector is located in region a within sector 2, the switching sequence is designed as follows:
[PPN]-[OON]-[NON]-[NPN]-[OPO]-[PPO]-[PPN]；
when the reference voltage vector is located in region B within sector 2, the switching sequence is designed as follows:
[NON]-[OON]-[OOO]-[OPO]-[PPO]-[OPO]-[OOO]-[OON]-[NON]。
when the reference voltage vector is located in region a within sector 3, the switching sequence is designed as follows:
[NPN]-[NON]-[NOO]-[NPP]-[OPP]-[OPO]-[NPN]；
when the reference voltage vector is located in region B within sector 3, the switching sequence is designed as follows:
[NON]-[NOO]-[OOO]-[OPO]-[OPP]-[OPO]-[OOO]-[NOO]-[NON]；
when the reference voltage vector is located in region a within sector 4, the switching sequence is designed as follows:
[NPP]-[NOO]-[NNO]-[NNP]-[OOP]-[OPP]-[NPP]；
when the reference voltage vector is located in region B within sector 4, the switching sequence is designed as follows:
[NNO]-[NOO]-[OOO]-[OOP]-[OPP]-[OOP]-[OOO]-[NOO]-[NNO]；
when the reference voltage vector is located in region a within sector 5, the switching sequence is designed as follows:
[NNP]-[NNO]-[ONO]-[PNP]-[POP]-[OOP]-[NNP]；
when the reference voltage vector is located in region B within sector 5, the switching sequence is designed as follows:
[NNO]-[ONO]-[OOO]-[OOP]-[POP]-[OOP]-[OOO]-[ONO]-[NNO]；
when the reference voltage vector is located in region a within sector 6, the switching sequence is designed as follows:
[PNP]-[ONO]-[ONN]-[PNN]-[POO]-[POP]-[PNP]；
when the reference voltage vector is located in region B within sector 6, the switching sequence is designed as follows:
[ONN]-[ONO]-[OOO]-[POO]-[POP]-[POO]-[OOO]-[ONO]-[ONN]。
7. the generalized virtual vector modulation method of a simplified three-level inverter as claimed in claim 1, wherein said virtual voltage vector comprises a virtual large vector, a virtual small vector and a virtual zero vector, wherein the virtual large vector is the same as the large vector; the virtual zero vector is the same as the zero vector; the virtual small vector is a combination of a P-type small vector and an N-type small vector.
8. A generalized virtual vector modulation system for a simplified three-level inverter, comprising:
the virtual voltage vector definition module is used for defining a virtual voltage vector according to the space voltage vector expression;
the virtual voltage vector selection and duty ratio calculation module is used for judging the sector and the area where the reference voltage vector is located currently according to the amplitude and phase angle value conditions of the reference voltage vector, if the reference voltage vector is located in the sector 1, synthesizing the reference voltage vector by adopting a corresponding virtual voltage vector selection rule method based on the relative position relation between the reference voltage and a space vector diagram, establishing a volt-second balance equation, calculating the duty ratio of each virtual voltage vector by utilizing coordinate transformation, and if the reference voltage vector is located in other sectors except the sector 1, converting the phase angle of the reference voltage vector to the sector 1 through a mapping relation;
the method for selecting the rule by adopting the corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically comprises the following steps:
when the reference voltage vector is positioned in the inner area of the space vector diagram, three virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by solving through a direct method;
when the reference voltage vector is positioned in the outer area of the space vector diagram, four virtual voltage vectors with the nearest distance are selected to synthesize the reference vector, and the duty ratio of each virtual vector is obtained by adopting an indirect method;
the capacitance voltage independent control module is used for converting the duty ratio of each virtual vector into the duty ratio of a basic vector, designing a capacitance voltage optimal controller, accurately adjusting neutral current to obtain optimal distribution factors of the duty ratios of the P-type and N-type small vectors and updating the duty ratios of the basic vectors;
and the driving signal generating module is used for designing a switching sequence based on the updated duty ratio of the basic vector and the sector and area where the reference voltage vector is located, and converting the switching sequence into a PWM driving signal of the power switching tube.
9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of a method for generalized virtual vector modulation of a simplified three-level inverter according to any of claims 1-7.
10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps in the generalized virtual vector modulation method of a simplified three-level inverter according to any of claims 1-7 when executing the program.
CN202210645806.0A 2022-06-09 2022-06-09 Generalized virtual vector modulation method and system for simplified three-level inverter Pending CN114884383A (en)

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CN117478110A (en) * 2023-11-13 2024-01-30 国网湖北省电力有限公司经济技术研究院 Space vector pulse width modulation method, system and equipment based on virtual chopping

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117478110A (en) * 2023-11-13 2024-01-30 国网湖北省电力有限公司经济技术研究院 Space vector pulse width modulation method, system and equipment based on virtual chopping
CN117478110B (en) * 2023-11-13 2024-04-16 国网湖北省电力有限公司经济技术研究院 Space vector pulse width modulation method, system and equipment based on virtual chopping

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