CN114884337A - HERIC inverter circuit - Google Patents
HERIC inverter circuit Download PDFInfo
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- CN114884337A CN114884337A CN202210796936.4A CN202210796936A CN114884337A CN 114884337 A CN114884337 A CN 114884337A CN 202210796936 A CN202210796936 A CN 202210796936A CN 114884337 A CN114884337 A CN 114884337A
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- pwm signal
- tube
- driving circuit
- power supply
- switching tube
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
- H02M1/092—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the control signals being transmitted optically
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a HERIC inverter circuit, wherein a first diagonal switch tube driving circuit is driven by a first PWM (pulse-width modulation) signal, a second follow current tube driving circuit is driven by a fourth PWM signal, and the power input end of the first diagonal switch tube driving circuit is clamped by the fourth PWM signal; the driving of the second diagonal switching tube driving circuit is driven by a second PWM signal, the first follow current tube driving circuit is driven by a third PWM signal, and the power supply input end of the second diagonal switching tube driving circuit is clamped by the third PWM signal; the low level of a driving signal input by the driving circuit is effective, the first PWM signal and the fourth PWM signal are complementary in logic in the positive half cycle of the output voltage, the second PWM signal is high level, and the third PWM signal is low level; in the negative half cycle of the output voltage, the second PWM signal is logically complementary to the third PWM signal, the first PWM signal is at a high level, and the fourth PWM signal is at a low level. The invention can prevent the switch tube and the logic complementary follow current tube from being conducted at the same time, and the circuit has good safety.
Description
Technical Field
The invention relates to an inverter circuit, in particular to a HERIC inverter circuit.
Background
The HERIC inversion topology is an efficient and reliable inversion topology, is one of main topologies applied to a single-phase inverter, and a protection circuit of a switching tube of the whole topology is complicated due to the fact that two follow current tubes are added.
In the inverter topology, the power semiconductor switching tubes are always symmetrically arranged, the switching-on time of the power semiconductor switching tubes is in a logic complementary relation, namely the switching tubes in a symmetrical relation are formed, when one switching tube is switched on, the other switching tube needs to be switched off, if the switching tubes in the symmetrical relation are switched on simultaneously, the switching tubes are equivalent to short-circuit of a direct current bus, and the switching tubes are damaged. The on and off of the switch tube is completely controlled by the driving signal, so that the logic complementary driving signal of the switch tube which well controls the symmetrical relation can protect the switch tube.
The driving voltage of the power semiconductor switch tube is usually much higher than the voltage of the driving signal sent by the CPU of the control chip, taking the IGBT as an example, the preferred on voltage is +15V, and the off voltage is-5V, and the signal sent by the control chip is usually only 3-5V, so that the isolation circuit is needed to convert the low-voltage driving signal of the control chip into the driving signal with higher voltage. Because the driving signals are logic complementary, the driving signals are likely to be interfered in the process of being transmitted to the isolation circuit, or the two driving signals are changed into effective levels due to the damage of components, if the isolation circuit at the moment is not added with a circuit with a protection function, the two driving signals which are simultaneously effective can be output, so that two switching tubes are simultaneously conducted, and the switching tubes are damaged due to short circuit.
The HERIC inversion topology has two more follow current tubes than the full-bridge inversion topology, the driving signal of the follow current tube is also in logic complementation with the driving signal of the bridge arm, and the bridge arm switching tube and the follow current tube with the logic complementation with the driving signal can also cause the damage of the whole topology under the condition of simultaneous conduction.
Disclosure of Invention
The invention aims to provide a HERIC inverter circuit with good safety performance.
In order to solve the technical problem, the invention adopts the technical scheme that the HERIC inverter circuit comprises a main circuit and a control circuit, wherein the main circuit comprises an H-bridge circuit consisting of two pairs of diagonal switching tubes and a follow current circuit consisting of two follow current tubes which are reversely connected in series, the control circuit comprises a plurality of driving circuits, and the plurality of driving circuits comprise a first pair of diagonal switching tube driving circuits, a second pair of diagonal switching tube driving circuits, a first follow current tube driving circuit and a second follow current tube driving circuit; the first diagonal switch tube driving circuit is driven by a first PWM signal, the second follow current tube driving circuit is driven by a fourth PWM signal, and the power supply input end of the first diagonal switch tube driving circuit is clamped by the fourth PWM signal; the driving of the second pair of diagonal switching tube driving circuits is driven by a second PWM signal, the first follow current tube driving circuit is driven by a third PWM signal, and the power supply input ends of the second pair of diagonal switching tube driving circuits are clamped by the third PWM signal; the low level of a driving signal input by the driving circuit is effective, the first PWM signal and the fourth PWM signal are complementary in logic in the positive half cycle of the output voltage of the HERIC inverter circuit, the second PWM signal is high level, and the third PWM signal is low level; in the negative half cycle of the output voltage of the HERIC inverter circuit, the second PWM signal is in logic complementation with the third PWM signal, the first PWM signal is at a high level, and the fourth PWM signal is at a low level.
In the HERIC inverter circuit, the driving circuit comprises an optical coupler, and the optical coupler is a totem-pole output type optical coupler; the power supply input ends of the primary sides of the optocouplers of the switch tube driving circuits at the first diagonal are connected with an auxiliary power supply through a first current-limiting resistor and connected with a fourth PWM signal through a first clamping circuit, and the signal input ends of the primary sides of the optocouplers of the switch tube driving circuits at the first diagonal are connected with the first PWM signal; the power supply input end of the primary side of the optocoupler of the second follow current tube driving circuit is connected with an auxiliary power supply through a second current limiting resistor, and the signal input end of the primary side of the optocoupler of the second follow current tube driving circuit is connected with a fourth PWM signal; the power supply input ends of the primary sides of the optocouplers of the switch tube driving circuits at the second pair of opposite angles are connected with an auxiliary power supply through a third current-limiting resistor and connected with a third PWM signal through a second clamping circuit, and the signal input ends of the primary sides of the optocouplers of the switch tube driving circuits at the second pair of opposite angles are connected with a second PWM signal; the power input end of the primary side of the optocoupler of the first follow current tube driving circuit is connected with an auxiliary power supply through a fourth current limiting resistor, and the signal input end of the primary side of the optocoupler of the first follow current tube driving circuit is connected with a third PWM signal.
In the inverter circuit of the HERIC, the switching tubes and the follow current tube are IGBT tubes, the first pair of diagonal switching tubes includes a first switching tube and a fourth switching tube, and the second pair of diagonal switching tubes includes a second switching tube and a third switching tube; the collector of the first switch tube and the collector of the third switch tube are connected with a direct current positive bus, and the emitter of the second switch tube and the emitter of the fourth switch tube are connected with a direct current negative bus; the emitter of the first switching tube is connected with the collector of the second switching tube, and the emitter of the third switching tube is connected with the collector of the fourth switching tube; the emitter of the first afterflow tube is connected with the emitter of the first switch tube, the collector of the first afterflow tube is connected with the collector of the second afterflow tube, and the emitter of the second afterflow tube is connected with the collector of the fourth switch tube; one end of the output filter capacitor is connected with the emitting electrode of the first follow current tube, and the other end of the output filter capacitor is connected with the emitting electrode of the second follow current tube; the inversion inductor is connected in series among the emitter of the first follow current tube, the emitter of the second follow current tube and the output filter capacitor.
In the inverter circuit of the HERIC, the driving circuit includes an NPN triode and a PNP triode, the power input positive pin, the power input negative pin and the driving signal output pin, the power input end of the secondary side of the optocoupler is connected with the power input positive pin, and the ground end of the secondary side of the optocoupler is connected with the power input negative pin; the collector of the NPN triode is connected with the positive pin of the power input, the emitter of the NPN triode is connected with the collector of the PNP triode, and the emitter of the PNP triode is connected with the negative pin of the power input; the base electrode of the NPN triode and the base electrode of the PNP triode are connected with the signal output end of the auxiliary side of the optocoupler, and the emitting electrode of the NPN triode is connected with the driving signal output pin.
In the inverter circuit, the first diagonal switching tube driving circuit comprises a first switching tube driving circuit and a fourth switching tube driving circuit, the power input end of the primary side of the first switching tube driving circuit optocoupler is connected with the auxiliary power supply through a fifth current-limiting resistor and is connected with the anode of the first clamping diode, and the cathode of the first clamping diode is connected with the fourth PWM signal; the signal input end of the primary side of the optical coupler of the first switching tube driving circuit is connected with a first PWM signal, the positive pin of the power input of the first switching tube driving circuit is connected with the positive pole of a first isolation power supply, the negative pin of the power input is connected with the negative pole of the first isolation power supply, and the output pin of the driving signal is connected with the gate pole of the first switching tube; the power supply input end of the primary side of the optical coupler of the fourth switching tube driving circuit is connected with an auxiliary power supply through a sixth current-limiting resistor and is connected with the anode of a second clamping diode, and the cathode of the second clamping diode is connected with a fourth PWM signal; the signal input end of the primary side of the optical coupler of the fourth switching tube driving circuit is connected with a first PWM signal, the positive pin of the power input of the fourth switching tube driving circuit is connected with the positive electrode of the fifth isolation power supply, the negative pin of the power input is connected with the negative electrode of the fifth isolation power supply, and the pin of the driving signal output is connected with the gate pole of the fourth switching tube.
In the inverter circuit, the second pair of diagonal switching tube driving circuits comprises a second switching tube driving circuit and a third switching tube driving circuit, the power input end of the primary side of the second switching tube driving circuit is connected with the auxiliary power supply through a seventh current-limiting resistor and is connected with the anode of a third clamping diode, and the cathode of the third clamping diode is connected with a third PWM signal; the signal input end of the primary side of the optical coupler of the second switching tube driving circuit is connected with a second PWM signal, the power input positive pin of the second switching tube driving circuit is connected with the positive electrode of a fifth isolation power supply, the power input negative pin is connected with the negative electrode of the fifth isolation power supply, and the driving signal output pin is connected with the gate pole of the second switching tube; the power supply input end of the primary side of the optocoupler of the third switching tube driving circuit is connected with an auxiliary power supply through an eighth current limiting resistor and is connected with the anode of a fourth clamping diode, and the cathode of the fourth clamping diode is connected with a third PWM signal; the signal input end of the primary side of the optical coupler of the third switching tube driving circuit is connected with a second PWM signal, the positive pin of the power input of the third switching tube driving circuit is connected with the positive pole of the third isolation power supply, the negative pin of the power input of the third switching tube driving circuit is connected with the negative pole of the third isolation power supply, and the pin of the driving signal output is connected with the gate pole of the third switching tube.
In the HERIC inverter circuit, the power input end of the primary side of the optical coupler of the first follow current tube driving circuit is connected with an auxiliary power supply through a ninth current-limiting resistor, the power input positive pin of the first follow current tube driving circuit is connected with the positive electrode of the fourth isolation power supply, the power input negative pin of the first follow current tube driving circuit is connected with the negative electrode of the fourth isolation power supply, and the driving signal output pin is connected with the gate pole of the first follow current tube; the power input end of the primary side of the optocoupler of the second follow current tube driving circuit is connected with an auxiliary power supply through a tenth current-limiting resistor, the power input positive pin of the second follow current tube driving circuit is connected with the anode of the second isolation power supply, the power input negative pin is connected with the cathode of the second isolation power supply, and the driving signal output pin is connected with the gate pole of the second follow current tube.
The invention can prevent the switch tube and the logic complementary follow current tube from being conducted at the same time, and the circuit has good safety.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a circuit diagram of a HERIC inverter circuit according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a first switching tube driving circuit according to an embodiment of the invention.
Fig. 3 is a circuit diagram of a fourth switching tube driving circuit according to an embodiment of the invention.
Fig. 4 is a circuit diagram of a first follow current tube driving circuit according to an embodiment of the present invention.
Fig. 5 is a circuit diagram of a third switching tube driving circuit according to an embodiment of the invention.
Fig. 6 is a circuit diagram of a second switching tube driving circuit according to an embodiment of the invention.
Fig. 7 is a circuit diagram of a second follow current tube driving circuit according to an embodiment of the present invention.
Fig. 8 is a driving waveform diagram of the inverter circuit according to the embodiment of the present invention.
Detailed Description
The structure and principle of the HERIC inverter circuit of the embodiment of the invention are shown in fig. 1 to 8, and the HERIC inverter circuit comprises a main circuit and a control circuit.
As shown in fig. 1, the main circuit includes an H-bridge circuit composed of two pairs of diagonal switching tubes and a freewheeling circuit composed of two freewheeling tubes connected in series in reverse direction, the switching tubes and the freewheeling tubes are IGBT tubes, the first pair of diagonal switching tubes includes a first switching tube Q101 and a fourth switching tube Q104, and the second pair of diagonal switching tubes includes a second switching tube Q102 and a third switching tube Q103. The collector of the first switch tube Q101 and the collector of the third switch tube Q103 are connected to the direct current positive BUS _ +, and the emitter of the second switch tube Q102 and the emitter of the fourth switch tube Q104 are connected to the direct current negative BUS _ N. The emitter of the first switching tube Q101 is connected to the collector of the second switching tube Q102, and the emitter of the third switching tube Q103 is connected to the collector of the fourth switching tube Q104. The emitter of the first freewheeling tube Q105 is connected to the emitter of the first switching tube Q101, the collector of the first freewheeling tube Q105 is connected to the collector of the second freewheeling tube Q106, and the emitter of the second freewheeling tube Q106 is connected to the collector of the fourth switching tube Q104. The emitter of the first freewheeling tube Q105 is connected to the first end of the output filter capacitor C1101 through the inverting inductor L1101, and the second end of the output filter capacitor C1101 is connected in series with the emitter of the second freewheeling tube Q106 through the inverting inductor L1102.
The control circuit comprises 6 driving circuits, and the driving circuits comprise totem-pole output type optocouplers. The circuit comprises an NPN triode and a PNP triode, a power input positive pin, a power input negative pin and a driving signal output pin, wherein a power input end of an optical coupler secondary side is connected with the power input positive pin, and a grounding end of the optical coupler secondary side is connected with the power input negative pin. The collector of the NPN triode is connected with the positive pin of the power input, the emitter of the NPN triode is connected with the collector of the PNP triode, and the emitter of the PNP triode is connected with the negative pin of the power input. The base electrode of the NPN triode and the base electrode of the PNP triode are connected with the signal output end of the secondary side of the optocoupler, and the emitting electrode of the NPN triode is connected with the driving signal output pin.
The 6 driving circuits comprise a driving circuit of a first pair of diagonal switching tubes, a driving circuit of a second pair of diagonal switching tubes, a driving circuit of a first follow current tube Q105 and a driving circuit of a second follow current tube Q106. The driving circuit of the first pair of diagonal switching tubes comprises a driving circuit of a first switching tube Q101 and a driving circuit of a fourth switching tube Q104, and the driving circuit of the second pair of diagonal switching tubes comprises a driving circuit of a second switching tube Q102 and a driving circuit of a third switching tube Q103.
The 6 driving circuits have substantially the same structure, and the driving circuit of the first switching tube Q101 is taken as an example for explanation: as shown in fig. 2, the driving circuit of the first switching tube Q101 includes a totem-pole output type optical coupler U2101. The driving circuit comprises an NPN triode Q2101, a PNP triode Q2102, a power input positive pin, a power input negative pin and a driving signal output pin, wherein a power input end on the secondary side of the optocoupler U2101 is connected with the power input positive pin, and a grounding end on the secondary side of the optocoupler U2101 is connected with the power input negative pin. The collector of the NPN triode Q2101 is connected with the positive pin of the power input, the emitter of the NPN triode Q2101 is connected with the collector of the PNP triode Q2102, and the emitter of the PNP triode Q2102 is connected with the negative pin of the power input. The base of the NPN triode Q2101 and the base of the PNP triode Q2102 are connected with the signal output end of the secondary side of the optocoupler U2101, and the emitting electrode of the NPN triode Q2101 is connected with a driving signal output pin.
As shown in fig. 2, a power input end of a primary side of the optocoupler U2101 is connected to an auxiliary power VCC through a current limiting resistor R2101, and is connected to an anode of a first clamping diode D2101, and a cathode of the first clamping diode D2101 is connected to a fourth PWM signal PWM 4. The signal input end of the primary side of the optocoupler U2101 is connected with a first PWM signal PWM1, the positive pin of the power input is connected with the positive pole DRV + VCC _1 of the first isolation power supply, the negative pin of the power input is connected with the negative pole DRV-VCC _1 of the first isolation power supply, and the pin of the driving signal output is connected with the gate pole DRV _ PWM1A of the first switching tube Q101.
As shown in fig. 3, a driving circuit of the fourth switching tube Q104 is that a power input end of a primary side of an optocoupler U2201 is connected to an auxiliary power VCC through a current limiting resistor R2201, and is connected to an anode of a second clamping diode D2201, and a cathode of the second clamping diode D2201 is connected to a fourth PWM signal PWM 4. The signal input end of the primary side of the optocoupler U2201 is connected with a first PWM signal PWM1, the positive pin of the power input is connected with the positive pole DRV + VCC of the fifth isolation power supply, the negative pin of the power input is connected with the negative pole DRV-VCC of the fifth isolation power supply, and the pin of the driving signal output is connected with the gate pole DRV _ PWM1B of the fourth switch tube Q104.
As shown in fig. 4, the driving circuit of the second freewheeling tube Q106 is configured such that a power input terminal of a primary side of the optocoupler U2301 is connected to an auxiliary power VCC through a current-limiting resistor R2301, a signal input terminal of a primary side of the optocoupler U2301 is connected to a fourth PWM signal PWM4, a power input positive pin of the driving circuit of the second freewheeling tube Q106 is connected to a second isolation power positive electrode DRV + VCC _2, a power input negative pin is connected to a second isolation power negative electrode DRV-VCC _2, and a driving signal output pin is connected to a gate electrode DRV _ PWM4 of the second freewheeling tube Q106.
As shown in fig. 5, a driving circuit of the second switching tube Q102 is that a power input end of a primary side of the optocoupler U2401 is connected to the auxiliary power VCC through a current limiting resistor R2401, and is connected to an anode of a third clamping diode D2401, and a cathode of the third clamping diode D2401 is connected to a third PWM signal PWM 3. The signal input end of the primary side of the optocoupler U2401 is connected with a second PWM signal PWM2, the positive pin of the power input is connected with the positive pole DRV + VCC of the fifth isolation power supply, the negative pin of the power input is connected with the negative pole DRV-VCC of the fifth isolation power supply, and the pin of the driving signal output is connected with the gate pole DRV _ PWM2B of the second switching tube Q102.
As shown in fig. 6, a driving circuit of the third switching tube Q103 is that a power input end of a primary side of the optocoupler U2501 is connected to an auxiliary power VCC through a current limiting resistor R2501, and is connected to an anode of a fourth clamping diode D2501, and a cathode of the fourth clamping diode D2501 is connected to the third PWM signal PWM 3. The signal input end of the primary side of the optocoupler U2501 is connected with a second PWM signal PWM2, the positive pin of the power input is connected with the positive pole DRV + VCC _3 of the third isolation power supply, the negative pin of the power input is connected with the negative pole DRV-VCC _3 of the third isolation power supply, and the pin of the driving signal output is connected with the gate pole DRV _ PWM2A of the third switching tube Q103.
As shown in fig. 7, the driving circuit of the first freewheeling tube Q105 is configured such that a power input end of a primary side of the optocoupler U2601 is connected to an auxiliary power VCC through a current-limiting resistor R2601, a signal input end of a primary side of the optocoupler U2601 is connected to a third PWM signal PWM3, a positive power input pin of the driving circuit of the first freewheeling tube Q105 is connected to a positive electrode DRV + VCC _4 of the fourth isolation power, a negative power input pin is connected to a negative electrode of the fourth isolation power, and a driving signal output pin is connected to a gate electrode DRV _ PWM3 of the first freewheeling tube Q105.
In the positive half cycle of the output voltage of the HERIC inverter circuit, the first PWM signal PWM1 is logically complementary to the fourth PWM signal PWM4, the second PWM signal PWM2 is at a high level, and the third PWM signal PWM3 is at a low level. In the negative half cycle of the output voltage of the HERIC inverter circuit, the second PWM signal PWM2 is logically complementary to the third PWM signal PWM3, the first PWM signal PWM1 is at a high level, and the fourth PWM signal PWM4 is at a low level. The low level of a PWM signal input by a signal input end of a primary side of the optical coupler is an effective signal, and the high level of the PWM signal is an ineffective signal.
As shown in fig. 8, the driving signal DRV _ PWM1A of the first switch Q101 and the driving signal DRV _ PWM1B of the fourth switch Q104 are logically complementary to the driving signal DRV _ PWM4 of the second freewheeling tube Q106, the driving signal DRV _ PWM3 of the first freewheeling tube Q105 is at a high level, and the driving signal DRV _ PWM2B of the second switch Q102 and the driving signal DRV _ PWM2A of the third switch Q103 are at a low level. In the negative half cycle of the output voltage of the inverter circuit, the driving signal DRV _ PWM2B of the second switching transistor Q102 and the driving signal DRV _ PWM2A of the third switching transistor Q103 are logically complementary to the driving signal DRV _ PWM3 of the first freewheeling transistor Q105, the driving signal DRV _ PWM4 of the second freewheeling transistor Q106 is at a high level, and the driving signal DRV _ PWM1A of the first switching transistor Q101 and the driving signal DRV _ PWM1B of the fourth switching transistor Q104 are at a low level.
In the positive half cycle of the inversion voltage, when the first switch tube Q101 and the fourth switch tube Q104 of the full-bridge topology diagonal tube are switched on, the BUS voltage BUS _ + passes through the first switch tube Q101 and the LC filter, flows through the load RL, and flows back to BUS _ N from the fourth switch tube Q104. When the first switching tube Q101 and the fourth switching tube Q104 are turned off, the currents of the inverting inductors L1101 and L1102 can flow through the body diode of the second freewheeling tube Q106 and the first freewheeling tube Q105 to realize freewheeling, and are completely disconnected from the direct-current bus during freewheeling, so that the common-mode interference of the system can be effectively reduced.
In the negative half cycle of the inversion voltage, when the second switching tube Q102 and the third switching tube Q103 of the full-bridge topology diagonal tube are conducted, the BUS voltage BUS _ + is filtered by the third switching tube Q103 and the LC, flows through the load RL, and flows back to BUS _ N from the second switching tube Q102. When the second switching tube Q102 and the third switching tube Q103 are turned off, the currents of the inverting inductors L1101 and L1102 can flow through the body diode of the first freewheeling tube Q105 and the second freewheeling tube Q106 to realize freewheeling, and are completely disconnected from the direct-current bus during freewheeling, so that the common-mode interference of the system is effectively reduced.
Regarding the switch of the switch tube, when the first switch tube Q101 and the fourth switch tube Q104 are turned on, the second freewheeling tube Q106 cannot be turned on, otherwise, the voltage of the BUS voltage BUS _ + passes through the first switch tube Q101, passes through the body diode of the first freewheeling tube Q105, and flows back to BUS _ N through the second freewheeling tube Q106 and the fourth switch tube Q104, which is equivalent to a short circuit of the dc BUS. When the second switching tube Q102 and the third switching tube Q103 are turned on, the first freewheeling tube Q105 cannot be turned on, otherwise, the voltage of the BUS voltage BUS _ + passes through the third switching tube Q103, passes through the body diode of the second freewheeling tube Q106, flows through the first freewheeling tube Q105 and the second switching tube Q102, and returns to BUS _ N, which is equivalent to a direct-current BUS short circuit. Namely, the driving signals of the first switch tube Q101 and the fourth switch tube Q104 of the full-bridge topology first diagonal tube and the second follow current tube Q106 are complementary logically, when the first switch tube Q101 and the fourth switch tube Q104 are switched on, the second follow current tube Q106 is switched off, and when the first switch tube Q101 and the fourth switch tube Q104 are switched off, the second follow current tube Q106 is switched on; the driving signals of the second follow current tube Q102 and the third follow current tube Q103 of the full-bridge topology second diagonal tube are complementary with the driving signals of the first follow current tube Q105 of the follow current tube, when the second switch tube Q102 and the third switch tube Q103 are switched on, the first follow current tube Q105 is switched off, and when the second switch tube Q102 and the third switch tube Q103 are switched off, the first follow current tube Q105 is switched on.
When the driving signal PMW1 of the driving circuit of the first switching tube Q101 and the driving circuit of the fourth switching tube Q104 is at a low level, in the driving circuit of the first switching tube Q101, a current flows from the auxiliary power source VCC through the current-limiting resistor R2101 and the primary diode of the optocoupler U2101, flows back to the reference ground of the auxiliary power source VCC through the PWM1 low-resistance path, and the power input positive pin of the optocoupler U2101 is connected to the first isolation power source positive electrode DRV + VCC _ 1. In the driving circuit of the fourth switching tube Q104, current flows from an auxiliary power supply VCC through a current-limiting resistor R2201 and a primary side diode of an optocoupler U2201, and flows back to the reference ground of the auxiliary power supply VCC through a PWM1 low-resistance path, and a power input positive pin of the optocoupler U2201 is connected with a fifth isolation power supply positive electrode DRV + VCC. DRV _ PWM1A and DRV _ PWM1B are driving signals output by the driving circuit of the first switching transistor Q101 and the driving circuit of the fourth switching transistor Q104, respectively, and the amplitudes of the driving signals are close to the voltages of the isolated power supplies DRV + VCC _1 and DRV + VCC 15V, respectively. At this time, if the driving signal PWM4 of the driving circuit of the second follow current transistor Q106 is also at the active level low level, the driving circuit of the first switching tube Q101 and the driving circuit of the fourth switching tube Q104 controlled by the PMW1 are clamped and cannot output the driving signal, the principle is that the diode conduction voltage drop of the primary side of the photocoupler is about 1V, the conduction voltage drops of the clamping circuit diodes D2101 and D2201 connected between the current limiting circuit and the anode of the primary side diode of the photocoupler are about 0.3-0.7V, the current of the auxiliary power VCC does not flow through the diode of the primary side of the photocoupler of the driving circuit of the first switching tube Q101 and the driving circuit of the fourth switching tube Q104, but directly flows through the clamping circuit diode, flows back to the reference ground of the auxiliary power VCC through the low resistance path of the driving signal PWM4, at this time, the diode of the isolation driving circuit of the first switching tube Q101 and the driving circuit of the fourth switching tube Q104 has no current, the output end of the photoelectric coupler has no output, and the bridge arm is in a cut-off state, so that the first switching tube Q101 and the fourth switching tube Q104 cannot be damaged due to short circuit. The protection principle of the second switching tube Q102 is the same as that of the third switching tube Q103.
The HERIC inverter circuit of the embodiment of the invention is simple and effective, can be applied to drive of HERIC topology and other power semiconductor switch tubes with complementary switch logics, and converts the driving state of simultaneously outputting effective levels caused by interference or misoperation and component damage into the driving state of only one effective level, so that the switch tubes are effectively protected.
Claims (7)
1. The HERIC inverter circuit is characterized by comprising a main circuit and a control circuit, wherein the main circuit comprises an H-bridge circuit consisting of two pairs of diagonal switching tubes and a follow current circuit consisting of two follow current tubes which are connected in series in a reverse direction, the control circuit comprises a plurality of driving circuits, and the plurality of driving circuits comprise a first pair of diagonal switching tube driving circuits, a second pair of diagonal switching tube driving circuits, a first follow current tube driving circuit and a second follow current tube driving circuit; the first diagonal switch tube driving circuit is driven by a first PWM signal, the second follow current tube driving circuit is driven by a fourth PWM signal, and the power supply input end of the first diagonal switch tube driving circuit is clamped by the fourth PWM signal; the driving of the second pair of diagonal switching tube driving circuits is driven by a second PWM signal, the first follow current tube driving circuit is driven by a third PWM signal, and the power supply input ends of the second pair of diagonal switching tube driving circuits are clamped by the third PWM signal; the low level of a driving signal input by the driving circuit is effective, the first PWM signal and the fourth PWM signal are complementary in logic in the positive half cycle of the output voltage of the HERIC inverter circuit, the second PWM signal is high level, and the third PWM signal is low level; in the negative half cycle of the output voltage of the HERIC inverter circuit, the second PWM signal is in logic complementation with the third PWM signal, the first PWM signal is at a high level, and the fourth PWM signal is at a low level.
2. The HERIC inverter circuit of claim 1, wherein the driving circuit comprises an optocoupler, said optocoupler being a totem-pole output optocoupler; the power supply input ends of the primary sides of the optocouplers of the switch tube driving circuits at the first diagonal are connected with an auxiliary power supply through a first current-limiting resistor and connected with a fourth PWM signal through a first clamping circuit, and the signal input ends of the primary sides of the optocouplers of the switch tube driving circuits at the first diagonal are connected with the first PWM signal; the power supply input end of the primary side of the optocoupler of the second follow current tube driving circuit is connected with an auxiliary power supply through a second current limiting resistor, and the signal input end of the primary side of the optocoupler of the second follow current tube driving circuit is connected with a fourth PWM signal; the power supply input ends of the primary sides of the optocouplers of the switch tube driving circuits at the second pair of opposite angles are connected with an auxiliary power supply through a third current-limiting resistor and connected with a third PWM signal through a second clamping circuit, and the signal input ends of the primary sides of the optocouplers of the switch tube driving circuits at the second pair of opposite angles are connected with a second PWM signal; the power input end of the primary side of the optocoupler of the first follow current tube driving circuit is connected with an auxiliary power supply through a fourth current limiting resistor, and the signal input end of the primary side of the optocoupler of the first follow current tube driving circuit is connected with a third PWM signal.
3. The HERIC inverter circuit according to claim 2, wherein the switching transistors and the freewheeling transistor are IGBT transistors, the first diagonal switching transistor pair comprises a first switching transistor and a fourth switching transistor, and the second diagonal switching transistor pair comprises a second switching transistor and a third switching transistor; the collector of the first switch tube and the collector of the third switch tube are connected with a direct current positive bus, and the emitter of the second switch tube and the emitter of the fourth switch tube are connected with a direct current negative bus; the emitter of the first switching tube is connected with the collector of the second switching tube, and the emitter of the third switching tube is connected with the collector of the fourth switching tube; the emitter of the first afterflow tube is connected with the emitter of the first switch tube, the collector of the first afterflow tube is connected with the collector of the second afterflow tube, and the emitter of the second afterflow tube is connected with the collector of the fourth switch tube; one end of the output filter capacitor is connected with the emitting electrode of the first follow current tube, and the other end of the output filter capacitor is connected with the emitting electrode of the second follow current tube; the inversion inductor is connected in series among the emitter of the first follow current tube, the emitter of the second follow current tube and the output filter capacitor.
4. The HERIC inverter circuit according to claim 3, wherein the driving circuit comprises an NPN transistor and a PNP transistor, a positive power input pin, a negative power input pin and a driving signal output pin, a power input end of the secondary side of the optical coupler is connected with the positive power input pin, and a ground end of the secondary side of the optical coupler is connected with the negative power input pin; the collector of the NPN triode is connected with the positive pin of the power input, the emitter of the NPN triode is connected with the collector of the PNP triode, and the emitter of the PNP triode is connected with the negative pin of the power input; the base electrode of the NPN triode and the base electrode of the PNP triode are connected with the signal output end of the secondary side of the optocoupler, and the emitting electrode of the NPN triode is connected with the driving signal output pin.
5. The HERIC inverter circuit according to claim 4, wherein the first diagonal switching tube driving circuit comprises a first switching tube driving circuit and a fourth switching tube driving circuit, the power input end of the primary side of the optical coupler of the first switching tube driving circuit is connected with an auxiliary power supply through a fifth current limiting resistor and is connected with the anode of a first clamping diode, and the cathode of the first clamping diode is connected with a fourth PWM signal; the signal input end of the primary side of the optical coupler of the first switching tube driving circuit is connected with a first PWM signal, the positive pin of the power input of the first switching tube driving circuit is connected with the positive pole of a first isolation power supply, the negative pin of the power input is connected with the negative pole of the first isolation power supply, and the output pin of the driving signal is connected with the gate pole of the first switching tube; the power supply input end of the primary side of the optical coupler of the fourth switching tube driving circuit is connected with an auxiliary power supply through a sixth current-limiting resistor and is connected with the anode of a second clamping diode, and the cathode of the second clamping diode is connected with a fourth PWM signal; the signal input end of the primary side of the optical coupler of the fourth switching tube driving circuit is connected with a first PWM signal, the positive pin of the power input of the fourth switching tube driving circuit is connected with the positive electrode of the fifth isolation power supply, the negative pin of the power input is connected with the negative electrode of the fifth isolation power supply, and the pin of the driving signal output is connected with the gate pole of the fourth switching tube.
6. The HERIC inverter circuit of claim 4, wherein the second pair of diagonal switching tube driving circuits comprises a second switching tube driving circuit and a third switching tube driving circuit, the power input end of the primary side of the optical coupler of the second switching tube driving circuit is connected with the auxiliary power supply through a seventh current limiting resistor and is connected with the anode of a third clamping diode, and the cathode of the third clamping diode is connected with a third PWM signal; the signal input end of the primary side of the optical coupler of the second switching tube driving circuit is connected with a second PWM signal, the power input positive pin of the second switching tube driving circuit is connected with the positive electrode of a fifth isolation power supply, the power input negative pin is connected with the negative electrode of the fifth isolation power supply, and the driving signal output pin is connected with the gate pole of the second switching tube; the power supply input end of the primary side of the optocoupler of the third switching tube driving circuit is connected with an auxiliary power supply through an eighth current limiting resistor and is connected with the anode of a fourth clamping diode, and the cathode of the fourth clamping diode is connected with a third PWM signal; the signal input end of the primary side of the optical coupler of the third switching tube driving circuit is connected with a second PWM signal, the positive pin of the power input of the third switching tube driving circuit is connected with the positive pole of a third isolation power supply, the negative pin of the power input is connected with the negative pole of the third isolation power supply, and the pin of the driving signal output is connected with the gate pole of the third switching tube.
7. The HERIC inverter circuit according to claim 4, wherein the primary side of the first freewheeling tube driver circuit is connected to the auxiliary power source through a ninth current-limiting resistor, the positive pin of the power input of the first freewheeling tube driver circuit is connected to the positive pole of the fourth isolation power source, the negative pin of the power input of the first freewheeling tube driver circuit is connected to the negative pole of the fourth isolation power source, and the pin of the driving signal output is connected to the gate of the first freewheeling tube; the power input end of the primary side of the optocoupler of the second follow current tube driving circuit is connected with an auxiliary power supply through a tenth current-limiting resistor, the power input positive pin of the second follow current tube driving circuit is connected with the anode of the second isolation power supply, the power input negative pin is connected with the cathode of the second isolation power supply, and the driving signal output pin is connected with the gate pole of the second follow current tube.
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| DE10221592A1 (en) * | 2002-05-15 | 2003-12-04 | Fraunhofer Ges Forschung | Current inverter for direct/alternating currents, has direct and alternating connections with an intermediate power store, a bridge circuit, rectifier diodes and a inductive choke |
| CN105375750A (en) * | 2015-12-17 | 2016-03-02 | 南京工程学院 | Driving protection circuit for preventing bridge arm direct connection |
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Application publication date: 20220809 |