CN114676629A - Multi-means composite light weight processing method for modulation type recognition model - Google Patents

Multi-means composite light weight processing method for modulation type recognition model Download PDF

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CN114676629A
CN114676629A CN202210271933.9A CN202210271933A CN114676629A CN 114676629 A CN114676629 A CN 114676629A CN 202210271933 A CN202210271933 A CN 202210271933A CN 114676629 A CN114676629 A CN 114676629A
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齐佩汉
杨子
高晶亮
孟永超
周小雨
李赞
张正宇
刘文琛
李鹏飞
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Xidian University
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Abstract

The invention discloses a multi-hand composite modulation type recognition model lightweight processing method, which comprises the steps of designing and building a high-performance electromagnetic signal modulation type recognition network ResNet, and collecting and generating a data set containing multiple modulation types under various signal-to-noise ratios from an FPGA (field programmable gate array); training the network based on the data set containing multiple modulation types under various signal-to-noise ratios; performing progressive pruning on the network by combining the resource amount of the FPGA through an FPGM pruning algorithm until each layer is pruned with 97% of parameters; calculating the similarity of fixed point numbers and floating point numbers by combining Euclidean distances, determining a quantization proportion capable of expressing the optimal performance of the network, and deriving quantized parameters; preprocessing IQ data on an FPGA, then fusing a BN layer and a convolution layer, designing a full-parallel and partial-parallel implementation scheme based on a shift register, analyzing the maximum and minimum values of output data of each layer by utilizing Matlab, and determining the truncation standard of the data; and finally, verifying the correctness of the network.

Description

Multi-means composite modulation type identification model lightweight processing method
Technical Field
The invention belongs to the cognitive radio related communication technology, and particularly relates to a lightweight processing method of a multi-means composite modulation type identification model.
Background
With the wide use of various radio devices, more and more radiation sources are used in the electromagnetic environment, the electromagnetic spectrum is more and more congested, and a large number of communication signals with different purposes are overlapped in the electromagnetic space to construct a more and more complex electromagnetic environment. In order to better monitor and analyze these signals, researchers have proposed cognitive radio technology, and modulation recognition is one of the key technologies in the field of cognitive radio technology. The basic task of communication signal modulation identification is to determine the modulation mode of a received signal in the environment with a large amount of interference signals and noise, and two identification methods based on decision theory or characteristics are developed for the purpose. But these two methods are not flexible to accommodate communication scenarios with different transmission channels and additive noise.
Along with the development of deep learning theory, artificial intelligence technology is applied to various industries, and partial research results are obtained by completing modulation recognition by utilizing deep learning. However, as the performance of the deep learning model needs to be improved by large data samples and deep hierarchical structures, the construction of the networks needs to rely on a server with high memory and high throughput. Therefore, in order to apply deep learning to resource-constrained devices, a neural network trained based on large data samples needs to be converted into small data samples, and further, the complex network needs to be light-weighted.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a light-weight processing method for a multi-means composite modulation type identification model.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a light-weight processing method of a multi-means composite modulation type identification model, which comprises the following steps:
designing and building a high-performance electromagnetic signal modulation type identification network ResNet, and acquiring and generating a data set containing multiple modulation types under various signal-to-noise ratios from an FPGA;
training the network based on the data set containing multiple modulation types under various signal-to-noise ratios;
performing progressive pruning on the network by combining the resource amount of the FPGA through an FPGM pruning algorithm until each layer is pruned with 97% of parameters;
calculating the similarity of fixed point numbers and floating point numbers by combining Euclidean distances, determining a quantization proportion capable of expressing the optimal performance of the network, and deriving quantized parameters;
preprocessing IQ data on an FPGA, then fusing a BN layer and a convolution layer, designing a full-parallel and partial-parallel implementation scheme based on a shift register, analyzing the maximum and minimum values of output data of each layer by utilizing Matlab, and determining the truncation standard of the data;
And finally, verifying the correctness of the network.
In the above scheme, the designing and building of the high-performance electromagnetic signal modulation type identification network ResNet, and the collecting and generating of the data set containing multiple modulation types under various signal-to-noise ratios from the FPGA specifically include: building a ResNet network, dividing 6 convolution blocks according to the number of output channels, totally 21 convolution layers, 1 average pooling layer and 1 full-connection layer, and deriving 12 modulation type signals of-10 dB to 20dB by using ILA based on a frequency spectrum sensing system of FPGA and AD 9361: ASK, BPSK, QPSK, 8PSK, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, MSK, 2FSK, 4FSK, and follows a 4: the scale of 1 is organized into a data set.
In the above scheme, the network is pruned progressively by combining the resource amount of the FPGA through the FPGM pruning algorithm until each layer is pruned with 97% of the parameters, specifically: pruning m convolution kernels from the ith convolution layer, and finding out m convolution kernels with the minimum sum of Euclidean distances between the m convolution kernels and the rest convolution kernels from the convolution kernels of the current layer; deleting m convolution kernels and feature maps corresponding to the convolution kernels; deleting m input channel parameters of the next layer of convolution kernels according to the feature mapping after pruning; creating a new convolution kernel matrix according to the pruning results of the current layer and the next layer, and copying the remaining weight into a new model; and comparing the DSP resource number under three parallel designs, pruning the network according to the FPGM algorithm by taking the input channel full parallel design scheme with the least resource requirement as a standard, and adopting a scheme of gradually pruning for 5 times in the pruning process, namely training the network again after each pruning is finished until each layer of the network has 97% of parameters.
In the above solution, the calculating, by combining the euclidean distance, the similarity between the fixed point number and the floating point number, determining the quantization scale capable of expressing the optimal performance of the network, and deriving the quantized parameters specifically include: selecting the Q value for multiple times, importing the parameters into the FPGA model after each quantization, and saving the fixed point number of each layer for output; then, verifying the output of each layer based on the Euclidean distance, wherein the smaller the Euclidean distance is, the greater the data similarity is; the larger the euclidean distance, the smaller the data similarity,
Figure RE-GDA0003602520650000031
where { x1,x2,...,xnDenotes the n floating-point number results output by the i-th layer of the neural network, { y }1,y2,...,ynN fixed points for indicating the output of the ith layer of the FPGAThe result of the floating point processing is finally the parameters which can best express the network are derived from Pythrch.
In the above scheme, the preprocessing is performed on the IQ data on the FPGA, specifically: i, Q data collected by hardware are respectively I (N) and Q (N), the sequence length is N, the mean value is obtained:
Figure RE-GDA0003602520650000032
Figure RE-GDA0003602520650000033
the standard deviation of the two sets of data were then calculated:
Figure RE-GDA0003602520650000034
Figure RE-GDA0003602520650000035
finally, based on the obtained mean and standard deviation, the normalized I, Q data sets can be calculated by the following formula:
Figure RE-GDA0003602520650000036
Figure RE-GDA0003602520650000037
in order to avoid normalization to obtain a positive number less than 1, the quantization operation is advanced and fused with the above formula to obtain the following formula:
Figure RE-GDA0003602520650000041
Figure RE-GDA0003602520650000042
In the above scheme, the merging of the BN layer and the convolutional layer and based on a shift register specifically includes: for the convolution layer, assuming the weight of a convolution kernel is W, the convolution process is calculated by using a sliding window of W in an input feature map of the convolution kernel; assuming that one element in W is W and one element in the input feature map is x, the calculation process for W and x is as follows:
yconv＝w·x+b
for a BN layer, determining the mean variance of elements in the mini-batch, then subtracting the mean value from x to divide by the standard deviation, and finally carrying out affine transformation by utilizing gamma and beta to obtain the final BN output, wherein the specific process is as follows:
Figure RE-GDA0003602520650000043
Figure RE-GDA0003602520650000044
Figure RE-GDA0003602520650000045
Figure RE-GDA0003602520650000046
the first is an average formula, the second is a variance formula, the third is a normalization formula, and the fourth is an affine transformation formula, and the convolutional layer formula is substituted into the BN layer formula to obtain the following formula:
Figure RE-GDA0003602520650000047
wherein gamma is,β、μ、σ2Are all parameters of the BN layer.
In the above scheme, the implementation scheme of designing full parallelism and partial parallelism specifically includes: when the Conv1 layer full parallel design is carried out, firstly, 30 shift registers are designed to respectively cache IQ two-path data, when all the registers are full, convolution multiplication operation is carried out, and then an adder of full flow water is designed to accumulate convolution multiplication results; when the Conv2_1 layer input channels are designed in a fully parallel mode, firstly, convolution kernels are spliced in groups according to the input channels and are stored permanently, then, the input parameters are repeatedly read for times equal to the number of output channels and are subjected to convolution operation with convolution kernel parameters in the same format, at the moment, results equal to the number of the input channels are obtained, each input channel corresponds to one input channel and contains the results of all the output channels, and then, the results are correspondingly added according to the input channels to obtain the final output result; and outputting the output result in a serial mode, disassembling the serial result, storing the serial result into a plurality of RAMs respectively, and waiting for the next convolution operation.
In the above scheme, the analyzing the maximum and minimum values of the output data of each layer by using Matlab, and determining the truncation standard of the data specifically include: respectively truncating the decimal and the integer, truncating the decimal according to a rounding method, and keeping the bit width at 16 bits; after each layer of building is completed, the output data of the layer needs to be simulated through a Vivado Simulator. In the simulation process, firstly, the output data of the layer is written into a text document through file writing operation, then the data in the text document is analyzed by using a Matlab program, the maximum value and the minimum value of the data of the current layer are found out, and finally, the integer part is truncated according to the maximum value and the minimum value.
In the above scheme, the verifying the correctness of the network specifically includes: a group of data is arbitrarily read in a data set, wherein the data set comprises 12 modulation modes, each group comprises 256 groups, each group comprises 512 x 2 data and 3072 groups of data, the data are decomposed into a coe file which can be identified by Xilinx FPGA through a python script, the file is associated to Rom, and a convolution module judges a final result based on the data.
Compared with the prior art, in order to avoid performance reduction caused by light weight, the ResNet residual error neural network model with higher complexity is selected for electromagnetic signal identification; according to the invention, a compression method combining pruning and quantization is adopted, on one hand, 97% of parameters are pruned in each layer, and the network still has good performance under a signal-to-noise ratio of more than 5db which is concerned, on the other hand, a 19-bit quantization scheme capable of best expressing a model is selected through Euclidean distance test, so that the parameter quantization is realized; the invention selects a method for directly carrying out logic design, and realizes the ResNet deployment on the resource-limited equipment (FPGA) through a full-parallel and partial-parallel scheme in the actual implementation process.
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The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a selected ResNet structure diagram;
FIG. 2 is a diagram of the amount of DSP resources required by the FPGA under three parallel schemes;
FIG. 3 is a comparison of test accuracy for a pruned network and an original network;
FIG. 4 is a diagram of the ResNet structure after pruning is complete;
FIG. 5 is a diagram of the amount of DSP resources required for the ResNet input full parallel design after pruning is complete;
FIG. 6 is a partial parameter value before and after quantization;
FIG. 7 is the architectural partitioning of an FPGA implementation ResNet;
FIG. 8 is an operation flow of the FPGA to implement Conv1 layer convolution;
FIG. 9 is the data flow of Conv2_0 layer in a fully parallel design;
FIG. 10 is a single layer computation process in a fully parallel design of input channels.
Fig. 11 shows the data flow of the Conv2_1 layer in the fully parallel input channel design.
Fig. 12 is (one of) FPGA decision result presentation.
Fig. 13 is a basis for FPGA decision results.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but also other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, article, or apparatus that comprises the element.
According to the method, firstly, a ResNet model with a complex structure is selected as a modulation recognition network, then the network is pruned 5 times by using an FPGM algorithm through a scheme of repeated progressive pruning, 50% of parameters are pruned each time, then the similarity between the quantized parameters and floating point parameters is checked by using Euclidean distance, a 19-bit quantization scheme capable of more accurately expressing the network is determined, finally, a realization scheme of combining full parallelism and partial parallelism is directly designed on the basis of Verilog codes on an FPGA, an intercept standard is determined by using Matlab, and the feasibility of a multi-hand lightweight method is verified through test simulation.
The embodiment of the invention provides a multi-means composite modulation type identification model lightweight processing method, which comprises the following steps:
step 1.1, building a ResNet network as shown in FIG. 1, and dividing 6 convolution blocks (21 convolution layers in total), 1 average pooling layer and 1 full connection layer according to the number of output channels.
Step 1.2, based on a spectrum sensing system of FPGA and AD9361, deriving 12 modulation type signals of-10 dB to 20dB by using ILA: ASK, BPSK, QPSK, 8PSK, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, MSK, 2FSK, 4 FSK. And collated into a data set.
Compared with a general neural network, the ResNet network introduces a cross-connection capable of enhancing information flow between layers, and a spectrum sensing system based on an FPGA and an AD9361 uses ILA to derive signals of 12 modulation types.
And 2.1, importing a data set, setting a batch parameter as 100, an epoch parameter as 10 and a learning rate as 0.001 in the network, training the network, and deriving the test accuracy under the optimal parameter.
And training the network on a server based on a Pythrch platform, and storing the optimal network parameters.
Step 3.1, pruning the network by using an FPGM pruning algorithm, wherein the process of pruning m convolution kernels from the ith convolution layer is as follows:
a. And finding the convolution kernel with the minimum sum of the m convolution kernels and the Euclidean distances of the rest convolution kernels from the convolution kernels of the current layer.
b. Deleting m convolution kernels and the feature maps corresponding to the convolution kernels (namely deleting m convolution kernels and the output feature matrix of the ith layer).
c. And deleting m input channel parameters of the convolution kernel of the next layer according to the pruned feature mapping (namely deleting m input channels in the convolution kernel of the (i + 1) th layer).
d. And creating a new convolution kernel matrix according to the pruning results of the current layer and the next layer, and copying the rest weight values into the new model.
And 3.2, comparing the DSP resource numbers under the three parallel designs in the figure 2, and pruning the network according to the method in the step 3.1 by taking the input channel full parallel design scheme with the least resource requirement as a standard. In the pruning process, a scheme of 5 times progressive pruning is adopted, namely, the network is trained again after each pruning process is finished until each layer of pruning process has 97% of parameters, so that the test accuracy shown in figure 3, the final network structure shown in figure 4 and the minimum DSP resource amount required for building the network on the FPGA shown in figure 5 are obtained;
and selecting an FPGM pruning algorithm based on a geometric median, and taking 900 dsp resources of the used FPGA and the speed requirement of the whole system into consideration, and performing progressive pruning on the network, namely training the network once after each pruning until a network model which can be deployed on the FPGA is obtained.
Step 4.1, as shown in fig. 6, the network parameters are quantized based on the method of converting floating point numbers into fixed point numbers, and the concrete formula is as follows:
y＝x×2Q
the Q value is decimal bit width set by fixed point, x is floating point number, and y is fixed point number.
Step 4.2, the Q values are selected multiple times in order to find the best quantization scheme. And importing the parameters into the FPGA model every time the quantization is finished, and saving the fixed point number of each layer for output. The output of each layer is then verified based on the euclidean distance. The smaller the Euclidean distance is, the greater the data similarity is; the larger the euclidean distance, the smaller the data similarity.
Figure RE-GDA0003602520650000081
Where { x1,x2,...,xnDenotes the n floating-point number results output by the i-th layer of the neural network, { y }1,y2,...,ynAnd (4) representing the result of floating pointing n fixed point numbers output by the ith layer of the FPGA, and finally deriving parameters capable of best expressing the network from the Pythrch.
As shown in fig. 7, the present invention implements a light neural network on an FPGA by a scheme of partial parallel and full parallel, and includes the following specific steps:
and 5.1, preprocessing the IQ data, normalizing the IQ data and quantizing the IQ data. The treatment process is as follows:
i, Q data collected by hardware are respectively I (N) and Q (N), the sequence length is N, the mean value is obtained:
Figure RE-GDA0003602520650000091
Figure RE-GDA0003602520650000092
The standard deviation of the two sets of data were then calculated:
Figure RE-GDA0003602520650000093
Figure RE-GDA0003602520650000094
finally, according to the obtained mean and standard deviation, the normalized I, Q data sets can be calculated by the following formula:
Figure RE-GDA0003602520650000095
Figure RE-GDA0003602520650000096
to avoid normalization to get positive numbers smaller than 1, we advance the quantization operation and fuse it with the above formula to get the following formula:
Figure RE-GDA0003602520650000097
Figure RE-GDA0003602520650000098
step 5.2, when designing the convolutional layer, in order to simplify the program design, the invention adopts a method of fusing a BN layer and the convolutional layer, and the detailed process is as follows:
for the convolutional layer:
assuming that the weight of a convolution kernel is W, the convolution process is calculated by utilizing a sliding window of W in an input feature map of the convolution kernel; assuming that one element in W is W and one element in the input feature map is x, the calculation process for W and x is as follows:
yconv＝w·x+b
for the BN layer:
the mean variance of elements in a mini-batch needs to be calculated, then the mean is subtracted from x to be divided by the standard deviation, finally, affine transformation is carried out by utilizing gamma and beta, and the final BN output can be obtained, wherein the specific process is as follows:
Figure RE-GDA0003602520650000101
Figure RE-GDA0003602520650000102
Figure RE-GDA0003602520650000103
Figure RE-GDA0003602520650000104
the first is a mean value solving formula, the second is a variance solving formula, the third is a normalization formula, and the fourth is an affine transformation formula. Substituting the convolutional layer formula into the BN layer formula results in the following formula:
Figure RE-GDA0003602520650000105
Wherein gamma, beta, mu, sigma2Are all parameters of the BN layer.
Step 5.3, as shown in fig. 8, when the Conv1 layer full parallel design is performed, first, 30 shift registers are designed to buffer IQ two-way data (15 each), and after all registers are full, convolution multiplication is performed. Then designing a full-flow adder to accumulate the result of convolution multiplication.
When the Conv2_0 layer is designed to be fully parallel, 3 shift registers are designed first, and the output of the previous layer is buffered. When all registers are full, convolution multiplication is performed. And then designing a full-flow adder to accumulate the result of the convolution multiplication. Fig. 9 shows the overall design of Conv2_ 0.
As shown in fig. 10, when the input channels are designed to be fully parallel, the convolution kernels are first grouped and concatenated (parameters of the same input channel are concatenated together) according to the input channels, and are permanently stored. And then, repeatedly reading the input parameters for times equal to the number of output channels, and carrying out convolution operation on the input parameters and the convolution kernel parameters with the same format. At this time, the result equal to the number of the input channels is obtained, each corresponding to one input channel and including the results of all the output channels, and then the results are correspondingly added according to the input channels to obtain the final output result. The result is output in a serial manner, and for the convenience of implementation of a subsequent network layer, the serial result needs to be disassembled and then stored in a plurality of RAMs respectively to wait for the next convolution operation. Fig. 11 shows the overall design of Conv2_1 implemented based on the above idea.
Step 5.4, respectively truncating the decimal and the integer, truncating the decimal according to a rounding method, and keeping the bit width at 16 bits; after each layer of building is completed, the output data of the layer needs to be simulated through a Vivado Simulator. In the simulation process, firstly, the output data of the layer is written into a text document through file writing operation, then the data in the text document is analyzed by using a Matlab program, the maximum value and the minimum value of the data of the current layer are found out, and finally, the integer part is truncated according to the maximum value and the minimum value. Through a plurality of experiments, the maximum value of the integer part of the first six modules does not exceed 7 (3-bit binary). However, in order to ensure the safety of the whole system, the integer bit is set to be 5 bits (maximum number can represent decimal number 31) in the implementation process of ResNet.
Step 5.5, verification of the result as in fig. 12, 13. And after the whole structure is realized, filling a data verification result, wherein the detailed process is as follows: a group of data is read in a data set (12 modulation modes, 256 groups of each modulation mode, 512 x 2 data in each group, 3072 groups of data in total), the data is decomposed into a coe file which can be identified by Xilinx FPGA through a python script, the file is associated to Rom, and a convolution module judges a final result based on the data. In this example, the 60 th group of data having a modulation scheme of 8PSK was used, and the verification was completed.
Firstly, IQ data acquired by hardware needs to be processed, then a ResNet network is divided into 5 large blocks, each block comprises 2 residual error structures, each residual error structure comprises 2 convolutional layers, 2 BN layers and 2 Relu active layers, due to the fact that the network structure is relatively complex, the interactive mode, the implementation mode, the data storage mode and the like of each block need to be designed, and meanwhile, in order to fully utilize the characteristic of parallelism of an FPGA, parallel operation needs to be achieved as much as possible.
And then, the bit width of the data in the operation process is intercepted, and finally, the correctness of the network function is verified through the simulation of multiple groups of data, so that the feasibility of the multi-hand composite lightweight method is verified.
Simulation conditions
1. Training an original ResNet network and a new network which carries out 5 times of progressive pruning based on an FPGM algorithm, and specifically setting the following steps:
(1) 12 modulation type signals with parameters of-10 dB to 20dB (starting from-10 dB, step size is 2, and total 16 signal-to-noise ratios) are adopted: ASK, BPSK, QPSK, 8PSK, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, MSK, 2FSK, 4 FSK;
(2) the learning rate is 0.001, the epoch is 10, and the batch is 100;
(3) a total of 21 convolutional layers, 10 residual blocks, in both networks use the Relu function as the activation function.
2. Simulating a network built by the FPGA, and setting the following settings:
(1) the network parameters are all parameters quantized by 19 bits, and the network structure design is strictly according to the method of the invention;
(2) one group of data is read in a data set (12 modulation modes, 256 groups of data, 512 x 2 data in each group, and 3072 groups of data in total), and the data is decomposed into coe files which can be identified by Xilinx FPGA through a python script, and the files are related to Rom. The convolution module determines a final result based on the data.
Two groups are randomly extracted from 12 modulation modes respectively for function verification.
Simulation result
1. As shown in fig. 3, under the signal-to-noise ratio condition below 5dB, the pruning causes the network performance loss to be large, the loss is the highest near 0dB, and the performance is reduced by about 14%. But the network exhibits good performance under the more interesting signal-to-noise ratio conditions of 5dB and above. With the loss of performance being greatest at 5dB, approximately a 3% decrease. While the larger the signal-to-noise ratio, the smaller the performance loss. Therefore, the network obtained by pruning 97% of parameters of each layer can still be used as an effective modulation type identification network, and the current progressive pruning scheme is feasible.
2. In this example, only the verification of the 60 th group of data with the modulation scheme of 8PSK is shown: as shown in fig. 12(a), 12 results outputted after passing through the full connection layer are shown, each result corresponds to one modulation mode; as shown in fig. 12(b), the final decision result is shown, and the result is the number corresponding to the maximum value obtained by comparing the 12 values in the graph (a). The decision is error free according to the criteria as in fig. 13. The judgment is correct when other data are tested, and the compression method combining pruning and quantification is proved to be capable of designing a light neural network which can be deployed on resource-limited equipment.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (9)

1. A multi-means composite modulation type recognition model lightweight processing method is characterized by comprising the following steps:
designing and building a high-performance electromagnetic signal modulation type identification network ResNet, and acquiring and generating a data set containing multiple modulation types under various signal-to-noise ratios from an FPGA;
training the network based on the data set containing multiple modulation types under various signal-to-noise ratios;
performing progressive pruning on the network by combining the resource amount of the FPGA through an FPGM pruning algorithm until each layer is pruned with 97% of parameters;
calculating the similarity of fixed point numbers and floating point numbers by combining Euclidean distances, determining a quantization proportion capable of expressing the optimal performance of the network, and deriving quantized parameters;
preprocessing IQ data on an FPGA, then fusing a BN layer and a convolution layer, designing a full-parallel and partial-parallel implementation scheme based on a shift register, analyzing the maximum and minimum values of output data of each layer by utilizing Matlab, and determining the truncation standard of the data;
and finally, verifying the correctness of the network.
2. The multi-means composite modulation type identification model lightweight processing method according to claim 1, characterized in that a high-performance electromagnetic signal modulation type identification network ResNet is designed and built, and a data set containing a plurality of modulation types under various signal-to-noise ratios is collected and generated from an FPGA, specifically: building a ResNet network, dividing 6 convolution blocks according to the number of output channels, totally 21 convolution layers, 1 average pooling layer and 1 full-connection layer, and deriving 12 modulation type signals of-10 dB to 20dB by using ILA based on a frequency spectrum sensing system of FPGA and AD 9361: ASK, BPSK, QPSK, 8PSK, 16QAM, 32QAM, 64QAM, 128QAM, 256QAM, MSK, 2FSK, 4FSK, and follows a 4: the scale of 1 is organized into a data set.
3. The multi-means composite modulation type recognition model lightweight processing method according to claim 1 or 2, wherein the network is pruned progressively by the FPGM pruning algorithm in combination with the resource amount of the FPGA until each layer prunes 97% of the parameters, specifically: pruning m convolution kernels from the ith convolution layer, and finding m convolution kernels with the minimum sum of Euclidean distances between the m convolution kernels and the rest convolution kernels from the convolution kernels of the current layer; deleting m convolution kernels and feature maps corresponding to the convolution kernels; deleting m input channel parameters of the next layer of convolution kernels according to the feature mapping after pruning; creating a new convolution kernel matrix according to the pruning results of the current layer and the next layer, and copying the remaining weight into a new model; and comparing the DSP resource number under three parallel designs, pruning the network according to the FPGM algorithm by taking the input channel full parallel design scheme with the least resource requirement as a standard, and adopting a scheme of gradually pruning for 5 times in the pruning process, namely training the network again after each pruning is finished until each layer of the network has 97% of parameters.
4. The multi-means composite modulation type identification model lightweight processing method according to claim 3, wherein the similarity between a fixed point number and a floating point number is calculated in combination with a euclidean distance, a quantization scale capable of expressing the optimal performance of a network is determined, and quantized parameters are derived, specifically: selecting the Q value for multiple times, importing the parameters into the FPGA model after quantization is completed once, and saving the fixed point number of each layer for output; then, verifying the output of each layer based on the Euclidean distance, wherein the smaller the Euclidean distance is, the greater the data similarity is; the larger the euclidean distance, the smaller the data similarity,
Figure RE-FDA0003602520640000021
Where { x1,x2,...,xnDenotes the n floating-point number results output by the i-th layer of the neural network, { y }1,y2,...,ynExpressing the result of floating-point processing of n fixed-point numbers output by the ith layer of the FPGA, and finally deriving parameters capable of best expressing the network from the Pythrch.
5. The multi-means composite modulation type identification model lightweight processing method according to claim 4, characterized in that IQ data is preprocessed on an FPGA, specifically: i, Q paths of data acquired by hardware are respectively I (N) and Q (N), the sequence lengths are both N, and the mean value is obtained:
Figure RE-FDA0003602520640000022
Figure RE-FDA0003602520640000023
the standard deviation of the two sets of data were then calculated:
Figure RE-FDA0003602520640000024
Figure RE-FDA0003602520640000025
finally, based on the obtained mean and standard deviation, the normalized I, Q data sets can be calculated by the following formula:
Figure RE-FDA0003602520640000031
Figure RE-FDA0003602520640000032
in order to avoid normalization to obtain a positive number less than 1, the quantization operation is advanced and fused with the above formula to obtain the following formula:
Figure RE-FDA0003602520640000033
Figure RE-FDA0003602520640000034
6. the multi-means composite modulation type identification model lightweight processing method according to claim 5, wherein the BN layer and the convolutional layer are fused and based on a shift register, and specifically: for the convolution layer, assuming the weight of a convolution kernel is W, the convolution process is calculated by using a sliding window of W in an input feature map of the convolution kernel; assuming that one element in W is W and one element in the input feature map is x, the calculation process for W and x is as follows:
yconv＝w·x+b
For a BN layer, determining the mean variance of elements in the mini-batch, then subtracting the mean value from x to divide by the standard deviation, and finally carrying out affine transformation by utilizing gamma and beta to obtain the final BN output, wherein the specific process is as follows:
Figure RE-FDA0003602520640000035
Figure RE-FDA0003602520640000036
Figure RE-FDA0003602520640000037
Figure RE-FDA0003602520640000038
the first is an average formula, the second is a variance formula, the third is a normalization formula, and the fourth is an affine transformation formula, and the convolutional layer formula is substituted into the BN layer formula to obtain the following formula:
Figure RE-FDA0003602520640000041
wherein gamma, beta, mu, sigma2Are all parameters of the BN layer.
7. The multi-means composite modulation type recognition model lightweight processing method according to claim 6, wherein the implementation schemes of designing full parallelism and partial parallelism specifically comprise: when the Conv1 layer full parallel design is carried out, firstly, 30 shift registers are designed to respectively cache IQ two-path data, when all the registers are full, convolution multiplication operation is carried out, and then an adder of full flow water is designed to accumulate convolution multiplication results; when the Conv2_1 layer input channels are designed in a fully parallel mode, firstly, convolution kernels are spliced in groups according to the input channels and are stored permanently, then, the input parameters are repeatedly read for times equal to the number of output channels and are subjected to convolution operation with convolution kernel parameters in the same format, at the moment, results equal to the number of the input channels are obtained, each input channel corresponds to one input channel and contains the results of all the output channels, and then, the results are correspondingly added according to the input channels to obtain the final output result; and outputting the output result in a serial mode, disassembling the serial result, storing the serial result into a plurality of RAMs respectively, and waiting for the next convolution operation.
8. The multi-means composite modulation type recognition model lightweight processing method according to claim 7, wherein the maximum and minimum values of each layer of output data are analyzed by using Matlab, and the truncation standard of the data is determined, specifically: respectively truncating the decimal and the integer, truncating the decimal according to a rounding method, and keeping the bit width at 16 bits; after each layer of building is completed, the output data of the layer needs to be simulated through a Vivado Simulator. In the simulation process, firstly, the output data of the layer is written into a text document through file writing operation, then the data in the text document is analyzed by using a Matlab program, the maximum value and the minimum value of the data of the current layer are found out, and finally, the integer part is truncated according to the maximum value and the minimum value.
9. The multi-means composite modulation type identification model lightweight processing method according to claim 8, wherein the verifying the correctness of the network specifically comprises: a group of data is arbitrarily read in a data set, wherein the data set comprises 12 modulation modes, each group comprises 256 groups, each group comprises 512 x 2 data and 3072 groups of data, the data are decomposed into a coe file which can be identified by Xilinx FPGA through a python script, the file is associated to Rom, and a convolution module judges a final result based on the data.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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