CN114499816B - Clock synchronization method and device, terminal equipment and readable storage medium - Google Patents
Clock synchronization method and device, terminal equipment and readable storage medium Download PDFInfo
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- CN114499816B CN114499816B CN202111608486.3A CN202111608486A CN114499816B CN 114499816 B CN114499816 B CN 114499816B CN 202111608486 A CN202111608486 A CN 202111608486A CN 114499816 B CN114499816 B CN 114499816B
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Abstract
The present application belongs to the field of clocks, and in particular, to a method and an apparatus for clock synchronization, a terminal device, and a readable storage medium. The method comprises the following steps: when the condition that the preset condition is met is detected, entering a first master clock mode, wherein the first master clock mode is used for carrying out clock synchronization according to a preset synchronization algorithm; when a control instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a first slave clock mode, wherein the first slave clock mode is used for carrying out clock synchronization according to the control instruction of the upper computer; entering a second master clock mode when a first verification instruction sent by an upper computer in communication connection with the terminal equipment is received, wherein the second master clock mode is used for verifying the synchronization result of the first master clock mode; and when a second verification instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a second slave clock mode, wherein the second slave clock mode is used for verifying the synchronization result of the first slave clock mode, and further improving the clock synchronization precision.
Description
Technical Field
The present application belongs to the field of clocks, and in particular, to a method and an apparatus for clock synchronization, a terminal device, and a readable storage medium.
Background
With the advent of the era of big data, cloud computing and internet of things, communication systems are developing from centralized systems to distributed systems, in the centralized systems, all processes or modules acquire time from a unique global clock of the system, and any two events in the system have a definite precedence relationship.
In a distributed system, the system cannot provide a uniform global clock for modules independent of each other. Since the timing rate and the operating environment of the local clocks are inconsistent, the local clocks are also inconsistent after a period of time. In order for these local clocks to reach the same time value again, a clock synchronization operation must be performed. However, the existing clock synchronization method generally has the problem that the clock cannot be accurately synchronized.
Disclosure of Invention
The embodiment of the application provides a clock synchronization method, a clock synchronization device, a terminal device and a readable storage medium, and further improves the accuracy of clock synchronization.
In a first aspect, an embodiment of the present application provides a method for clock synchronization, where the method is applied to a terminal device including a clock module, and the method includes:
when a preset condition is detected to be met, entering a first master clock mode, wherein the first master clock mode is used for carrying out clock synchronization according to a preset synchronization algorithm, and the preset condition comprises that the terminal equipment completes a import program;
entering a first slave clock mode when receiving a control instruction sent by an upper computer in communication connection with the terminal equipment, wherein the first slave clock mode is used for carrying out clock synchronization according to the control instruction of the upper computer;
entering a second master clock mode when a first verification instruction sent by an upper computer in communication connection with the terminal equipment is received, wherein the second master clock mode is used for verifying the synchronization result of the first master clock mode;
and when a second verification instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a second slave clock mode, wherein the second slave clock mode is used for verifying the synchronization result of the first slave clock mode.
In a possible implementation manner of the first aspect, the first master clock mode is configured to perform clock synchronization according to a preset synchronization algorithm, and includes:
when the clock module is in a first master clock mode, acquiring a first second pulse signal generated by a satellite and a second pulse signal generated by the clock module;
and synchronizing the second pulse signal with the first second pulse signal to obtain the synchronized second pulse signal.
Wherein the terminal device is configured with a timer for recording the counting time between second pulse signals, and the synchronizing the second pulse signal with the first second pulse signal comprises:
at a rising edge of the second pulse-per-second signal, the timer starts counting;
determining reference time according to the acquired first second pulse signal within preset time;
after the preset time, according to the rising edge of a second pulse signal and the rising edge of a first second pulse signal, performing initial synchronization on the second pulse signal and the first second pulse signal, and determining second counting time of the second pulse signal adjacent to the initial synchronization;
and adjusting the primarily synchronized second pulse signal according to the reference time, and taking the adjusted second pulse signal as the synchronized second pulse signal.
Wherein, in the preset time, determining the reference time according to the acquired first second pulse signal comprises:
if the first second pulse signals are continuously acquired for N times within the preset time, determining the counting time of every two adjacent first second pulse signals of the counter, and determining the average second counting time corresponding to the counting time of all the two adjacent first second pulse signals of the counter;
determining the average second count time as the reference time.
Wherein, according to the reference time, adjusting the second pulse signal after the initial synchronization includes:
determining the time difference between the second counting time of the second pulse signal adjacent to the initial synchronization and the reference time;
and adjusting the second counting time of the adjacent second pulse signals after the initial synchronization according to the time difference value, so that the second counting time of the adjacent second pulse signals after the initial synchronization is synchronized with the reference time.
Adjusting the second counting time of the adjacent second pulse signals after the initial synchronization according to the time difference, comprising:
and adjusting the counting number of the timers corresponding to the adjacent second-second pulse signals after initial synchronization according to the time difference.
Adjusting the second counting time of the adjacent second pulse signals after initial synchronization according to the time difference, comprising:
if the time difference is larger than a preset threshold, determining corresponding target adjustment times and each adjustment time according to the time difference;
after the second counting time of the second pulse signal after initial synchronization is determined, when the clock module generates a new second pulse signal each time, the second counting time between the new second pulse signal and the adjacent second pulse signal is adjusted according to each adjustment time until the adjustment times reach the target adjustment times, and the second pulse signal generated after the target adjustment times is adjusted is used as the synchronized second pulse signal.
In a second aspect, an embodiment of the present application provides an apparatus for clock synchronization, where the apparatus is applied to a terminal device including a clock module, and the method includes:
the first master clock module is used for entering a first master clock mode when a preset condition is detected to be met, the first master clock mode is used for carrying out clock synchronization according to a preset synchronization algorithm, and the preset condition comprises that the terminal equipment completes a import program;
the first slave clock module is used for entering a first slave clock mode when receiving a control instruction sent by an upper computer in communication connection with the terminal equipment, and the first slave clock mode is used for carrying out clock synchronization according to the control instruction of the upper computer;
the second master clock module is used for entering a second master clock mode when receiving a first verification instruction sent by an upper computer in communication connection with the terminal equipment, and the second master clock mode is used for verifying the synchronization result of the first master clock mode;
and the second slave clock module is used for entering a second slave clock mode when receiving a second verification instruction sent by an upper computer in communication connection with the terminal equipment, and the second slave clock mode is used for verifying the synchronization result of the first slave clock mode.
In a third aspect, an embodiment of the present application provides a terminal device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the method for clock synchronization according to the first aspect is implemented.
In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program, where the computer program is executed by a processor to implement the method for clock synchronization according to the first aspect.
Compared with the prior art, the embodiment of the application has the beneficial effects that: when the method detects that preset conditions are met, a first master clock mode is entered, the first master clock mode is used for carrying out clock synchronization according to a preset synchronization algorithm, and the preset conditions comprise that the terminal equipment finishes a importing program; when a control instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a first slave clock mode, wherein the first slave clock mode is used for carrying out clock synchronization according to the control instruction of the upper computer; entering a second master clock mode when a first verification instruction sent by an upper computer in communication connection with the terminal equipment is received, wherein the second master clock mode is used for verifying the synchronization result of the first master clock mode; when a second verification instruction sent by an upper computer in communication connection with the terminal equipment is received, a second slave clock mode is entered, and the second slave clock mode is used for verifying a synchronization result of the first slave clock mode, namely, the clock synchronization is performed through the first master clock mode, the clock synchronization is performed through the first slave clock mode, the synchronization result of the first master clock mode can also be verified through the second master clock mode, the synchronization result of the second slave clock mode is verified through the second slave clock mode, and the accuracy of the clock synchronization is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic view of an application scenario of a clock synchronization method according to an embodiment of the present application;
FIG. 2 is a schematic flow chart diagram of a method for clock synchronization provided by an embodiment of the present application;
FIG. 3 is a schematic flow chart diagram of a method for clock synchronization using a first master clock mode according to an embodiment of the present application;
fig. 4 is a schematic flow chart of synchronizing the second-second pulse signal with the first-second pulse signal according to the embodiment of the present application;
fig. 5 is a schematic flow chart of a method for adjusting a second pulse signal after initial synchronization according to an embodiment of the present application;
FIG. 6 is a schematic flow chart diagram of a method for adjusting a second counting time of an adjacent second pulse signal after initial synchronization according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of an apparatus for clock synchronization according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail, and in other instances, specific technical details may be mutually referenced in various embodiments, and a specific system not described in one embodiment may be referenced in other embodiments.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.
Reference throughout this specification to "one embodiment of the present application" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in other embodiments," "in one embodiment of the present application," "in other embodiments of the present application," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
With the advent of the era of big data, cloud computing and internet of things, communication systems are developing from centralized systems to distributed systems, in the centralized systems, all processes or modules acquire time from a unique global clock of the system, and any two events in the system have a definite precedence relationship.
In a distributed system, the system cannot provide a uniform global clock for modules independent of each other. Since the timing rate and the operating environment of the local clocks are inconsistent, the local clocks are also inconsistent after a period of time. In order for these local clocks to reach the same time value again, a clock synchronization operation must be performed. However, the existing clock synchronization method generally has the problem that the clock cannot be accurately synchronized.
In order to solve the above defects, the inventive concept of the present application is:
according to the terminal equipment, clock synchronization is carried out through the first master clock mode and the first slave clock mode, and the synchronization result is verified through the second master clock mode and the second slave clock mode, so that the clock synchronization accuracy is improved.
In order to explain the technical means of the present application, the following description will be given by way of specific examples.
Referring to fig. 1, fig. 1 is a schematic view of an application scenario of a clock synchronization method according to an embodiment of the present application, and only a portion related to the present application is shown for convenience of description. The application scenario includes: host computer 100, terminal equipment 200, host computer 100 and terminal equipment 200 communication connection, this application embodiment does not limit the mode of host computer 100 and terminal equipment 200 communication connection.
The upper computer 100 is a computer that can directly issue an operation instruction. The upper computer 100 in this embodiment is configured to send a control instruction to the terminal device 200, and is configured to control the terminal device 200 to enter different clock modes, such as a first master clock mode, a first slave clock mode, a second master clock mode, or a second slave clock mode.
The terminal device 200 may be a mobile phone, a tablet computer, a wearable device, an in-vehicle device, an Augmented Reality (AR)/Virtual Reality (VR) device, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a Personal Digital Assistant (PDA), and the like, and the specific type of the terminal device 200 is not limited in this embodiment.
The terminal device 200 may also be a Station (ST) in a WLAN, and may be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA) device, a handheld device with Wireless communication capability, a computing device or other processing device connected to a Wireless modem, a vehicle-mounted device, a vehicle-mounted networking terminal, a computer, a laptop, a handheld communication device, a handheld computing device, a satellite Wireless device, a Wireless modem card, a television Set Top Box (STB), a Customer Premises Equipment (CPE), and/or other devices for communicating on a Wireless system and a next generation communication system, such as a Mobile terminal in a 5G Network or a Mobile terminal in a future-evolution Public Land Mobile Network (PLMN) Network, and the like.
In this application scenario, the terminal device 200 configures a first master clock mode, a first slave clock mode, a second master clock mode, and a second slave clock mode. The terminal device 200 performs clock synchronization using the configured first master clock mode and first slave clock mode, and verifies the clock synchronization result using the configured second master clock mode and second slave clock mode.
The terminal device 200 includes a timer 201 and a clock module 202. The timer 201 is used to record the counting time between the second pulse signals. The clock module 202 is used to generate the pulse-per-second signal.
Referring to fig. 2, fig. 2 is a schematic flowchart of a clock synchronization method according to an embodiment of the present disclosure. The main body of execution of the method in fig. 2 may be the terminal device 200 in fig. 1. As shown in fig. 2, the method includes: s201 to S204.
S201, when the condition that the preset condition is met is detected, entering a first master clock mode, wherein the first master clock mode is used for carrying out clock synchronization according to a preset synchronization algorithm, and the preset condition comprises that the terminal equipment completes a import program.
Specifically, when the terminal device detects that the import procedure is completed, the terminal device enters a first master clock mode, where the first master clock mode mainly performs clock synchronization by using a synchronization algorithm (i.e., a preset synchronization algorithm) pre-stored in an internal storage area (e.g., an internal register) of the terminal device.
In some embodiments, please refer to fig. 3 for a specific method for performing clock synchronization according to a preset synchronization algorithm in the first master clock mode, and fig. 3 is a schematic flowchart of a method for performing clock synchronization using the first master clock mode according to an embodiment of the present disclosure. The execution subject of the method in fig. 3 may be the terminal device 200 in fig. 1. As shown in fig. 3, the method includes: s301 to S302.
S301, when the satellite is in the first master clock mode, a first second pulse signal generated by the satellite and a second pulse signal generated by the clock module are acquired.
Specifically, when the terminal device is in the first master clock mode, the terminal device is initialized in order to prevent the terminal device from "crashing" or other factors from interfering with the operation of a program in the terminal device.
After the initialization operation is completed, the terminal device acquires a satellite-generated pulse-per-second signal, which is a kind of time reference signal. The embodiment of the present application refers to the acquired second pulse signal generated by the satellite as a first second pulse signal. In some embodiments, the first second pulse signal comprises a GPS second pulse signal, the GPS second pulse signal indicating a time of positive seconds, which in the present embodiment is indicated by a rising edge of the GPS second pulse signal.
And when the terminal equipment acquires the first second pulse signal generated by the satellite, acquiring a second pulse signal generated by a clock module of the terminal equipment, wherein the clock module is a system clock of the terminal equipment and is a driving source of each beat working sequence of a clock processor of the terminal equipment.
S302, synchronizing the second pulse signal with the first second pulse signal to obtain a synchronized second pulse signal.
Specifically, the first second pulse signal of the clock in the embodiment of the present application may be a GPS second pulse signal, since the GPS second pulse signal may provide a precision as high as 1 × 10 for the terminal device -9 The second reference time, the second pulse signal generated by the system clock of the terminal equipment and the GPS second pulse signal are synchronized, so that the system clock of the terminal equipment and the reference time can be precisely subjected to 'table alignment'.
In the embodiment of the present application, the terminal device is configured with a timer for recording the counting time between the pulse signals of the second, and in the embodiment of the present application, the timer is used for recording the counting time between the first pulse signal of the second and the second pulse signal of the second.
In the embodiment of the present application, please refer to fig. 4 for a specific method for synchronizing the second pulse signal and the first second pulse signal, and fig. 4 is a schematic flowchart of the method for synchronizing the second pulse signal and the first second pulse signal according to the embodiment of the present application. The execution subject of the method in fig. 4 may be the terminal device 200 in fig. 1. As shown in fig. 4, the method includes: s401 to S404.
S401, at the rising edge of the second pulse signal, the timer starts counting.
Specifically, when the terminal device acquires the second pulse signal, the timer starts to count at a rising edge of the second pulse signal, but in other embodiments, the timer may also start to count at a falling edge of the second pulse signal.
S402, determining reference time according to the acquired first second pulse signal within preset time.
Specifically, in the embodiment of the present application, the preset time may be stored in a storage area of the terminal device in advance. For example, the preset time may be 50S to 70S, for example, the preset time is 60S.
In the embodiment of the application, if N times of first second pulse signals are continuously acquired within a preset time, the counting time of every two adjacent first second pulse signal counters is determined, and the average second counting time corresponding to the counting time of all the two adjacent first second pulse signal counters is determined.
Specifically, in order to remove the signal jitter of the first second pulse signal, in the embodiment of the present invention, the first second pulse signal is acquired 60 times within 60S, and ideally, the count time of every two adjacent first second pulse signal counters in the 60 first second pulse signals is 1S, but the count time may be greater than 1S or less than 1S due to the signal jitter, so that the embodiment of the present invention must continuously acquire the first second pulse signal 60 times, and if the first second pulse signal is lost, the first second pulse signal 60 times is acquired again from the first time. After 60 times of acquiring the first-second pulse signal, the counting time of every two adjacent first-second pulse signal counters is calculated, and the average second counting time corresponding to the counting time of all the two adjacent first-second pulse signal counters is determined, and the average second pulse signal counting time may be 0.09 second, 1 second, 1.1 second, or the like, for example.
In the embodiment of the present application, the average second counting time is determined as the reference time.
Specifically, in the embodiment of the present application, 0.09 second, 1 second, or 1.1 second may be determined as the reference time, and for convenience of description, the reference time is denoted as a in the embodiment of the present application.
And S403, after the preset time, performing initial synchronization on the second pulse signal and the first second pulse signal according to the rising edge of the second pulse signal and the rising edge of the first second pulse signal, and determining second counting time of the adjacent second pulse signal after the initial synchronization.
Specifically, in the embodiment of the present invention, the terminal device may acquire a first second pulse signal generated by the satellite and a second pulse signal generated by the clock module, and start acquiring a rising edge of the second pulse signal at 61 seconds after the first second pulse signal is debounced within 60 seconds of the preset time, where the embodiment of the present invention refers to the case where the second pulse signal and the first second pulse signal are initially synchronized with each other when the rising edge of the second pulse signal at 61 seconds starts to be acquired.
In the present embodiment, after the second pulse signal and the first second pulse signal are initially synchronized, the second count time of the second pulse signal adjacent to the first second pulse signal after the initial synchronization is calculated.
And S404, adjusting the primarily synchronized second pulse signal according to the reference time, and taking the adjusted second pulse signal as the synchronized second pulse signal.
Specifically, in the embodiment of the present application, the second pulse signal after initial synchronization is adjusted according to the reference time a, and fig. 5 is a schematic flowchart of a method for adjusting the second pulse signal after initial synchronization provided in the embodiment of the present application. The execution subject of the method in fig. 5 may be the terminal device 200 in fig. 1. As shown in fig. 5, the method includes: s501 to S502.
And S501, determining the time difference between the second counting time of the adjacent second pulse signals after the initial synchronization and the reference time.
Specifically, in the embodiment of the present application, the time difference between the second counting time of the adjacent second pulse signal after the initial synchronization and the reference time is determined by calculating the difference or the absolute value between the B value and the a value.
And S502, adjusting the second counting time of the adjacent second pulse signals after the initial synchronization according to the time difference value, so that the second counting time of the adjacent second pulse signals after the initial synchronization is synchronous with the reference time.
In the embodiment of the present application, the second counting time of the adjacent second pulse signal after the initial synchronization may be adjusted by synchronizing the second counting time of the adjacent second pulse signal after the initial synchronization with the reference time a once, or may be adjusted by synchronizing the second counting time of the adjacent second pulse signal after the initial synchronization with the reference time a in multiple times.
In this embodiment, adjusting the second counting time of the second pulse signal after the initial synchronization according to the time difference includes:
and adjusting the counting number of the timers corresponding to the adjacent second-second pulse signals after the initial synchronization according to the time difference.
Specifically, in this embodiment of the present application, the counted number of the timers corresponding to the second pulse signals after the initial synchronization may be calculated according to the time difference. For example, in some embodiments, the timer 0.01 second records the pulse signal time of one second, the reference time a is 1.1 second, the second counting time B of the second pulse signal adjacent to the initial synchronization is 0.9 second, the counting number of the timer corresponding to the second pulse signal adjacent to the initial synchronization is 90, the counting number of the timer corresponding to the reference time a is 110, and the counting number of the timer corresponding to the second pulse signal adjacent to the initial synchronization needs to be adjusted to 90 until the counting number of the timer corresponding to the reference time a is 110.
In some embodiments, the method for adjusting the second counting time of the second pulse signal after the initial synchronization according to the time difference may further refer to fig. 6, where fig. 6 is a schematic flow chart of the method for adjusting the second counting time of the second pulse signal after the initial synchronization according to the embodiments of the present application. The execution subject of the method in fig. 6 may be the terminal device 200 in fig. 1. As shown in fig. 6, the method includes: s601 to S602.
S601, if the time difference is larger than a preset threshold, determining corresponding target adjustment times and each adjustment time according to the time difference.
Specifically, the preset threshold value in the embodiment of the present application is 0.1 second, and if the time difference is greater than 0.1 second, the second counting time of the adjacent second pulse signal after the initial synchronization needs to be adjusted for multiple times, so that the second counting time of the adjacent second pulse signal after the initial synchronization is synchronized with the reference time.
In some embodiments, the adjustment in multiple times may determine the corresponding target adjustment times and each adjustment time according to the size of the time difference.
Illustratively, the reference time a is 1.1 seconds, the second counting time B of the adjacent second-second pulse signal after the initial synchronization is 0.9 seconds, the calculated time difference is 0.2 seconds, 0.2 seconds is greater than the preset threshold value of 0.1 seconds, 0.2 seconds can be divided into 4 times, and each time is adjusted by 0.05S, so that the second counting time of the adjacent second-second pulse signal after the initial synchronization is synchronized with the reference time, in the embodiment of the present application, 0.2 seconds is referred to as each adjustment time, and 4 times are referred to as target adjustment times.
S602, after the second counting time of the second pulse signal after initial synchronization is determined, when a clock module generates a new second pulse signal each time, adjusting the second counting time between the new second pulse signal and the adjacent second pulse signal according to each adjustment time until the adjustment frequency reaches the target adjustment frequency, and taking the second pulse signal generated after the target adjustment frequency is adjusted as the synchronized second pulse signal.
Specifically, in some embodiments, after determining the second counting time of 0.9 seconds of the second-second pulse signal after the initial synchronization, each time the clock module generates a new second-second pulse signal, and adjusting the second counting time between a new second pulse signal and an adjacent second pulse signal according to the adjustment time of 0.2 second each time until the adjustment frequency reaches the target adjustment frequency of 4 times, and taking the second pulse signal generated after the target adjustment frequency is adjusted as the second pulse signal which is completed synchronously.
S202, when a control instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a first slave clock mode, wherein the first slave clock mode is used for carrying out clock synchronization according to the control instruction of the upper computer.
In this embodiment, a method for performing clock synchronization in the first slave clock mode according to the control instruction of the upper computer is the same as a method for performing clock synchronization in the first master clock mode according to the preset synchronization algorithm, and is not described herein again.
S203, when a first verification instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a second master clock mode, wherein the second master clock mode is used for verifying the synchronization result of the first master clock mode.
In the embodiment of the present application, when verifying the synchronization result of the first master clock mode, the second master clock mode verifies by calculating the difference between the time corresponding to the rising edge of the second pulse signal and the time corresponding to the rising edge of the first second pulse signal, and if the difference between the time corresponding to the rising edge of the second pulse signal and the time corresponding to the rising edge of the first second pulse signal is 1 second, it is verified that the synchronization is completed.
S204, when a second verification instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a second slave clock mode, wherein the second slave clock mode is used for verifying the synchronization result of the first slave clock mode.
In the embodiment of the present application, the method for verifying the synchronization result of the first slave clock mode in the second slave clock mode is the same as the method for verifying the synchronization result of the first master clock mode in the second master clock mode, and details are not repeated here.
To sum up, the clock synchronization method provided in the embodiment of the present application enters a first master clock mode when it is detected that a preset condition is met, where the first master clock mode is used for performing clock synchronization according to a preset synchronization algorithm, and the preset condition includes that a terminal device completes a boot program; when a control instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a first slave clock mode, wherein the first slave clock mode is used for carrying out clock synchronization according to the control instruction of the upper computer; entering a second master clock mode when a first verification instruction sent by an upper computer in communication connection with the terminal equipment is received, wherein the second master clock mode is used for verifying the synchronization result of the first master clock mode; when a second verification instruction sent by an upper computer in communication connection with the terminal equipment is received, a second slave clock mode is entered, and the second slave clock mode is used for verifying a synchronization result of the first slave clock mode, namely, the clock synchronization is performed through the first master clock mode, the clock synchronization is performed through the first slave clock mode, the synchronization result of the first master clock mode can be verified through the second master clock mode, the synchronization result of the second slave clock mode is verified through the second slave clock mode, the accuracy of the clock synchronization is improved, and the terminal equipment can switch different clock modes to ensure the stability and reliability of the whole terminal equipment.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
Referring to fig. 7, fig. 7 is a schematic structural diagram of an apparatus for clock synchronization according to an embodiment of the present application, where the apparatus is applied to the terminal device in fig. 1, and the apparatus includes:
the first master clock mode 71 is configured to enter a first master clock mode when it is detected that a preset condition is met, where the first master clock mode is configured to perform clock synchronization according to a preset synchronization algorithm, and the preset condition includes that the terminal device completes a boot program.
And the first slave clock mode 72 is used for entering a first slave clock mode when receiving a control instruction sent by an upper computer in communication connection with the terminal equipment, and the first slave clock mode is used for carrying out clock synchronization according to the control instruction of the upper computer.
And the second master clock mode 73 is configured to enter the second master clock mode when receiving a first verification instruction sent by an upper computer in communication connection with the terminal device, where the second master clock mode is used to verify a synchronization result of the first master clock mode.
And the second slave clock mode 74 is used for entering the second slave clock mode when receiving a second verification instruction sent by an upper computer in communication connection with the terminal device, wherein the second slave clock mode is used for verifying the synchronization result of the first slave clock mode.
The first master clock mode 71 is further configured to, when the first master clock mode is in the first master clock mode, acquire a first second pulse signal generated by a satellite and a second pulse signal generated by the clock module;
and synchronizing the second pulse signal with the first second pulse signal to obtain the synchronized second pulse signal.
Wherein the terminal device is configured with a timer for recording the counting time between the pulse signals of the second, the first master clock mode 71 is further configured for starting counting by the timer at the rising edge of the second pulse signal;
determining reference time according to the acquired first second pulse signal within preset time;
after the preset time, according to the rising edge of a second pulse signal and the rising edge of a first second pulse signal, carrying out primary synchronization on the second pulse signal and the first second pulse signal, and determining second counting time of the adjacent second pulse signal after the primary synchronization;
and adjusting the primarily synchronized second pulse signal according to the reference time, and taking the adjusted second pulse signal as the synchronized second pulse signal.
The first master clock mode 71 is further configured to determine the counting time of each two adjacent first second pulse signals in the counter if the N times of first second pulse signals are continuously acquired within a preset time, and determine an average second counting time corresponding to the counting time of all the two adjacent first second pulse signals in the counter;
determining the average second count time as the reference time.
A first master clock mode 71, further configured to determine a time difference between a second counting time of the second pulse signal after initial synchronization and the reference time;
and adjusting the second counting time of the adjacent second pulse signals after the initial synchronization according to the time difference value, so that the second counting time of the adjacent second pulse signals after the initial synchronization is synchronized with the reference time.
In some embodiments, the first master clock mode 71 is further configured to adjust, according to the time difference, the count number of the timers corresponding to the adjacent second-second pulse signals after the initial synchronization.
The first master clock mode 71 is further configured to determine, if the time difference is greater than a preset threshold, a corresponding target adjustment number of times and each adjustment time according to the size of the time difference;
after the second counting time of the second pulse signal after initial synchronization is determined, when a new second pulse signal is generated by the clock module each time, the second counting time between the new second pulse signal and the adjacent second pulse signal is adjusted according to each adjusting time until the adjusting frequency reaches the target adjusting frequency, and the second pulse signal generated after the target adjusting frequency is adjusted is used as the synchronized second pulse signal.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules, so as to perform all or part of the functions described above. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
As shown in fig. 8, the present embodiment further provides a terminal device 200, which includes a memory 21, a processor 22, and a computer program 23 stored in the memory 21 and operable on the processor 22, where the processor 22 implements the clock synchronization method of the foregoing embodiments when executing the computer program 23.
The Processor 22 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 21 may be an internal storage unit of the terminal device 200. The memory 21 may also be an external storage device of the terminal device 200, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) and the like provided on the terminal device 200. Further, the memory 21 may also include both an internal storage unit of the terminal device 200 and an external storage device. The memory 21 is used to store computer programs and other programs and data required by the terminal device 200. The memory 21 may also be used to temporarily store data that has been output or is to be output.
The embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method for clock synchronization in the foregoing embodiments is implemented.
The embodiment of the present application provides a computer program product, which when running on a mobile terminal, enables the mobile terminal to implement the clock synchronization method of the above embodiments when executed.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above can be implemented by instructing relevant hardware by a computer program, which can be stored in a computer readable storage medium, and when the computer program is executed by a processor, the steps of the embodiments of the methods described above can be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable storage medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/terminal apparatus, a recording medium, computer memory, read-only memory (ROM), random Access Memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable storage media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and proprietary practices.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (9)
1. A method for clock synchronization, the method is applied to a terminal device comprising a clock module, and the method comprises the following steps:
when the preset condition is met, entering a first master clock mode, and acquiring a first second pulse signal generated by a satellite and a second pulse signal generated by a clock module when the first master clock mode is detected;
synchronizing the second pulse signal with the first pulse signal to obtain the synchronized second pulse signal, wherein the preset condition comprises that the terminal equipment completes a import program;
when a control instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a first slave clock mode, wherein the first slave clock mode is used for carrying out clock synchronization according to the control instruction of the upper computer;
entering a second master clock mode when a first verification instruction sent by an upper computer in communication connection with the terminal equipment is received, wherein the second master clock mode is used for verifying the synchronization result of the first master clock mode;
and when a second verification instruction sent by an upper computer in communication connection with the terminal equipment is received, entering a second slave clock mode, wherein the second slave clock mode is used for verifying the synchronization result of the first slave clock mode.
2. The method according to claim 1, wherein the terminal device configures a timer for recording a count time between the pulse signals for second seconds, and the synchronizing the pulse signals for second seconds with the pulse signals for first seconds comprises:
at a rising edge of the second pulse-per-second signal, the timer starts counting;
determining reference time according to the acquired first second pulse signal within preset time;
after the preset time, according to the rising edge of a second pulse signal and the rising edge of a first second pulse signal, performing initial synchronization on the second pulse signal and the first second pulse signal, and determining second counting time of the second pulse signal adjacent to the initial synchronization;
and adjusting the primarily synchronized second pulse signal according to the reference time, and taking the adjusted second pulse signal as the synchronized second pulse signal.
3. The method according to claim 2, wherein the determining a reference time according to the acquired first second pulse signal within a preset time comprises:
if the first second pulse signals are continuously acquired for N times within the preset time, determining the counting time of every two adjacent first second pulse signals of the counter, and determining the average second counting time corresponding to the counting time of all the two adjacent first second pulse signals of the counter;
determining the average second count time as the reference time.
4. The method according to claim 2 or 3, wherein the adjusting the second pulse signal after the initial synchronization according to the reference time comprises:
determining the time difference between the second counting time of the second pulse signal adjacent to the initial synchronization and the reference time;
and adjusting the second counting time of the adjacent second pulse signals after the initial synchronization according to the time difference value, so that the second counting time of the adjacent second pulse signals after the initial synchronization is synchronized with the reference time.
5. The method of claim 4, wherein adjusting the second counting time of the adjacent second pulse signals after the initial synchronization according to the time difference comprises:
and adjusting the counting number of the timers corresponding to the adjacent second-second pulse signals after initial synchronization according to the time difference.
6. The method of claim 4, wherein adjusting the second counting time of the adjacent second pulse signal after the initial synchronization according to the time difference comprises:
if the time difference is larger than a preset threshold, determining corresponding target adjustment times and each adjustment time according to the size of the time difference;
after the second counting time of the second pulse signal after initial synchronization is determined, when the clock module generates a new second pulse signal each time, the second counting time between the new second pulse signal and the adjacent second pulse signal is adjusted according to each adjustment time until the adjustment times reach the target adjustment times, and the second pulse signal generated after the target adjustment times is adjusted is used as the synchronized second pulse signal.
7. An apparatus for clock synchronization, the apparatus being applied to a terminal device including a clock module, the apparatus comprising:
a first master clock module for entering a first master clock mode upon detecting that a preset condition is satisfied,
when the clock module is in a first master clock mode, acquiring a first second pulse signal generated by a satellite and a second pulse signal generated by the clock module;
synchronizing the second pulse signal with the first pulse signal to obtain the synchronized second pulse signal, wherein the preset condition comprises that the terminal equipment finishes a importing program;
the first slave clock module is used for entering a first slave clock mode when receiving a control instruction sent by an upper computer in communication connection with the terminal equipment, and the first slave clock mode is used for carrying out clock synchronization according to the control instruction of the upper computer;
the second master clock module is used for entering a second master clock mode when receiving a first verification instruction sent by an upper computer in communication connection with the terminal equipment, and the second master clock mode is used for verifying the synchronization result of the first master clock mode;
and the second slave clock module is used for entering a second slave clock mode when receiving a second verification instruction sent by an upper computer in communication connection with the terminal equipment, and the second slave clock mode is used for verifying the synchronization result of the first slave clock mode.
8. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the method of clock synchronization according to any one of claims 1 to 6 when executing the computer program.
9. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method of clock synchronization according to any one of claims 1 to 6.
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