CN114244347B

CN114244347B - CMT suppression circuit for four-port isolator and four-port isolator

Info

Publication number: CN114244347B
Application number: CN202111485155.5A
Authority: CN
Inventors: 张峰; 王文静; 孙建民; 马春宇
Original assignee: Gl Microelectronics Inc
Current assignee: Gl Microelectronics Inc
Priority date: 2021-12-07
Filing date: 2021-12-07
Publication date: 2022-11-08
Anticipated expiration: 2041-12-07
Also published as: CN114244347A

Abstract

The invention relates to a CMT suppression circuit for a four-port isolator and the four-port isolator, wherein the CMT suppression circuit comprises: the circuit comprises an overvoltage protection circuit, a one-way conduction circuit, a switch circuit, a CMT detection circuit and a current release circuit; the CMT detection circuit is used for receiving and switching on or switching off the switch circuit or the current bleeder circuit according to the change of an output signal output by the second output end of the unidirectional conduction circuit; the current leakage circuit is used for performing current leakage on the output signal of the switch circuit so as to control the amplitude of the output signal of the switch circuit to be stable; the switch circuit is used for receiving and sending an output signal output by the first output end of the unidirectional conducting circuit to the output circuit of the four-port isolator according to the output signal of the CMT detection circuit. The CMT suppression circuit provided by the invention has a simple structure, can effectively suppress CMT events, and can significantly improve the CMTI performance and the working reliability of the four-port isolator when being applied to the four-port isolator.

Description

CMT suppression circuit for four-port isolator and four-port isolator

Technical Field

The invention relates to a common mode transient suppression circuit, in particular to a CMT suppression circuit for a four-port isolator and the four-port isolator.

Background

In electronic devices such as military electronic systems, aerospace devices, and medical devices, in order to eliminate signal noise and protect devices and users from high voltage, isolators are generally added to the electronic devices.

Currently, an optical coupler is always the main choice of an isolator, but the optical coupler has the defects of easy aging, high power consumption, short service life and the like, and the use scenes of the optical coupler are limited. To be compatible with the ports of the optocoupler and to circumvent the disadvantages of optocouplers, the patent application No. 201610878177.0 proposes a four port digital isolator fabricated using integrated circuit technology to replace the optocoupler at system level 1. However, the four-port isolator only supports external positive-level signal input, and then the linear isolator and the pin-compatible four-port optical coupler proposed by the patent with the application number of 201910330563.X can be used for isolating and transmitting analog signals or digital signals and simultaneously transmitting positive-level signals or negative-level signals. However, the receiving terminal of the four-port isolator proposed in the above patent is sensitive to common mode noise, and has poor performance of common mode transient suppression and low operational reliability.

Disclosure of Invention

In order to solve the technical problem, the invention provides a CMT suppression circuit for a four-port isolator and the four-port isolator.

The technical scheme of the CMT suppression circuit for the four-port isolator is as follows:

the method comprises the following steps: the circuit comprises an overvoltage protection circuit (110), a unidirectional conduction circuit (120), a switch circuit (130), a CMT detection circuit (140) and a current leakage circuit (150); the input end of the overvoltage protection circuit (110) is connected with a rectifying and filtering circuit (25) of the four-port isolator, the output end of the overvoltage protection circuit (110) is connected with the input end of the unidirectional conduction circuit (120), and the unidirectional conduction circuit (120) comprises two output ends which are respectively connected with the first input end of the switch circuit (130) and the input end of the CMT detection circuit (140);

the CMT detection circuit (140) is configured to: receiving and turning on or off the switch circuit (130) or the current bleeding circuit (150) according to the change of the output signal output by the second output end of the unidirectional conducting circuit (120);

the current bleeding circuit (150) is configured to: performing current bleeding on the output signal of the switch circuit (130) to control the amplitude of the output signal of the switch circuit (130) to be stable;

the switching circuit (130) is configured to: and receiving and sending an output signal output by a first output end of the unidirectional conduction circuit (120) to an output circuit (27) of the four-port isolator according to an output signal of the CMT detection circuit (140).

The CMT suppression circuit for the four-port isolator has the following beneficial effects:

the CMT suppression circuit for the four-port isolator provided by the invention has a simple structure, can effectively suppress CMT events, and can significantly improve the CMTI performance and the working reliability of the four-port isolator when being applied to the four-port isolator.

On the basis of the scheme, the CMT suppression circuit for the four-port isolator can be further improved as follows.

Further, the CMT detection circuit (140) specifically includes: the CMOS image sensor comprises a signal input end, a first PMOS tube (1), a second PMOS tube (8), a third PMOS tube (10), a first NMOS tube (7), a second NMOS tube (9), a third NMOS tube (11), a first resistor (2), a second resistor (3), a third resistor (4), a fourth resistor (6), a capacitor (5) and a signal output end, wherein the signal input end of a CMT detection circuit (140) is respectively connected with the source electrode of the first PMOS tube (1), the source electrode of the second PMOS tube (8), the source electrode of the third PMOS tube (10) and the fourth resistor (6), the grid electrode of the first PMOS tube (1) is connected with the first resistor (2), the drain electrode of the first PMOS tube (1) is respectively connected with the second resistor (3) and the third resistor (4), the other end of the third resistor (4) is respectively connected with the capacitor (5) and the grid electrode of the first NMOS tube (7), the drain electrode of the first NMOS tube (7) is connected with the fourth resistor (6), the grid electrode of the second PMOS tube (8) and the grid electrode of the second NMOS tube (9), the drain electrode of the second PMOS tube (8), the drain electrode of the second NMOS tube (9), the grid electrode of the third PMOS tube (10) and the grid electrode of the third NMOS tube (11), and the drain electrode of the third PMOS tube (10) and the drain electrode of the third NMOS tube (11) are connected with the CMT detection circuit The signal output terminals of the paths (140) are connected.

The beneficial effect of adopting the further scheme is that: monitoring the change of an input signal through a CMT detection circuit to control the states of a switch circuit and a current leakage circuit; when the change of the input signal reaches a preset threshold value, the CMT detection circuit outputs a control signal, the current release circuit is placed in a conducting state, and the switch circuit is placed in a switching-off state; when the amplitude change of the input signal does not reach the preset threshold value, the switch circuit is in a conducting state, and the current leakage circuit is in a switching-off state.

Further, the current bleeding circuit (150) specifically includes: the grid electrode of the fourth NMOS tube is connected with the signal output end of the CMT detection circuit (140), the drain electrode of the fourth NMOS tube is connected with the output end of the switch circuit (130), and the source electrode of the fourth NMOS tube is grounded.

The beneficial effect of adopting the above further scheme is: the amplitude of the output signal is controlled by the current bleeding circuit.

The technical scheme of the four-port isolator is as follows:

the four-port isolator comprises a four-port isolator body and the CMT suppression circuit for the four-port isolator, wherein the input end of the overvoltage protection circuit (110) of the CMT suppression circuit (26) is connected with the output end of the rectifying and filtering circuit (25) of the four-port isolator body, and the output end of the switching circuit (130) of the CMT suppression circuit (26) is connected with the output circuit (27) of the four-port isolator body.

The four-port isolator has the following beneficial effects:

according to the invention, the CMT suppression circuit is arranged in the four-port isolator body, so that a CMT event can be effectively suppressed, and the performance and the working reliability of the four-port isolator are obviously improved.

Further, still include: the device comprises a sending circuit (22) and a coupling transmission circuit (23) which are connected in sequence, wherein the sending circuit (22) is provided with a first signal input end (20) and a first grounding end (21);

the coupling transmission circuit (23) is used for: -coupling the output signal of the transmission circuit (22) to a rectifying and filtering circuit (25);

the transmission circuit (22) is configured to: and converting and coding the original input signal received by the first signal input end (20) to obtain a coded signal, and sending the coded signal to the rectifying and filtering circuit (25) through the coupling transmission circuit (23).

Further, still include: the rectification filter circuit (25), the CMT suppression circuit (26) and the output circuit (27) form a receiving circuit (24), and the receiving circuit (24) is provided with a first signal output end (28) and a second grounding end (29);

the receiving circuit (24) is configured to: and decoding the received coding signal through the rectifying and filtering circuit (25) to obtain a decoding signal, transmitting the decoding signal to the CMT suppression circuit (26) for processing to obtain a driving signal, and driving the output circuit (27) according to the driving signal so that the output circuit (27) outputs a final output signal through the first signal output end (28).

Further, the four-port isolator may transmit digital signals or analog signals, which may be positive level signals or negative level signals.

The technical scheme of the packaging tube shell is as follows:

the method comprises the following steps: a first chip (100) and a second chip (200), wherein:

the first chip (100) is formed by packaging the transmitting circuit (22) and the coupling transmission circuit (23) in the four-port isolator embodiment;

the second chip (200) is packaged by the receiving circuit (24) in the four-port isolator embodiment described above.

The technical scheme of the electronic equipment is as follows:

including the four-port isolator described in the above technical solutions.

Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a block diagram of a CMT suppression circuit for a four-port isolator according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an overvoltage protection circuit in a CMT suppression circuit for a four-port isolator according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a unidirectional conducting circuit in a CMT suppression circuit for a four-port isolator according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a CMT detection circuit in a CMT suppression circuit for a four-port isolator according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the circuit configuration of another embodiment of a CMT suppression circuit for a four port isolator;

FIG. 6 is a schematic diagram of a four-port isolator according to an embodiment of the present invention;

FIG. 7 is a schematic diagram showing waveforms of signals at a key node in the absence of a CMT event in a four-port isolator according to an embodiment of the present invention;

FIG. 8 is a schematic diagram showing waveforms of signals at a key node when a CMT event occurs in a four-port isolator according to an embodiment of the present invention;

FIG. 9 is a waveform diagram of signals at each node without CMTI suppression circuit in four-port isolation according to an embodiment of the present invention;

fig. 10 is a schematic diagram of a chip package structure of a package in an embodiment of the invention.

Detailed Description

As shown in fig. 1, a CMT suppression circuit for a four-port isolator according to an embodiment of the present invention includes: the circuit comprises an overvoltage protection circuit (110), a unidirectional conduction circuit (120), a switch circuit (130), a CMT detection circuit (140) and a current leakage circuit (150); the input end of the overvoltage protection circuit (110) is connected with a rectifying and filtering circuit (25) of the four-port isolator, the output end of the overvoltage protection circuit (110) is connected with the input end of the unidirectional conduction circuit (120), and the unidirectional conduction circuit (120) comprises two output ends which are respectively connected with the first input end of the switch circuit (130) and the input end of the CMT detection circuit (140);

the current bleeding circuit (150) is configured to: performing current leakage on the output signal of the switching circuit (130) to control the amplitude of the output signal of the switching circuit (130) to be stable;

the switching circuit (130) is configured to: and receiving and sending an output signal output by the first output end of the unidirectional conduction circuit to an output circuit (27) of the four-port isolator according to an output signal of the CMT detection circuit (140).

Specifically, in the CMT suppression circuit (26), the input end of an overvoltage protection circuit (110) is used for connecting the output end of a rectification filter circuit (25) of a four-port isolator; the output end of the overvoltage protection circuit (110) is connected with the input end of the unidirectional conducting circuit (120), and the unidirectional conducting circuit (120) comprises two output ends which are respectively connected with the first input end of the switch circuit (130) and the input end of the CMT detection circuit (140); the output end of the CMT detection circuit (140) is respectively connected with the first input end of the current leakage circuit (150) and the second input end of the switch circuit (130); the output end of the switch circuit (130) is connected with the second input end of the current leakage circuit (150).

Wherein the overvoltage protection circuit (110) is configured to: receiving a first original input signal sent by an output end of the rectifying and filtering circuit (25), performing clamping processing on the first original input signal exceeding a preset second threshold voltage to obtain a first input signal, and sending the first input signal to the unidirectional conducting circuit (120); the unidirectional conduction circuit (120) is configured to: transmitting the first input signal to the switch circuit (130) and the CMT detection circuit (140) when a positive terminal voltage of the unidirectional conducting circuit (120) is higher than a negative terminal voltage; otherwise, the unidirectional conducting circuit (120) is turned off.

Specifically, as shown in fig. 2, the over-voltage protection circuit (110) may be implemented by a zener diode, wherein the anode of the zener diode is connected to the reference ground and the cathode of the diode is connected to the input signal. When the amplitude of an input signal is higher than a preset high threshold value of the overvoltage protection circuit due to CMT interference, a Zener diode in the overvoltage protection circuit (110) is broken down, the amplitude of the input signal is clamped at the breakdown voltage value of the diode, and the clamped signal has no common-mode interference, so that the damage that other devices in the circuit are broken down due to overhigh potential of the input signal is avoided; when the amplitude of an input signal is lower than a preset low threshold value of the overvoltage protection circuit (110) due to CMT interference, the input signal is usually a Zener diode conduction voltage drop, at the moment, the Zener diode is conducted in the forward direction, the voltage at two ends of the diode is clamped on the conduction voltage drop of the diode, and the clamped signal has no common-mode interference, so that the damage that other devices in the circuit are broken down due to overhigh potential of a grounding end is avoided.

As shown in fig. 3, the unidirectional circuit (120) may be implemented by two diodes, the anodes of the diodes are both connected to the input signal, the cathode of one diode, i.e. the first output terminal, is connected to the first input terminal of the switch circuit (130), and the cathode of the other diode, i.e. the second output terminal, is connected to the CMT detection circuit (140).

Preferably, the CMT detection circuit (140) comprises in particular: the CMOS image sensor comprises a signal input end, a first PMOS (P-channel metal oxide semiconductor) tube (1), a second PMOS tube (8), a third PMOS tube (10), a first NMOS tube (7), a second NMOS tube (9), a third NMOS tube (11), a first resistor (2), a second resistor (3), a third resistor (4), a fourth resistor (6), a capacitor (5) and a signal output end, wherein the signal input end of a CMT (constant current transistor) detection circuit (140) is respectively connected with a source electrode of the first PMOS tube (1), a source electrode of the second PMOS tube (8), a source electrode of the third PMOS tube (10) and the fourth resistor (6), a grid electrode of the first PMOS tube (1) is connected with the first resistor (2), the drain electrode of the first PMOS tube (1) is connected with the second resistor (3) and the third resistor (4) respectively, the other end of the third resistor (4) is connected with the capacitor (5) and the grid electrode of the first NMOS tube (7) respectively, the drain electrode of the first NMOS tube (7) is connected with the fourth resistor (6), the grid electrode of the second PMOS tube (8) and the grid electrode of the second NMOS tube (9), the drain electrode of the second PMOS tube (8), the drain electrode of the second NMOS tube (9), the grid electrode of the third PMOS tube (10) and the grid electrode of the third NMOS tube (11) are connected, and the drain electrode of the third PMOS tube (10) and the drain electrode of the third NMOS tube (11) are connected with the CMT detection circuit The signal output terminals of the paths (140) are connected.

When CMT interference exists, the first PMOS tube (1) is conducted, so that current passing through the first PMOS tube (1) charges the capacitor (5) through the third resistor (4), the grid voltage of the first NMOS tube (7) does not reach the threshold voltage of the NMOS tube, and the current bleeder circuit (150) is controlled to be in a conducting state and the switch circuit (130) is controlled to be in a switching-off state; when no CMT interference exists or the capacitor (5) is charged completely, and the gate voltage of the first NMOS tube (7) reaches the corresponding threshold voltage, the first NMOS tube (7) is conducted, the switch circuit (130) is controlled to be placed in a conducting state, and the current bleeder circuit (150) is placed in a cut-off state.

Specifically, as shown in fig. 4, when the CMT is interfered, the source voltage of the first PMOS transistor (1) rises, when the source voltage of the first PMOS transistor (1) reaches the threshold voltage of the PMOS transistor, the first PMOS transistor (1) is turned on, the drain voltage of the first PMOS transistor (1) is consistent with the source voltage of the first PMOS transistor (1), the current flowing through the first PMOS transistor (1) charges the capacitor (5) through the third resistor (4), due to the presence of the third resistor (4) and the capacitor (5), the gate voltage of the first NMOS transistor (7) does not change along with the drain voltage of the first PMOS transistor (1), the drain voltage of the first NMOS transistor (7) and the source voltage of the first PMOS transistor (1) are both higher than the threshold voltage of the PMOS transistor, the signal output end voltage of the CMT detection circuit (140) after passing through the two-stage inverter is also both higher than the threshold voltage of the PMOS transistor, at this time, the switch circuit (130) is placed in an off state, and the current relief circuit (150) is placed in an on state to relieve the CMT current; when the capacitor (5) is charged, the grid voltage of the first NMOS tube (7) is increased to the threshold voltage of the NMOS tube, the first NMOS tube (7) is conducted, the drain voltage of the first NMOS tube (7) is set to be low, the drain voltage is also set to be low after passing through the two-stage phase inverter, the switch circuit (130) is set to be in a conducting state at the moment, and the current bleeder circuit (150) is set to be in a stopping state.

Preferably, the current bleeding circuit (150) specifically includes: the grid electrode of the fourth NMOS tube is connected with the signal output end of the CMT detection circuit (140), the drain electrode of the fourth NMOS tube is connected with the output end of the switch circuit (130), and the source electrode of the fourth NMOS tube is grounded.

Wherein the current bleeding circuit (150) is specifically configured to: receiving an output signal output by a signal output end of the CMT detection circuit (140) through a grid electrode of the fourth NMOS tube, wherein no current passes through the current bleeder circuit (150) when the output voltage of the CMT detection circuit (140) is smaller than the preset threshold value; otherwise, when the current bleeder circuit (150) is controlled to be in a conducting state, the CMT current flowing through the switch circuit (130) is bled through the source electrode of the fourth NMOS tube.

Specifically, the current leakage circuit (150) controls the amplitude of an output signal of the CMT suppression circuit (26), and the CMT suppression circuit has two states of conduction and cut-off, when the circuit is in the cut-off state, a branch where the circuit is located is in a high-impedance state, and no current flows through the circuit; when the circuit is in a conducting state, the branch where the circuit is located is in a low-resistance state, and a current path is provided for current leakage; the current bleeder circuit (150) can be realized by a fourth NMOS tube, the grid electrode of the fourth NMOS tube is connected with the output end of the CMT detection circuit (140), the drain electrode of the fourth NMOS tube is connected with the output end of the switch circuit (130), and the source electrode of the fourth NMOS tube is grounded.

Another embodiment of the CMT suppression circuit for a four-port isolator of the present invention includes:

aiming at CMT interference, the circuit is divided into four cases to be respectively processed.

The first condition is that the input signal is high, the CMT interference further increases the amplitude of the signal to enable the amplitude to reach a high threshold value of the overvoltage protection circuit (110), at the moment, the overvoltage protection circuit (110) starts to work to clamp the amplitude of the input signal at a safe voltage value, the clamped signal eliminates common mode interference, the signal is output after passing through the one-way conduction circuit (120) and the switch circuit (130), at the moment, the one-way conduction circuit (120) is conducted, the CMT detection circuit (140) works, the output control signal enables the switch circuit (130) to be in an on state, the current relief circuit (150) to be in an off state, and no current flows through the current relief circuit (150);

the second condition is that the input signal is low, the CMT interference increases the amplitude of the signal but does not reach the high threshold value of the overvoltage protection circuit 1, at the moment, the overvoltage protection circuit (110) does not work, the unidirectional conduction circuit (120) is conducted, the CMT detection circuit (140) works, the output control signal puts the switch circuit (130) in the off state, the CMT transmission path is blocked, and simultaneously the current relief circuit (150) is put in the on state, the current generated by the CMT event is relieved, and the stability of the output signal is ensured;

the third situation is that the input signal is high, the CMT interference enables the amplitude of the signal to be reduced but does not reach the low threshold value of the overvoltage protection circuit (110), at the moment, the overvoltage protection circuit (110) does not work, the unidirectional conduction circuit (120) is cut off, a common mode interference channel is blocked, the CMT detection circuit (140) works, the output control signal enables the switch circuit (130) to be in an on state, the current relief circuit (150) to be in an off state, no current flows through the current relief circuit (150), and the amplitude of the output signal is guaranteed to be stable;

and in the fourth situation, the input signal is low, the CMT event further reduces the amplitude of the signal to enable the amplitude to reach the low threshold value of the overvoltage protection circuit (110), at the moment, the overvoltage protection circuit (110) starts to work, the amplitude of the input signal is clamped at a safe voltage value, the clamped signal eliminates common-mode interference, the signal is output after passing through the one-way conduction circuit (120) and the switch circuit (130), at the moment, the one-way conduction circuit (120) is conducted, the CMT detection circuit (140) works, the output control signal enables the switch circuit (130) to be in an on state, the current relief circuit (150) to be in an off state, and no current flows through the current relief circuit (150).

Specifically, as shown in fig. 5, the method includes: the transistor comprises a first diode (51), a second diode (52), a third diode (69), a fifth resistor (53), a sixth resistor (55), a seventh resistor (56), an eighth resistor (57), a ninth resistor (60), a tenth resistor (68), a first capacitor (58), a fifth PMOS (P-channel metal oxide semiconductor) tube (54), a sixth PMOS tube (59), a seventh PMOS tube (62), an eighth PMOS tube (64), a ninth PMOS tube (66), a fifth NMOS tube (61), a sixth NMOS tube (63), a seventh NMOS tube (65) and an eighth NMOS tube (67).

The third diode (69) can be a Zener diode, the cathode of the third diode (69) is connected with the input end, and the anode of the third diode is connected with the reference ground. The anode of the first diode (51) and the anode of the second diode (52) are connected to the input terminal. The cathode of the first diode (51) is connected with one end of a fifth resistor (53), the source of a fifth PMOS tube (54), one end of a ninth resistor (60), the source of a seventh PMOS tube (62), the source of an eighth PMOS tube (64) and the grid of a ninth PMOS tube (66). The cathode of the second diode (52) is connected with the source electrode of the sixth PMOS tube (59). The grid electrode of the sixth PMOS tube (59) is connected with the drain electrode of the eighth PMOS tube (64), the drain electrode of the seventh NMOS tube (65) and the grid electrode of the eighth NMOS tube (67). The drain electrode of the sixth PMOS tube (59), the source electrode of the ninth PMOS tube (66), the drain electrode of the eighth NMOS tube (67) and one end of the tenth resistor (68) are connected with the output end. The grid electrode of the fifth PMOS tube (54) is connected with one end of a sixth resistor (55), and the drain electrode of the fifth PMOS tube (54) is connected with one ends of a seventh resistor (56) and an eighth resistor (57). The other end of the eighth resistor (57) is connected with one end of the first capacitor (58) and the grid electrode of the fifth NMOS tube (61). The drain electrode of the fifth NMOS tube (61) is connected with the other end of the ninth resistor (60), the grid electrode of the seventh PMOS tube (62) and the grid electrode of the sixth NMOS tube (63). The drain electrode of the seventh PMOS tube (62) is connected with the drain electrode of the sixth NMOS tube (63), the grid electrode of the eighth PMOS tube (64) and the grid electrode of the seventh NMOS tube (65). The other end of the fifth resistor (53), the other end of the sixth resistor (55), the other end of the seventh resistor (56), the other end of the first capacitor (58), the source electrode of the fifth NMOS tube (61), the source electrode of the sixth NMOS tube (63), the source electrode of the seventh NMOS tube (65), the drain electrode of the ninth PMOS tube (66) and the source electrode of the eighth NMOS tube (67), and the other end of the tenth resistor (68) is connected with the reference ground. V1 is the input signal of the CMT suppression circuit (26), V4 is the output signal of the CMT suppression circuit (26), and V4 can be used to drive the output circuit. The signal amplitude of V4 is slightly lower than the signal amplitude of V1 when no CMT event occurs.

When a CMT event occurs, when the ground potential of the transmitting circuit is higher than the ground potential of the receiving circuit, the signal amplitude of V1 is increased rapidly due to common mode interference, when the signal amplitude of V1 reaches the breakdown voltage of the third diode (69), the third diode (69) is broken down, and the signal amplitude of V1 is clamped at the breakdown voltage value of the third diode (69).

When the signal amplitude of V1 does not reach the breakdown voltage of the third diode (69), the signal amplitude of V2 is rapidly increased along with V1, V3 is rapidly increased along with the change of V2, at the moment, the sixth PMOS tube (59) is turned off, the eighth NMOS tube (67) is opened to rapidly discharge the CMT current, the stability of the V4 signal is ensured, and the output circuit is protected from breakdown. When the RC circuit formed by the eighth resistor (57) and the first capacitor (58) finishes charging, V3 is changed into low level, at the moment, the sixth PMOS tube (59) is opened, the eighth NMOS tube (67) is closed, and V4 is output normally.

When the ground potential of the receiving circuit is higher than the ground potential of the receiving and transmitting circuit, the signal amplitude of V1 is reduced rapidly due to common mode interference, when the signal amplitude of V1 is lower than the conduction voltage drop of a third diode (69) which is referenced to the ground, the third diode (69) is conducted, and the signal amplitude of V1 is clamped at the conduction voltage drop of the third diode (69).

When the signal amplitude of V1 is rapidly reduced but is higher than the conduction voltage drop of a third diode (69) which is referenced to the ground, the first diode (51) and the second diode (52) are cut off, and V2 and V4 do not rapidly reduce along with V1 at the moment, so that the stability of the V4 signal is ensured, and V4 is normally output.

When no CMT event occurs, when an input signal is high level, V1 and V2 are high level, the ninth PMOS tube (66) is turned off, V3 is low level, the sixth PMOS tube (59) is turned on, the eighth NMOS tube (67) is turned off, and V4 outputs stable high level. When no CMT event occurs, when an input signal changes from a high level to a low level, V1, V2 and V3 are low levels, a sixth PMOS tube (59) is turned off, a ninth PMOS tube (66) is turned on, an eighth NMOS tube (67) is turned off, residual charges of V4 are discharged to the ground through the ninth PMOS tube (66), and V4 stably outputs the low level.

As shown in fig. 6, a four-port isolator according to an embodiment of the present invention includes:

the input end of the overvoltage protection circuit (110) of the CMT suppression circuit (26) is connected with the output end of the rectification filter circuit (25) of the four-port isolator body, and the output end of the switch circuit (130) of the CMT suppression circuit (26) is connected with the output circuit (27) of the four-port isolator body.

Preferably, the method further comprises the following steps: the device comprises a sending circuit (22) and a coupling transmission circuit (23) which are connected in sequence, wherein the sending circuit (22) is provided with a first signal input end (20) and a first grounding end (21);

the coupling transmission circuit (23) is configured to: -coupling the output signal of the transmission circuit (22) to a rectifying and filtering circuit (25);

Preferably, the method further comprises the following steps: the rectification filter circuit (25), the CMT suppression circuit (26) and the output circuit (27) form a receiving circuit (24), and the receiving circuit (24) is provided with a first signal output end (28) and a second grounding end (29);

Preferably, the four-port isolator can transmit a digital signal or an analog signal, which can be a positive level signal or a negative level signal.

Specifically, the four-port isolator includes: the device comprises a sending circuit (22), a coupling transmission circuit (23) and a receiving circuit (24) which are sequentially connected, wherein the sending circuit (22) is provided with a first signal input end (20) and a first grounding end (21), the receiving circuit (24) is provided with a first signal output end (28) and a second grounding end (29), when the input signal is a negative level signal (such as-5-0V), the negative level signal is converted into a positive level signal (0-5V), and the positive level signal is encoded to obtain an encoding signal which is high in frequency and changes randomly; when the input signal is a positive level signal (such as 0-5V), coding the positive level signal to obtain a coding signal with higher frequency and random variation; when the input signal is at a reference level (typically 0), the output encoded signal is at the reference level. The coded signal is transmitted to a receiving circuit (24) by a coupling transmission circuit (23). The receiving circuit (24) comprises a rectifying and filtering circuit (25), a CMT suppression circuit (26) and an output circuit (27) which are sequentially connected, the rectifying and filtering circuit (25) carries out rectifying and filtering on the coded signals to obtain decoded signals, the decoded signals are processed by the CMT suppression circuit (26) to obtain driving signals, and the driving signals are used for driving the output circuit (27) to obtain final output signals. The CMT suppression circuit (26) suppresses the influence of the CMT event on the output circuit (27), and ensures that the output circuit (27) is not damaged in structure and outputs a correct signal. When the coded signal is a signal with randomly changing frequency, the coded signal is transmitted to a receiving circuit (24) through a coupling transmission circuit (23). A rectifying and filtering circuit (25) in the receiving circuit (24) rectifies and filters the coded signal to obtain a decoded signal, the decoded signal passes through a CMT suppression circuit (26) to obtain a driving signal, the driving signal is used for driving an output circuit (27), and the output circuit (27) works and finally outputs a low-level signal, namely a preset reference level, which usually adopts 0V; when the coded signal is at the reference level, the decoding signal output by the rectifying and filtering circuit (25) in the receiving circuit 3 is at the reference level, the driving signal is at the reference level, the output circuit (27) is cut off and finally outputs a high-level signal, namely a positive level.

The rectifying and filtering circuit (25) can be realized by adopting a full-bridge rectifying and RC filtering circuit and is used for rectifying and filtering the received coding signal to obtain a decoding signal.

As shown in fig. 7, the input signal may be a positive level signal or a negative level signal, wherein when the negative level signal is input, the phase of the negative level signal is inverted by 180 degrees and converted into the positive level signal after being processed by a bidirectional rectifying circuit in the transmitting circuit (22), and the signal becomes an a waveform. Then the positive level signal is coded by a coding circuit in a sending circuit (22) to obtain a coding signal with higher frequency and random variation, namely a B waveform. The coded signal is converted into a C waveform after being transmitted by the coupling transmission circuit (23), when no CMT event occurs, the C is decoded by the rectifying and filtering circuit (25) to obtain a decoded signal with the same frequency as the input signal, namely a D waveform, and a driving signal, namely an E waveform, is obtained through the CMT suppression circuit (26). The drive signal E drives the output circuit (27) to obtain a final output waveform, when the drive signal is in a high level, the output circuit is opened, and a low level signal is output, and when the drive signal is in a low level, the output circuit is closed, and a high level is output, so that the phase of the output signal is opposite to that of the input signal.

As shown in fig. 8, the input signal may be a positive level signal or a negative level signal, wherein when the negative level signal is input, the phase of the negative level signal is inverted by 180 degrees and converted into the positive level signal after being processed by a bidirectional rectifying circuit in the transmitting circuit (22), and the signal becomes an a waveform. Then the positive level signal is coded by a coding circuit in a sending circuit (22) to obtain a coding signal with higher frequency and random variation, namely a B waveform. The coded signal is converted into a C waveform after being transmitted by the coupling transmission circuit (23), the C waveform is decoded by the rectifying and filtering circuit (25) to obtain a decoded signal with the same frequency as the input signal, namely a D waveform, and the D waveform passes through the CMT suppression circuit (26) to obtain a driving signal, namely an E waveform. When the input signal is at a low level and the potential of the first ground terminal (21) is higher than that of the second ground terminal (29), the coded signal B is interfered by common mode noise, a peak appears at a point 1104, a signal at the point 1104 corresponds to a point 1107 of a demodulated signal D after being coupled, transmitted and demodulated, and is acted by a CMT suppression circuit (26), the amplitude of the signal at the point 1107 is remarkably reduced compared with that of a signal at a point 307 in FIG. 9, the signal at the point 1107 corresponds to a point E1110 after being processed by the CMT suppression circuit (26), and the amplitude of the signal at the point 1110 is very low, so that the wrong opening of an output circuit is avoided, and further the wrong output signal is avoided. When the input signal is at a high level and the potential of the first ground terminal (21) is higher than that of the second ground terminal (29), the common-mode noise interference is received, the oscillation amplitude of the coded signal B is remarkably increased at a point 1105, the signal at the point 1105 corresponds to a point 1108 of the demodulated signal D after being coupled, transmitted and demodulated, and is acted by the CMT suppression circuit (26), the signal amplitude at the point 1108 is remarkably reduced compared with that at a point 308 in FIG. 9, and the signal amplitude at the point 1108 is normal after passing through the CMT suppression circuit (26), so that the breakdown of the output circuit cannot be caused. When the input signal is at a high level and the potential of the second ground terminal (29) is higher than that of the first ground terminal (21), the common mode noise interference is received, the oscillation amplitude of the coded signal B at the 1106 point is remarkably reduced, the signal at the 1106 point corresponds to the 1109 point of the demodulated signal D after coupling transmission and demodulation and is acted by the CMT suppression circuit (26), the amplitude of the signal at the 1109 point is remarkably increased compared with that of the signal at the 309 point in FIG. 9, the signal at the point cannot cause the output circuit to be turned off mistakenly, and further the occurrence of a wrong output signal is avoided.

As shown in fig. 10, a package according to an embodiment of the present invention includes: a first chip (100) and a second chip (200), wherein:

The first chip (100) and the second chip (200) are packaged in the same tube shell through a bonding wire or other connection modes, pins of the first chip (100) are a signal input end and a first grounding end, pins of the second chip (200) are a signal output end and a second grounding end, and in actual work, a signal output end of the second chip (200) can be externally connected with a resistor RL and a power VCC to finish signal output.

An electronic device in an embodiment of the invention comprises a CMT suppression circuit for a four port isolator or a four port isolator as described in any of the above embodiments.

It is to be understood that electronic equipment refers to military electronic systems, aerospace electronic equipment, medical equipment, etc. incorporating the four port isolator described in any of the various embodiments above.

The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, a circuit may be divided into only one logic function, and may be actually implemented in another way, for example, a plurality of electronic components may be combined or may be integrated into another circuit.

While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A CMT suppression circuit for a four port isolator, comprising: the circuit comprises an overvoltage protection circuit (110), a one-way conduction circuit (120), a switch circuit (130), a CMT detection circuit (140) and a current relief circuit (150); the input end of the overvoltage protection circuit (110) is connected with a rectifying and filtering circuit (25) of the four-port isolator, the output end of the overvoltage protection circuit (110) is connected with the input end of the unidirectional conduction circuit (120), and the unidirectional conduction circuit comprises two output ends which are respectively connected with the first input end of the switch circuit (130) and the input end of the CMT detection circuit (140);

the CMT detection circuit (140) is configured to: receiving and switching on or off the switch circuit (130) or the current bleeder circuit (150) according to the change of an output signal output by a second output terminal of the unidirectional conduction circuit (120);

2. The CMT suppression circuit for a four-port isolator according to claim 1, characterized in that the CMT detection circuit (140) comprises in particular: the CMOS image sensor comprises a signal input end, a first PMOS (P-channel metal oxide semiconductor) tube (1), a second PMOS tube (8), a third PMOS tube (10), a first NMOS tube (7), a second NMOS tube (9), a third NMOS tube (11), a first resistor (2), a second resistor (3), a third resistor (4), a fourth resistor (6), a capacitor (5) and a signal output end, wherein the signal input end of a CMT (constant current transistor) detection circuit (140) is respectively connected with a source electrode of the first PMOS tube (1), a source electrode of the second PMOS tube (8), a source electrode of the third PMOS tube (10) and the fourth resistor (6), a grid electrode of the first PMOS tube (1) is connected with the first resistor (2), the drain electrode of the first PMOS tube (1) is respectively connected with the second resistor (3) and the third resistor (4), the other end of the third resistor (4) is respectively connected with the capacitor (5) and the grid electrode of the first NMOS tube (7), the drain electrode of the first NMOS tube (7) is connected with the fourth resistor (6), the grid electrode of the second PMOS tube (8) and the grid electrode of the second NMOS tube (9), the drain electrode of the second PMOS tube (8), the drain electrode of the second NMOS tube (9), the grid electrode of the third PMOS tube (10) and the grid electrode of the third NMOS tube (11), and the drain electrode of the third PMOS tube (10) and the drain electrode of the third NMOS tube (11) are connected with the CMT detection circuit The signal output terminals of the paths (140) are connected.

3. The CMT suppression circuit for four-port isolators according to claim 1 or 2, characterized in that the current bleeding circuit (150) comprises in particular: the grid electrode of the fourth NMOS tube is connected with the signal output end of the CMT detection circuit (140), the drain electrode of the fourth NMOS tube is connected with the output end of the switch circuit (130), and the source electrode of the fourth NMOS tube is grounded.

4. Four-port isolator, comprising a four-port isolator body and a CMT suppression circuit for a four-port isolator according to any of the preceding claims 1 to 3, the input of the overvoltage protection circuit (110) of the CMT suppression circuit (26) being connected to the output of the rectifying-filtering circuit (25) of the four-port isolator body, the output of the switching circuit (130) of the CMT suppression circuit (26) being connected to the output circuit (27) of the four-port isolator body.

5. The four port isolator of claim 4, further comprising: the device comprises a sending circuit (22) and a coupling transmission circuit (23) which are connected in sequence, wherein the sending circuit (22) is provided with a first signal input end (20) and a first grounding end (21);

6. The four port isolator of claim 5, further comprising: the rectification filter circuit (25), the CMT suppression circuit (26) and the output circuit (27) form a receiving circuit (24), and the receiving circuit (24) is provided with a first signal output end (28) and a second grounding end (29);

the receiving circuit (24) is configured to: and decoding the received coded signal through the rectification filter circuit (25) to obtain a decoded signal, transmitting the decoded signal to the CMT suppression circuit (26) for processing to obtain a driving signal, and driving the output circuit (27) according to the driving signal so that the output circuit (27) outputs a final output signal through the first signal output end (28).

7. Four-port isolator according to any of claims 4-6, wherein said four-port isolator is adapted to transmit digital signals or analog signals, said analog signals or said digital signals being positive level signals or negative level signals.