CN113991722A - Multi-feed-in direct current short-circuit ratio calculation method and device, storage medium and calculation equipment - Google Patents
Multi-feed-in direct current short-circuit ratio calculation method and device, storage medium and calculation equipment Download PDFInfo
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Abstract
The invention discloses a method, a device, a storage medium and a computing device for calculating a multi-feed-in direct-current short-circuit ratio, wherein a node admittance matrix of a power grid electric island is obtained based on a primary device model, remote signaling measurement information and remote measurement information, a node impedance matrix under the ground state condition is solved in a multi-thread parallel mode according to the node admittance matrix, the fast calculation of the node impedance matrix under the ground state condition is realized, relevant elements related to the calculation of the multi-feed-in direct-current short-circuit ratio in the node impedance matrix under the ground state condition are corrected, the node impedance matrix under the condition that a line N-1 is disconnected is obtained, and therefore the fast calculation of the multi-feed-in direct-current short-circuit ratio of the line N-1 is considered is realized.
Description
Technical Field
The invention relates to a method and a device for calculating a multi-feed-in direct current short-circuit ratio, a storage medium and calculation equipment, and belongs to the technical field of power system automation.
Background
With the construction of power grids, high-voltage direct-current power transmission becomes an important form of large-area interconnection and long-distance large-capacity power transmission, and a grid structure of a multi-loop direct-current high-power feed-in receiving-end alternating-current power grid is formed in multiple areas. The interaction among the multi-feed-in direct current transmission systems has great influence on the safe and stable operation of the whole power grid, the electrical distance among a plurality of direct current inversion stations in the multi-feed-in direct current system is often smaller, the simultaneous phase commutation failure of a plurality of direct current systems is easily caused by the fault of an alternating current side, and when the voltage supporting capacity of the alternating current power grid is insufficient, the oscillation and the hysteresis of direct current power recovery can be caused by the direct current dynamic reactive demand, so that the risks of transient voltage instability and power angle instability of the system are increased, and the operation safety of the alternating current and direct current power grid is threatened.
In practical engineering application, a multi-input short circuit ratio (MISCR) is generally adopted to evaluate the supporting capability of an alternating current system in a multi-input DC power transmission system on alternating current bus voltage of a direct current converter station, the traditional multi-input DC short circuit ratio mainly realizes the calculation of the multi-input short circuit ratio by establishing an equivalent circuit of the alternating current system through Thevenin equivalent, along with the increase of the scale of a power grid, when the operation mode of the power grid is adjusted, the time for calculating the Thevenin equivalent circuit is too long, the quick calculation considering the condition that the N-1 line is disconnected cannot be adapted, and the requirement of quick analysis decision of the large-scale power grid cannot be met.
Disclosure of Invention
The invention provides a method, a device, a storage medium and a computing device for calculating a multi-feed-in direct-current short-circuit ratio, which solve the problems disclosed in the background art.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a multi-feed-in direct current short circuit ratio calculation method is provided, and comprises the following steps:
acquiring a primary equipment model, remote signaling measurement information and remote measurement information of a power grid;
acquiring a node admittance matrix of the power grid electric island according to the primary equipment model, the remote signaling measurement information and the remote measuring measurement information;
calculating a node impedance matrix under the ground state condition by adopting a multithreading parallel mode according to the node admittance matrix;
correcting related elements related to multi-feed-in direct current short circuit ratio calculation in the node impedance matrix under the ground state condition to obtain the node impedance matrix under the condition that the power grid line N-1 is disconnected;
and calculating the multi-feed-in direct current short-circuit ratio of the line N-1 according to the node impedance matrix under the condition that the power grid line N-1 is disconnected.
The primary equipment model comprises primary equipment element parameters and a connection relation between primary equipment elements, and the telemetering measurement information comprises transformer gear measurement information; acquiring a node admittance matrix of the power grid electric island according to the primary equipment model, the remote signaling measurement information and the remote sensing measurement information, and the specific process is as follows:
acquiring an electric island-node-branch model of the power grid according to the connection relation between the remote signaling measurement information and the primary equipment element;
and acquiring a node admittance matrix of the power grid electric island according to the electric island-node-branch model, the primary equipment element parameters and the transformer gear measurement information.
And elements in the node admittance matrix are stored in a sparse format based on the associated container, and non-zero elements and indexes thereof are stored.
According to the node admittance matrix, a node impedance matrix under the ground state is calculated in a multi-thread parallel mode, and the specific process can be as follows:
carrying out LDU factorization on the node admittance matrix to obtain a factor table;
and calculating a node impedance matrix under the ground state condition by adopting a multithreading parallel mode according to the factor table.
Performing LDU factorization on the node admittance matrix to obtain a factor table, which comprises the following steps:
reordering the node numbers of the node admittance matrix by adopting a minimum node ordering method;
and performing LDU factorization on the node admittance matrix after the node numbers are reordered to obtain a factor table.
Correcting related elements related to multi-feed-in direct current short circuit ratio calculation in the node impedance matrix under the ground state condition to obtain the node impedance matrix under the condition that the power grid line N-1 is disconnected, wherein the specific process can be as follows:
and correcting related elements related to multi-feed-in direct current short circuit ratio calculation in the node impedance matrix under the ground state by adopting a branch addition pair to obtain the node impedance matrix under the condition that the power grid line N-1 is disconnected.
The formula for correcting the node impedance matrix elements under the ground state condition is as follows:
wherein Z isijThe element of the ith row and the jth column in the node impedance matrix under the ground state condition; z'ijIs to ZijElements after correction are carried out; zaaThe element of the a-th row and the a-th column in the node impedance matrix under the ground state condition; zbbThe element of the b-th row and the b-th column in the node impedance matrix under the ground state condition; zabThe element of the a-th row and the b-th column in the node impedance matrix under the ground state condition; z is a radical ofabIs the open line impedance between node a and node b; ziaThe element of the ith row and the a th column in the node impedance matrix under the ground state condition; zibThe element of the ith row and the b th column in the node impedance matrix under the ground state condition; zajIn a nodal impedance matrix in the ground stateRow a, column j elements; zbjThe element of the b th row and the j th column in the node impedance matrix under the ground state condition.
The formula for calculating the multi-feed-in direct current short circuit ratio considering the circuit N-1 is as follows:
wherein, BSDCFor a set of AC bus nodes, MSCR, of a DC converter station in a multi-feed DC systemiFor the i-th feedback DC feed-in current conversion bus short-circuit ratio, UiFor converting the voltage of the busbar node i, PdiFor the ith return DC transmission power, PdjFor the jth return dc transmission power,
the ith row and ith column elements in the node impedance matrix under the condition that the line N-1 is disconnected,
the ith row and the jth column elements in the node impedance matrix under the condition that the line N-1 is disconnected.
Provided is a multi-feed direct current short circuit ratio calculation device, comprising:
the acquisition module is used for acquiring a primary equipment model, remote signaling measurement information and remote measurement information of the power grid;
the node admittance matrix module is used for acquiring a node admittance matrix of the power grid electric island according to the primary equipment model, the remote signaling measurement information and the remote measuring measurement information;
the node impedance matrix module is used for calculating a node impedance matrix under the ground state condition in a multithreading parallel mode according to the node admittance matrix;
the correction module is used for correcting related elements related to multi-feed-in direct current short circuit ratio calculation in the node impedance matrix under the ground state condition to obtain the node impedance matrix under the condition that the power grid line N-1 is disconnected;
and the short circuit ratio calculation module is used for calculating the multi-feed-in direct current short circuit ratio of the line N-1 according to the node impedance matrix under the condition that the power grid line N-1 is switched on and off.
The correction module is used for: and correcting related elements related to the calculation of the multi-feed-in direct current short circuit ratio in the node impedance matrix under the ground state by adopting a branch addition method to obtain the node impedance matrix under the condition that the line N-1 is disconnected.
The formula of the correction element of the correction module is as follows:
wherein Z isijThe element of the ith row and the jth column in the node impedance matrix under the ground state condition; z'ijIs to ZijElements after correction are carried out; zaaThe element of the a-th row and the a-th column in the node impedance matrix under the ground state condition; zbbThe element of the b-th row and the b-th column in the node impedance matrix under the ground state condition; zabThe element of the a-th row and the b-th column in the node impedance matrix under the ground state condition; z is a radical ofabIs the open line impedance between node a and node b; ziaThe element of the ith row and the a th column in the node impedance matrix under the ground state condition; zibThe element of the ith row and the b th column in the node impedance matrix under the ground state condition; zajElements of the a-th row and the j-th column in the node impedance matrix under the ground state; zbjThe element of the b th row and the j th column in the node impedance matrix under the ground state condition.
A storage medium is provided that is a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform a multi-feed dc-to-short ratio calculation method.
There is provided a computing device comprising one or more processors, one or more memories, and one or more programs stored in the one or more memories and configured to be executed by the one or more processors, the one or more programs including instructions for performing a multi-feed dc-to-short ratio calculation method.
The invention achieves the following beneficial effects: the method comprises the steps of obtaining a node admittance matrix of the electric island of the power grid based on a primary equipment model, remote signaling measurement information and remote measurement information, solving a node impedance matrix under the ground state condition in a multi-thread parallel mode according to the node admittance matrix, realizing rapid calculation of the node impedance matrix under the ground state condition, correcting related elements related to multi-feed-in direct current short circuit ratio calculation in the node impedance matrix under the ground state condition, obtaining the node impedance matrix under the condition that a line N-1 is disconnected, and accordingly realizing rapid calculation of the multi-feed-in direct current short circuit ratio considering the line N-1.
Drawings
FIG. 1 is a flow chart of a method for calculating a multi-feed DC short circuit ratio;
FIG. 2 is a flow chart of solving a node impedance matrix in a multi-thread parallel manner under a ground state condition;
fig. 3 is a block diagram of a multi-feed dc short-circuit ratio calculating device.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
As shown in fig. 1, the method for calculating the multi-feed dc short-circuit ratio includes the following steps:
step 1, acquiring a primary equipment model, remote signaling measurement information and remote measuring measurement information of a power grid;
step 2, acquiring a node admittance matrix of the power grid electric island according to the primary equipment model, the remote signaling measurement information and the remote measurement information;
step 3, calculating a node impedance matrix under the ground state condition by adopting a multithreading parallel mode according to the node admittance matrix;
the node is an alternating current system bus node comprising a current conversion bus node fed into an alternating current system by a direct current system;
step 4, correcting related elements related to multi-feed-in direct current short circuit ratio calculation in the node impedance matrix under the ground state condition to obtain the node impedance matrix under the condition that the power grid line N-1 is disconnected;
and 5, calculating the multi-feed-in direct current short-circuit ratio of the line N-1 according to the node impedance matrix under the condition that the power grid line N-1 is disconnected.
The method includes the steps of obtaining a node admittance matrix of the power grid electric island based on a primary equipment model, remote signaling measurement information and remote measurement information, solving a node impedance matrix under a ground state condition in a multi-thread parallel mode according to the node admittance matrix, achieving rapid calculation of the node impedance matrix under the ground state condition, correcting relevant elements related to multi-feed-in direct current short circuit ratio calculation in the node impedance matrix under the ground state condition, obtaining the node impedance matrix under the condition that a line N-1 is disconnected, and achieving rapid calculation of the multi-feed-in direct current short circuit ratio considering the line N-1.
The primary equipment model can be directly obtained from a power grid model service of a dispatching control system, and comprises primary equipment element parameters of a generator, a transformer, an alternating current circuit, a current converter, a capacitor, a reactor, a bus and the like and connection relations among primary equipment elements. A primary equipment model can be obtained from a dispatching control system database through a power grid model service provided by a regulation and control system supporting platform, and a power grid model can be obtained across a multi-stage dispatching center and a dispatching system through the power grid model service, so that wide-area obtaining of the power grid model is realized.
The remote signaling measurement information and the remote measurement information can be directly obtained from the measurement service of the dispatching control system, and the power grid measurement information can be obtained by spanning a multilevel dispatching center and a dispatching system, so that the wide-area acquisition of the measurement information is realized; the remote measurement information comprises transformer gear measurement information and direct current pole power, the remote signaling measurement information comprises remote signaling states of a circuit breaker and a disconnecting switch, and the acquired measurement information is associated with the primary equipment model.
Acquiring a node admittance matrix of the power grid electric island according to the primary equipment model, the remote signaling measurement information and the remote measurement information, wherein the specific process can be as follows:
11) performing network topology analysis according to the connection relation between the remote signaling measurement information and the primary equipment element to obtain an electric island-node-branch model of the power grid;
in the normal operation of an actual power grid, the states of the circuit breaker and the disconnecting switch are rarely changed, and when the remote signaling state is not changed when the state of the circuit breaker and the disconnecting switch is calculated at this time compared with the state of the circuit breaker and the disconnecting switch calculated at the last time, topology analysis is not needed; when only part of the telecommand states are changed, only the plant stations with the changed telecommand states are subjected to local network topology analysis according to the voltage grades so as to improve the calculation speed;
12) acquiring a node admittance matrix Y of the electric island of the power grid according to the electric island-node-branch model, the parameters of primary equipment elements and the gear measurement information of the transformer;
in order to improve the calculation speed, the elements in the node admittance matrix Y are stored in a sparse format based on the associated container, and only non-zero elements and indexes thereof are stored.
The sparse matrix structure defined based on the associative container map is defined as:
typedef std::map<int,float>SparseRowMap；
typedef std::map<int,SparseRowMap>SparseMatrixMap；
the structure sparsemaxmap is used to store a sparse matrix, where sparsemowmap sparsely stores a row of non-zero elements, the column number is represented by an int-type key index, and the sparse matrix non-zero elements are represented by float-type associated values.
Because the node numbering sequence in the node admittance matrix directly influences the sparsity of a factor table of the node admittance matrix and has direct influence on the calculation efficiency, after the node admittance matrix is obtained, the node numbering of the node admittance matrix is reordered by adopting a minimum node ordering method according to a non-zero element structure.
And reordering the node numbers by adopting a minimum node ordering method to reduce the number of injection elements in the factorization process, and only processing the change of the network structure of the power grid without performing the operation of simulating floating point numbers in a Gaussian elimination method in the reordering process of the node numbers.
And performing LDU factorization on the reordered node admittance matrix by adopting a Gaussian elimination method to obtain a factor table, and solving a node impedance matrix Z under the ground state condition by adopting a multithreading parallel mode according to the factor table.
When the multi-feed-in direct-current short-circuit ratio of a plurality of direct-current drop points and the multi-feed-in direct-current short-circuit ratio under the condition that a line N-1 is disconnected need to be calculated, due to the fact that the solving of each row/each column of the node impedance matrix is independent, the node impedance matrix is calculated in a multi-thread parallel mode on a large-scale power grid, the calculating speed of the node impedance matrix is improved, the specific flow is shown in figure 2, each thread calculates a row value of Z through a continuous back substitution method, and finally the result is converged into the node impedance matrix Z.
The line N-1 is disconnected, namely a branch circuit is removed from the power grid, which is equivalent to adding a negative impedance branch circuit, so that a node impedance matrix under the ground state condition is subjected to partial element correction by adopting a branch circuit addition method to obtain the node impedance matrix under the condition that the line N-1 is disconnected.
In an actual power grid, a plurality of high-voltage direct-current transmission lines are connected to a power grid structure in the same region, and the direct-current systems with short electrical distances and the fed-in alternating-current power grid form a multi-feed direct-current system together. In an actual direct current system, multiple converter poles exist in the same converter station, alternating current sides of different converter poles may be the same topological bus or different topological nodes, and a set BS is formed for the nodesDCI.e. BSDCThe method is characterized in that a direct current converter station alternating current bus node set in a multi-feed direct current system is shown. Since the calculation of the multi-feed DC short circuit ratio only involves the set BSDCThe self impedance and the mutual impedance of each node in the node impedance matrix are calculated by only collecting BS (direct current) drop point nodes in the node impedance matrixDCAnd correcting the element of the row in which the middle node is positioned, wherein other elements do not need to be calculated.
Let the end nodes of the open line a-b (i.e. the line between node a and node b) be a and b, respectively, and the formula for correcting the node impedance matrix element in the ground state is:
wherein Z isijThe mutual impedance between the node i and the node j is the element of the ith row and the jth column in the node impedance matrix under the ground state; z'ijIs to ZijElements after correction are carried out; zaaThe self impedance of the node a of the open-circuit line a-b is the element of the a-th row and the a-th column in the node impedance matrix under the ground state; zbbThe self impedance of the node b of the open-circuit line a-b is the element of the b-th row and the b-th column in the node impedance matrix under the ground state; zabThe mutual impedance between the node a and the node b is the element of the a-th row and the b-th column in the node impedance matrix under the ground state; z is a radical ofabIs the open line impedance between node a and node b; ziaThe mutual impedance between the node i and the node a is the element of the ith row and the a th column in the node impedance matrix under the ground state; zibThe mutual impedance between the node i and the node b is the element of the ith row and the b th column in the node impedance matrix under the ground state; zajThe mutual impedance between the node a and the node j is the element of the a-th row and the j-th column in the node impedance matrix under the ground state; zbjThe mutual impedance between the node b and the node j is the element of the b th row and the j th column in the node impedance matrix under the ground state.
It should be noted that the disconnection of the line N-1 may cause grid disconnection, before the node impedance element is corrected, it needs to be judged in advance whether the disconnection of the line N-1 may cause grid disconnection, and if the system disconnection is caused, topology analysis is performed again to form a disconnected electric island-node-branch model.
According to a node impedance matrix under the condition that the power grid line N-1 is disconnected, calculating a multi-feed-in direct current short circuit ratio of the line N-1, wherein a specific formula can be as follows:
wherein, BSDCFor a set of AC bus nodes, MSCR, of a DC converter station in a multi-feed DC systemiFor the ith feedback DC feed-in switchShort-circuit ratio of current bus, UiFor converting the voltage of the busbar node i, PdiFor the ith return DC transmission power, PdjFor the jth return dc transmission power,
the ith row and ith column elements in the node impedance matrix under the condition that the line N-1 is disconnected,
the ith row and the jth column elements in the node impedance matrix under the condition that the line N-1 is disconnected.
The method realizes the rapid calculation of the node impedance matrix based on a multithreading parallel mode, and when the network structure is changed, the rapid calculation of the node impedance under the condition that the line N-1 is disconnected is realized by using a node impedance local correction method, the method only needs to calculate the self impedance of the AC bus node of the DC convertor station and the mutual impedance between the AC bus nodes of the convertor station, and does not need to calculate all elements of the node impedance matrix under the condition that the line N-1 is disconnected, thereby greatly reducing the calculation amount, and improving the overall calculation speed of a large-scale power grid considering the multi-feed-in DC short-circuit ratio of the line N-1.
The method can be used for fast calculation of the multi-feed-in direct current short-circuit ratio, can be popularized to functions of network analysis sensitivity calculation, short-circuit current calculation, network equivalence and the like, and is used for fast solving of the node impedance matrix.
Based on the same inventive concept, an embodiment of the present application further provides a multi-feed dc-to-short ratio calculating apparatus, as shown in fig. 3, the multi-feed dc-to-short ratio calculating apparatus includes:
the acquisition module is used for acquiring a primary equipment model, remote signaling measurement information and remote measurement information of the power grid;
the node admittance matrix module is used for acquiring a node admittance matrix of the power grid electric island according to the primary equipment model, the remote signaling measurement information and the remote measurement information;
the node impedance matrix module is used for calculating a node impedance matrix under the ground state condition in a multithreading parallel mode according to the node admittance matrix;
the correction module is used for correcting related elements related to multi-feed-in direct current short circuit ratio calculation in a node impedance matrix under the ground state condition by adopting a branch addition method to obtain the node impedance matrix under the condition that the power grid line N-1 is disconnected;
and the short circuit ratio calculation module is used for calculating the multi-feed-in direct current short circuit ratio of the line N-1 according to the node impedance matrix under the condition that the power grid line N-1 is switched on and off.
The formula of the correction element of the correction module is as follows:
wherein Z isijThe mutual impedance between the node i and the node j is the element of the ith row and the jth column in the node impedance matrix under the ground state; z'ijIs to ZijElements after correction are carried out; zaaThe self impedance of the node a of the open-circuit line a-b is the element of the a-th row and the a-th column in the node impedance matrix under the ground state; zbbThe self impedance of the node b of the open-circuit line a-b is the element of the b-th row and the b-th column in the node impedance matrix under the ground state; zabThe mutual impedance between the node a and the node b is the element of the a-th row and the b-th column in the node impedance matrix under the ground state; z is a radical ofabIs the open line impedance between node a and node b; ziaThe mutual impedance between the node i and the node a is the element of the ith row and the a th column in the node impedance matrix under the ground state; zibThe mutual impedance between the node i and the node b is the element of the ith row and the b th column in the node impedance matrix under the ground state; zajThe mutual impedance between the node a and the node j is the element of the a-th row and the j-th column in the node impedance matrix under the ground state; zbjThe mutual impedance between the node b and the node j is the element of the b th row and the j th column in the node impedance matrix under the ground state.
All the related contents of the steps involved in the embodiment of the multi-feed-in dc short-circuit ratio calculation method corresponding to fig. 1 can be cited to the functional description of the functional module corresponding to the multi-feed-in dc short-circuit ratio calculation apparatus in the embodiment of the present application, and are not repeated herein.
The program of the multi-feed-in direct current short circuit ratio calculation device in the embodiment of the application can run independently, is irrelevant to network analysis functions such as state estimation, static safety analysis and reactive voltage optimization functions in the dispatching automation system, and does not influence the running of the production function of the actual dispatching system.
Based on the same inventive concept, the present application also provides a storage medium, which is a computer-readable storage medium storing one or more programs, the one or more programs including instructions, which when executed by a computing device, cause the computing device to execute a multi-feed dc-to-short ratio calculation method.
Based on the same inventive concept, embodiments of the present application also provide a computing device comprising one or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs comprise instructions for executing the multi-feed dc-to-short ratio calculation method.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The present invention is not limited to the above embodiments, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the claims of the present invention which are filed as the application.
Claims (13)
1. The multi-feed-in direct current short circuit ratio calculation method is characterized by comprising the following steps:
acquiring a primary equipment model, remote signaling measurement information and remote measurement information of a power grid;
acquiring a node admittance matrix of the power grid electric island according to the primary equipment model, the remote signaling measurement information and the remote measuring measurement information;
calculating a node impedance matrix under the ground state condition by adopting a multithreading parallel mode according to the node admittance matrix;
correcting related elements related to multi-feed-in direct current short circuit ratio calculation in the node impedance matrix under the ground state condition to obtain the node impedance matrix under the condition that the power grid line N-1 is disconnected;
and calculating the multi-feed-in direct current short-circuit ratio of the line N-1 according to the node impedance matrix under the condition that the power grid line N-1 is disconnected.
2. The method according to claim 1, wherein the primary equipment model includes primary equipment element parameters and connection relationships between primary equipment elements, and the telemetric measurement information includes transformer step measurement information; acquiring a node admittance matrix of the power grid electric island according to the primary equipment model, the remote signaling measurement information and the remote sensing measurement information, and the specific process is as follows:
acquiring an electric island-node-branch model of the power grid according to the connection relation between the remote signaling measurement information and the primary equipment element;
and acquiring a node admittance matrix of the power grid electric island according to the electric island-node-branch model, the primary equipment element parameters and the transformer gear measurement information.
3. The method according to claim 1 or 2, wherein the elements in the node admittance matrix are stored in a sparse format based on associative containers, and non-zero elements and their indices are stored.
4. The method for calculating the multi-feed-in direct-current short-circuit ratio according to claim 1, wherein a node impedance matrix under a ground state is calculated in a multi-thread parallel manner according to the node admittance matrix, and the specific process is as follows:
carrying out LDU factorization on the node admittance matrix to obtain a factor table;
and calculating a node impedance matrix under the ground state condition by adopting a multithreading parallel mode according to the factor table.
5. The method according to claim 4, wherein said LDU factorization of the node admittance matrix to obtain a factor table comprises:
reordering the node numbers of the node admittance matrix by adopting a minimum node ordering method;
and performing LDU factorization on the node admittance matrix after the node numbers are reordered to obtain a factor table.
6. The method according to claim 1, wherein the correction of the relevant elements related to the calculation of the multi-feed dc short-circuit ratio in the nodal impedance matrix under the ground state condition is performed to obtain the nodal impedance matrix under the condition that the power grid line N-1 is disconnected, and the specific process is as follows:
and correcting related elements related to the calculation of the multi-feed-in direct current short circuit ratio in the node impedance matrix under the ground state by adopting a branch addition method to obtain the node impedance matrix under the condition that the line N-1 is disconnected.
7. The method according to claim 6, wherein the formula of element correction is:
wherein Z isijThe element of the ith row and the jth column in the node impedance matrix under the ground state condition; z'ijIs to ZijElements after correction are carried out; zaaThe element of the a-th row and the a-th column in the node impedance matrix under the ground state condition; zbbThe element of the b-th row and the b-th column in the node impedance matrix under the ground state condition; zabThe element of the a-th row and the b-th column in the node impedance matrix under the ground state condition; z is a radical ofabIs the open line impedance between node a and node b; ziaThe element of the ith row and the a th column in the node impedance matrix under the ground state condition; zibThe element of the ith row and the b th column in the node impedance matrix under the ground state condition; zajElements of the a-th row and the j-th column in the node impedance matrix under the ground state; zbjThe element of the b th row and the j th column in the node impedance matrix under the ground state condition.
8. The method according to claim 1, wherein the formula for calculating the multi-feed dc short-circuit ratio considering the N-1 line is:
wherein, BSDCFor a set of AC bus nodes, MSCR, of a DC converter station in a multi-feed DC systemiFor the i-th feedback DC feed-in current conversion bus short-circuit ratio, UiFor converting the voltage of the busbar node i, PdiFor the ith return DC transmission power, PdjFor the jth return dc transmission power,
the ith row and ith column elements in the node impedance matrix under the condition that the line N-1 is disconnected,
the ith row and the jth column elements in the node impedance matrix under the condition that the line N-1 is disconnected.
9. A multi-feed dc-to-short ratio calculating apparatus, comprising:
the acquisition module is used for acquiring a primary equipment model, remote signaling measurement information and remote measurement information of the power grid;
the node admittance matrix module is used for acquiring a node admittance matrix of the power grid electric island according to the primary equipment model, the remote signaling measurement information and the remote measuring measurement information;
the node impedance matrix module is used for calculating a node impedance matrix under the ground state condition in a multithreading parallel mode according to the node admittance matrix;
the correction module is used for correcting related elements related to multi-feed-in direct current short circuit ratio calculation in the node impedance matrix under the ground state condition to obtain the node impedance matrix under the condition that the power grid line N-1 is disconnected;
and the short circuit ratio calculation module is used for calculating the multi-feed-in direct current short circuit ratio of the line N-1 according to the node impedance matrix under the condition that the power grid line N-1 is switched on and off.
10. The multi-feed dc-to-short ratio calculation apparatus according to claim 9, wherein the correction module is configured to: and correcting related elements related to the calculation of the multi-feed-in direct current short circuit ratio in the node impedance matrix under the ground state by adopting a branch addition method to obtain the node impedance matrix under the condition that the line N-1 is disconnected.
11. The apparatus according to claim 10, wherein the formula of the correction element of the correction module is:
wherein Z isijThe element of the ith row and the jth column in the node impedance matrix under the ground state condition; z'ijIs to ZijElements after correction are carried out; zaaThe element of the a-th row and the a-th column in the node impedance matrix under the ground state condition; zbbThe element of the b-th row and the b-th column in the node impedance matrix under the ground state condition; zabThe element of the a-th row and the b-th column in the node impedance matrix under the ground state condition; z is a radical ofabIs the open line impedance between node a and node b; ziaThe element of the ith row and the a th column in the node impedance matrix under the ground state condition; zibThe element of the ith row and the b th column in the node impedance matrix under the ground state condition; zajElements of the a-th row and the j-th column in the node impedance matrix under the ground state; zbjIs a ground stateIn the case of the element in the b-th row and j-th column of the nodal impedance matrix.
12. A storage medium, characterized by: the storage medium is a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform any of the methods of claims 1-8.
13. A computing device, comprising:
one or more processors, one or more memories, and one or more programs stored in the one or more memories and configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the methods of claims 1-8.
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