CN113708604B

CN113708604B - Resonant switching power converter

Info

Publication number: CN113708604B
Application number: CN202011110647.1A
Authority: CN
Inventors: 刘国基; 白忠龙; 杨大勇
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2020-05-20
Filing date: 2020-10-16
Publication date: 2023-01-31
Anticipated expiration: 2040-10-16
Also published as: TW202145697A; TWI767346B; CN113708604A

Abstract

A resonant switching power converter, comprising: a plurality of capacitors; a plurality of switches; at least one charging inductor; at least one discharge inductor; the controller is used for generating a charging operation signal and at least one discharging operation signal; and at least one zero current detection circuit, for detecting the charging resonance current flowing through the charging inductor during the charging procedure and/or detecting the discharging resonance current flowing through the discharging inductor during the discharging procedure, when the zero current detection circuit detects that the charging resonance current and/or the discharging resonance current is zero, at least one zero current detection signal is correspondingly generated to the controller; the controller determines respective starting time and ending time of the charging process and the discharging process according to the at least one zero current detection signal.

Description

Resonant switching power converter

Technical Field

The present invention relates to a resonant switching power converter, and more particularly, to a resonant switching power converter which determines a switching time by detecting a zero current.

Background

Fig. 1 shows a known power converter. In the charging operation, the switches Q1, Q3, Q5, Q8, Q9 are turned on, and the switches Q2, Q4, Q6, Q7, Q10 are turned off, such that the capacitor C1 is connected in series with the inductor L1 between the input voltage VIN and the output voltage VOUT, and the capacitor C2 is connected in series with the capacitor C3 and the inductor L2 between the ground potential and the output voltage VOUT. In the discharging operation, the switches Q2, Q4, Q6, Q7, Q10 are turned on, and the switches Q1, Q3, Q5, Q8, Q9 are turned off, such that the inductor L1 is connected in series with the capacitor C1 and the capacitor C2 between the ground potential and the output voltage VOUT, and the inductor L2 is connected in series with the capacitor C3 between the ground potential and the output voltage VOUT. The capacitor of the conventional power converter needs to withstand a higher rated voltage, for example, the dc bias of the capacitor C1 is 3 times Vc1=3VOUT of the output voltage, the dc bias of the capacitor C2 is 2 times Vc2=2VOUT of the output voltage, and the dc bias of the capacitor C3 is equal to Vc3= VOUT of the output voltage. In addition, the capacitance of the capacitor usually decreases with the increase of the dc bias voltage, and when the input voltage ranges between 36V and 76V, the dc bias voltage of the capacitor C1 ranges between 27V and 57V, and the variation range of the dc bias voltage is wide, so the capacitance of the conventional power converter varies greatly, and the resonant frequency also varies with the variation of the capacitor. This causes large switching power losses and requires complex control to change the power conversion efficiency. Furthermore, the voltage conversion ratio of the input voltage VIN to the output voltage VOUT of the conventional power converter can only be 4:1 or 2:1, and the voltage conversion ratio of 3:1 cannot be performed. Fig. 2 shows an example in which the capacitance value of the capacitor changes with the dc bias voltage. The capacitance value decreases by 70% when the dc bias is increased to 50V.

In view of the above, the present invention provides an innovative power converter to overcome the above-mentioned shortcomings in the prior art.

Disclosure of Invention

In one aspect, the present invention provides a resonant switching power converter for converting an input voltage to an output voltage, the resonant switching power converter comprising: a plurality of capacitors; a plurality of switches coupled to the plurality of capacitors; at least one charging inductor which is correspondingly connected in series with at least one of the plurality of capacitors; at least one discharge inductor connected in series with at least one of the capacitors; a controller for generating a charging operation signal and at least a discharging operation signal to correspond to a charging procedure and at least a discharging procedure respectively, and operating the corresponding switches to switch the corresponding electric connection relation of the capacitor; and at least one zero current detection circuit for detecting a charging resonant current flowing through the at least one charging inductor during the charging process and/or detecting at least one discharging resonant current flowing through the at least one discharging inductor during the discharging process, wherein when the at least one zero current detection circuit detects that the charging resonant current and/or the at least one discharging resonant current is zero, at least one zero current detection signal is correspondingly generated to the controller; wherein the charging operation signal and the discharging operation signal are respectively switched to a conducting level for a conducting period, and the conducting periods are not overlapped with each other, so that the charging process and the discharging process are not overlapped with each other; wherein, in the charging procedure, the controller controls the switch of the switches through the charging operation signal, so that the capacitors and the at least one charging inductor are connected in series between the input voltage and the output voltage to form a charging path; in the at least one discharging procedure, the controller controls the switching of the switches through the at least one discharging operation signal, so that each capacitor and the corresponding discharging inductor are connected in series between the output voltage and a ground potential, and a plurality of discharging paths are formed simultaneously or alternately; wherein, the controller determines the respective starting time and ending time of the charging process and the discharging process according to the at least one zero current detection signal; the charging process and the at least one discharging process are repeatedly and alternately sequenced to convert the input voltage into the output voltage.

In an embodiment, the controller further determines a start time and an end time of each of the charging process and the at least one discharging process according to the charging operation signal and/or the at least one discharging operation signal.

In one embodiment, the at least one zero current detection circuit includes a current sensing circuit for sensing the charging resonant current during the charging process or sensing the discharging resonant current during the discharging process to generate a current sensing signal; and a comparator for comparing the current sensing signal with a reference signal to generate the at least one zero current detection signal.

In an embodiment, the resonant switching power converter further includes a plurality of switch drivers respectively coupled between the controller and the corresponding switches for respectively controlling the switches according to the corresponding charging operation signal or the corresponding discharging operation signal.

In one embodiment, the controller includes: a logic circuit coupled to the at least one zero current detection circuit for generating a charging determination signal and a discharging determination signal according to the at least one zero current detection signal and the charging operation signal and/or the at least one discharging operation signal; and a decision circuit, coupled to the logic circuit, for generating the charging operation signal and the at least one discharging operation signal according to the charging determination signal and the discharging determination signal to determine respective start time and end time of the charging process and the at least one discharging process.

In one embodiment, the controller further includes a delay circuit coupled between the logic circuit and the determining circuit for delaying a delay time from the start of the charging process and/or the at least one discharging process.

In one embodiment, the charging determination signal is used to determine a start time of the charging process and an end time of the at least one discharging process.

In one embodiment, the logic circuit performs an and logic operation on the at least one zero-current detection signal and an inverted signal of the charging operation signal to generate the charging determination signal.

In one embodiment, the determining circuit includes a first latch circuit for setting the charging operation signal according to the charging determination signal, switching a level of the charging operation signal according to the discharging determination signal, and generating an inverted signal of the charging operation signal to be input to the logic circuit.

In one embodiment, the discharge determination signal is used to determine a start time of the at least one discharge process and an end time of the charging process.

In one embodiment, the logic circuit performs an and logic operation on the at least one zero-current detection signal and an inverted signal of the at least one discharge operation signal to generate the discharge determination signal.

In one embodiment, the determining circuit includes a second latch circuit for setting the at least one discharge operation signal according to the discharge determination signal, switching a level of the at least one discharge operation signal according to the charge determination signal, and generating an inverted signal of the at least one discharge operation signal to be input to the logic circuit.

In one embodiment, the at least one charging inductor is a single charging inductor, and the at least one discharging inductor is a single discharging inductor.

In one embodiment, the inductance of the single charging inductor is equal to the inductance of the single discharging inductor.

In one embodiment, the at least one charging inductor and the at least one discharging inductor are a single same inductor.

In one embodiment, the single same inductor is a variable inductor.

In one embodiment, the charging process has a charging resonant frequency, and the at least one discharging process has a discharging resonant frequency, and the charging resonant frequency is the same as the discharging resonant frequency.

In one embodiment, the charging process has a charging resonant frequency, and the at least one discharging process has a discharging resonant frequency, and the charging resonant frequency is different from the discharging resonant frequency.

In one embodiment, the level of the reference signal is adjusted to adjust the duration of the charging process to achieve zero-voltage switching of soft switching (soft switching).

In one embodiment, the level of the reference signal is adjusted to adjust the duration of the at least one discharging process to achieve zero-voltage switching of soft switching (soft switching).

In one embodiment, the resonant switching power converter is a bidirectional resonant switching power converter.

In one embodiment, the voltage conversion ratio of the input voltage to the output voltage of the resonant switching power converter is 4:1, 3:1 or 2:1.

In one embodiment, the time point of generating the at least one zero current detection signal when the at least one zero current detection circuit detects that the charging resonant current is zero is delayed by a delay time, and the discharging operation signal is switched to perform the at least one discharging process at the end of the delay time.

In one embodiment, the charging process is performed by delaying a time point of the at least one zero current detection signal when the at least one zero current detection circuit detects a time point of the discharge resonant current being zero, and switching the charging operation signal at an end time point of the delay time.

An advantage of the present invention is that the present invention can reduce the number of inductors, compensate for device variations due to dc bias or operating temperature, and reduce the switching frequency to improve efficiency at low loads.

Another advantage of the present invention is that the present invention can support the output voltage regulation function, reduce the voltage stress, and make all the resonant capacitors have the same rated current and rated voltage, thereby enabling the use of a smaller-sized capacitor.

Still another advantage of the present invention is that the present invention can be dynamically controlled to achieve flexible switching with Zero Current Switching (ZCS) or Zero Voltage Switching (ZVS), can have better dynamic load transient response, and can have better current-voltage balance.

Still another advantage of the present invention is that the present invention can have a stable resonant frequency, can more flexibly modulate the voltage conversion ratio, and can operate bidirectionally.

The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.

Drawings

Fig. 1 shows a known power converter.

FIG. 2 is a diagram showing capacitance values as a function of DC bias.

Fig. 3A is a circuit diagram of a resonant switching power converter according to an embodiment of the invention.

Fig. 3B is a circuit diagram of a resonant switching power converter according to an embodiment of the invention.

Fig. 4 is a circuit diagram of a resonant switching power converter according to another embodiment of the invention.

Fig. 5 is a circuit diagram of a resonant switching power converter according to another embodiment of the invention.

Fig. 6 is a circuit diagram of a resonant switching power converter according to another embodiment of the invention.

Fig. 7 is a circuit diagram of a resonant switching power converter according to another embodiment of the invention.

Fig. 8A and 8B are signal waveforms illustrating a circuit and related signals of a resonant switching power converter according to still another embodiment of the invention.

Fig. 9 is a circuit diagram of a resonant switching power converter according to another embodiment of the invention.

Fig. 10 is a circuit diagram of a resonant switching power converter according to another embodiment of the invention.

Fig. 11A, 11B and 11C are signal waveform diagrams illustrating corresponding operation signals and corresponding inductor currents of a charging process and a discharging process according to an embodiment of the invention.

Description of the symbols in the drawings

30. 40, 50, 60, 70, 80, 90, 100 resonant switching power converter

301. 401, 501, 601, 701, 801, 901, 1001 controller

302. 402, 502, 602, 702, 802, 902, 1002 zero current detection circuit

3021. 4021, 5021, 6021, 7021, 8021, 9021, and 10021 Current sensing Circuit

3022. 4022, 5022, 6022, 7022, 8022, 9022 and 10022 comparators

303. 403, 503, 603, 703, 803, 903, 1003 switching driver

4011. 7011 logic circuit

4012. 7012 decision circuit

4012a, 5012a, 7012a first latch circuit

4012b, 5012b, 7012b second latch circuit

4013. 7013 delay circuit

5011a, 8011a first AND gate

5011b, 8011b second AND gate

5012. 8012 inverter

5013. 8013 delay circuit

8014a first latch

8014b second latch

C1-C3, C1 (CR), C2 (CF), C3 (CR) capacitors

Co output capacitance

G1, GA charging operation signal

G2, G3, G4, GB discharge operation signal

Iin is input current

IL1 charging inductor current (charging resonance current)

IL2 discharge inductor current (discharge resonance current)

IL3 inductive current (charging resonance current/discharging resonance current)

L1 charging inductor

L2 discharge inductor

L1 (LR), L2 (LR), L3, lb, inductance

Q is output end

Reverse output end

Q1 to Q10, Q1 (S1A), Q2 (S2A), Q3 (S1B), Q4 (S2B), Q5 (S1A), Q6 (S2A), Q7 (S2A), Q8 (S1B), Q9 (S1B), Q10 (S2B), qb switches

R is reset terminal

S is a setting end

RL load resistance

T1, T2, T3 period

Vc1 capacitor C1 DC bias

Vc2 capacitor C2 DC bias

Vc3 capacitor C3 DC bias

Vin is input voltage

Vout output voltage

Vref1 reference signal

ZCD zero current detection signal

Detailed Description

The drawings in the present disclosure are schematic and are intended to show the coupling relationship between circuits and the relationship between signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

Fig. 3A is a circuit diagram of a resonant switching power converter 30 according to an embodiment of the invention. In the embodiment, the plurality of capacitors share one charging inductor or one discharging inductor, so that no matter the number of the capacitors, only one charging inductor and one discharging inductor are needed, and the number of the inductors can be further reduced. As shown in fig. 3A, the resonant switching power converter 30 of the present invention includes capacitors C1, C2, and C3, switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, and Q10, a charging inductor L1, a discharging inductor L2, a controller 301, at least one zero current detection circuit 302, and a switch driver 303. Switches Q1-Q3 are connected in series with corresponding capacitors C1-C3, respectively, and switch Q4 is connected in series with charging inductor L1. It should be noted that the number of capacitors in the resonant switching power converter 30 of the present invention is not limited to three in the present embodiment, and may be two or more than four, and the number of elements shown in the present embodiment is only for illustration and is not limited to the present invention.

As shown in fig. 3A, one terminal of the switch Q5 is coupled to the node between the switch Q1 and the capacitor C1, one terminal of the switch Q6 is coupled to the node between the switch Q2 and the capacitor C2, and one terminal of the switch Q7 is coupled to the node between the switch Q3 and the capacitor C3. One terminal of the switch Q8 is coupled to the node between the capacitor C1 and the switch Q2, one terminal of the switch Q9 is coupled to the node between the capacitor C2 and the switch Q3, and one terminal of the switch Q10 is coupled to the node between the capacitor C3 and the switch Q4. As shown in fig. 3A, the other ends of the switches Q5-Q7 are connected to a node in series to the discharge inductor L2. The other terminals of the switches Q8-Q10 are commonly coupled to ground potential. The other ends of the charging inductor L1 and the discharging inductor L2 are coupled to the output voltage Vout together, and the other end of the switch Q1 is coupled to the input voltage Vin. The controller 301 is configured to generate the charging operation signal GA and the discharging operation signal GB to respectively correspond to a charging procedure and a discharging procedure, and operate the corresponding switches Q1 to Q10 to switch the electrical connection relationship of the corresponding capacitors C1 to C3. The zero current detection circuit 302 is coupled between the controller 301 and the output voltage Vout, and is configured to detect a charging resonant current IL1 at a node between the charging inductor L1 and the output voltage Vout during a charging process or detect a discharging resonant current IL2 at a node between the discharging inductor L2 and the output voltage Vout during a discharging process. When the zero current detection circuit 302 detects that the charging resonant current IL1 or the discharging resonant current IL2 is zero, a zero current detection signal ZCD is generated to the controller 301, so that the controller 301 generates the charging operation signal GA and the discharging operation signal GB.

In one embodiment, the controller 301 may determine the respective start time and end time of the charging process and the discharging process according to the zero current detection signal ZCD, the charging operation signal GA, and/or the discharging operation signal GB. The zero current detection circuit 302 may include a current sensing circuit 3021 for sensing the charging resonant current IL1 during the charging process or the discharging resonant current IL2 during the discharging process. The zero current detection circuit 302 may further include a comparator 3022 for comparing the sensed charging resonant current IL1 or discharging resonant current IL2 with a reference signal Vref1 to generate a zero current detection signal ZCD. The switch driver 303 is coupled between the controller 301 and the switches Q1 to Q10, and is used for controlling the switches Q1 to Q10 according to the charging operation signal GA or the discharging operation signal GB. In this embodiment and other embodiments, when the zero current detection circuit 302 detects the time point when the charging resonant current IL1 is zero and generates the zero current detection signal ZCD, a delay time is delayed, and the discharging operation signal GB is switched to a high level signal at the end of the delay time for performing the discharging process. In this embodiment and other embodiments, when the zero current detection circuit 302 detects the time point when the discharge resonant current IL2 is zero and generates the zero current detection signal ZCD, a delay time is delayed, and the charging operation signal GA is switched to a high level signal at the end of the delay time for performing the charging process.

The switches Q1-Q10 can switch the corresponding capacitors C1-C3 to the charging inductor L1 and the discharging inductor L2 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 301 through the control of the switch driver 303. In one embodiment, the charging operation signal GA and the discharging operation signal GB are respectively switched to an on level for an on period, and the on periods of the plurality of segments do not overlap each other.

In a charging process, the switches Q1-Q4 are turned on and the switches Q5-Q10 are turned off according to the charging operation signal GA, so that the capacitors C1-C3 are serially connected to each other and then serially connected to the charging inductor L1 between the input voltage Vin and the output voltage Vout to form a charging path. In a discharging process, the switches Q5-Q10 are turned on and the switches Q1-Q4 are turned off according to the discharging operation signal GB, so that the capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel and then connected in series with the discharging inductor L2, thereby forming a plurality of discharging paths.

It should be noted that the charging process and the discharging process are repeatedly performed alternately in different time periods, rather than simultaneously. The charging process and the discharging process are repeatedly interleaved to convert the input voltage Vin into the output voltage Vout. In the present embodiment, the dc bias voltage of each of the first capacitors C1, C2, and C3 is Vo, so that the first capacitors C1, C2, and C3 in the present embodiment only need to bear a lower rated voltage in the application of the same input voltage and output voltage compared to the prior art, and thus a capacitor with a smaller volume can be used.

In one embodiment, the charging resonant frequency of the charging process is the same as the discharging resonant frequency of the discharging process. In one embodiment, the charging resonant frequency of the charging process is different from the discharging resonant frequency of the discharging process. In one embodiment, the resonant switching power converter 30 may be a bidirectional resonant switching power converter. By bi-directional resonant switching power converter, it is meant that the roles of the input terminal (providing the input voltage Vin) and the output terminal (providing the output voltage Vout) are reversed, i.e. in the embodiment shown in fig. 3A, the resonant switching power converter 30 can convert the output voltage Vout into the input voltage Vin. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the resonant switching power converter 30 can be 4:1, 3:1 or 2:1.

In one embodiment, the duration (Ton 1) of the charging process is related to the charging resonant frequency (fr 1) of the charging process. In a preferred embodiment, the duration (Ton 1) of the charging process is related to the positive half-wave of the charging resonant current of the charging process, for example, the conducting time and the non-conducting time of the switches Q1-Q4 are substantially synchronous to the starting time and the ending time of a positive half-wave of a charging resonant current of the charging process. In one embodiment, the duration (Ton 2) of the discharging process is related to the discharging resonant frequency (fr 2) of the discharging process. In a preferred embodiment, the duration (Ton 2) of the discharging process is related to the positive half-wave of the discharging resonant current of the discharging process, such as the conducting time and the non-conducting time of the switches Q5-Q10 are substantially synchronous to the beginning time and the ending time of a positive half-wave of a discharging resonant current of the discharging process.

In an embodiment where the charging resonant frequency (fr 1) of the charging process is equal to the discharging resonant frequency (fr 2) of the discharging process, when the duration (Ton 1) of the charging process is equal to the duration (Ton 2) of the discharging process, for example, substantially equal to fifty percent of the duty cycle, the switching can be performed at a time point when the current flowing through the switch is relatively low in the positive half-wave thereof, so as to achieve the flexible switching. In a preferred embodiment, zero Current Switching (ZCS) is achieved.

Further, it should be noted that: since the parasitic effect of the circuit components or the matching between the components is not necessarily ideal, although the duration of the charging process is equal to the duration of the discharging process (i.e. the duration of the charging process is fifty percent of the duty cycle in this embodiment), the zero current switching of soft switching (soft switching) is achieved. However, it may not be exactly fifty percent duty cycle, but only close to fifty percent duty cycle, that is, it is acceptable according to the present invention that the duration of the charging process has a certain degree of error from the duration of the fifty percent duty cycle due to the non-ideality of the circuit, i.e., the aforementioned discharge to "substantially" fifty percent duty cycle, and the same applies to the other references to "substantially" herein.

In one embodiment, the duration of the charging process is less than a specific percentage of the duty cycle for a predetermined period, such as less than fifty percent of the duty cycle for a predetermined period; therefore, after the switches Q1 to Q4 are turned off in advance, a small current is still maintained and flows through the charging inductor L1, so that the accumulated charges stored in the parasitic capacitor of the switch Q10 can be taken away through the parasitic diode of the switch Q4, thereby reducing the voltage across the switch Q10 and achieving flexible switching. In a preferred embodiment, the level of the reference signal is adjusted to adjust the predetermined period to achieve Zero Voltage Switch (ZVS). In one embodiment, the duration of the discharge process is greater than a specific percentage of the duty cycle for a predetermined period, such as greater than fifty percent of the duty cycle for a predetermined period; therefore, after the switches Q5-Q10 are turned off, the negative current of the discharge inductor L2 charges the parasitic capacitance of the switch Q1 through the parasitic diode of the switch Q5, and the voltage across the switch Q1 is reduced, so as to achieve flexible switching. In a preferred embodiment, the level of the reference signal is adjusted to adjust the predetermined period to achieve zero voltage switching.

Fig. 3B is a circuit diagram of a resonant switching power converter according to an embodiment of the invention. The difference between the present embodiment and the embodiment of fig. 3A is that the present embodiment has a plurality of discharge processes. The controller 301 is configured to generate a charging operation signal GA and a plurality of discharging operation signals GB1, GB2, and GB3, respectively corresponding to a charging procedure and a three-discharging procedure, and operate the corresponding switches Q1-Q10 to switch the electrical connection relationship of the corresponding capacitors C1-C3. The zero current detection circuit 302 is coupled between the controller 301 and the output voltage Vout, and is configured to detect a charging resonant current IL1 at a node between the charging inductor L1 and the output voltage Vout during a charging process; or during each discharging process, a discharging resonant current IL2 at the node between the discharging inductor L2 and the output voltage Vout is detected. When the zero current detection circuit 302 detects that the charging resonant current IL1 or the discharging resonant current IL2 is zero, a zero current detection signal ZCD is generated to the controller 301, so that the controller 301 generates the charging operation signal GA and the discharging operation signals GB1, GB2, and GB3.

In one embodiment, the controller 301 may determine the start time and the end time of the charging process and the discharging process according to the zero current detection signal ZCD, the charging operation signal GA, and/or the discharging operation signals GB1, GB2, and GB3. The zero current detection circuit 302 may include a current sensing circuit 3021 for sensing the charging resonant current IL1 during the charging process or the discharging resonant current IL2 during the discharging process. The zero current detection circuit 302 may further include a comparator 3022 for comparing the sensed charging resonant current IL1 or discharging resonant current IL2 with a reference signal Vref1 to generate a zero current detection signal ZCD. The switch driver 303 is coupled between the controller 301 and the switches Q1 to Q10, and is used for controlling the switches Q1 to Q10 according to the charging operation signal GA or the discharging operation signal GB.

The switches Q1 to Q10 can switch the electrical connection relationship between the corresponding capacitors C1 to C3 and the charging inductor L1 and the discharging inductor L2 under the control of the switch driver 303 according to the charging operation signal GA and the discharging operation signals GB1, GB2 and GB3 generated by the controller 301. In one embodiment, the charging operation signal GA and the discharging operation signals GB1, GB2, and GB3 are respectively switched to an on level for an on period, and the on periods do not overlap each other.

For example, in a charging process, the switches Q1-Q4 are turned on and the switches Q5-Q10 are turned off according to the charging operation signal GA, so that the capacitors C1-C3 are serially connected to each other and then serially connected to the charging inductor L1 between the input voltage Vin and the output voltage Vout to form a charging path. In the first discharging procedure, according to the discharging operation signal GB1, the switches Q5 and Q8 are turned on, and the switches Q1 to Q4, Q6, Q7, Q9 and Q10 are turned off, so that the capacitor C1 is connected in series with the discharging inductor L2 to form a first discharging path. In the second discharging procedure, the switches Q6 and Q9 are turned on and the switches Q1 to Q4, Q5, Q7, Q8 and Q10 are turned off according to the discharging operation signal GB2, so that the capacitor C2 is connected in series with the discharging inductor L2 to form a second discharging path. In the third discharging procedure, according to the discharging operation signal GB3, the switches Q7 and Q10 are turned on, and the switches Q1 to Q4, Q5, Q6, Q8 and Q9 are turned off, so that the capacitor C3 is connected in series with the discharging inductor L2 to form a third discharging path.

It should be noted that the charging process and the first, second and third discharging processes are repeatedly performed alternately, not simultaneously, in different time periods. The charging process and the three discharging processes are alternately sequenced to convert the input voltage Vin to the output voltage Vout, that is, after one charging process is finished, the first discharging process, the second discharging process and the third discharging process are executed in turn, and then the charging process is executed, and so on.

Referring to fig. 4, a circuit diagram of a resonant switching power converter 40 according to another embodiment of the invention is shown. The configuration of the capacitors C1-C3, the charging inductor L1, the discharging inductor L2, the switches Q1-Q10, the zero current detection circuit 402, the current sensing circuit 4021, the comparator 4022, and the switch driver 403 in fig. 4 is similar to that in fig. 3A, and therefore, the description thereof is omitted. The present embodiment is different from the embodiment of fig. 3A in that the controller 401 of the present embodiment may include a logic circuit 4011, a decision circuit 4012, and a delay circuit 4013, and the decision circuit 4012 may include a first latch circuit 4012a and a second latch circuit 4012b.

In one embodiment, the delay circuit 4013 is optional. The logic circuit 4011 may be coupled to the zero current detection circuit 402 for generating a charge determination signal and a discharge determination signal according to the zero current detection signal and the charge operation signal GA and/or the discharge operation signal GB. In one embodiment, the charge determination signal can be used to determine a start time of the charge process and an end time of the discharge process. The logic circuit 4011, for example but not limited to, performs and logic operation on the zero current detection signal and the inverted signal of the charging operation signal GA to generate the charging determination signal. In one embodiment, the discharge determination signal can be used to determine a start time of the discharge process and an end time of the charge process. The logic circuit 4011, for example but not limited to, performs and logic operation on the zero current detection signal and the inverted signal of the discharge operation signal GB to generate the discharge determination signal. The decision circuit 4012 is coupled to the logic circuit 4011 for generating a charging operation signal GA and a discharging operation signal GB according to the charging determination signal and the discharging determination signal to determine a start time and an end time of the charging process and the discharging process, respectively. The delay circuit 4013 is coupled between the logic circuit 4011 and the decision circuit 4012 for delaying a start time of the charging process and/or the discharging process by a delay time, thereby reducing the switching frequency and adjusting the ratio of the input voltage Vin to the output voltage Vout.

For example, in the charging process, the charging operation signal GA is at a high level, and when the zero current detection signal ZCD of the zero current detection circuit 402 is switched to a high level, the logic circuit 4011 generates a high-level discharging determination signal according to the high-level charging operation signal GA and the high-level zero current detection signal ZCD, and outputs the high-level discharging determination signal to the decision circuit 4012, and the decision circuit 4012 generates a high-level discharging operation signal GB to be output to the switch driver 403, so that the switches Q5 to Q10 are turned on. On the other hand, the logic circuit 4011 generates a low-level charge determination signal according to a low-level inverted signal of the charge operation signal GA during the charge procedure. The decision circuit 4012 switches the charge operation signal GA to a low level according to the discharge determination signal with a high level and the charge determination signal with a low level, so that the switches Q1 to Q4 are not turned on, and the charging procedure is ended.

On the other hand, during the discharging process, the discharging operation signal GB is at a high level, and when the logic circuit 4011 receives the zero current detection signal ZCD from the zero current detection circuit 402 and switches to a high level, the logic circuit 4011 generates a high-level charging determination signal according to the discharging operation signal GB at the high level and the zero current detection signal ZCD at the high level at this time, so as to output the high-level charging determination signal to the decision circuit 4012, and the decision circuit 4012 generates a high-level charging operation signal GA, so as to output the high-level charging operation signal GA to the switch driver 403, so that the switches Q1 to Q4 are turned on. On the other hand, the logic circuit 4011 generates a low-level discharge determination signal according to a low-level inverted signal of the discharge operation signal GB during the discharge process. The decision circuit 4012 switches the discharging operation signal GB to a low level according to the charging determination signal at the high level and the discharging determination signal at the low level, so that the switches Q5 to Q10 are not turned on, and the discharging process is ended.

The first latch circuit 4012a is configured to set the charging operation signal GA according to the charging determination signal, switch the level of the charging operation signal GA according to the discharging determination signal, and generate an inverted signal of the charging operation signal GA to be input to the logic circuit 4011, for example, when the first latch circuit 4012a receives a high-level charging determination signal, the first latch circuit 4012a sets the charging operation signal GA to be at a high level, and generates an inverted signal of the low-level charging operation signal GA to be input to the logic circuit 4011. On the other hand, when the first latch circuit 4012a receives the discharge determination signal with a high level, the first latch circuit 4012a switches the level of the charge operation signal GA to a low level and generates an inverted signal of the charge operation signal with a high level to be input to the logic circuit 4011.

The second latch circuit 4012b is configured to set the discharging operation signal GB according to the discharging determination signal, switch the level of the discharging operation signal GB according to the charging determination signal, and generate an inverted signal of the discharging operation signal GB to be input to the logic circuit 4011, for example, when the second latch circuit 4012b receives the discharging determination signal of a high level, the second latch circuit 4012b sets the discharging operation signal GB to a high level, and generates an inverted signal of the discharging operation signal GB of a low level to be input to the logic circuit 4011. On the other hand, when the second latch circuit 4012b receives the charge determination signal with a high level, the second latch circuit 4012b switches the level of the discharge operation signal GB to a low level and generates an inverted signal of the discharge operation signal with a high level to be input to the logic circuit 4011.

Referring to fig. 5, a more detailed circuit diagram of a resonant switching power converter 50 according to another embodiment of the invention is shown. The configuration of the capacitors C1-C3, the charging inductor L1, the discharging inductor L2, the switches Q1-Q10, the zero current detection circuit 502, the current sensing circuit 5021, the comparator 5022 and the switch driver 503 in fig. 5 is similar to that in fig. 3A, and therefore, the description thereof is omitted. The difference between this embodiment and the embodiment of fig. 3A is that the controller 501 of this embodiment may include a logic circuit 5011, a decision circuit 5012, and a delay circuit 5013. The determining circuit 5012 may include a first latch circuit 5012a and a second latch circuit 5012b. Among other things, the delay circuit 5013 may include a delay unit 5013a and a delay unit 5013b.

In one embodiment, the delay circuit 5013 is optional. In the embodiment, the logic circuit 5011 may include a first and gate 5011a, a second and gate 5011b, and a not gate 5011c. The first and gate 5011a is coupled between the comparator 5022 and the first latch circuit 5012 a; the second and gate 5011b is coupled between the comparator 5022 and the second latch circuit 5012 b; the non-gate 5011c is coupled between the first latch circuit 5012a and the second and gate 5011b. In the decision circuit 5012, a first latch circuit 5012a is coupled between the first and gate 5011a and the corresponding switch driver 503, and a second latch circuit 5012b is coupled between the second and gate 5011b and the corresponding switch driver 503.

One mode of operation according to the present invention is illustrated in the embodiment shown in fig. 5. At the beginning of the charging process, the reset terminal R of the second latch circuit 5012b receives the high-level charging determination signal and resets the output terminal Q of the second latch circuit 5012b, so that the output terminal Q of the second latch circuit 5012b outputs the low-level discharging operation signal GB to turn off the switches Q5-Q10. During the charging process, the output terminal Q of the first latch circuit 5012a outputs the high-level charging operation signal GA to turn on the switches Q1-Q4. At this time, the not gate 5011c outputs the inverted output of the first latch circuit 5012a

The inverted signal (low level) of the outputted charging operation signal GA performs an inverse logic operation, generating a high level operation result, to be inputted to the second and gate 5011b. The second and gate 5011b holds the low level discharge determination signal until the zero current detection signal ZCD of the zero current detection circuit 502 detects that the charging resonant current IL1 decreases to zero current, and switches to high level (indicating the end of the charging process), and the operation result of the high level output from the not gate 5011c by the second and gate 5011b and the high level zero current detection signal ZCD perform and logic operation to generate a high level discharge determination signal to be output to the decision circuit 5012, so that the second latch circuit 5012b generates a high level discharge operation signal GB at its output terminal Q to be output to the switch driver 503, so that the switches Q5-Q10 are turned on, and the discharging process is started. In addition, the first latch circuit 50The reset terminal R of 12a receives the high discharge determination signal, and resets the output terminal Q of the first latch circuit 5012a, so that the output terminal Q generates the low charge operation signal GA for outputting to the switch driver 503, such that the switches Q1-Q4 are turned off, thereby ending the charging procedure.

On the other hand, at the beginning of the discharging procedure, the reset terminal R of the first latch circuit 5012a receives the discharging determination signal with high level, and resets the output terminal Q of the first latch circuit 5012a, so that the output terminal Q of the first latch circuit 5012a outputs the charging operation signal GA with low level to turn off the switches Q1-Q4. During the discharging process, the output terminal Q of the second latch circuit 5012b outputs the high-level discharging operation signal GB to turn on the switches Q5-Q10. At this time, the inverting output terminal of the first latch circuit 5012a

The inverted signal (high level) of the outputted charging operation signal GA is inputted to the first and gate 5011a. The first and gate 5011a keeps the low level charge determination signal until the zero current detection signal ZCD of the zero current detection circuit 502 detects that the discharge resonant current IL2 is reduced to zero current, and switches to high level (indicating the end of the discharge process), and the first and gate 5011a outputs the high level inverted output

The inverted signal of the output charging operation signal GA and the high-level zero-current detection signal ZCD are subjected to and logical operation to generate a high-level charging determination signal to be output to the decision circuit 5012, so that the first latch circuit 5012a generates a high-level charging operation signal GA at its output terminal Q to be output to the switch driver 503, so that the switches Q1 to Q4 are turned on to start the charging process. In addition, the reset terminal R of the second latch circuit 5012b receives the high-level charge determination signal, and resets the output terminal Q of the second latch circuit 5012b, so that the output terminal Q generates the low-level discharge operation signal GB to be output to the switch driver 503, such that the switches Q5-Q10 are turned off, thereby ending the discharge procedure.

The delay unit 5013a is coupled between the first and gate 5011a and the setting terminal S of the first latch circuit 5012a, and configured to delay the turn-on time of the switches Q1 to Q4 by a delay time, and delay the start time of the charging process by a delay time when all the corresponding switches Q1 to Q4 are turned off during the delay time. The delay unit 5013b is coupled between the second and gate 5011b and the set terminal S of the second latch circuit 5012b for delaying the turn-on time of the switches Q5-Q10 by a delay time, and delaying the start time of the discharging process by a delay time when all the corresponding switches Q5-Q10 are not turned on during the delay time.

In one embodiment, the inductance of L1 may be equal to the inductance of L2. In one embodiment, it is noted that a specific example of the inductance value of L1 being equal to the inductance value of L2 is that the charging inductor L1 and the discharging inductor L2 can share the same inductor and function as the charging inductor and the discharging inductor respectively at different times.

Therefore, referring to fig. 6, a circuit diagram of a resonant switching power converter 60 according to still another embodiment of the invention is shown. The configurations of the controller 601, the zero-current detection circuit 602, the current sensing circuit 6021, the comparator 6022 and the switch driver 603 in fig. 6 are similar to those in fig. 3A, and thus are not repeated. The difference between this embodiment and fig. 3A is that the charging inductor and the discharging inductor of this embodiment can be the same inductor L3, so that the number of inductors can be further reduced. As shown in fig. 6, the resonant switching power converter 60 of the present invention includes capacitors C1, C2, and C3, switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, and Q10, and an inductor L3. Switches Q1-Q3 are connected in series with corresponding capacitors C1-C3, respectively, and switch Q4 is connected in series with inductor L3. It should be noted that the number of capacitors in the resonant switching power converter of the present invention is not limited to three in the present embodiment, and may be two or more than four.

In the present embodiment, the charging inductor and the discharging inductor are a single same inductor L3, and in the discharging process, the switches Q1 to Q10 are switched to connect the capacitors C1 to C3 in parallel and then connect the same inductor L3 in series. The charging inductor and the discharging inductor are a single same inductor L3, which means that the charging resonant current and the discharging resonant current respectively flow through only one inductor L3 and do not flow through other inductor elements in the charging procedure and the discharging procedure.

As shown in fig. 6, one terminal of the switch Q5 is coupled to the node between the switch Q1 and the capacitor C1, one terminal of the switch Q6 is coupled to the node between the switch Q2 and the capacitor C2, and one terminal of the switch Q7 is coupled to the node between the switch Q3 and the capacitor C3. One terminal of the switch Q8 is coupled to the node between the capacitor C1 and the switch Q2, one terminal of the switch Q9 is coupled to the node between the capacitor C2 and the switch Q3, and one terminal of the switch Q10 is coupled to the node between the capacitor C3 and the switch Q4. As shown in FIG. 6, the other terminals of the switches Q5-Q7 are commonly connected to a node, and then coupled to the node between the switch Q4 and the inductor L3, and the other terminals of the switches Q8-Q10 are commonly coupled to the ground potential. The other end of the inductor L3 is coupled to the output voltage Vout, and the other end of the switch Q1 is coupled to the input voltage Vin.

The switches Q1-Q10 can switch the corresponding electrical connection relationship between the capacitors C1-C3 and the inductor L3 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 601 through the control of the switch driver 603. In a charging process, the switches Q1-Q4 are turned on and the switches Q5-Q10 are turned off according to the charging operation signal GA, so that the capacitors C1-C3 are connected in series with each other and then connected in series with the inductor L3 between the input voltage Vin and the output voltage Vout to form a charging path. In a discharging process, the switches Q5-Q10 are turned on and the switches Q1-Q4 are turned off according to the discharging operation signal GB, so that the capacitor C1, the capacitor C2 and the capacitor C3 are connected in parallel and then connected in series with the inductor L3, thereby forming a plurality of discharging paths. It should be noted that the charging process and the discharging process are repeatedly performed alternately in different time periods, rather than simultaneously. The charging process and the discharging process are repeatedly interleaved to convert the input voltage Vin into the output voltage Vout. In the present embodiment, the dc bias voltage of each of the first capacitors C1, C2, and C3 is Vo, so the first capacitors C1, C2, and C3 in the present embodiment need to withstand a lower rated voltage, and thus a capacitor with a smaller volume can be used.

In the present embodiment in which the charging inductor and the discharging inductor are set as a single same inductor L1, the ratio of the duration time (Ton 1) of the charging procedure and the duration time (Ton 2) of the discharging procedure can be configured appropriately, so as to achieve the zero current switching of the flexible switching. Specifically, in one embodiment, the duration of the charging process is substantially equal to twenty-five percent of the duty cycle; therefore, the switch can be switched at the time point when the current flowing through the switch is at a relatively low level of the positive half wave of the switch, so that flexible switching is realized. In a preferred embodiment, zero Current Switching (ZCS) is achieved. In an embodiment, the duration of the charging process is less than a specific percentage of the duty cycle for a predetermined period, for example, less than twenty-five percent of the duty cycle for a predetermined period; therefore, after the switches Q1 to Q4 are turned off in advance, a small current is still maintained and flows through the charging inductor L1, so that the accumulated charges stored in the parasitic capacitor of the switch Q10 can be taken away through the parasitic diode of the switch Q4, thereby reducing the voltage across the switch Q10 and achieving flexible switching.

In a preferred embodiment, the level of the reference signal is adjusted to adjust the predetermined period to achieve Zero Voltage Switch (ZVS). In one embodiment, the duration of the discharge process is greater than a specific percentage of the duty cycle for a predetermined period, for example, greater than seventy-five percent of the duty cycle for a predetermined period; therefore, after the switches Q5 to Q10 are turned off, the negative current of the discharging inductor L2 charges the parasitic capacitor of the switch Q1 through the parasitic diode of the switch Q5, and the voltage across the switch Q1 is reduced, so as to achieve flexible switching. In a preferred embodiment, the level of the reference signal is adjusted to adjust the predetermined period to achieve Zero Voltage Switch (ZVS).

In one embodiment, the resonant switching power converter 60 may be a bidirectional resonant switching power converter. In one embodiment, the voltage conversion ratio of the input voltage Vin to the output voltage Vout of the resonant switching power converter 60 can be 4:1, 3:1 or 2:1. In one embodiment, the voltage conversion ratio of the resonant switching power converter 60 can be flexibly adjusted, for example, the voltage conversion ratio of the resonant switching power converter 60 can be adjusted to 3:1 by selectively keeping the switch Q7 conductive and selectively keeping the switches Q10 and Q4 non-conductive during the charging process and the discharging process. Similarly, for example, if the switch Q6 is selectively kept on and the switches Q9, Q3, Q7, Q10, and Q4 are selectively kept off, the voltage conversion ratio of the resonant switching power converter 60 can be adjusted to 2:1.

Referring to fig. 7, a circuit 70 of a resonant switching power converter according to another embodiment of the invention is shown. The controller 701, the logic circuit 7011, the determining circuit 7012, the first latch circuit 7012a, the second latch circuit 7012b, the delay circuit 7013, the zero current detection circuit 702, the current sensing circuit 7021, the comparator 7022, and the switch driver 703 in fig. 7 are similar to fig. 4, and the capacitors C1 to C3, the switches Q1 to 10, and the inductor L3 in fig. 7 are similar to fig. 6, and therefore are not repeated. The present embodiment mainly applies the controller architecture in fig. 4 to a resonant switching power converter with a single inductor.

Referring to fig. 8A, a circuit 80 of a resonant switching power converter according to another embodiment of the invention is shown. The capacitors C1-C3, the switches Q1-10, and the inductor L3 in fig. 8A are similar to those in fig. 6, and therefore are not described again. The present embodiment applies the controller architecture in fig. 5 to a single-inductor resonant switching power converter. In addition, the controller 801 of the present embodiment may include a logic circuit 8011, a decision circuit 8012 and a delay circuit 8013. The determining circuit 8012 may include a first latch circuit 8012a and a second latch circuit 8012b. The delay circuit 8013 may include a delay unit 8013a and a delay unit 8013b.

In one embodiment, the delay circuit 8013 is optional. In this embodiment, the logic circuit 8011 may include a first and gate 8011a, a second and gate 8011b and a not gate 8011c. The first and gate 8011a is coupled between the comparator 8022 and the first latch circuit 8012 a; the second and gate 8011b is coupled between the comparator 8022 and the second latch circuit 8012 b; the not gate 8011c is coupled between the second latch circuit 8012b and the first and gate 8011a. In the determining circuit 8012, the first latch circuit 8012a is coupled between the first and gate 8011a and the corresponding switch driver 803, and the second latch circuit 8012b is coupled between the second and gate 8011b and the corresponding switch driver 803.

One mode of operation according to the present invention is illustrated in the embodiment shown in fig. 8A. At the beginning of the charging process, the reset terminal R of the second latch circuit 8012b receives the charging determination signal with a high level, and resets the output terminal Q of the second latch circuit 8012b, so that the output terminal Q of the second latch circuit 8012b outputs the discharging operation signal GB with a low level to turn off the switches Q5-Q10. During the charging process, the output terminal Q of the first latch circuit 8012a outputs the charging operation signal GA at a high level to turn on the switches Q1-Q4. At this time, the inverting output terminal of the second latch circuit 8012b

The inverted signal (high level) of the output discharge operation signal GB is input to the second and gate 8011b. The second and gate 8011b keeps the low level discharge determination signal until the zero current detection signal ZCD of the zero current detection circuit 802 detects that the charging resonant current IL1 is reduced to zero current, and switches to high level (indicating the end of the charging process), and the second and gate 8011b inverts the output terminal of the high level output terminal

The inverted signal of the output discharging operation signal GB and the high-level zero-current detection signal ZCD are subjected to and logical operation to generate a high-level discharging determination signal, which is output to the determining circuit 8012, so that the second latch circuit 8012b generates a high-level discharging operation signal GB at the output terminal Q thereof, which is output to the switch driver 803, so that the switches Q5 to Q10 are turned on, and a discharging process is started. In addition, the reset terminal R of the first latch circuit 8012a receives the high-level discharge determination signal, and resets the output terminal Q of the first latch circuit 8012a, so that the output terminal Q generates the low-level charge operation signal GA for being output to the switch driver 803, so that the switches Q1-Q4 are turned off, and the charge procedure is ended.

On the other hand, at the beginning of the discharging procedure, the reset terminal R of the first latch circuit 8012a receivesThe high level discharge determination signal resets the output Q of the first latch circuit 8012a, so that the output Q of the first latch circuit 8012a outputs the low level charge operation signal GA to turn off the switches Q1-Q4. During the discharging process, the output terminal Q of the second latch circuit 8012b outputs the discharging operation signal GB at a high level to turn on the switches Q5 to Q10. At this time, the not gate 8011c is coupled to the inverting output terminal of the second latch circuit 8012b

The inverted signal (low level) of the output discharging operation signal GB performs an inverted logic operation to generate a high level operation result, which is input to the first and gate 8011a. The first and gate 8011a keeps the low level charge determination signal until the zero current detection signal ZCD of the zero current detection circuit 802 detects that the discharge resonant current IL2 decreases to zero current, and switches to high level (indicating that the discharge process ends), and the operation result of the first and gate 8011a on the not gate 8011c at high level and the zero current detection signal ZCD at high level are logically operated to generate the high level charge determination signal to be output to the decision circuit 8012, so that the first latch circuit 8012a generates the high level charge operation signal GA at the output terminal Q thereof to be output to the switch driver 803, so that the switches Q1 to Q4 are turned on, and the charge process is started. In addition, the reset terminal R of the second latch circuit 8012b receives the high charging determination signal, and resets the output terminal Q of the second latch circuit 8012b, so that the output terminal Q generates the low discharging operation signal GB to be output to the switch driver 803, so that the switches Q5 to Q10 are turned off, and the discharging process is ended.

The delay unit 8013a is coupled between the first and gate 8011a and the setting end S of the first latch circuit 8012a, and is configured to delay the turn-on time of the switches Q1 to Q4 by a delay time, and delay the start time of the charging process by the delay time when all the corresponding switches Q1 to Q4 are turned off. The delay unit 8013b is coupled between the second and gate 8011b and the setting end S of the second latch circuit 8012b, and is configured to delay the turn-on time of the switches Q5-Q10 by a delay time, and delay the start time of the discharging process by a delay time when all the corresponding switches Q5-Q10 are turned off.

Fig. 8B is a schematic diagram showing signal waveforms of related signals in the resonant switching power converter shown in fig. 8A without the delay circuit 8013. Fig. 8B shows a charging resonant current/discharging resonant current (also referred to as inductor current) IL3, an input current Iin, a zero current detection signal ZCD, a charging operation signal GA, and a discharging operation signal GB. In the present embodiment, the duration of the charging process is approximately twenty-five percent of the duty cycle, and the duration of the discharging process is approximately seventy-five percent of the duty cycle. It should be noted that the inductor current IL3 sensed during the charging process is a charging resonant current, and the inductor current IL3 sensed during the discharging process is a discharging resonant current. As shown in fig. 8B, for example, each time the zero current detection signal ZCD generates the pulse signal, the charging operation signal GA and the discharging operation signal GB are triggered to switch the levels, so as to determine the start time and the end time of the charging process and the discharging process.

Fig. 9 is a circuit diagram of a resonant switching power converter 90 according to another embodiment of the invention. The configuration of the controller 901, the zero current detection circuit 902, the current sensing circuit 9021, the comparator 9022, the switch driver 903, the capacitors C1-C3, the switches Q1-Q10, the charging inductor L1, and the discharging inductor L2 in fig. 9 is similar to that in fig. 3A, and thus is not repeated. In this embodiment, the discharging procedure is divided into a plurality of discharging procedures, which are performed in different periods of time in turn, so that the discharging operation signal G2 is used to turn on the switches Q5 and Q8 and turn off the switches Q1 to Q4, Q6, Q7, Q9 and Q10, so as to discharge the capacitor C1 in a first period of time, the discharging operation signal G3 is used to turn on the switches Q6 and Q9 and turn off the switches Q1 to Q5, Q7, Q8 and Q10, so as to discharge the capacitor C2 in a second period of time, the discharging operation signal G4 is used to turn on the switches Q7 and Q10 and turn off the switches Q1 to Q6 and Q8 to Q9, so as to discharge the capacitor C3 in a third period of time, and the charging operation signal G1 is used to turn on the switches Q1 to Q4 and turn off the switches Q5 to Q10, so as to charge the capacitors C1 to C3. It should be appreciated that, in an embodiment, the controller 901 of the present embodiment may be alternatively implemented with the controller architecture of fig. 4 or fig. 5.

Referring to fig. 10, a circuit diagram of a resonant switching power converter 100 according to still another embodiment of the invention is shown. The controller 1001, the zero current detection circuit 1002, the current sensing circuit 10021, the comparator 10022, and the switch driver 1003 in fig. 10 are similar to those in fig. 3A, and are not repeated. As shown in fig. 10, the resonant switching power converter 100 of the present invention includes capacitors C1, C2, and C3, switches Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, and Q10, and inductors L1, L2, and L3. The switches Q1-Q3 are respectively connected in series with corresponding capacitors C1-C3, and the capacitors C1-C3 are respectively connected in series with corresponding inductors L1-L3. It should be noted that the number of capacitors in the resonant switching power converter of the present invention is not limited to three, but may also be two or more, and the number of inductors is not limited to three, or may also be two or more, and the number of elements shown in the present embodiment is only for illustration and is not intended to limit the present invention. It should be appreciated that, in an embodiment, the controller 1001 of the present embodiment may be implemented in place of the controller architecture of fig. 4 or fig. 5.

As shown in fig. 10, one terminal of the switch Q5 is coupled to the node between the switch Q1 and the capacitor C1, one terminal of the switch Q6 is coupled to the node between the switch Q2 and the capacitor C2, and one terminal of the switch Q7 is coupled to the node between the switch Q3 and the capacitor C3. One terminal of the switch Q8 is coupled to the node between the inductor L1 and the switch Q2, one terminal of the switch Q9 is coupled to the node between the inductor L2 and the switch Q3, and one terminal of the switch Q10 is coupled to the node between the inductor L3 and the switch Q4. As shown in FIG. 10, the other terminals of the switches Q5-Q7 are commonly coupled to the output voltage Vout. The other terminals of the switches Q8-Q10 are commonly coupled to ground potential. The switch Q4 is coupled between the inductor L3 and the output voltage Vout, and one end of the switch Q1 is coupled to the input voltage Vin.

The switches Q1 to Q10 can switch the electrical connection relationship between the corresponding capacitors C1 to C3 and the inductors L1 to L3 under the control of the switch driver 1003 according to the charging operation signal GA and the discharging operation signal GB generated by the controller 1001. In a charging process, the switches Q1-Q4 are turned on and the switches Q5-Q10 are turned off, so that the capacitors C1-C3 and the inductors L1-L3 are connected in series between the input voltage Vin and the output voltage Vout to form a charging path. In a discharging process, the switches Q5-Q10 are turned on, the switches Q1-Q4 are turned off, so that the capacitor C1 and the corresponding inductor L1 are connected in series between the output voltage Vout and the ground potential, the capacitor C2 and the corresponding inductor L2 are connected in series between the output voltage Vout and the ground potential, and the capacitor C3 and the corresponding inductor L3 are connected in series between the output voltage Vout and the ground potential, thereby forming a plurality of discharging paths. It should be noted that the charging process and the discharging process are performed alternately, not simultaneously. The charging process and the discharging process are repeatedly interleaved to convert the input voltage Vin into the output voltage Vout. In the present embodiment, the dc bias voltage of each of the capacitors C1, C2, and C3 is Vo, so the capacitors C1, C2, and C3 in the present embodiment need to withstand a lower rated voltage, and thus a capacitor with a smaller volume can be used.

In one embodiment, the duration of the charging process is substantially a duty cycle (duty cycle) of a specific ratio, such as, but not limited to, substantially fifty percent duty cycle; therefore, the switch can be switched at the time point when the current flowing through the switch is at a relatively low level of the positive half wave of the switch, so that flexible switching is realized. In a preferred embodiment, zero Current Switching (ZCS) is achieved.

In one embodiment, the specific ratio is related to the resonant frequency. In one embodiment, the charging process has a charging resonant frequency, and the discharging process has a discharging resonant frequency. In a preferred embodiment, the charging resonant frequency is the same as the discharging resonant frequency.

Fig. 11A is a signal waveform diagram illustrating corresponding operation signals and corresponding inductor currents of a charging process and a discharging process according to an embodiment of the invention. Referring to fig. 3A, in the embodiment shown in fig. 11A, the charging operation signal GA of the switches Q1 to Q4 is at a high level during the charging process, and the discharging operation signal GB of the switches Q5 to Q10 is at a high level during the discharging process. In the embodiment of FIG. 11A, the duration of the charging process is approximately fifty percent of the duty cycle; therefore, the switch Q1 can be switched when the current flowing through the switch is at a relatively low level in the positive half wave, and also when the charging inductor current IL1 of the charging inductor L1 is zero current, so as to realize flexible switching. In a preferred embodiment, zero current switching is achieved.

Fig. 11B and 11C are schematic signal waveforms illustrating corresponding operation signals and corresponding inductor currents of a charging process and a discharging process according to another embodiment of the invention. Referring to fig. 3A, in the embodiment shown in fig. 11B, the charging operation signal GA of the switches Q1 to Q4 is at a high level during the charging process, and the discharging operation signal GB of the switches Q5 to Q10 is at a high level during the discharging process. In the embodiment of fig. 11B, the reference signal may be adjusted high so that the duration of the charging process is substantially less than fifty percent of the duty cycle for a predetermined period T1; therefore, after the switches Q1-Q4 are turned off in advance, a small current is still maintained to flow through the charging inductor L1, so that the accumulated charges stored in the parasitic capacitor of the switch Q10 can be discharged through the parasitic diode of the switch Q4, thereby reducing the voltage across the switch Q10 and achieving flexible switching. In a preferred embodiment, the predetermined period T1 is adjusted to achieve zero voltage switching. Referring to fig. 3A, in the embodiment shown in fig. 11C, the charging operation signal GA of the switches Q1 to Q4 is at a high level during the charging process, and the discharging operation signal GB of the switches Q5 to Q10 is at a high level during the discharging process. In the embodiment of FIG. 11C, the reference signal may be adjusted low such that the duration of the discharge process is substantially greater than fifty percent of the duty cycle for a predetermined period T2+ T3; therefore, after the switches Q5 to Q10 are turned off, the negative current of the discharging inductor L2 charges the parasitic capacitor of the switch Q1 through the parasitic diode of the switch Q5, and the voltage across the switch Q1 is reduced, so as to achieve flexible switching. In a preferred embodiment, the predetermined periods T2 and T3 are adjusted to achieve zero voltage switching. In one embodiment, it should be noted that the embodiments of FIG. 11B and FIG. 11C may be implemented together or only one of them may be implemented.

The present invention provides a resonant switching power converter, which can reduce the number of inductors, mask the variation of elements due to dc bias or operating temperature, reduce the switching frequency to improve the efficiency under low load, support the output voltage regulation function, reduce the voltage stress, make all resonant capacitors have the same rated current and rated voltage, use smaller capacitors, can be dynamically controlled to achieve flexible switching with Zero Current Switching (ZCS) or Zero Voltage Switching (ZVS), have better dynamic load transient response, have better current-voltage balance, have stable resonant frequency, more flexibly modulate the voltage conversion ratio, and can operate bidirectionally, through a special circuit design.

It should be noted that the above mentioned "high level" and "low level" are only examples and are not intended to limit the scope of the present invention, and in other embodiments, the above mentioned "high level" and "low level" can be at least partially adjusted or exchanged according to the actually adopted switch type and logic base under the same spirit of the present invention.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of facilitating the understanding of the present invention by those skilled in the art, and is not intended to limit the broadest scope of the present invention. The embodiments described are not limited to single use, but may be used in combination, for example, two or more embodiments may be combined, and some components in one embodiment may be substituted for corresponding components in another embodiment. Further, equivalent variations and combinations are contemplated by those skilled in the art within the spirit of the present invention, and the term "processing or computing or generating an output result based on a signal" is not limited to the signal itself, and includes, if necessary, performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling on the signal, and then processing or computing the converted signal to generate an output result. It is understood that equivalent variations and combinations, not necessarily all illustrated, will occur to those of skill in the art, which combinations are not necessarily intended to be limiting. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above.

Claims

1. A resonant switching power converter for converting an input voltage to an output voltage, the resonant switching power converter comprising:

a plurality of capacitors;

a plurality of switches coupled to the plurality of capacitors;

at least one charging inductor which is correspondingly connected in series with at least one of the plurality of capacitors;

at least one discharge inductor connected in series with at least one of the capacitors;

a controller for generating a charging operation signal and at least one discharging operation signal to respectively correspond to a charging procedure and at least one discharging procedure, and operating the corresponding switches to switch the corresponding electrical connection relationship of the capacitor, wherein the controller comprises:

a logic circuit, coupled to the at least one zero current detection circuit, for generating a charging determination signal and a discharging determination signal according to the at least one zero current detection signal and the charging operation signal and/or the at least one discharging operation signal;

a decision circuit, coupled to the logic circuit, for generating the charging operation signal and the at least one discharging operation signal according to the charging determination signal and the discharging determination signal to determine respective starting time and ending time of the charging process and the at least one discharging process; and

a delay circuit, coupled between the logic circuit and the decision circuit, for delaying a delay time from the start time of the charging process and/or the at least one discharging process; and

at least one zero current detection circuit for detecting a charging resonant current flowing through the at least one charging inductor during the charging process and/or detecting at least one discharging resonant current flowing through the at least one discharging inductor during the discharging process, wherein at least one zero current detection signal is correspondingly generated to the controller when the at least one zero current detection circuit detects that the charging resonant current and/or the at least one discharging resonant current is zero;

wherein the charging operation signal and the discharging operation signal are respectively switched to a conducting level for a conducting period, and the conducting periods are not overlapped with each other, so that the charging process and the discharging process are not overlapped with each other;

wherein, in the charging procedure, the controller controls the switch of the switches through the charging operation signal, so that the capacitors and the at least one charging inductor are connected in series between the input voltage and the output voltage to form a charging path;

in the at least one discharging procedure, the controller controls the switching of the switches through the at least one discharging operation signal, so that each capacitor and the corresponding discharging inductor are connected in series between the output voltage and a ground potential, and a plurality of discharging paths are formed simultaneously or alternately;

wherein, the controller determines the respective starting time and ending time of the charging process and the discharging process according to the at least one zero current detection signal;

the charging process and the at least one discharging process are repeatedly and alternately sequenced to convert the input voltage into the output voltage.

2. The resonant switching power converter as claimed in claim 1, wherein the controller further determines a start time and an end time of the charging process and the at least one discharging process according to the charging operation signal and/or the at least one discharging operation signal.

3. The resonant switching power converter of claim 1, wherein the at least one zero current detection circuit comprises a current sensing circuit for sensing the charging resonant current during the charging process or the at least one discharging resonant current during the at least one discharging process to generate a current sensing signal; and a comparator for comparing the current sensing signal with a reference signal to generate the at least one zero current detection signal.

4. The resonant switching power converter of claim 3, further comprising a plurality of switch drivers respectively coupled between the controller and the corresponding switches for respectively controlling the switches according to the corresponding charging operation signal or the corresponding discharging operation signal.

5. The resonant switching power converter of claim 1, wherein the charge determination signal is used to determine a start time of the charging process and an end time of the at least one discharging process.

6. The resonant switching power converter as claimed in claim 5, wherein the logic circuit performs an AND operation on the at least one zero current detection signal and an inverted signal of the charging operation signal to generate the charging determination signal.

7. The resonant switching power converter as claimed in claim 6, wherein the determining circuit comprises a first latch circuit for setting the charging operation signal according to the charging determination signal, switching the level of the charging operation signal according to the discharging determination signal, and generating an inverted signal of the charging operation signal for input to the logic circuit.

8. The resonant switching power converter of claim 1, wherein the discharge determination signal is used to determine a start time of the at least one discharge process and an end time of the charge process.

9. The resonant switching power converter of claim 8, wherein the logic circuit performs an and logic operation on the at least one zero current detection signal and an inverted signal of the at least one discharge operation signal to generate the discharge determination signal.

10. The resonant switching power converter as claimed in claim 9, wherein the determining circuit comprises a second latch circuit for setting the at least one discharging operation signal according to the discharging determination signal, switching a level of the at least one discharging operation signal according to the charging determination signal, and generating an inverted signal of the at least one discharging operation signal to be input to the logic circuit.

11. The resonant switching power converter of claim 1, wherein the at least one charging inductor is a single charging inductor and the at least one discharging inductor is a single discharging inductor.

12. The resonant switching power converter of claim 11, wherein the inductance of the single charging inductor is equal to the inductance of the single discharging inductor.

13. The resonant switching power converter of claim 1, wherein the at least one charging inductor and the at least one discharging inductor are a single same inductor.

14. The resonant switching power converter of claim 13, wherein the single identical inductor is a variable inductor.

15. The resonant switching power converter according to claim 1 or 11, wherein the charging procedure has a charging resonant frequency, and the at least one discharging procedure has a discharging resonant frequency, and the charging resonant frequency is the same as the discharging resonant frequency.

16. The resonant switching power converter of claim 1, 11, 12 or 13, wherein the charging process has a charging resonant frequency and the at least one discharging process has a discharging resonant frequency, and the charging resonant frequency is different from the discharging resonant frequency.

17. The resonant switching power converter of claim 3, wherein the level of the reference signal is adjusted to adjust the duration of the charging process to achieve soft switching of zero-voltage switching.

18. The resonant switching power converter of claim 3, wherein the level of the reference signal is adjusted to adjust the duration of the at least one discharging process to achieve soft switching zero voltage switching.

19. The resonant switching power converter of claim 1, 11, 12 or 13, wherein the resonant switching power converter is a bidirectional resonant switching power converter.

20. The resonant switching power converter of claim 1, 11, 12 or 13, wherein a voltage conversion ratio of the input voltage to the output voltage of the resonant switching power converter is 4:1, 3:1 or 2:1.

21. The resonant switching power converter as claimed in claim 1, wherein the delay time is delayed after the time point when the at least one zero current detection circuit generates the at least one zero current detection signal when the at least one zero current detection circuit detects that the charging resonant current is zero, and the discharging operation signal is switched at the end of the delay time to perform the at least one discharging procedure.

22. The resonant switching power converter as claimed in claim 1, wherein the delay time is delayed after the time point when the at least one zero current detection circuit generates the at least one zero current detection signal when the at least one zero current detection circuit detects that the discharging resonant current is zero, and the charging operation signal is switched at the end of the delay time to perform the charging process.