CN113379021A - Reconfigurable NFC coprocessor - Google Patents
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- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
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- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
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Abstract
The invention belongs to the technical field of integrated circuit design, and particularly relates to a reconfigurable NFC coprocessor. The reconfigurable NFC coprocessor is composed of a reconfigurable processing core, a sequence controller, a memory and a control/state register. And the reconfigurable processing core realizes the baseband processing specified by the NFC protocol according to the configuration information and the control information generated by the sequence controller. The NFC antenna comprises a protocol controller, a transceiver controller, an encoding module, a decoding module, a frame synthesis module, a frame analysis module, a selection unit, a merging and exiting unit, a serial-in and parallel-out unit, a receiving preprocessing unit and a variable rate unit, wherein the selection unit is used for determining a baseband processing mode specified by an NFC protocol. The reconfigurable processing core and the sequence controller jointly realize an NFC protocol.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, particularly relates to a reconfigurable NFC coprocessor, and particularly relates to a method for realizing baseband processing specified by an NFC protocol by using a reconfigurable processing core through configuration and control.
Background
NFC (Near Field Communication) was developed by philips semiconductors, nokia, and sony, and is based on RFID (Radio Frequency Identification) and interconnection technology. It is a high frequency, short range radio technology using a 13.56MHz carrier frequency for near field communication over a distance of 10 cm. In recent years, progress has been made in establishing systems using NFC chips in various fields. As an alternative to the conventional smart card, the NFC chip is used in various fields such as identification and mobile payment.
The operating modes of NFC are divided into three types: Reader/Writer mode (Reader/Writer), Card Emulation mode (Card Emulation), and Peer-to-Peer mode (Peer-to-Peer). Two communication modes, namely active communication mode and passive communication mode are adopted. Generally, the three modes need to be realized by combining software and hardware, the hardware realizes a bottom layer protocol, and the software realizes a high layer protocol, so as to meet the compatibility and integration of NFC. Generally, the Activity of NFC adopts a software implementation method to flexibly process NFC multiple communication protocols. It has a drawback that it is difficult to achieve a good balance between power consumption and performance. In order to take performance into account, the CPU needs to run at full power, but the power consumption is large; to account for power consumption, the CPU requires low power operation, but impacts performance. Thus, Activity needs to consider hardware implementation without losing the flexibility of the processing of multiple communication protocols.
Disclosure of Invention
In view of the above, the present invention provides a reconfigurable NFC coprocessor to balance the requirements of flexibility, power consumption and performance. If the modules with the same function are combined into a new general module for cost saving, the advantages of reducing power consumption and saving space can be achieved. The invention adopts a general architecture and configuration control to realize the processing of the NFC multi-communication protocol, and can achieve better balance between flexibility, power consumption and performance.
The invention provides a reconfigurable NFC coprocessor, which comprises:
the reconfigurable processing core is used for flexibly configuring and controlling different protocol information to complete various communication protocols;
a sequence controller for generating configuration information and control information of the reconfigurable processing core in real time;
a memory for storing data and instruction sequences required by the NFC protocol;
a control register for starting, terminating and resetting the NFC coprocessor;
a status register for generating a processing status and an interrupt;
the reconfigurable processing core comprises a protocol controller, a transceiver controller, an encoding module, a decoding module, a frame synthesis module, a frame analysis module, a plurality of selection units, a merging-in-and-out unit, a serial-in-and-parallel-out unit, a receiving preprocessing unit and a variable rate unit. The protocol controller is used for executing the Activity required by the NFC protocol, namely polling identification, conflict negotiation, device activation, data exchange, device failure and state conversion; the receiving and transmitting controller is used for executing transmitting, receiving and timing required by the NFC protocol; the encoding module is used for realizing improved Miller/Manchester/non-return-to-zero/Pulse Position Modulation (PPM) encoding of the signal; the decoding module is used for realizing improved Miller/Manchester/non-return-to-zero/Pulse Position Modulation (PPM) decoding of the signal; the frame synthesis module is used for realizing the NFC-A/B/F/V frame synthesis of the signal; the frame analysis module is used for realizing the NFC-A/B/F/V frame analysis of the signal; a selection unit for realizing connection selection of reconfigurable processing; the parallel-in serial-out unit is composed of a shift register and is used for realizing parallel-serial conversion of the transmitted data; the serial-in parallel-out unit is composed of a shift register and is used for realizing serial-parallel conversion of received data; the receiving preprocessing unit is used for realizing preprocessing of received signals; and the variable rate unit is used for controlling the transmission of different baud rates in real time.
The coding module consists of an improved Miller coding unit, a Manchester coding unit, a non-return-to-zero coding unit and a pulse position modulation coding unit. The improved Miller coding unit is used for realizing signal coding of an NFC-A polling mode; the Manchester coding unit is provided with a subcarrier and no subcarrier, and the subcarrier is used for realizing signal coding of 106 Kbaud rate in an NFC-A monitoring mode and signal coding in an NFC-V monitoring mode; no subcarrier is used for realizing signal coding of NFC-F; the non-return-to-zero coding unit is provided with a subcarrier and no subcarrier, and the subcarrier is used for realizing signal coding of a non-106 Kbaud rate in an NFC-A monitoring mode and signal coding in an NFC-B monitoring mode; signal encoding without subcarriers for implementing NFC-B polling mode; and the pulse position modulation coding unit is used for realizing signal coding of the NFC-V polling mode.
The decoding module consists of an improved Miller decoding unit, a Manchester decoding unit, a non-return-to-zero decoding unit and a pulse position modulation decoding unit. The improved Miller decoding unit is used for realizing signal decoding in an NFC-A monitoring mode; the Manchester decoding unit is provided with a subcarrier and no subcarrier, and the subcarrier is used for realizing signal decoding of an NFC-A polling mode with a 106 Kbaud rate and signal decoding of an NFC-V polling mode; no subcarrier is used for realizing signal decoding of NFC-F; the non-return-to-zero decoding unit is provided with subcarriers and no subcarriers, and the subcarriers are used for realizing signal decoding of a non-106 Kbaud rate in an NFC-A polling mode and signal decoding of an NFC-B polling mode; no subcarrier is used for signal decoding in the NFC-B monitoring mode; and the pulse position modulation decoding unit is used for realizing signal decoding in an NFC-V monitoring mode.
The frame synthesis module consists of an NFC-A frame synthesis unit, an NFC-B frame synthesis unit, an NFC-F frame synthesis unit and an NFC-V frame synthesis unit. The NFC-A frame synthesis unit is used for realizing signal synthesis of an NFC-A frame format and comprises a frame start, a parity check, a CRC16 check and a frame end; the NFC-B frame synthesis unit is used for realizing signal synthesis of an NFC-B frame format and comprises a frame start, a start bit, a stop bit, CRC16 verification and a frame end; the NFC-F frame synthesis unit is used for realizing signal synthesis of an NFC-F frame format and comprises a preamble, a frame start and CRC16 verification; and the NFC-V frame synthesis unit is used for realizing signal synthesis of an NFC-V frame format and comprises a frame start, CRC16 check and a frame end.
The frame analysis module consists of an NFC-A frame analysis unit, an NFC-B frame analysis unit, an NFC-F frame analysis unit and an NFC-V frame analysis unit. The NFC-A frame analysis unit is used for realizing signal analysis of the NFC-A frame format, and comprises a frame start, a parity check, a CRC16 check, a frame end and checking whether the format and the check are correct or not; the NFC-B frame analysis unit is used for realizing signal analysis of the NFC-B frame format, and comprises a frame start, a start bit, a stop bit, CRC16 verification, frame ending, and checking whether the format and the verification are correct; the NFC-F frame analysis unit is used for realizing signal analysis of the NFC-F frame format, and comprises a preamble, a frame start, CRC16 verification and checking whether the format and the verification are correct; and the NFC-V frame analysis unit is used for realizing signal analysis of the NFC-V frame format, and comprises frame start, CRC16 check, frame end, and checking whether the format and the check are correct.
The frame synthesis module and the coding module may implement different protocol transmission through different connection combinations, for example: the combination of the NFC-A frame synthesis unit and the improved Miller coding unit can realize data transmission in an NFC-A polling mode; the combination of the NFC-F frame synthesis unit and the Manchester coding unit without subcarriers can realize data transmission of NFC-F.
The decoding module and the frame parsing module may implement different protocol receiving through different connection combinations, for example: the combination of the non-return-to-zero decoding unit without the subcarrier and the NFC-B frame analysis unit can realize data reception in an NFC-B monitoring mode; the data reception in the NFC-V polling mode can be realized by combining the Manchester decoding unit with the subcarrier and the NFC-V frame analyzing unit;
the transceiver controller comprises a transmission control unit, a receiving control unit and a timing control unit. The sending control unit is used for realizing data sending specified by an NFC protocol; a receiving control unit for realizing data receiving specified by NFC protocol; and the timing control unit is used for realizing the timing between the two events.
The protocol controller comprises a state conversion unit, a polling identification unit, a conflict negotiation unit, a device activation unit, a data exchange unit and a device invalidation unit. The state conversion unit is used for realizing a state machine of T3T/T4T card simulation and Target; the polling identification unit is used for realizing scanning detection on the NFC-ACM/A/B/F/V device; the conflict negotiation unit is used for realizing the conflict negotiation of the NFC-A/B/F/V; the device activation unit is used for activating the NFC-ACM/A/B/F device; the data exchange unit is used for realizing an NFC-ACM/A/B/F/V data exchange protocol; and the device failure unit is used for failing the NFC-ACM/A/B/F device.
The selection unit is arranged between or in each component module of the reconfigurable processing core and is used for selecting the configuration information and the control information generated by the sequence controller.
The sequence controller includes an instruction parsing unit and a memory access unit. The instruction analysis unit is used for generating configuration information and control information of the reconfigurable processing core; and the memory access unit is used for reading instructions and data from the memory and writing data to the memory.
The sending data is input from the merging and stringing-out unit and sequentially enters the frame synthesis unit and the coding module; the received data sequentially enters a decoding module, a frame analysis unit and a serial-in and parallel-out unit through a receiving preprocessing unit;
the configuration information is generated by the sequence controller and is transmitted to an encoding module, a decoding module, a frame synthesis module, a frame analysis module, a variable rate unit, a receiving and transmitting controller and a protocol controller in the reconfigurable processing core, and is used for determining a baseband processing mode specified by the NFC protocol; the NFC protocol is jointly realized by analyzing instructions by the sequence controller and executing Activity by the protocol controller.
The invention is characterized in that: firstly, an NFC coprocessor supporting multiple communication protocols is realized in a reconfigurable mode, the mode is multiplexing on the basis of a basic transceiving structure, and hardware consumption is saved to the maximum extent; secondly, the reconfigurable processing core can configure a plurality of communication protocols under the action of configuration information generated by the sequence controller so as to realize different protocol processing; thirdly, any communication protocol can be decomposed into a basic transceiving structure, the decomposition process is given in real time by control information, and the reconfigurable processing core is controlled to establish the basic transceiving structure according to the decomposition steps so as to gradually complete protocol processing; fourthly, the control of the basic transceiving structure is divided into an external control part and an internal control part which are respectively realized by a sequence controller and a protocol controller, thereby improving the flexibility of the processing of the NFC multi-communication protocol.
Drawings
Fig. 1 is a functional block diagram of an NFC coprocessor.
Fig. 2 is a schematic diagram of a state transition unit.
Detailed Description
Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a functional block diagram of an NFC coprocessor of the present invention. The reconfigurable processing core 101 configures various communication protocols in real time under the configuration information and the control information generated by the sequence controller 102 to realize the required NFC baseband processing. Reconfigurable processing core 101 is composed of a protocol controller 103, a transceiver controller 104, a variable rate unit 105, a parallel-in serial-out unit 106, a serial-in parallel-out unit 107, a frame synthesis module 108, a frame parsing module 109, an encoding module 110, a decoding module 111, a reception preprocessing unit 112, and a plurality of selection units.
The protocol controller 103 includes a polling identification unit 113, a collision negotiation unit 114, a device activation unit 115, a data exchange unit 116, a device deactivation unit 117, and a state transition unit 118. The protocol controller implements the various required baseband processing. The polling identification unit 113 can scan five types of NFC devices to identify the NFC technologies used by the devices: NFC-ACM/A/B/F/V and the like; the collision negotiation unit 114 can realize four classes of anti-collision functions of NFC-a/B/F/V (note that the NFC-ACM device has no anti-collision), the NFC-a anti-collision adopts a bit frame anti-collision loop (bit frame anti-collision) mechanism, and the NFC-B/F/V anti-collision adopts a time slot (time slot) anti-collision method; the device activation unit 115 may implement activation of four types of NFC devices (note that the NFC-V device has been activated at the time of collision negotiation), so that it may perform data exchange; the data exchange unit 116 may implement six NFC data exchange protocols: NFC-DEP (NFC-ACM/A/F), ISO-DEP (NFC-A/B), T1T (NFC-A), T2T (NFC-A), T3T (NFC-F), T5T (NFC-V); the device failure unit 117 may implement three device failures: NFC-DEP (NFC-ACM/A/F), ISO-DEP (NFC-A/B), T2T (NFC-A); the state transition unit 118 may implement three listening state machine functions: T3T (NFC-F), ISO-DEP (NFC-A/B), NFC-DEP (NFC-ACM/A/F), namely T3T/T4T card simulation, Target state machine.
The transceiver controller 104 includes a transmission control unit, a reception control unit, and a timing control unit. The sending control unit is used for realizing data sending specified by an NFC protocol; a receiving control unit for realizing data receiving specified by NFC protocol; and the timing control unit is used for realizing the timing between the two events.
A variable rate unit 105 for controlling the transmission of different baud rates in real time.
The merge/exit unit 106 is formed of a shift register, and is configured to perform parallel/serial conversion of transmission data.
The serial-in parallel-out unit 107 is formed of a shift register, and is configured to perform serial-to-parallel conversion of received data.
The frame synthesis module 108 is composed of an NFC-a frame synthesis unit, an NFC-B frame synthesis unit, an NFC-F frame synthesis unit, and an NFC-V frame synthesis unit. The NFC-A frame synthesis unit is used for realizing signal synthesis of an NFC-A frame format and comprises a frame start, a parity check, a CRC16 check and a frame end; the NFC-B frame synthesis unit is used for realizing signal synthesis of an NFC-B frame format and comprises a frame start, a start bit, a stop bit, CRC16 verification and a frame end; the NFC-F frame synthesis unit is used for realizing signal synthesis of an NFC-F frame format and comprises a preamble, a frame start and CRC16 verification; and the NFC-V frame synthesis unit is used for realizing signal synthesis of an NFC-V frame format and comprises a frame start, CRC16 check and a frame end.
The frame parsing module 109 is composed of an NFC-a frame parsing unit, an NFC-B frame parsing unit, an NFC-F frame parsing unit, and an NFC-V frame parsing unit. The NFC-A frame analysis unit is used for realizing signal analysis of the NFC-A frame format, and comprises a frame start, a parity check, a CRC16 check, a frame end and checking whether the format and the check are correct or not; the NFC-B frame analysis unit is used for realizing signal analysis of the NFC-B frame format, and comprises a frame start, a start bit, a stop bit, CRC16 verification, frame ending, and checking whether the format and the verification are correct; the NFC-F frame analysis unit is used for realizing signal analysis of the NFC-F frame format, and comprises a preamble, a frame start, CRC16 verification and checking whether the format and the verification are correct; and the NFC-V frame analysis unit is used for realizing signal analysis of the NFC-V frame format, and comprises frame start, CRC16 check, frame end, and checking whether the format and the check are correct.
The encoding module 110 is composed of a modified miller encoding unit, a manchester encoding unit, a non-return-to-zero encoding unit, and a pulse position modulation encoding unit. The improved Miller coding unit is used for realizing signal coding of an NFC-A polling mode; the Manchester coding unit is provided with a subcarrier and no subcarrier, and the subcarrier is used for realizing signal coding of 106 Kbaud rate in an NFC-A monitoring mode and signal coding in an NFC-V monitoring mode; no subcarrier is used for realizing signal coding of NFC-F; the non-return-to-zero coding unit is provided with a subcarrier and no subcarrier, and the subcarrier is used for realizing signal coding of a non-106 Kbaud rate in an NFC-A monitoring mode and signal coding in an NFC-B monitoring mode; signal encoding without subcarriers for implementing NFC-B polling mode; and the pulse position modulation coding unit is used for realizing signal coding of the NFC-V polling mode.
The decoding module 111 is composed of a modified miller decoding unit, a manchester decoding unit, a non-return-to-zero decoding unit and a pulse position modulation decoding unit. The improved Miller decoding unit is used for realizing signal decoding in an NFC-A monitoring mode; the Manchester decoding unit is provided with a subcarrier and no subcarrier, and the subcarrier is used for realizing signal decoding of an NFC-A polling mode with a 106 Kbaud rate and signal decoding of an NFC-V polling mode; no subcarrier is used for realizing signal decoding of NFC-F; the non-return-to-zero decoding unit is provided with subcarriers and no subcarriers, and the subcarriers are used for realizing signal decoding of a non-106 Kbaud rate in an NFC-A polling mode and signal decoding of an NFC-B polling mode; no subcarrier is used for signal decoding in the NFC-B monitoring mode; and the pulse position modulation decoding unit is used for realizing signal decoding in an NFC-V monitoring mode.
And a receiving preprocessing unit 112, configured to implement preprocessing of the received signal.
The selection unit is arranged between or in each component module of the reconfigurable processing core and is used for selecting the configuration information and the control information generated by the sequence controller.
The configuration control of the reconfigurable processing core transceiving structure comprises transceiving control among all components of the reconfigurable processing core transceiving structure and working modes and circuit connection in all the components, and the configuration control is divided into external transceiving control directly configured by a sequence controller and internal transceiving control configured by a protocol controller, and the two types of transceiving control are realized by different instructions. The instructions of the sequence controller comprise configuration instructions, jump instructions, comparison instructions, sending instructions, receiving instructions, transceiving instructions, timing instructions, field-on instructions, field-off instructions, assignment instructions and composite instructions (polling identification, conflict negotiation, device activation, data exchange, device failure and state conversion).
Fig. 2 is a schematic diagram of the state transition unit 118. The state transition unit comprises a command parser 201 and a listening state machine 202. The command parser 201 parses the NFC-a/B/F polling command, and the listening state machine 202 performs state transition according to the NFC-a/B/F polling command. The NFC-A state comprises IDLE, READY _ A, ACTIVE _ A, SLEEP _ A, READY _ A*、ACTIVE_A*And CARD _ EMULATOR _4A, ATR _ READY _ A, TARGET _ A. The NFC-B state includes IDLE, READY _ B _ REQU, READY _ B _ DECL, SLEEP _ B, CARD _ EMULATOR _ 4B. The NFC-F states include IDLE, READY _ F, SLEEP _ AF, CARD _ EMULATOR _3, ATR _ READY _ F, TARGET _ F. The NFC-a command includes ALL _ REQ, SENS _ REQ, SDD _ REQ, SEL _ REQ, SLP _ REQ, RATS, ATR _ REQ, PSL _ REQ, DEP _ REQ, DSL _ REQ, RLS _ REQ, DESELECT. The NFC-B commands include ALLB _ REQ, SENSB _ REQ, SLOT _ MARKER, SLPB _ REQ, ATTRIB, DESLECT. The NFC-F command includes SENSF _ REQ, ATR _ REQ, PSL _ REQ, DEP _ REQ, DSL _ REQ, RLS _ REQ, and CUP (T3T command).
Finally, it should be noted that: although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that: modifications and equivalents may be made thereto without departing from the spirit and scope of the invention and it is intended to cover in the claims the invention any modifications or partial substitutions.
Claims (8)
1. A reconfigurable NFC coprocessor, comprising:
the reconfigurable processing core is used for realizing the baseband processing specified by the NFC protocol;
a sequence controller for generating configuration information and control information of the reconfigurable processing core;
a memory for storing data and instruction sequences required by the NFC protocol;
a control register for starting, terminating and resetting the NFC coprocessor;
a status register for generating a processing status and an interrupt;
wherein, the reconfigurable processing core comprises:
a protocol controller for executing the Activity required by the NFC protocol, namely polling identification, conflict negotiation, device activation, data exchange, device failure and state conversion;
a transceiver controller for executing the transmission, reception and timing required by the NFC protocol;
a coding module for implementing improved Miller/Manchester/non-return-to-zero/Pulse Position Modulation (PPM) coding of the signal;
a decoding module for implementing improved Miller/Manchester/non-return-to-zero/Pulse Position Modulation (PPM) decoding of the signal;
the frame synthesis module is used for realizing the NFC-A/B/F/V frame synthesis of the signal;
the frame analysis module is used for realizing the NFC-A/B/F/V frame analysis of the signal;
a plurality of selection units for realizing connection selection of reconfigurable processing;
a parallel-serial-out unit for realizing parallel-serial conversion of signals;
a serial-in parallel-out unit for performing serial-to-parallel conversion of the signal;
a receiving preprocessing unit for preprocessing the received signal;
a variable rate unit for implementing different baud rate transmissions;
the sending data is input from the merging and serial-out unit and sequentially enters the frame synthesis module and the coding module; the received data sequentially enters a decoding module, a frame analysis module and a serial-in and parallel-out unit through a receiving preprocessing unit;
the configuration information is generated by the sequence controller and is transmitted to an encoding module, a decoding module, a frame synthesis module, a frame analysis module, a variable rate unit, a receiving and transmitting controller and a protocol controller in the reconfigurable processing core, and is used for determining a baseband processing mode specified by the NFC protocol; the NFC protocol is jointly realized by analyzing instructions by the sequence controller and executing Activity by the protocol controller.
2. The reconfigurable NFC coprocessor of claim 1, wherein the encoding module is comprised of a plurality of encoding units, each of which is:
the improved Miller coding unit is used for realizing signal coding of an NFC-A polling mode;
the Manchester coding unit is provided with a subcarrier and no subcarrier, and the subcarrier is used for realizing signal coding of 106 Kbaud rate in an NFC-A monitoring mode and signal coding in an NFC-V monitoring mode; no subcarrier is used for realizing signal coding of NFC-F;
the non-return-to-zero coding unit is provided with subcarriers and no subcarriers, and the subcarriers are used for realizing signal coding of a non-106 Kbaud rate in an NFC-A monitoring mode and signal coding in an NFC-B monitoring mode; signal encoding without subcarriers for implementing NFC-B polling mode;
and the pulse position modulation coding unit is used for realizing signal coding of the NFC-V polling mode.
3. The reconfigurable NFC coprocessor according to claim 1, wherein said decoding module is composed of a plurality of decoding units, each of which is:
the improved Miller decoding unit is used for realizing signal decoding in an NFC-A listening mode;
a Manchester decoding unit which is provided with a subcarrier and no subcarrier, wherein the subcarrier is used for realizing signal decoding of 106 Kbaud rate in an NFC-A polling mode and signal decoding in an NFC-V polling mode; no subcarrier is used for realizing signal decoding of NFC-F;
the non-return-to-zero decoding unit is provided with subcarriers and no subcarriers, and the subcarriers are used for realizing signal decoding of a non-106 Kbaud rate in an NFC-A polling mode and signal decoding of an NFC-B polling mode; no subcarrier is used for signal decoding in the NFC-B monitoring mode;
and the pulse position modulation decoding unit is used for realizing signal decoding in the NFC-V monitoring mode.
4. The reconfigurable NFC coprocessor according to claim 1, wherein said frame synthesis module is composed of a plurality of frame synthesis units, each of which is:
an NFC-A frame synthesis unit, which is used for realizing signal synthesis of an NFC-A frame format and comprises a frame start, a parity check, a CRC16 check and a frame end;
an NFC-B frame synthesis unit, which is used for realizing signal synthesis of an NFC-B frame format and comprises a frame start, a start bit, a stop bit, CRC16 verification and a frame end;
an NFC-F frame synthesis unit, which is used for realizing signal synthesis of an NFC-F frame format and comprises a preamble, a frame start and CRC16 verification;
and the NFC-V frame synthesis unit is used for realizing signal synthesis of an NFC-V frame format and comprises a frame start, a CRC16 check and a frame end.
5. The reconfigurable NFC coprocessor according to claim 1, wherein said frame parsing module is composed of a plurality of frame parsing units, each of which is:
an NFC-A frame analysis unit, which is used for realizing signal analysis of the NFC-A frame format, including frame start, parity check, CRC16 check, frame end, and checking whether the format and the check are correct;
an NFC-B frame analysis unit, which is used for realizing signal analysis of the NFC-B frame format and comprises a frame start, a start bit, a stop bit, CRC16 verification, frame end and checking whether the format and the verification are correct;
an NFC-F frame analysis unit, which is used for realizing signal analysis of the NFC-F frame format, including preamble, frame start, CRC16 check, and checking whether the format and check are correct;
and the NFC-V frame analysis unit is used for realizing signal analysis of the NFC-V frame format, and comprises frame start, CRC16 check, frame end, and checking whether the format and the check are correct.
6. A reconfigurable NFC coprocessor according to claim 1, wherein said transceiver controller comprises:
a transmission control unit for realizing data transmission specified by the NFC protocol;
a receiving control unit for realizing data receiving specified by NFC protocol;
and the timing control unit is used for realizing the timing between the two events.
7. The reconfigurable NFC coprocessor of claim 1, wherein said protocol controller comprises:
a state conversion unit for realizing T3T/T4T card simulation and Target state machine;
the polling identification unit is used for realizing scanning detection on the NFC-ACM/A/B/F/V device;
a conflict negotiation unit for implementing conflict negotiation of NFC-A/B/F/V;
a device activation unit for activating the NFC-ACM/A/B/F device;
a data exchange unit for implementing NFC-ACM/A/B/F/V data exchange protocol;
and the device failure unit is used for failing the NFC-ACM/A/B/F device.
8. A reconfigurable NFC coprocessor according to claim 1, wherein said sequence controller comprises:
an instruction parsing unit for generating configuration information and control information of the reconfigurable processing core;
and the memory access unit is used for reading instructions and data from the memory and writing data to the memory.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110616631.6A CN113379021A (en) | 2021-06-03 | 2021-06-03 | Reconfigurable NFC coprocessor |
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| CN202110616631.6A CN113379021A (en) | 2021-06-03 | 2021-06-03 | Reconfigurable NFC coprocessor |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101031901A (en) * | 2004-07-08 | 2007-09-05 | 阿苏克斯有限公司 | Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards |
| CN101136070A (en) * | 2007-10-18 | 2008-03-05 | 复旦大学 | Multiple protocol radio frequency label read-write machine baseband processor based on reconstruction structure |
| CN103077365A (en) * | 2012-12-28 | 2013-05-01 | 广州中大微电子有限公司 | RFID (radio frequency identification) reader compatible with Type A protocol and Type B protocol |
| CN104079327A (en) * | 2014-04-28 | 2014-10-01 | 天津安普德科技有限公司 | Reconfigurable system-on-chip chip for Bluetooth, WiFi and NFC |
| CN104680214A (en) * | 2015-03-13 | 2015-06-03 | 江苏物联网研究发展中心 | Digital baseband system of multi-protocol UHF RFID (ultrahigh-frequency radio-frequency identification) reader |
| CN105574456A (en) * | 2015-12-14 | 2016-05-11 | 谭焕玲 | RIFD reader |
-
2021
- 2021-06-03 CN CN202110616631.6A patent/CN113379021A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101031901A (en) * | 2004-07-08 | 2007-09-05 | 阿苏克斯有限公司 | Low-power reconfigurable architecture for simultaneous implementation of distinct communication standards |
| CN101136070A (en) * | 2007-10-18 | 2008-03-05 | 复旦大学 | Multiple protocol radio frequency label read-write machine baseband processor based on reconstruction structure |
| CN103077365A (en) * | 2012-12-28 | 2013-05-01 | 广州中大微电子有限公司 | RFID (radio frequency identification) reader compatible with Type A protocol and Type B protocol |
| CN104079327A (en) * | 2014-04-28 | 2014-10-01 | 天津安普德科技有限公司 | Reconfigurable system-on-chip chip for Bluetooth, WiFi and NFC |
| CN104680214A (en) * | 2015-03-13 | 2015-06-03 | 江苏物联网研究发展中心 | Digital baseband system of multi-protocol UHF RFID (ultrahigh-frequency radio-frequency identification) reader |
| CN105574456A (en) * | 2015-12-14 | 2016-05-11 | 谭焕玲 | RIFD reader |
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