CN113014252A

CN113014252A - Phase adjustment circuit, control method and measurement method

Info

Publication number: CN113014252A
Application number: CN202110191723.4A
Authority: CN
Inventors: 陈建文
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2016-11-11
Filing date: 2016-11-11
Publication date: 2021-06-22
Also published as: CN108075774A; CN108075774B

Abstract

A phase adjusting circuit, a control method and a measuring method are provided, wherein the control method is suitable for a phase interpolator which is used for generating output signals based on current distribution proportion. The control method comprises the following steps: selecting a first input pair and a second input pair from a phase interpolator; sequentially switching a plurality of currents related to the current distribution proportion from flowing through the first input pair to flowing through the second input pair so as to adjust the phase of the output signal to correspond to a first phase interval; and after the plurality of currents all flow through the second input pair, selecting the second input pair and the third input pair from the phase interpolator, and adjusting the current distribution proportion to adjust the phase of the output signal to correspond to the second phase interval.

Description

Phase adjustment circuit, control method and measurement method

The present application is a divisional application of the chinese invention patent application with the application number CN201610996946.7 and the title "phase adjustment method, control method and measurement method".

Technical Field

The present disclosure relates to an integrated circuit, and more particularly, to a phase rotator, a control method thereof, and a measurement method of a phase interpolator.

Background

In the prior art, the phase interpolator is configured to determine the phase of the output signal according to at least one clock signal and a current sharing ratio. The aforementioned current sharing ratio is generally determined by a plurality of switches. However, in the conventional method, during the switching of the switches, pulses are generated on the rising or falling edges of the output signal, thereby reducing the smoothness and accuracy of the phase switching of the output signal. In addition, when the phase switching pitch of the output signal is small, the above-mentioned pulse makes it difficult to measure the phase change of the output signal.

Disclosure of Invention

In order to solve the above problem, an embodiment of the present disclosure provides a control method for a phase interpolator, the phase interpolator is configured to generate an output signal based on a current distribution ratio, and the control method includes: selecting a first input pair and a second input pair from a phase interpolator; sequentially switching a plurality of currents related to the current distribution proportion from flowing through the first input pair to flowing through the second input pair so as to adjust the phase of the output signal to correspond to the first phase interval; and after the currents all flow through the second input pair, selecting the second input pair and the third input pair from the phase interpolator, and adjusting the current distribution proportion to adjust the phase of the output signal to correspond to a second phase interval, wherein the first phase interval and the second phase interval are continuous.

Another embodiment of the present disclosure provides a phase adjustment circuit, which includes a phase interpolator and a phase rotator. The phase interpolator is used for generating an output signal based on the current distribution ratio and comprises a plurality of input pairs. The phase rotator is used for selecting a first input pair and a second input pair from the input pairs. The phase rotator is further used for sequentially switching a plurality of currents related to the current distribution ratio from flowing through the first input pair to flowing through the second input pair so as to adjust the phase of the output signal to correspond to the first phase interval. After the currents all flow through the second input pair, the phase rotator is further used for selecting the second input pair and a third input pair from the plurality of input pairs, and adjusting the current distribution ratio to adjust the phase of the output signal to correspond to a second phase interval, wherein the first phase interval and the second phase interval are continuous.

Another embodiment of the present disclosure provides a measuring method for measuring an output signal of a phase interpolator, wherein the phase interpolator is configured to generate the output signal based on a plurality of clock signals and at least one current, and the measuring method comprises: switching the current share ratio of the phase interpolator back and forth between the initial ratio and a first ratio to generate a first jitter signal component, wherein the phase interpolator is used for determining the phase of the output signal based on the current share ratio; switching the current sharing ratio back and forth between the initial ratio and a second ratio to generate a second dither signal component; measuring the output signal to analyze a first total phase noise energy associated with the first dither signal component and a second total phase noise energy associated with the second dither signal component in the output signal; and determining whether a change in phase is linear based on the first phase noise total energy and the second phase noise total energy.

Drawings

FIG. 1A is a schematic diagram of a phase adjustment circuit according to some embodiments;

FIG. 1B is a schematic diagram of a plurality of clock signals of FIG. 1A according to some embodiments;

FIG. 1C is a circuit schematic of the phase interpolator of FIG. 1A, according to some embodiments;

FIG. 2 is a flow chart illustrating a control method according to some embodiments;

FIG. 3 is a diagram illustrating switching of multiple signal values of the multiple select signals and the switching signal of FIG. 1C according to some embodiments;

FIG. 4A is a schematic diagram illustrating a phase interpolator according to further embodiments of the present disclosure;

FIG. 4B is a flow diagram illustrating a measurement method for measuring the phase interpolator of FIG. 4B in accordance with some embodiments;

FIG. 5A is a switching diagram illustrating the operation of the method of FIG. 4B with respect to the signal values of the select signals and the switching signal of FIG. 1C according to some embodiments;

FIG. 5B is a graph illustrating measured frequency spectra corresponding to the switching pattern of FIG. 5A, in accordance with some embodiments of the present disclosure; and

FIG. 5C is a switching diagram illustrating a method of operating the method of FIG. 4B with a plurality of signal values of the plurality of select signals and the switching signal of FIG. 1C according to some other embodiments of the present disclosure.

Description of reference numerals:

100A: phase adjustment circuits 120, 400: phase interpolator

100: phase rotators SELAb to SELDb: selection signal

SELA-SELD: selection signals CLKAb to CLKDb: clock signal

CLKA to CLKD: clock signals VO, VO 1-VO 2: output signal

VS: switching signals Ab to Db: falling edge

A to D: rising edge 124, 420: output circuit

Phi 1-phi 8: phase interval SWAb to SWDb: switch with a switch body

122 to 123, 410: input circuits 122A to 122D: input pair

SWA to SWb: switches 123A to 123D: input pair

SW 1-SW 2: switch N2: second end

N1: first ends M1-M16: transistor with a metal gate electrode

126: current source circuit In: electric current

200: the control method 400A: measuring method

S210 to S240: the operation 500: frequency spectrum

S410 to S440: operations 502-503: side frequency band

501: main single-frequency CK: clock signal

430: switching circuit

Detailed Description

Referring to fig. 1A, the phase adjustment circuit 100A includes a phase rotator 100 and a phase rotator 120. The phase interpolator 120 is coupled to the phase rotator 100 to receive a plurality of selection signals SELA-SELD and SELAb-SELDb and a switching signal VS. The phase interpolator 120 generates the output signal VO1 and the output signal VO2 according to a plurality of sets of clock signals (CLKA, CLKAb) - (CLKD, CLKDb), wherein a phase difference between each set of clock signals is about 180 degrees, for example, a phase difference between the clock signal CLKA and the clock signal CLKAb is about 180 degrees.

In some embodiments, the phase interpolator 120 adjusts the phases of the output signal VO1 and the output signal VO2 according to the selection signals SELA-SELD and SELAb-SELDb and the switching signal VS. In some embodiments, the plurality of selection signals SELA-SELD and SELAb-SELDb are binary codes.

Referring to FIG. 1B, in some embodiments, the clock signals CLKA through CLKD are phase-shifted with respect to each other to define a plurality of consecutive phase intervals φ 1 through φ 8.

For example, as shown in FIG. 1B, a phase interval φ 1 exists between the rising edge A of the clock signal CLKA and the rising edge B of the clock signal CLKB. A phase interval φ 2 exists between the rising edge B of the clock signal CLKB and the rising edge C of the clock signal CLKC. A phase interval φ 3 exists between the rising edge C of the clock signal CLKC and the rising edge D of the clock signal CLKD. A phase interval φ 4 exists between the rising edge D of the clock signal CLKD and the falling edge Ab of the clock signal CLKA.

A phase interval φ 5 exists between the falling edge Ab of the clock signal CLKA and the falling edge Bb of the clock signal CLKB. A phase interval φ 6 exists between the falling edge Bb of the clock signal CLKB and the falling edge Cb of the clock signal CLKC. A phase interval φ 7 exists between the falling edge Cb of the clock signal CLKC and the falling edge Db of the clock signal CLKD. A phase interval φ 8 exists between the falling edge Db of the clock signal CLKD and the rising edge A of the clock signal CLKA.

In some embodiments, the phase interpolator 120 adjusts the phases of the output signal VO1 and the output signal VO2 to corresponding ones of a plurality of phase intervals φ 1- φ 8 according to the plurality of selection signals SELA-SELD and SELAb-SELDb and the switching signal VS. The relevant operation here will be explained with reference to fig. 2 described later.

Referring to FIG. 1C, in some embodiments, the phase interpolator 120 includes a plurality of input circuits 122-123, an output circuit 124, a plurality of switches SWA-SWD, SWAb-SWDb, SW 1-SW 2, and a current source circuit 126.

The input circuit 122 includes a plurality of input pairs 122A-122D corresponding to two sets of clock signals (CLKA, CLKAb) and clock signals (CLKC, CLKCb).

In some embodiments, the input pair 122A includes a transistor M1 and a transistor M2. A first terminal of the transistor M1 is coupled to the first terminal N1 of the output circuit 124, a second terminal of the transistor M1 is coupled to the first terminal of the switch SWA, and a control terminal of the transistor M1 receives the clock signal CLKA. A first terminal of the transistor M2 is coupled to the second terminal N2 of the output circuit 124, a second terminal of the transistor M2 is coupled to the first terminal of the switch SWA, and a control terminal of the transistor M2 receives the clock signal CLKAb.

In some embodiments, the input pair 122B includes a plurality of transistors M3-M4. A first terminal of the transistor M3 is coupled to the first terminal N1 of the output circuit 124, a second terminal of the transistor M3 is coupled to the first terminal of the switch SWAb, and a control terminal of the transistor M3 receives the clock signal CLKAb. A first terminal of the transistor M4 is coupled to the second terminal N2 of the output circuit 124, a second terminal of the transistor M4 is coupled to the first terminal of the switch SWAb, and a control terminal of the transistor M4 receives the clock signal CLKA.

A second terminal of the switch SWA is coupled to first terminals of the plurality of switches SW1, and a control terminal of the switch SWA receives the selection signal SELA. The switch SWA is set to be turned on according to the selection signal SELA, so that a plurality of currents In generated by the current source circuit 126 flow through the input pair 122A. A second terminal of the switch SWAb is coupled to first terminals of the plurality of switches SW2, and a control terminal of the switch SWAb receives the selection signal SELAb. The switch SWAb is set to be turned on according to a selection signal SELAb so that a plurality of currents In generated by the current source circuit 126 flow through the input pair 122B.

In some embodiments, the input pair 122C includes a plurality of transistors M5-M6, and the input pair 122D includes a plurality of transistors M7-M8. The arrangement of the transistors M5-M8, the switches SWC and SWCb, the selection signals SELC and SELCb, and the current source circuit 126 is similar to the arrangement of the input pairs 122A-122B, and thus, the description thereof is not repeated.

In some embodiments, the input circuit 123 includes a plurality of input pairs 123A-123D configured to correspond to two sets of clock signals (CLKB, CLKBb) and clock signals (CLKD, CLKDb).

In some embodiments, the input pair 123A includes a plurality of transistors M9-M10, the input pair 123B includes a plurality of transistors M11-M12, the input pair 123C includes a plurality of transistors M13-M14, and the input pair 123D includes a plurality of transistors M15-M16. The arrangement of the transistors M9-M16, the switches SWB, SWBb, SWD, and SWDb, the selection signals SELB, SELBb, SELD, and SELDb, and the current source circuit 126 is similar to the arrangement of the input circuit 122, and therefore, the description thereof is not repeated.

In some embodiments, the output circuit 124 operates as a load. The first terminal N1 of the output circuit 124 is configured to generate the output signal VO1, and the second terminal N2 of the output circuit 124 is configured to generate the output signal VO 2. In some embodiments, the output circuit 124 is configured to provide at least one active load to the input circuit 122 and the input circuit 123. The current source circuit 126 includes a plurality of current sources to generate a plurality of currents In, respectively. In some embodiments, the plurality of current sources may be implemented by one or more current mirror circuits.

The second terminals of the switches SW1 and SW2 are coupled to the current sources of the current source circuit 126, respectively. The control terminals of the switches SW1 and SW2 respectively receive the signal values of the switching signal VS, and are selectively turned on according to the signal values of the switching signal VS. For example, when the signal values of the switching signal VS are logic values 0, the switches SW1 are turned on, and the switches SW2 are turned off. Accordingly, the entire current In flows through the input circuit 122. Alternatively, when the signal values of the switching signal VS are logic values 1, the switches SW2 are turned on, and the switches SW1 are turned off. Accordingly, the entire current In flows through the input circuit 123. It should be noted that, although the embodiment takes the case that all the current In flows through the input circuit 122 or the input circuit 123 as an example, the disclosure is not limited thereto, and a part of the current In may also be designed to flow through the input circuit 122 or the input circuit 123. In some embodiments, switches SW1 and SW2 are configured to distribute the current through the input pairs 122A-122D and 123A-123D according to a determined ratio.

With the above arrangement, the phase interpolator 120 can adjust the phases of the output signal VO1 and the output signal VO2 according to the plurality of selection signals SELA to SELD and SELAb to SELDb and the current distribution ratio. For example, when the select signal SELA and the select signal SELB are logic 1, representing that the input pair 122A and the input pair 123 are selected, the phase interpolator 120 adjusts the phases of the output signal VO1 and the output signal VO2 to the phase interval φ 1.

The above-described arrangement of the phase interpolator 120 is merely an example. Various types of phase interpolators 120 are within the scope of the present disclosure.

Referring to fig. 2 and 3, the operation of the phase rotator 100 of fig. 1A will be described along with the control method 200 of fig. 2 and the signal states of fig. 3. In some embodiments, the control method 200 includes a plurality of operations S210, S220, S230, and S240.

In operation S210, the phase rotator 100 outputs a plurality of selection signals SELA and SELB having a logic value 1, and outputs a plurality of selection signals SELC to SELD and SELAb to SELDb having a logic value 0. Under this condition, the switches SWA and SWB are turned on, and the switches SWC, SWD, and SWAb to SWDb are turned off. Accordingly, the input pairs 122A and 123A are selected, and the start interval of the phases of the output signals VO1 and VO2 is determined as the phase interval Φ 1.

In operation S220, the phase rotator 100 sequentially switches the signal values of the control signal VS from logic values 0 to logic values 1 so that the phase interpolator 120 determines the phases of the output signals VO1 and VO2 in response to the clock signals CLKA and CLKB.

For the example of fig. 1C, as mentioned above, when the signal value of the switching signal VS is logic 0, the corresponding switch SW1 is turned on, and the corresponding switch SW2 is turned off. On the contrary, when the signal value of the switching signal VS is logic 1, the corresponding switch SW1 is turned off, and the corresponding switch SW2 is turned on. When the values of the switching signal VS are all logic values 0, all the switches SW1 are turned on, and all the switches SW2 are turned off. Under this condition, all the current In flows through the input pair 122A via the conducting switch SWA. Accordingly, the phases of the output signals VO1 and VO2 are adjusted to approximately correspond to the phase of the clock signal CLKA. When the signal values of the switching signal VS are sequentially switched from logic values 0 to logic values 1, the switches SW1 are sequentially turned off, and the switches SW2 are sequentially turned on. Under this condition, a plurality of currents In sequentially become to flow through the input pair 123A via the switch SWB. Accordingly, the phases of the output signals VO1 and VO2 are adjusted toward the phase of the clock signal CLKB. When all of the switches SW2 are turned on and all of the switches SW1 are turned off, all of the current In flows through the input pair 123A. Under this condition, the phases of the output signals VO1 and VO2 are adjusted to approximately correspond to the phase of the clock signal CLKB.

Equivalently, the phase interpolator 120 determines the phases of the output signals VO 1-VO 2 according to different current sharing ratios between the phase intervals Φ 1 through operations S210 and S220.

With continued reference to fig. 2, In operation S230, after all the current In flows through the input pair 123A, the phase rotator 100 outputs the selection signal SELA having a logic value 0 and the selection signal SELC having a logic value 1, so that the phases of the output signals VO1 and VO2 are set to correspond to the phase interval Φ 2. In operation S240, the phase rotator 100 sequentially switches the signal values of the switching signal VS from logic values 1 to logic values 0, so that the phase interpolator 120 determines the phases of the output signals VO1 and VO2 in response to the clock signals CLKB and CLKC.

For example, as shown in FIG. 3, when the phase interval φ 1 is switched to the phase interval φ 2, the signal values of the switching signal VS first stay at the logic values 1. Thus, the entire current In continues to flow through the input circuit 123. Then, the phase rotator 100 outputs the selection signal SELC having a logic value 1 to turn on the switch SWC. Meanwhile, the phase rotator 100 outputs a selection signal SELA having a logic value 0 to turn off the switch SWA. Next, the phase rotator 100 sequentially switches the signal values of the switching signal VS from logic values 1 to logic values 0. Under this condition, the plurality of currents In are sequentially switched to flow through the input pair 122C via the conducting switch SWC. Accordingly, the phases of the output signals VO1 and VO2 are adjusted toward the phase of the clock signal CLKC. When all of the switches SW1 are turned on and all of the switches SW2 are turned off, all of the current In flows to the input pair 122C. Under this condition, the phases of the output signals VO1 and VO2 are adjusted to approximately correspond to the phase of the clock signal CLKC. Through the above operations, equivalently, the phase rotator 100 determines the phases of the output signals VO1 through VO2 according to different current sharing ratios between the phase intervals Φ 2.

In some related art, when the phase of the output signal is rotated, the phase interpolator is set to simultaneously select the corresponding input pair when a plurality of switches (e.g., switches SW1 and SW2) controlling the current distribution ratio are switched. In this way, during a transient state In which the switches are switched simultaneously, a plurality of currents (e.g., the current In) associated with the current sharing ratio flow through the unselected input pairs, and pulse the rising or falling edge of the output signal. Thus, the smoothness of the edge switching of the output signal is reduced.

Compared to the related art, through the operation of the control method 200, when the phase of the output signal VO1 or VO2 is to be rotated, the phase interpolator 120 turns on a corresponding one of the switches SELA to SELD or SELAb to SELDb after the switching states of the switches SW1 and SW2 determining the current sharing ratio are determined (i.e., all switches SW1 are set to be on and all switches SW2 are off or all switches SW1 are set to be off and all switches SW2 are on), so as to select a corresponding one of the input pairs 122A to 122D or 123A to 123D to complete the phase interval switching. Therefore, the influence of the pulses on the rising or falling edges of the output signals VO1 and VO2 during the switching of the switches and the switching of the phase intervals can be reduced, so as to improve the smoothness of the phase switching of the output signals VO1 and VO 2.

The above description is only for the continuous phase interval Φ 1 and the continuous phase interval Φ 2, but the disclosure is not limited thereto. The above operation can also be applied to the phase intervals φ 2- φ 8, and thus the description thereof is not repeated herein.

In some embodiments, to increase the switching speed of the phase, in the aforementioned operation S220, the phase rotator 100 is configured to sequentially switch the signal values of the switching signal VS according to the first switching step. In some embodiments, the switching step is defined as the magnitude of the digital code jittered by a plurality of signal values of the switching signal VS at each switching. For example, as shown in fig. 3, in some embodiments, the signal values of the switching signal VS are encoded in a thermometer code manner, and the first switching step is 32. As shown in fig. 3, since the first switching step is 32, the previous encoding of the signal values of the switching signal VS is "111101111" before all are switched to logic value 1.

In other embodiments, the phase rotator 100 is configured to sequentially switch the signal values of the switching signal VS in batches according to a second switching step, and the second switching step is smaller than the first switching step. In the previous example, the second switching step may be changed to 16, and the phase rotator 100 may switch the plurality of signal values of the switching signal VS in two batches. Compared with using a larger switching step, the smaller switching step is used to switch the switching signal VS in batches, so that the influence of pulse or jitter (jitter) signal components on the rising or falling edges of the output signals VO1 and VO2 during switching of a plurality of switches can be further reduced. Therefore, the smoothness of the phase switching of the output signals VO1 and VO2 can be further improved.

The above mentioned coding modes, the signal values of the switching signal VS and the values of the switching steps are only examples. Various types of encoding schemes and various values of the switching steps are all within the scope of the present disclosure. In addition, in some embodiments, at different switching steps, during the adjustment of the output signals VO 1-VO 2, the switching signal VS with a specific code can be temporarily stopped to reduce the pulse caused by the switching.

In some embodiments, the phase rotator 100 may be implemented by one or more integrated circuits that perform the control method 200. For example, the control method 200 may be implemented as a state machine, and the phase rotator 100 may be implemented by at least one digital circuit corresponding to the state machine. In still other embodiments, the phase rotator 100 may be implemented by a processing unit executing the method 200. In various embodiments, the processing unit may be a central processing unit, a micro control unit, a microprocessor, a digital signal processor, an application specific integrated circuit, or a logic circuit. The above are merely examples, and various phase rotators 100 capable of executing the control method 200 are all within the scope of the disclosure.

Referring to fig. 4A, phase interpolator 400 includes an input circuit 410, an output circuit 420, and a switching circuit 430. In some embodiments, the input circuit 410 includes at least one input pair configured to generate the output signal VO (e.g., the output signal VO1 or VO2 of fig. 1C) in response to a current sharing ratio and at least one clock signal CK (e.g., CLKA-CLKD of fig. 1C). In some embodiments, the input circuit 410 is configured in a manner similar to the input circuits 122-123 of FIG. 1C. The output circuit 420 is coupled to the input circuit 410 and is used for generating the output signal VO in cooperation with the input circuit 410. In some embodiments, the output circuit 420 is configured in a manner similar to the input circuit 124 of FIG. 1C.

The switching circuit 430 is coupled between the input circuit 410 and the current source circuit 440, and is used for determining the current sharing ratio. In some embodiments, the switching circuit 430 is configured in a manner similar to the switches SW 1-SW 2 and the current source circuit 126 of FIG. 1C. For example, as described previously, when the number of signal values having a logic value 0 In the switching signal VS In fig. 1C is more, the current In flowing through the input circuit 122 is more. Conversely, the less the plurality of signal values having a logic value 0, the less the current In flows through the input circuit 122. In other words, the current distribution ratio can be determined by a plurality of signal values of the switching signal VS. In a further embodiment, the switch circuit 430 may further include a plurality of switches (e.g., the switches SWA-SWD, SWAb-SWDb in fig. 1C) for selecting the corresponding phase intervals.

As mentioned above, when the switches of the phase interpolator are switched simultaneously, a pulse is generated on the rising or falling edge of the output signal. In other words, in some embodiments, the jitter signal component (i.e., the aforementioned pulse) may be generated in the output signal generated by the phase interpolator 400 by switching the on states of the switches in the circuit 430.

Referring to fig. 4B, the measurement method 400A includes a plurality of operations S410, S420, S430, and S440.

In operation S410, the current share ratio of the phase interpolator 400 is toggled between the initial ratio and the first ratio to generate a first wobble signal component.

In operation S420, the current share ratio is switched back and forth between the initial ratio and the second ratio to generate a second wobble signal component.

In operation S430, the output signal is measured to analyze a first total phase noise energy associated with the first dither signal component and a second total phase noise energy associated with the second dither signal component in the output signal.

In operation S440, it is determined whether the change of the phase of the output signal is linear based on the first phase noise total energy and the second phase noise total energy.

As mentioned above, when the switches of the phase interpolator are switched simultaneously, a pulse is generated on the rising or falling edge of the output signal. In other words, in some embodiments, the linearity of the phase change of the output signal can be measured by generating a jitter signal component (i.e., the aforementioned pulse) on the output signal. In some embodiments, the measurement method 400A may be used to measure the phase change of the phase interpolator 400 in a single phase interval. In other embodiments, the measurement method 400A may be used to measure the phase change of the phase interpolator 400 between different phase regions.

For ease of understanding, the operation of measurement method 400A will be described below with phase interpolator 400 in conjunction with the specific circuit example shown in FIG. 1C and FIG. 5A. For the example shown in fig. 5A, a plurality of selection signals SELA and SELB have a logic value 1, and the other selection signals SELC, SELD, and SELAb to SELDb have a logic value 0. Accordingly, the phases of the output signals VO 1-VO 2 are mapped to a single phase interval φ 1. As mentioned above, the current sharing ratio can be determined by a plurality of signal values of the switching signal VS. In this example, the initial ratio of the current distribution ratio corresponds to a plurality of signal values "000000000" (which can be regarded as a plurality of initial values of the switching signal VS) of the switching signal VS, and the first ratio corresponds to a plurality of signal values "000011111" (which can be regarded as a plurality of first signal values of the switching signal VS). Therefore, in operation S410, the signal values of the switching signal VS are switched back and forth between "000000000" and "000011111" to generate the first wobble signal component on the output signals VO1 VO 2.

Similarly, in this example, the second ratio of the current distribution ratio corresponds to a plurality of signal values "111111111" of the switching signal VS (which can also be regarded as a plurality of second signal values of the switching signal VS). In operation S420, the signal values of the switching signal VS are toggled between "000000000" and "111111111" to generate the second wobble signal components on the output signals VO 1-VO 2.

Referring to fig. 5B, fig. 5B is a diagram illustrating a frequency spectrum 500 of the output signal VO1 and/or the output signal VO2 generated by the phase interpolator 120 based on the operation shown in fig. 5A. The first dither signal component and the energy distribution can be known by spectral analysis. For example, in some embodiments, the total energy of the first phase noise associated with the first dither signal component may be observed by summing the amplitude values of the dominant single frequency (tone)501 and its side bands (side bands) 502-503 of the frequency spectrum 500. In some embodiments, the total phase noise energy is a harmonic frequency in the side band within a predetermined bandwidth and a ratio between a sum of the noise power and the power of the main tone. In various embodiments, the predetermined bandwidth and the range of the side bands can be adjusted according to actual requirements.

In some embodiments, the phase change of the output signals VO 1-VO 2 may be determined to be linear when the total energy of the second phase noise associated with the second dither signal component is greater than the total energy of the first phase noise associated with the first dither signal component. For the example of fig. 1C, the plurality of switches SW 1-SW 2 are switched more than they are switched in operation S420 than in operation S410. Accordingly, more pulses are generated during the switching of the switches SW 1-SW 2. Therefore, if the phase change of the output signals VO 1-VO 2 is linear, the total energy of the second phase noise should be theoretically larger than the first dither signal component. Accordingly, by performing the spectrum analysis of fig. 5B, the total energy of the first phase noise associated with the first wobble signal component and the total energy of the second phase noise associated with the second wobble signal component can be measured to determine whether the phase adjustments of the first ratio and the second ratio of the output signals VO 1-VO 2 in the single phase interval Φ 1 are linear.

In other embodiments, the measurement method 400A may be used to measure the phase change of the phase interpolator 400 between different phase regions. For ease of understanding, the operation of measurement method 400A will be described below with phase interpolator 400 in conjunction with the specific circuit example shown in FIG. 1C and FIG. 5C. For the example of fig. 5C, the plurality of selection signals SELA and SELB are switched to a logical value of 1 (i.e., corresponding to the phase interval Φ 1). Meanwhile, the signal values of the switching signal VS are sequentially switched back and forth from a plurality of logic values 0 (i.e., initial ratios) to a plurality of logic values 1 (i.e., first ratios). Equivalently, in operation S410, the phases of the output signals VO 1-VO 2 are continuously adjusted between the phase intervals φ 1 to generate the corresponding first wobble signal components.

In operation S420, the plurality of selection signals SELA and SELB are switched to a logic value 1 (i.e., corresponding to a phase interval Φ 1). Then, the selection signal SELA is also switched to a logic value 0, and the selection signal SELC is switched to a logic value 1 (i.e., corresponding to the phase interval Φ 2). The signal values of the switching signal VS are sequentially switched back and forth from a plurality of logic values 0 to a plurality of logic values 1 in correspondence to the phase interval Φ 1. The signal values of the switching signal VS are sequentially switched back and forth from a plurality of logic values 1 (i.e., a first ratio) to a plurality of logic values 0 (i.e., a second ratio) corresponding to the phase interval Φ 2. Equivalently, in operation S420, the phases of the output signals VO 1-VO 2 are continuously adjusted between the phase intervals φ 1- φ 2 to generate the corresponding second wobble signal components.

In some embodiments, if the phase change of the phase interpolator 120 between the different phase intervals is linear, the total energy of the wobble signal component should be proportional to the number of corresponding phase intervals. For example, since the aforementioned second dither signal component corresponds to the phase intervals φ 1- φ 2, and the first dither signal component corresponds to only a single phase interval φ 1, the total energy of the second phase noise associated with the second dither signal component should be greater than the total energy of the first phase noise associated with the first dither signal component. By a spectral analysis similar to that shown in FIG. 5B, when the total energy of the second phase noise is greater than the total energy of the first phase noise, it can be determined that the phase change of the output signals VO 1-VO 2 generated by the phase interpolator 120 during the phase interval φ 1- φ 2 is linear. Conversely, if the total second phase noise energy is less than the total first phase noise energy, the phase change of the phase interpolator 120 may be determined to be non-linear. By repeating the above operations, it can be determined whether the phase change of the phase interpolator 120 at the time of switching the phase intervals φ 1 φ 8 is linear.

The operation of the measurement method 400A is described above with reference to the specific circuit of fig. 1C, but the disclosure is not limited thereto, and various related circuits that can be implemented in the phase interpolator 400 of fig. 4A can be tested by using the measurement method 400A.

In summary, the phase rotator and the control method thereof provided by the present disclosure can reduce the influence of the pulse when the phase of the output signal of the phase interpolator is rotated, so as to improve the accuracy of the output signal of the phase interpolator. On the other hand, the measurement method provided by the present disclosure may utilize the jitter signal component introduced by the aforementioned pulse by using multiple switching modes to measure the linearity of the phase interpolator with higher phase rotation pitch requirement (e.g., the pitch of each phase rotation is in the picosecond (picosecond) level).

Although the present disclosure has been described with reference to the above embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure is to be determined by the appended claims.

Claims

1. A method of measurement, comprising:

switching a current share ratio of a phase interpolator back and forth between an initial ratio and a first ratio to generate a first wobble signal component,

wherein the phase interpolator is used for determining a phase of an output signal based on the current distribution ratio;

switching the current sharing ratio back and forth between the initial ratio and a second ratio to generate a second jitter signal component;

measuring the output signal to analyze a first phase noise total energy associated with the first dither signal component and a second phase noise total energy associated with the second dither signal component in the output signal; and

determining whether a change in the phase is linear based on the first phase noise total energy and the second phase noise total energy.

2. The method of claim 1, wherein generating the first wobble signal component comprises:

switching a plurality of signal values of a switching signal back and forth between a plurality of initial values and a plurality of first signal values to alternately turn on at least one corresponding one of a plurality of switches,

the plurality of initial values correspond to the initial proportion, the plurality of first signal values correspond to the first proportion, and the plurality of switches are selectively turned on according to the plurality of signal values to determine the current distribution proportion.

3. The method of claim 1, wherein the phase interpolator is configured to generate the output signal based on the current share ratio and a plurality of clock signals defining a plurality of phase intervals, and the method further comprises:

switching a plurality of selection signals such that the output signal corresponds to at least one of the plurality of phase intervals,

wherein the first wobble signal component corresponds to one of the plurality of phase intervals and the second wobble signal component corresponds to both of the plurality of phase intervals.

4. The method of claim 1, wherein the phase change of the output signal is determined to be linear when the second ratio is greater than the first ratio and the second phase noise total energy is greater than the first phase noise total energy.