CN112688338A - UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering - Google Patents

UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering Download PDF

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CN112688338A
CN112688338A CN202011403395.1A CN202011403395A CN112688338A CN 112688338 A CN112688338 A CN 112688338A CN 202011403395 A CN202011403395 A CN 202011403395A CN 112688338 A CN112688338 A CN 112688338A
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voltage
upqc
compensation
current
component
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郁正纲
伏祥运
朱立位
封�波
程振华
王建新
刘明
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State Grid Jiangsu Electric Power Co Ltd
Lianyungang Power Supply Co of State Grid Jiangsu Electric Power Co Ltd
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State Grid Jiangsu Electric Power Co Ltd
Lianyungang Power Supply Co of State Grid Jiangsu Electric Power Co Ltd
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Abstract

The invention provides a UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering, which is used for carrying out steady-state linear Kalman filter control on a three-phase UPQC system under a nonlinear load so as to realize power quality compensation. Firstly, designing a structural topology of a UPQC system, and designing parameters according to the designed structural topology; then, filtering the voltage based on a steady-state linear Kalman filter of the frequency locking loop FLL to calculate a voltage fundamental wave positive sequence component; and finally, generating a UPQC reference signal to control the UPQC according to the generated voltage positive sequence fundamental wave component. The method adopts SSLKF-FLL control, can obviously improve direct current offset filtering, has the characteristics of less calculation amount and high dynamic response speed, can better improve the capacity of UPQC for controlling the electric energy quality of the system, can improve the electric energy quality of the power grid under nonlinear load, improves the stability and robustness of the power grid, and enhances the control effect and the dynamic response performance of the UPQC system.

Description

UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering
Technical Field
The invention relates to the field of power electronic control, in particular to a UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering.
Background
The rapid development of nonlinear loads in power systems has resulted in the degradation of the quality of the Power (PQ) at the point of common coupling. Nonlinear loads are mostly based on power electronics. Flexible Alternating Current Transmission System (FACTS) devices based on power electronics technology are the most effective means to improve transmission system reactive power reliability and control capability. FACTS can guarantee system flexibility and can respond quickly to failures. The adoption of a Unified Power Flow Controller (UPFC) can regulate and control the bus voltage and the power flow in a direct current transmission system. In order to improve the power quality of the power distribution network, FACTS devices in parallel connection, series connection, parallel connection and the like are also configured. Among these devices, the Unified Power Quality Controller (UPQC) is a hybrid device similar to the UPFC, which combines the functions of parallel and series active power compensators (APFs). The parallel-type APF is used to compensate for the power quality problem of current, and the series-type APF is used to compensate for the power quality problem of voltage. Meanwhile, the UPQC can also improve the power factor of the system. Therefore, the UPQC is considered to be the most efficient device to solve the power quality problem.
Common control techniques for UPQC include Instantaneous Reactive Power Theory (IRPT), synchronous reference frame theory (SRF), unit vector template method, and Instantaneous Symmetric Component Theory (ISCT). Among these theories, the SRF algorithm has the simplest structure and the lowest computational cost, and is the simplest control method. The extraction of the fundamental component of the grid voltage is an important requirement for injecting balanced positive-sequence current under the condition of asymmetric voltage or harmonic distortion, but the SRF algorithm needs to use a low-pass filter (LPF) to cause signal delay, which has adverse effect on the extraction of the fundamental component of the grid voltage, affects the control effect of UPQC, and is not beneficial to realizing the compensation of the power quality. A traditional second-order generalized integrator frequency-locked loop (SOGI-FLL) filter extracts a fundamental component and has higher precision under the condition of smooth grid voltage. However, because the attenuation capability of a second-order generalized integrator (SOGI) filter is limited, the synchronization error is large under the condition of distorted power grid, and the filter is easily influenced by low-order harmonic waves and direct current offset in the system.
Disclosure of Invention
The invention aims to: the UPQC power quality compensation control method based on the frequency-locked loop steady-state linear Kalman filtering is provided, and the capacity of the UPQC in controlling the power quality of the system can be better improved.
The technical solution of the invention is as follows: a UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering comprises the following steps:
step 1: designing a structural topology of the UPQC system, and designing parameters aiming at the structural topology;
step 2: voltage alpha component v is subjected to steady-state linear Kalman filter SSLKF based on frequency-locked loop FLLaAnd a beta component vbAnd filtering to obtain a voltage fundamental wave positive sequence component.
And step 3: and (3) generating a UPQC reference signal to control the UPQC according to the voltage fundamental wave component generated in the step (2), and triggering the compensator to generate a compensation current and a compensation voltage.
A UPQC power quality compensation control system based on frequency-locked loop steady-state linear Kalman filtering comprises the following modules:
structure and parameter design module: the UPQC system is used for designing the structural topology of the UPQC system and carrying out parameter design aiming at the structural topology;
a filtering module: alpha component v for counter-voltageaAnd a beta component vbFiltering to obtain a voltage fundamental positive sequence component;
the compensator triggering module: and the voltage fundamental component generated by the filtering module is used for generating a UPQC reference signal according to the provided control strategy to control the UPQC, and triggering the compensator to generate a compensation current and a compensation voltage.
Compared with the prior art, the invention has the beneficial effects that: 1) the method comprises the following steps of performing steady-state linear Kalman filter (SSLKF) control on a three-phase UPQC system under a nonlinear load, improving the power quality of a power grid under the nonlinear load, improving the stability and robustness of the power grid, and enhancing the control effect and dynamic response performance of the UPQC system; 2) the SSLKF-FLL obviously improves direct current offset filtering, has the characteristics of less calculation amount and high dynamic response speed, and can better improve the capacity of UPQC in controlling the power quality of the system.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a topological structure diagram of the UPQC of the present invention.
Fig. 2 is a structure diagram of a frequency locking loop based on a steady-state linear kalman filter.
FIG. 3 shows the in-phase component (V) of the present inventionfα) Relative to the input signal (V) of the SSLKF-FLLin) Bode diagram of
FIG. 4 is a graph of the generation of UPQC compensator reference signals using the SSLKF-FLL method in an embodiment of the present invention.
Fig. 5 is a dynamic characteristic diagram of the UPQC control algorithm and the parallel converter in an embodiment of the present invention.
FIG. 6 is a graph of UPQC steady-state and dynamic responses using SSLKF-FLL in an example of the invention.
Detailed Description
A UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering is characterized by comprising the following steps:
step 1: with reference to fig. 1, a structure topology of the UPQC system is designed, and parameter design is performed for the structure topology, which specifically includes the following steps:
step 1-1: the UPQC system comprises parallel compensators, series compensators, an additional direct current capacitor, a series-parallel connection port inductor and a ripple wave filter, wherein the direct current bus voltage control adopts an SSLKF-FLL algorithm and adopts proportional-integral PI control and Sinusoidal Pulse Width Modulation (SPWM) switching technology, each compensator consists of six Insulated Gate Bipolar Transistor (IGBT) switches, and the series compensators and the parallel compensators are respectively connected with a power grid through the series-parallel connection port inductor;
step 1-2: the UPQC system parameters are designed as follows: calculating the DC voltage VDC：
Figure BDA0002817749170000031
Wherein m is a modulation index, VLIs the grid voltage;
calculating phase current I of parallel compensatorsh：
Figure BDA0002817749170000032
Wherein f isswTo the switching frequency, Icr,ppIs the current ripple, a is the overload coefficient;
calculating the DC capacitance CDC：
Figure BDA0002817749170000033
Wherein k is the coefficient of dynamic change of energy, VphIs the phase voltage, t is the time to recover the DC line voltage, VDC1Is the minimum dc voltage value;
calculating serial interface inductor Lse：
Figure BDA0002817749170000034
Wherein: i iscr,swellRipple current is shown, and N is the turn ratio.
Step 2: using a frequency-locked loop (FLL) -based steady-state linear Kalman filter (SSLKF) to measure the alpha component v of the voltageaAnd a beta component vbFiltering to obtain a voltage fundamental wave positive sequence component, specifically:
using a frequency-locked loop (FLL) -based steady-state linear Kalman filter (SSLKF) to measure the alpha component v of the voltageaAnd a beta component vbFiltering to calculate voltage fundamental component vfaAnd vfb：
Figure BDA0002817749170000035
Figure BDA0002817749170000041
Where ω is a constant and vinIs a supply voltage vsabc，k1、k2Is a kalman parameter.
And step 3: generating a UPQC reference signal to control the UPQC according to the voltage fundamental wave component generated in the step 2, and triggering the compensator to generate compensation current and compensation voltage, wherein the method specifically comprises the following steps:
step 3-1: using voltage fundamental component vfaAnd vfbAnd an orthogonal component qv obtained by orthogonal transformationfaAnd qvfbAnd (3) calculating:
Figure BDA0002817749170000042
Figure BDA0002817749170000043
step 3-2: using inverse matrix of Clark transformation matrix to correct sequence voltage of fundamental wave
Figure BDA0002817749170000044
And
Figure BDA0002817749170000045
is inversely transformed to obtain
Figure BDA0002817749170000046
Step 3-3: calculating a reference DC link voltage
Figure BDA0002817749170000047
And the actually measured DC voltage VDCIs obtained as a difference of vdeThe difference value is processed by a PI controller to obtain a power loss component PlossThe calculation formula is as follows:
Ploss(t)＝Ploss(t-1)+kp{vde(t)-vde(t-1)}
wherein the power Ploss(t) active power, P, of the supply current at time tlossNot only all switching losses are included, but also the losses of the UPQC device are included, kp is a droop control coefficient, vde(t) reference DC link voltage at time t
Figure BDA0002817749170000048
And the actually measured DC voltage VDCA difference of (d);
to load voltage VlabcAnd a load current ilabcPerforming dot product processing to obtain average load power PlavgThen reference power PrefExpressed as:
Pref＝Plavg+Ploss
step 3-4: generating a compensation current, specifically:
step 3-4-1: calculating a reference current
Figure BDA0002817749170000049
Figure BDA00028177491700000410
Wherein the content of the first and second substances,
Figure BDA00028177491700000411
the actually measured balanced positive sequence reference power grid input voltage is obtained;
step 3-4-2: reference current
Figure BDA00028177491700000412
And the actual current i of the side tosabcAfter difference operation is carried out, a difference signal is sent into an SPWM pulse trigger, and a compensation current control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the parallel compensator; thereby completing compensation;
step 3-5: generating a compensation voltage, specifically:
step 3-5-1: calculating a reference load voltage
Figure BDA0002817749170000051
Figure BDA0002817749170000052
Figure BDA0002817749170000053
Figure BDA0002817749170000054
Wherein the content of the first and second substances,
Figure BDA0002817749170000055
in order to set the peak reference voltage,
Figure BDA0002817749170000056
is a unit template;
step 3-5-2: will be referenced to the load voltage
Figure BDA0002817749170000057
And the actual load voltage v from side to sidelabcAfter difference operation is carried out, a difference signal is sent into the SPWM pulse trigger, a compensation voltage control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the series compensator, and therefore compensation is completed.
A UPQC power quality compensation control system based on frequency-locked loop steady-state linear Kalman filtering comprises the following modules:
structure and parameter design module: the UPQC system is used for designing the structural topology of the UPQC system and carrying out parameter design aiming at the structural topology;
a filtering module: alpha component v for counter-voltageaAnd a beta component vbFiltering to obtain a voltage fundamental positive sequence component;
the compensator triggering module: the voltage fundamental component generated by the filtering module is used for generating a UPQC reference signal to control the UPQC, and the compensator is triggered to generate a compensation current and a compensation voltage.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor when executing the computer program implements the steps of:
step 1: the method comprises the following steps of designing a structure topology of the UPQC system, and designing parameters aiming at the structure topology, wherein the method specifically comprises the following steps:
step 1-1: the UPQC system comprises parallel compensators, series compensators, an additional direct current capacitor, a series-parallel connection port inductor and a ripple wave filter, wherein the direct current bus voltage control adopts an SSLKF-FLL algorithm and adopts proportional-integral PI control and Sinusoidal Pulse Width Modulation (SPWM) switching technology, each compensator consists of six Insulated Gate Bipolar Transistor (IGBT) switches, and the series compensators and the parallel compensators are respectively connected with a power grid through the series-parallel connection port inductor;
step 1-2: the UPQC system parameters are as follows: calculating the DC voltage VDC：
Figure BDA0002817749170000058
Wherein m is a modulation index, VLIs the grid voltage;
calculating phase current I of parallel compensatorsh：
Figure BDA0002817749170000061
Wherein f isswTo the switching frequency, Icr,ppIs the current ripple, a is the overload coefficient;
calculating the DC capacitance CDC：
Figure BDA0002817749170000062
Wherein k is the coefficient of dynamic change of energy, VphIs the phase voltage, t is the time to recover the DC line voltage, VDC1Is the minimum dc voltage value;
calculating serial interface inductor Lse：
Figure BDA0002817749170000063
Wherein: i iscr,swellRipple current is shown, and N is the turn ratio.
Step 2: according to the structural topology and parameters of the UPQC system designed in the step 1, a steady-state linear Kalman filter SSLKF based on a Frequency Locking Loop (FLL) is used for carrying out a voltage alpha component vaAnd a beta component vbFiltering to obtain a voltage fundamental wave positive sequence component, specifically:
voltage alpha component v is subjected to steady-state linear Kalman filter SSLKF based on frequency-locked loop FLLaAnd a beta component vbFiltering to calculate voltage fundamental component vfaAnd vfb：
Figure BDA0002817749170000064
Figure BDA0002817749170000065
Where ω is a constant and vinIs a supply voltage vsabc，k1、k2Is a Kalman referenceAnd (4) counting.
And step 3: generating a UPQC reference signal to control the UPQC according to the voltage fundamental wave component generated in the step 2, and triggering the compensator to generate compensation current and compensation voltage, wherein the method specifically comprises the following steps:
step 3-1: using voltage fundamental component vfaAnd vfbAnd an orthogonal component qv obtained by orthogonal transformationfaAnd qvfbAnd (3) calculating:
Figure BDA0002817749170000066
Figure BDA0002817749170000071
step 3-2: using inverse matrix of Clark transformation matrix to correct sequence voltage of fundamental wave
Figure BDA0002817749170000072
And
Figure BDA0002817749170000073
is inversely transformed to obtain
Figure BDA0002817749170000074
Step 3-3: calculating a reference DC link voltage
Figure BDA0002817749170000075
And the actually measured DC voltage VDCIs obtained as a difference of vdeThe difference value is processed by a PI controller to obtain a power loss component PlossThe calculation formula is as follows:
Ploss(t)＝Ploss(t-1)+kp{vde(t)-vde(t-1)}
wherein the power Ploss(t) is the active power of the supply current at the moment t, and kp is a droop control coefficient;
to load voltage VlabcAnd a load current ilabcPerforming dot product processingTo obtain the average load power PlavgThen reference power PrefExpressed as:
Pref＝Plavg+Ploss
step 3-4: generating a compensation current, specifically:
step 3-4-1: calculating a reference current
Figure BDA0002817749170000076
Figure BDA0002817749170000077
Wherein the content of the first and second substances,
Figure BDA0002817749170000078
the actually measured balanced positive sequence reference power grid input voltage is obtained;
step 3-4-2: reference current
Figure BDA0002817749170000079
And the actual current i of the side tosabcAfter difference operation is carried out, a difference signal is sent into an SPWM pulse trigger, and a compensation current control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the parallel compensator; thereby completing compensation;
step 3-5: generating a compensation voltage, specifically:
step 3-5-1: calculating a reference load voltage
Figure BDA00028177491700000710
Figure BDA00028177491700000711
Figure BDA00028177491700000712
Figure BDA00028177491700000713
Wherein the content of the first and second substances,
Figure BDA00028177491700000714
in order to set the peak reference voltage,
Figure BDA00028177491700000715
is a unit template;
step 3-5-2: will be referenced to the load voltage
Figure BDA00028177491700000716
And the actual load voltage v from side to sidelabcAfter difference operation is carried out, a difference signal is sent into the SPWM pulse trigger, a compensation voltage control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the series compensator, and therefore compensation is completed.
A computer-storable medium on which a computer program is stored, wherein the computer program, when executed by a processor, performs the steps of:
step 1: the method comprises the following steps of designing a structure topology of the UPQC system, and designing parameters aiming at the structure topology, wherein the method specifically comprises the following steps:
step 1-1: the UPQC system comprises parallel compensators, series compensators, an additional direct current capacitor, a series-parallel connection port inductor and a ripple wave filter, wherein the direct current bus voltage control adopts an SSLKF-FLL algorithm and adopts proportional-integral PI control and Sinusoidal Pulse Width Modulation (SPWM) switching technology, each compensator consists of six Insulated Gate Bipolar Transistor (IGBT) switches, and the series compensators and the parallel compensators are respectively connected with a power grid through the series-parallel connection port inductor;
step 1-2: the UPQC system parameters are as follows: calculating the DC voltage VDC：
Figure BDA0002817749170000081
Wherein m isModulation index, VLIs the grid voltage;
calculating phase current I of parallel compensatorsh：
Figure BDA0002817749170000082
Wherein f isswTo the switching frequency, Icr,ppIs the current ripple, a is the overload coefficient;
calculating the DC capacitance CDC：
Figure BDA0002817749170000083
Wherein k is the coefficient of dynamic change of energy, VphIs the phase voltage, t is the time to recover the DC line voltage, VDC1Is the minimum dc voltage value;
calculating serial interface inductor Lse：
Figure BDA0002817749170000084
Wherein: i iscr,swellRipple current is shown, and N is the turn ratio.
Step 2: according to the structural topology and parameters of the UPQC system designed in the step 1, a steady-state linear Kalman filter SSLKF based on the frequency-locked loop FLL is used for measuring the alpha component v of the voltageaAnd a beta component vbFiltering to obtain a voltage fundamental wave positive sequence component, specifically:
voltage alpha component v is subjected to steady-state linear Kalman filter SSLKF based on frequency-locked loop FLLaAnd a beta component vbFiltering to calculate voltage fundamental component vfaAnd vfb：
Figure BDA0002817749170000091
Figure BDA0002817749170000092
Where ω is a constant and vinIs a supply voltage vsabc，k1、k2Is a kalman parameter.
And step 3: generating a UPQC reference signal to control the UPQC according to the voltage fundamental wave component generated in the step 2, and triggering the compensator to generate compensation current and compensation voltage, wherein the method specifically comprises the following steps:
step 3-1: using voltage fundamental component vfaAnd vfbAnd an orthogonal component qv obtained by orthogonal transformationfaAnd qvfbAnd (3) calculating:
Figure BDA0002817749170000093
Figure BDA0002817749170000094
step 3-2: using inverse matrix of Clark transformation matrix to correct sequence voltage of fundamental wave
Figure BDA0002817749170000095
And
Figure BDA0002817749170000096
is inversely transformed to obtain
Figure BDA0002817749170000097
Step 3-3: calculating a reference DC link voltage
Figure BDA0002817749170000098
And the actually measured DC voltage VDCIs obtained as a difference of vdeThe difference value is processed by a PI controller to obtain a power loss component PlossThe calculation formula is as follows:
Ploss(t)＝Ploss(t-1)+kp{vde(t)-vde(t-1)}
wherein the power Ploss(t) is the active power of the supply current at the moment t, and kp is a droop control coefficient;
to load voltage VlabcAnd a load current ilabcPerforming dot product processing to obtain average load power PlavgThen reference power PrefExpressed as:
Pref＝Plavg+Ploss
step 3-4: generating a compensation current, specifically:
step 3-4-1: calculating a reference current
Figure BDA0002817749170000099
Figure BDA00028177491700000910
Wherein the content of the first and second substances,
Figure BDA00028177491700000911
the actually measured balanced positive sequence reference power grid input voltage is obtained;
step 3-4-2: reference current
Figure BDA00028177491700000912
And the actual current i of the side tosabcAfter difference operation is carried out, a difference signal is sent into an SPWM pulse trigger, and a compensation current control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the parallel compensator; thereby completing compensation;
step 3-5: generating a compensation voltage, specifically:
step 3-5-1: calculating a reference load voltage
Figure BDA0002817749170000101
Figure BDA0002817749170000102
Figure BDA0002817749170000103
Figure BDA0002817749170000104
Wherein the content of the first and second substances,
Figure BDA0002817749170000105
in order to set the peak reference voltage,
Figure BDA0002817749170000106
is a unit template;
step 3-5-2: will be referenced to the load voltage
Figure BDA0002817749170000107
And the actual load voltage v from side to sidelabcAfter difference operation is carried out, a difference signal is sent into the SPWM pulse trigger, a compensation voltage control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the series compensator, and therefore compensation is completed.
The invention is described in detail below with reference to the accompanying drawings and examples.
Examples
A UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering is characterized by comprising the following steps:
step 1: with reference to fig. 1, a structure topology of the UPQC system is designed, and parameter design is performed for the structure topology, which specifically includes the following steps:
step 1-1: the UPQC system comprises parallel compensators, series compensators, an additional direct current capacitor, a series-parallel connection port inductor and a ripple wave filter, wherein the direct current bus voltage control adopts an SSLKF-FLL algorithm and adopts proportional-integral PI control and Sinusoidal Pulse Width Modulation (SPWM) switching technology, each compensator consists of six Insulated Gate Bipolar Transistor (IGBT) switches, and the series compensators and the parallel compensators are respectively connected with a power grid through the series-parallel connection port inductor;
step 1-2: the UPQC system parameters are designed as follows: calculating the DC voltage VDC：
Figure BDA0002817749170000108
Wherein m is a modulation index, VLIs the grid voltage;
calculating phase current I of parallel compensatorsh：
Figure BDA0002817749170000111
Wherein f isswTo the switching frequency, Icr,ppIs the current ripple, a is the overload coefficient;
calculating the DC capacitance CDC：
Figure BDA0002817749170000112
Wherein k is the coefficient of dynamic change of energy, VphIs the phase voltage, t is the time to recover the DC line voltage, VDC1Is the minimum dc voltage value;
calculating serial interface inductor Lse：
Figure BDA0002817749170000113
Wherein: i iscr,swellRipple current is shown, and N is the turn ratio.
Step 2: voltage alpha component v is subjected to steady-state linear Kalman filter SSLKF based on frequency-locked loop FLLaAnd a beta component vbFiltering to obtain a voltage fundamental wave positive sequence component, specifically:
voltage alpha component v is subjected to steady-state linear Kalman filter SSLKF based on frequency-locked loop FLLaAnd a beta component vbFiltering is carried outWave to calculate voltage fundamental wave component vfaAnd vfb：
Figure BDA0002817749170000114
Figure BDA0002817749170000115
Where ω is a constant and vinIs a supply voltage vsabc，k1、k2For kalman parameters, fig. 2 is a block diagram of an SSLKF-based FLL filter.
For damping factor and Kalman parameter (k)1、k2) In different combinations of SSLKF, in-phase signal VfaWith respect to the supply voltage VinThe bode diagram of (a) is shown in fig. 3.
From fig. 3, it can be concluded that SSLKF-FLL produces a relatively small dc offset and better harmonic suppression capability. These characteristics can be attributed to the second control gain (β -axis gain) of SSLKF-FLL. Therefore, its dynamic response and damping are greater than those of the SOGI-FLL.
And step 3: with reference to fig. 4, according to the voltage fundamental component generated in step 2, a UPQC reference signal is generated to control the UPQC, and the compensator is triggered to generate a compensation current and a compensation voltage, specifically:
step 3-1: using voltage fundamental component vfaAnd vfbAnd an orthogonal component qv obtained by orthogonal transformationfaAnd qvfbAnd (3) calculating:
Figure BDA0002817749170000121
Figure BDA0002817749170000122
step 3-2: using inverse matrix of Clark transformation matrix to correct sequence voltage of fundamental wave
Figure BDA0002817749170000123
And
Figure BDA0002817749170000124
is inversely transformed to obtain
Figure BDA0002817749170000125
Step 3-3: calculating a reference DC link voltage
Figure BDA0002817749170000126
And the actually measured DC voltage VDCIs obtained as a difference of vdeThe difference value is processed by a PI controller to obtain a power loss component PlossThe calculation formula is as follows:
Ploss(t)＝Ploss(t-1)+kp{vde(t)-vde(t-1)}
wherein the power Ploss(t) active power, P, of the supply current at time tlossNot only all switching losses are included, but also the losses of the UPQC device are included, kp is a droop control coefficient, vde(t) reference DC link voltage at time t
Figure BDA0002817749170000127
And the actually measured DC voltage VDCA difference of (d);
to load voltage VlabcAnd a load current ilabcPerforming dot product processing to obtain average load power PlavgThen reference power PrefExpressed as:
Pref＝Plavg+Ploss
step 3-4: generating a compensation current, specifically:
step 3-4-1: calculating a reference current
Figure BDA0002817749170000128
Figure BDA0002817749170000129
Wherein the content of the first and second substances,
Figure BDA00028177491700001210
the actually measured balanced positive sequence reference power grid input voltage is obtained;
step 3-4-2: reference current
Figure BDA00028177491700001211
And the actual current i of the side tosabcAfter difference operation is carried out, a difference signal is sent into an SPWM pulse trigger, and a compensation current control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the parallel compensator; thereby completing compensation;
step 3-5: generating a compensation voltage, specifically:
step 3-5-1: calculating a reference load voltage
Figure BDA00028177491700001212
Figure BDA0002817749170000131
Figure BDA0002817749170000132
Figure BDA0002817749170000133
Wherein the content of the first and second substances,
Figure BDA0002817749170000134
in order to set the peak reference voltage,
Figure BDA0002817749170000135
is a unit template;
step 3-5-2: will be referenced to the load voltage
Figure BDA0002817749170000136
And the actual load voltage v from side to sidelabcAfter difference operation is carried out, a difference signal is sent into the SPWM pulse trigger, a compensation voltage control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the series compensator, and therefore compensation is completed.
The SSLKF-based FLL control algorithm is subjected to simulation verification on an UPQC system, the model is analyzed by using a Matlab/Simulink software platform, the sampling time is 10 mu s, and a discrete domain is obtained by 5 ode solvers. The following table is the system parameters and the three-phase UPQC detailed design value parameters:
Figure BDA0002817749170000137
(1) application of SSLKF-FLL control and parallel converter based on dynamic characteristics in UPQC
The dynamic behavior of UPQC under unbalanced load and current distortion is shown in FIG. 5, the compensation current i of the parallel compensatorcoma、icomb、icomcAs shown in fig. 5, it is shown that the reactive compensation for the power supply current is orderly, the dc bus voltage is within the 3% tolerance, and the dc voltage is adapted to its 700 v voltage level and is not affected by the 16 v voltage fluctuation.
Due to the use of low order filters in the dc link voltage and active average power calculations, there is a period of imperceptible excursion in the waveform. Load voltage v, regardless of load imbalance1The curves are all kept at their desired levels.
The waveform shows that the three-phase power current i is due to the presence of the injection current of the parallel compensatorsAlmost equal to the reference supply current
Figure BDA0002817749170000141
The consistency is achieved; likewise, the supply voltage vsLoad voltage v1And a supply current isIn phase with each other. Therefore, the parallel compensation of the UPQCThe compensator plays a role in power factor correction in the load dynamic process.
The results show that the "c-phase" load is connected from 0.5 seconds and that the compensation current i for each phase is showncoma、icomb、icomcA change in (c). At this point it can be seen that the parallel type compensator provides the necessary compensation current with the required amplitude in all three phases before and after the unbalanced load condition to maintain the sinusoidal supply current.
(2) UPQC steady-state and dynamic response using SSLKF-FLL method
The steady-state and dynamic response of UPQC using SSLKF-FLL control is shown in FIG. 6, where the waveform is three-phase supply voltage vsPower supply current isLoad voltage vlLoad current ilD.c. voltage VDCSeries compensator compensation voltage vinja、vinjb、vinjcParallel compensator compensating current icoma、icomb、icomc。
Between 0.5-0.56s, a voltage recess on the order of 0.70p.u can be seen; the voltage expansion at 0.6-0.66s is 1.30p.u amplitude; at 0.5-0.56s, applying a power supply voltage vsThe power supply voltage on the power supply is from-11 th harmonic to +13 th harmonic, and the amplitude is 1/15 and 1/20 of the basic voltage;
at 0.5-0.6 seconds, when the "c-phase" is disconnected from the supply line, the load is adjusted from three to two phases, which results in an unbalanced load condition in the network. As a result, the parallel compensator portion of the UPQC compensates for unbalanced loads, which balances the sinusoidal supply current isAnd is connected to the supply voltage vsThe phases are the same;
UPQC series compensator compensates for voltage sag/expansion and distortion and generates an undistorted load voltage vlAs shown in fig. 6. It can also compensate the load voltage v from all PQ disturbanceslProblematic and remains equal to the desired amplitude. Therefore, it maintains a constant voltage at the load side point of common coupling. Meanwhile, the parallel compensator maintains balanced power supply current and uniformly adjusts the power factor. SSLKF-FLL control Algorithm as described aboveThe DC side voltage is kept close to the reference level under PQ disturbance. Supply voltage vsSupply current isLoad voltage vlAnd a load current ilThe harmonic spectrum of (a) is shown in the following table:
Figure BDA0002817749170000142
Figure BDA0002817749170000151
the Total Harmonic Distortion (THD) of the harmonic load was 63.83% of the total harmonic load. Similarly, the THD of the load voltage is 3.16%, also filtered from the 16.85% supply voltage THD. Harmonic levels can be limited to below 5% according to the IEEE standard controlled by the UPQC system SSLKF-FLL.
Therefore, the method can improve the power quality of the power grid under the nonlinear load, improve the stability and robustness of the power grid, and enhance the control effect and the dynamic response performance of the UPQC system.

Claims (7)

1. A UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering is characterized by comprising the following steps:
step 1: constructing a structure topology of the UPQC system, and determining parameters aiming at the structure topology;
step 2: voltage alpha component v is subjected to steady-state linear Kalman filter SSLKF based on frequency-locked loop FLLaAnd a beta component vbFiltering to obtain a voltage fundamental positive sequence component;
and step 3: and (3) generating a UPQC reference signal to control the UPQC according to the voltage fundamental wave component generated in the step (2), triggering the compensator to generate compensation current and compensation voltage, and finishing the compensation of the power quality.
2. The UPQC power quality compensation control method according to claim 1, characterized in that said step 1 of constructing a UPQC system structure and determining parameters according to structure topology specifically comprises the steps of:
step 1-1: constructing a structural topology of the UPQC system; the UPQC system comprises parallel compensators, series compensators, an additional direct current capacitor, a series-parallel connection port inductor and a ripple wave filter, wherein the direct current bus voltage control adopts an SSLKF-FLL algorithm and adopts proportional-integral PI control and Sinusoidal Pulse Width Modulation (SPWM) switching technology, each compensator consists of six Insulated Gate Bipolar Transistor (IGBT) switches, and the series compensators and the parallel compensators are respectively connected with a power grid through the series-parallel connection port inductor;
step 1-2: determining parameters; the UPQC system parameters are as follows: DC voltage VDC：
Figure FDA0002817749160000011
Wherein m is a modulation index, VLIs the grid voltage;
parallel compensator phase current Ish：
Figure FDA0002817749160000012
Wherein f isswTo the switching frequency, Icr,ppIs the current ripple, a is the overload coefficient;
DC capacitor CDC：
Figure FDA0002817749160000013
Wherein k is the coefficient of dynamic change of energy, VphIs the phase voltage, t is the time to recover the DC line voltage, VDC1Is the minimum dc voltage value;
series interface inductor Lse：
Figure FDA0002817749160000021
Wherein: i iscr,swellRipple current is shown, and N is the turn ratio.
3. The UPQC power quality compensation control method according to claim 1, wherein according to design structure topology and parameters, calculating voltage fundamental component in step 2 specifically comprises:
voltage alpha component v is subjected to steady-state linear Kalman filter SSLKF based on frequency-locked loop FLLaAnd a beta component vbFiltering to calculate voltage fundamental component vfaAnd vfb：
Figure FDA0002817749160000022
Figure FDA0002817749160000023
Where ω is a constant and vinIs a supply voltage vsabc，k1、k2Is a kalman parameter.
4. The UPQC power quality compensation control method according to claim 1, wherein generating UPQC reference signals to control UPQC according to the voltage fundamental component generated in step 3 according to the voltage fundamental component generated in step 2 specifically comprises:
step 3-1: using voltage fundamental component vfaAnd vfbAnd an orthogonal component qv obtained by orthogonal transformationfaAnd qvfbAnd (3) calculating:
Figure FDA0002817749160000024
Figure FDA0002817749160000025
step 3-2: using inverse matrix of Clark transformation matrix to correct sequence voltage of fundamental wave
Figure FDA0002817749160000026
And
Figure FDA0002817749160000027
is inversely transformed to obtain
Figure FDA0002817749160000028
Step 3-3: calculating a reference power Pref(ii) a First, a reference DC link voltage is calculated
Figure FDA0002817749160000029
And the actually measured DC voltage VDCIs obtained as a difference of vdeThe difference value is processed by a PI controller to obtain a power loss component PlossThe calculation formula is as follows:
Ploss(t)＝Ploss(t-1)+kp{vde(t)-vde(t-1)}
wherein the power Ploss(t) is the active power of the supply current at the moment t, and kp is a droop control coefficient;
to load voltage VlabcAnd a load current ilabcPerforming dot product processing to obtain average load power PlavgThen reference power PrefExpressed as:
Pref＝Plavg+Ploss
step 3-4: generating a compensation current, specifically:
step 3-4-1: calculating a reference current
Figure FDA0002817749160000031
Figure FDA0002817749160000032
Wherein the content of the first and second substances,
Figure FDA0002817749160000033
the actually measured balanced positive sequence reference power grid input voltage is obtained;
step 3-4-2: reference current
Figure FDA0002817749160000034
And the actual current i of the side tosabcAfter difference operation is carried out, a difference signal is sent into an SPWM pulse trigger, and a compensation current control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the parallel compensator; thereby completing compensation;
step 3-5: generating a compensation voltage, specifically:
step 3-5-1: calculating a reference load voltage
Figure FDA0002817749160000035
Figure FDA0002817749160000036
Figure FDA0002817749160000037
Figure FDA0002817749160000038
Wherein the content of the first and second substances,
Figure FDA0002817749160000039
in order to set the peak reference voltage,
Figure FDA00028177491600000310
is a unit template;
step 3-5-2: will be referenced to the load voltage
Figure FDA00028177491600000311
And the actual load voltage v from side to sidelabcAfter difference operation is carried out, a difference signal is sent into the SPWM pulse trigger, a compensation voltage control signal is generated in the pulse trigger to control the turn-off of a VSC converter switch in the series compensator, and therefore compensation is completed.
5. A UPQC power quality compensation control system based on frequency-locked loop steady-state linear Kalman filtering is characterized by comprising the following modules:
structure and parameter design module: the UPQC system is used for designing the structural topology of the UPQC system and carrying out parameter design aiming at the structural topology;
a filtering module: alpha component v for counter-voltageaAnd a beta component vbFiltering to obtain a voltage fundamental positive sequence component;
the compensator triggering module: the voltage fundamental component generated by the filtering module is used for generating a UPQC reference signal to control the UPQC, and the compensator is triggered to generate a compensation current and a compensation voltage.
6. A computer arrangement comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method as claimed in any one of claims 1 to 4 are implemented by the processor when executing the computer program.
7. A computer-storable medium having a computer program stored thereon, wherein the computer program is adapted to carry out the steps of the method according to any one of claims 1-4 when executed by a processor.
CN202011403395.1A 2020-12-04 2020-12-04 UPQC power quality compensation control method based on frequency-locked loop steady-state linear Kalman filtering Pending CN112688338A (en)

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