CN112613080A - Reconfigurable array unit and array for lightweight block cipher algorithm - Google Patents

Reconfigurable array unit and array for lightweight block cipher algorithm Download PDF

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Publication number
CN112613080A
CN112613080A CN202011486285.6A CN202011486285A CN112613080A CN 112613080 A CN112613080 A CN 112613080A CN 202011486285 A CN202011486285 A CN 202011486285A CN 112613080 A CN112613080 A CN 112613080A
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China
Prior art keywords
unit
data
mux
multiplexer
reconfigurable array
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CN202011486285.6A
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Chinese (zh)
Inventor
黄海
徐江
刘志伟
赵石磊
于斌
孙铭玮
刘玲
石峰硕
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Harbin University of Science and Technology
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Harbin University of Science and Technology
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Priority to CN202011486285.6A priority Critical patent/CN112613080A/en
Publication of CN112613080A publication Critical patent/CN112613080A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure

Abstract

The invention provides a reconfigurable array unit and array for lightweight block cipher algorithm, which relates to the field of integrated circuits and comprises: a logic unit LOU, an S-box lookup table unit LUT, an arithmetic unit AU, a replacement unit PU, a shift unit SU, a finite field multiplication unit GU, a multiplexer MUX and a register REG; after the logic unit LOU, the S box lookup table unit LUT, the arithmetic unit AU, the replacement unit PU, the shift unit SU and the finite field multiplication unit GU receive 16bit data and input the data, the arithmetic output of each functional unit is transmitted to the multiplexer MUX, and the reconstructed password data output is completed through the register REG, so that the problem that the realization mode of an ASIC (application specific integrated circuit) of a password processor chip in the prior art is poor in flexibility and expansibility is solved; the technical problem of low energy efficiency of the ISAP implementation mode of the microprocessor adopting the instruction set architecture.

Description

Reconfigurable array unit and array for lightweight block cipher algorithm
Technical Field
The invention relates to the field of integrated circuits, in particular to a reconfigurable array unit and an array for a lightweight block cipher algorithm.
Background
In recent years, with the rapid development of internet of things technology, communication technology and computer technology, communication computing functions can be implemented in embedded devices with smaller hardware area and lower end, application programs usually exchange sensitive or private data, so that ensuring an appropriate data security level is a basic requirement, and lightweight block cipher algorithms are specially designed for resource-constrained devices.
As an important guarantee for information security, cryptographic processor chips have increasingly high requirements for security, flexibility, power consumption, and the like. Current cryptographic processor chips can be divided into two categories from the architecture: the Processor is implemented by an Application Specific Integrated Circuit (ASIC), and is implemented by an Instruction Set Architecture (ISAP) microprocessor. ASIC implementations customize the circuit structure according to the particular application, without the need for an instruction set. The method has the advantages of high execution speed, low power consumption and the like, but also has the defects of poor flexibility and expansibility and the like. The great advantage of ISAP implementation is high flexibility, which has the disadvantage of low energy efficiency, and therefore, it is necessary to construct a cryptographic processor chip mode that can balance the above two implementations.
Disclosure of Invention
Based on the existing problems, the invention provides a reconfigurable array unit and an array facing to a lightweight block cipher algorithm, which are used for solving the problem that the cipher processor chip in the prior art adopts an ASIC implementation mode of an application specific integrated circuit, and the flexibility and the expansibility are poor; the technical problem of low energy efficiency of the ISAP implementation mode of the microprocessor adopting the instruction set architecture.
The embodiment of the invention discloses a reconfigurable array unit for a lightweight block cipher algorithm, which comprises: a logic unit LOU, an S-box lookup table unit LUT, an arithmetic unit AU, a replacement unit PU, a shift unit SU, a finite field multiplication unit GU, a multiplexer MUX and a register REG;
and after the logic unit LOU, the S box lookup table unit LUT, the arithmetic unit AU, the replacement unit PU, the shift unit SU and the finite field multiplication unit GU receive 16bit data and input, the arithmetic output of each functional unit is transmitted to the multiplexer MUX after the corresponding operation of the units is finished, and the reconstructed password data output is finished through the register REG.
Further, the logic unit LOU, the circuit unit includes: a first-level XOR operation unit, a second-level XOR operation unit, a first-level AND operation unit and a multiplexer;
the logic unit LOU is used for realizing the logic operation of data, 3 groups of 16-bit data in0, in1, in2, in0 and in1 are subjected to exclusive-or operation in a first-stage exclusive-or operation unit, and the operation result and in2 are subjected to exclusive-or operation in a second-stage exclusive-or operation unit; in0 and in1 are AND-operated in a primary AND operation unit;
the in0 and in1 are XOR-ed by the first stage XOR unit, and the XOR-ed result of in0 and in1 is XOR-ed by in2, and the XOR-ed result of in0 and in1 is MUX-ed to obtain the LOU _ 0.
Further, the S-box lookup table unit LUT, the circuit unit includes: four Random Access Memories (RAMs) and a Multiplexer (MUX);
the S-box lookup table unit LUT is used for realizing S-box lookup operation of data, the input 16-bit data in0 of the S-box lookup table unit LUT is divided into 4 groups of 4-bit I1, I2, I3 and I4, and meanwhile lookup operation is carried out in the RAM, and output results O1, O2, O3, O4, O1, O2, O3 and O4 are output to LUT _0 through a multiplexer MUX.
Further, the arithmetic unit AU, the circuit unit includes: 3 32-bit registers REG, 2 multiplexers, 1 AU arithmetic unit;
the arithmetic unit AU mainly implements arithmetic operation of data, and can implement modulo addition, modulo subtraction, modulo multiplication or modulo division operation of data with 16 bits or 32 bits of 2 operands, and output an operation result AU _ 0.
Further, the permutation unit PU, the circuit unit includes: 2 32-bit registers REG, 1 multiplexer MUX, 1 BENES network structure 64-bit replacement unit;
the in0, in1, in2 and in3 four paths of 16bit input data pass through the registers REG0 and REG1, the multiplexer MUX and the BENES network structure 64bit replacement unit to complete data replacement, and a replacement result PU _0 is output.
Further, the shift unit SU, the circuit unit includes: 2 32-bit registers REG, 1 multiplexer MUX, 1 shift register SH;
the in0, in1, in2 and in3 four paths of 16bit input data pass through the registers REG0 and REG1, the multiplexer MUX and the shift register to complete data shift, and a shift result SU _0 is output.
Further, the finite field multiplication unit GU, the circuit unit includes: 68bit static configuration register, finite field matrix multiplication circuit;
the finite field multiplication unit GU realizes finite field multiplication operation of data and GF (2)4) And (3) performing multiplication on the domain, inputting 16-bit data, and outputting the 16-bit data subjected to finite field multiplication.
A reconfigurable array facing to a lightweight block cipher algorithm is composed of a plurality of reconfigurable array units facing to the lightweight block cipher algorithm.
A processor, comprising: the reconfigurable array unit and array facing to the lightweight block cipher algorithm are used for finishing lightweight block cipher reconfiguration.
Compared with the prior art, the method at least achieves the following beneficial effects: the reconfigurable array unit and the array facing the lightweight block cipher algorithm have low power consumption, strong flexibility and good expandability, and solve the problem that the cipher processor chip in the prior art adopts an ASIC implementation mode of a special integrated circuit, and the flexibility and the expandability are very poor; the technical problem of low energy efficiency of the ISAP implementation mode of the microprocessor adopting the instruction set architecture.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a circuit structure diagram of a reconfigurable array unit facing a lightweight block cipher algorithm according to an embodiment of the present invention;
fig. 2 is a circuit structure diagram of a reconfigurable array unit LOU circuit oriented to a lightweight block cipher algorithm according to an embodiment of the present invention;
fig. 3 is a circuit structure diagram of a reconfigurable array unit S-box lookup table unit LUT facing to a lightweight block cipher algorithm according to an embodiment of the present invention;
fig. 4 is a circuit structure diagram of a reconfigurable array unit arithmetic unit AU facing to a lightweight block cipher algorithm provided in an embodiment of the present invention;
fig. 5 is a circuit structure diagram of a reconfigurable array unit replacement unit PU oriented to a lightweight block cipher algorithm according to an embodiment of the present invention;
fig. 6 is a circuit structure diagram of a reconfigurable array unit shift unit SU for a lightweight block cipher algorithm according to an embodiment of the present invention;
fig. 7 is a circuit structure diagram of a reconfigurable array unit finite field multiplication unit GU oriented to a lightweight block cipher algorithm according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a reconfigurable array facing a lightweight block cipher algorithm according to an embodiment of the present invention;
in the figure, an LOU-logic unit, an LUT-S box lookup table unit, an AU-arithmetic unit, a PU-permutation unit, an SU-shift unit, a GU-finite field multiplication unit, an MUX-multiplexer, and an REG-register;
an XOR-exclusive OR operation unit, an AND-AND operation unit, a RAM-random access memory, a BENES64-BENES network structure 64bit replacement unit AND an SH-shift register.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, a detailed description of a reconfigurable array unit and an array for a lightweight block cipher algorithm according to an embodiment of the present invention is provided below with reference to the accompanying drawings.
It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The embodiment of the invention discloses a reconfigurable array unit for a lightweight block cipher algorithm, which comprises: a logic unit LOU, an S-box lookup table unit LUT, an arithmetic unit AU, a replacement unit PU, a shift unit SU, a finite field multiplication unit GU, a multiplexer MUX and a register REG;
and after the logic unit LOU, the S box lookup table unit LUT, the arithmetic unit AU, the replacement unit PU, the shift unit SU and the finite field multiplication unit GU receive 16bit data and input, the arithmetic output of each functional unit is transmitted to the multiplexer MUX after the corresponding operation of the units is finished, and the reconstructed password data output is finished through the register REG.
Preferably, the logic unit LOU, the circuit unit includes: a first-level XOR operation unit, a second-level XOR operation unit, a first-level AND operation unit and a multiplexer;
the logic unit LOU is used for realizing the logic operation of data, 3 groups of 16-bit data in0, in1, in2, in0 and in1 are subjected to exclusive-or operation in a first-stage exclusive-or operation unit, and the operation result and in2 are subjected to exclusive-or operation in a second-stage exclusive-or operation unit; in0 and in1 are AND-operated in a primary AND operation unit;
the in0 and in1 are XOR-ed by the first stage XOR unit, and the XOR-ed result of in0 and in1 is XOR-ed by in2, and the XOR-ed result of in0 and in1 is MUX-ed to obtain the LOU _ 0.
Preferably, the S-box lookup table unit LUT, the circuit unit includes: four Random Access Memories (RAMs) and a Multiplexer (MUX);
the S-box lookup table unit LUT is used for realizing S-box lookup operation of data, the input 16-bit data in0 of the S-box lookup table unit LUT is divided into 4 groups of 4-bit I1, I2, I3 and I4, and meanwhile lookup operation is carried out in the RAM, and output results O1, O2, O3, O4, O1, O2, O3 and O4 are output to LUT _0 through a multiplexer MUX.
Preferably, the arithmetic unit AU, the circuit unit includes: 3 32-bit registers REG, 2 multiplexers, 1 AU arithmetic unit;
the arithmetic unit AU mainly implements arithmetic operation of data, and can implement modulo addition, modulo subtraction, modulo multiplication or modulo division operation of data with 16 bits or 32 bits of 2 operands, and output an operation result AU _ 0.
Preferably, the permutation unit PU, the circuit unit comprises: 2 32-bit registers REG, 1 multiplexer MUX, 1 BENES network structure 64-bit replacement unit;
the in0, in1, in2 and in3 four paths of 16bit input data pass through the registers REG0 and REG1, the multiplexer MUX and the BENES network structure 64bit replacement unit to complete data replacement, and a replacement result PU _0 is output.
Preferably, the shift unit SU, the circuit unit includes: 2 32-bit registers REG, 1 multiplexer MUX, 1 shift register SH;
the in0, in1, in2 and in3 four paths of 16bit input data pass through the registers REG0 and REG1, the multiplexer MUX and the shift register to complete data shift, and a shift result SU _0 is output.
Preferably, the finite field multiplication unit GU, the circuit unit includes: 68bit static configuration register, finite field matrix multiplication circuit;
the finite field multiplication unit GU realizes finite field multiplication operation of data and GF (2)4) And (3) performing multiplication on the domain, inputting 16-bit data, and outputting the 16-bit data subjected to finite field multiplication.
A reconfigurable array facing to a lightweight block cipher algorithm is composed of a plurality of reconfigurable array units facing to the lightweight block cipher algorithm.
A processor, comprising: the reconfigurable array unit and array facing to the lightweight block cipher algorithm are used for finishing lightweight block cipher reconfiguration.
Compared with the prior art, the method at least achieves the following beneficial effects: the reconfigurable array unit and the array facing the lightweight block cipher algorithm have low power consumption, strong flexibility and good expandability, and solve the problem that the cipher processor chip in the prior art adopts an ASIC implementation mode of a special integrated circuit, and the flexibility and the expandability are very poor; the technical problem of low energy efficiency of the ISAP implementation mode of the microprocessor adopting the instruction set architecture.
Through the above description of the embodiments, those skilled in the art will clearly understand that the embodiments of the present invention may be implemented by hardware, or by a combination of software and a necessary general hardware platform. Based on such understanding, the technical solutions of the embodiments of the present invention may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.), and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods according to the embodiments of the present invention.
Those skilled in the art will appreciate that the drawings are merely schematic representations of one preferred embodiment and that the blocks or flow diagrams in the drawings are not necessarily required to practice the present invention.
Those skilled in the art will appreciate that the modules in the devices in the embodiments may be distributed in the devices in the embodiments according to the description of the embodiments, and may be correspondingly changed in one or more devices different from the embodiments. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (9)

1. A reconfigurable array unit oriented to a lightweight block cipher algorithm is characterized by comprising: a logic unit (LOU), an S-box lookup table unit (LUT), an Arithmetic Unit (AU), a Permutation Unit (PU), a Shift Unit (SU) and a finite field multiplication unit (GU), a Multiplexer (MUX), a Register (REG);
the logic unit (LOU), the S box lookup table unit (LUT), the Arithmetic Unit (AU), the replacement unit (PU), the Shift Unit (SU) and the finite field multiplication unit (GU) receive 16bit data input, and after the corresponding operation of the units is completed, the operation output of each functional unit is transmitted to the Multiplexer (MUX), and the reconstructed password data output is completed through the Register (REG).
2. The reconfigurable array unit according to claim 1, wherein the logic unit (LOU), the circuit unit comprises: a first-level XOR operation unit, a second-level XOR operation unit, a first-level AND operation unit and a multiplexer;
the logic unit (LOU) is used for realizing the logic operation of data, 3 groups of 16-bit data in0, in1, in2, in0 and in1 are subjected to exclusive-OR operation in a first-stage exclusive-OR operation unit, and the operation result and in2 are subjected to exclusive-OR operation in a second-stage exclusive-OR operation unit; in0 and in1 are AND-operated in a primary AND operation unit;
the in0 and in1 are XOR-ed by the first stage XOR unit, and the XOR-ed result of in0 and in1 is XOR-ed by in2, and the XOR-ed result of in0 and in1 is MUX-ed to obtain the LOU _ 0.
3. The reconfigurable array unit of claim 1, wherein the S-box lookup table unit (LUT), circuit unit comprises: four Random Access Memories (RAMs), a Multiplexer (MUX);
the S-box lookup table unit (LUT) is used for realizing S-box lookup operation of data, 16-bit data in0 of the input S-box lookup table unit (LUT) is divided into 4 groups of 4-bit I1, I2, I3 and I4, meanwhile, lookup operation is carried out in the RAM, and output results O1, O2, O3, O4, O1, O2, O3 and O4 are obtained through a Multiplexer (MUX) to obtain a 16-bit result and output LUT _ 0.
4. The reconfigurable array unit according to claim 1, characterized in that the Arithmetic Unit (AU), the circuit unit comprises: 3 32-bit Registers (REG), 2 Multiplexers (MUX), 1 Arithmetic Unit (AU);
the Arithmetic Unit (AU) mainly realizes arithmetic operation of data, can realize modular addition, modular subtraction, modular multiplication or modular division operation of data with 16 bits or 32 bits of 2 operands, and outputs an operation result AU _ 0.
5. The reconfigurable array unit of claim 1, wherein the permutation unit PU, circuit unit comprises: 2 32-bit Registers (REG), 1 Multiplexer (MUX), 1 BENES network structure 64-bit permutation unit (BENES 64);
the in0, in1, in2 and in3 four paths of 16bit input data complete data replacement through the registers REG0 and REG1, the Multiplexer (MUX) and the BENES network structure 64bit replacement unit (BENES64), and a replacement result PU _0 is output.
6. The reconfigurable array unit according to claim 1, characterized in that the Shift Unit (SU), circuit unit comprises: 2 32-bit Registers (REG), 1 Multiplexer (MUX), 1 shift register (SH);
the in0, in1, in2 and in3 four paths of 16bit input data complete data shift through the registers REG0 and REG1, the Multiplexer (MUX) and the shift register, and a shift result SU _0 is output.
7. The reconfigurable array unit according to claim 1, characterized in that the finite field multiplication unit (GU), circuit unit comprises: 68bit static configuration register, finite field matrix multiplication circuit;
the finite field multiplication unit GU realizes finite field multiplication operation of data and GF (2)4) And (3) performing multiplication on the domain, inputting 16-bit data, and outputting the 16-bit data subjected to finite field multiplication.
8. A reconfigurable array facing a lightweight block cipher algorithm is characterized by comprising a plurality of reconfigurable array units facing the lightweight block cipher algorithm.
9. A processor, comprising: the reconfigurable array unit and array facing to the lightweight block cipher algorithm are used for finishing lightweight block cipher reconfiguration.
CN202011486285.6A 2020-12-16 2020-12-16 Reconfigurable array unit and array for lightweight block cipher algorithm Pending CN112613080A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113259088A (en) * 2021-05-19 2021-08-13 哈尔滨理工大学 Reconfigurable data path facing stream cipher algorithm
CN115037485A (en) * 2022-08-12 2022-09-09 北京智芯微电子科技有限公司 Method, device and equipment for realizing lightweight authentication encryption algorithm

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113259088A (en) * 2021-05-19 2021-08-13 哈尔滨理工大学 Reconfigurable data path facing stream cipher algorithm
CN113259088B (en) * 2021-05-19 2023-10-20 哈尔滨理工大学 Reconfigurable data path oriented to stream cipher algorithm
CN115037485A (en) * 2022-08-12 2022-09-09 北京智芯微电子科技有限公司 Method, device and equipment for realizing lightweight authentication encryption algorithm
CN115037485B (en) * 2022-08-12 2022-11-08 北京智芯微电子科技有限公司 Method, device and equipment for realizing lightweight authentication encryption algorithm

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