CN112583257A - Current mode DC-DC power converter and control method and controller thereof - Google Patents

Current mode DC-DC power converter and control method and controller thereof Download PDF

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Publication number
CN112583257A
CN112583257A CN202010964270.XA CN202010964270A CN112583257A CN 112583257 A CN112583257 A CN 112583257A CN 202010964270 A CN202010964270 A CN 202010964270A CN 112583257 A CN112583257 A CN 112583257A
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China
Prior art keywords
signal
current
slope
generate
output
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CN202010964270.XA
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Chinese (zh)
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D·罗密欧
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Priority claimed from US16/674,143 external-priority patent/US10985655B1/en
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Publication of CN112583257A publication Critical patent/CN112583257A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

Abstract

The invention discloses a current mode DC-DC power converter, a control method and a controller thereof. An exemplary embodiment is a method for operating a slope compensated current mode dc-to-dc converter, the method comprising: asserting a Pulse Width Modulation (PWM) signal in a switching period to couple an input voltage to an inductor; sensing an inductor current through an inductor to generate a sensed current signal; generating a slope compensation signal having a peak amplitude during the switching period; generating a slope offset signal based on a sum of a predetermined threshold and a product of a duty cycle of the PWM signal and the peak amplitude; and disabling the PWM signal during the switching period based on the sensed current signal and the slope offset signal.

Description

Current mode DC-DC power converter and control method and controller thereof
Technical Field
The present application relates to power converters, and in particular to current mode dc-to-dc power converters.
Background
Peak current limit protection is typically used with dc-to-dc converters to prevent damage that may be caused by excessive current. Conventional peak current limiting causes the output current to stop when the current exceeds the peak value. However, conventional peak current limiting can lead to instability and sub-harmonic regulation, especially where the duty cycle exceeds 50%. Slope compensation may be used to address some of the problems of conventional peak current limiting. However, conventional slope compensation may result in a reduction in accuracy, especially at relatively high duty cycles.
Disclosure of Invention
An exemplary embodiment is a method of operating a dc-to-dc converter, the method comprising: asserting a Pulse Width Modulation (PWM) signal in a switching period to couple an input voltage to an inductor; sensing an inductor current through the inductor to generate a sensed current signal; generating a slope compensation signal having a peak amplitude during a switching period; generating a slope offset signal based on a sum of a predetermined threshold and a product of a duty cycle of the PWM signal and the peak amplitude; and disabling the PWM signal during the switching period based on the sensed current signal and the slope offset signal.
The exemplary method may further comprise: generating a feedback signal using an output voltage of the dc-to-dc converter; generating an error signal as a difference between the feedback signal and the voltage reference signal; and clamping the error signal to not exceed the slope offset signal to define a clamped error signal. Disabling the PWM signal may also include disabling the PWM signal in response to the sensed current signal exceeding the clamp error signal.
In an exemplary method, disabling the PWM signal may further include disabling the PWM signal in response to the sensed current signal exceeding a difference of the slope offset signal and the slope compensation signal.
In an exemplary system, generating the slope compensation signal may further include integrating the resulting current over a switching period. Generating the slope offset signal may further include: averaging the PWM signal over time to determine a duty cycle from the PWM signal; and generating a slope offset signal using the duty cycle and the generation current. Generating the slope offset signal may further include: a dummy ramp signal is generated that is independent of the slope compensation signal. Generating the dummy ramp signal may include: generating a slope current proportional to the generation current; generating a slope signal using the slope current; sampling the slope signal using the PWM signal to generate a dummy ramp signal; and holding the dummy ramp signal as a slope offset signal.
Another exemplary embodiment is a power converter, comprising: an inductor defining a first lead and a second lead, the first lead defining an output node; a Field Effect Transistor (FET) defining a drain coupled to the second lead, a source coupled to a power source, and a gate; the FET is configured to selectively conduct current from a power supply to the inductor to energize the output node with the output voltage; a latch circuit defining a reset input and an output coupled to the gate of the FET, the latch circuit configured to generate a PWM signal on the output; a slope compensation circuit configured to generate a slope compensation signal having a peak amplitude during a switching period; an offset generating circuit configured to generate a slope offset signal based on a product of a duty cycle of the PWM signal and a peak amplitude of the slope compensation signal; and a comparator having a first input coupled to the sensed current signal, a second input coupled to the slope offset signal, and a comparison output coupled to the reset input of the latch circuit, the comparator configured to reset the latch circuit based on the sensed current signal and the slope offset signal during the switching period.
In an exemplary power converter, the offset generation circuit may further include: a ramp offset calculation circuit configured to provide an offset signal based on a product of a duty cycle of the PWM signal and a peak amplitude of the slope compensation signal; a threshold generator configured to provide a threshold signal representative of a predetermined threshold; and an adder defining a first signal input connected to the ramp offset calculation circuit for receiving the offset signal and a second signal input connected to the threshold generator for receiving the threshold signal, the adder being configured to generate the slope offset signal as a sum of the offset signal and the threshold signal.
The exemplary power converter may also include a compensation current source configured to generate a production current. The slope compensation circuit may be further configured to generate a slope compensation signal using the production current. The offset generation circuit may further include: a filter defining an input coupled to the output of the latch circuit for receiving the PWM signal, the filter configured to generate a duty signal indicative of a duty cycle of the PWM signal; and a signal generator configured to generate a slope offset signal using the duty signal and the generation current.
The exemplary power converter may also include a compensation current source configured to generate a production current. The slope compensation circuit uses the generated current to generate a slope compensation signal. The offset generation circuit may include: a current source defining a current output and configured to generate a slope current as a predetermined multiple of a resulting current; a dummy ramp generator defining an input coupled to the current source and a signal output, the dummy ramp generator configured to generate a slope signal on the signal output, the slope signal being independent of the slope compensation signal and having a slope equal to a slope of the slope compensation signal.
The exemplary power converter may further include: a feedback circuit defining an input coupled to the output node and configured to generate a feedback signal based on the output voltage; and an error amplifier defining a feedback input coupled to the feedback circuit for receiving the feedback signal, the error amplifier configured to generate an error signal using the feedback signal.
The exemplary power converter may also include a compensation current source configured to generate a production current. The slope compensation circuit may further include an integrating amplifier configured to integrate the resulting current over a switching period to generate a slope compensation signal.
Another example embodiment is a controller for a power converter, the controller comprising: a current sense terminal having a sensed current signal, a switch control terminal, and a feedback terminal; a slope compensation circuit configured to generate a slope compensation signal having a peak amplitude during a switching period; a latch circuit coupled to the switch control terminal, the latch circuit configured to energize the switch control terminal for a duty cycle that is a fraction of a switching period; and an offset generating circuit configured to generate a slope offset signal on an offset output, the slope offset signal being a sum of a predetermined threshold and a product of a duty cycle of the PWM signal and a peak amplitude of the slope compensation signal; the latch circuit is configured to de-energize the switch control terminal during the switching period based on the sensed current signal and the slope offset signal.
The exemplary controller may further include: an error amplifier configured to generate an error signal based on a difference between a reference voltage and a feedback signal from a feedback terminal; an error clamp configured to generate a clamped error signal using the lesser of the error signal and the slope offset signal. The latch circuit may be configured to de-energize the switch control terminal during the switching period based on the sensed current signal and the clamp error signal.
The example controller may also include a compensation current source configured to generate a production current. The slope compensation circuit may also include an integrating amplifier configured to integrate the resulting current over a switching period to generate a slope compensation signal.
The controller may also include a compensation current source configured to generate a production current. The slope compensation circuit may be configured to generate a slope compensation signal using the generation current. The offset generation circuit may further include: a filter defining an input coupled to the PWM signal, the filter configured to generate a duty signal indicative of a duty cycle of the PWM signal; and a signal generator configured to generate a slope offset signal using the duty signal and the generation current.
The example controller may also include a compensation current source configured to generate a production current. The slope compensation circuit may be configured to generate a slope compensation signal based on the generation current. The offset generation circuit may further include: a current source defining a current output and configured to generate a slope current as a predetermined multiple of a resulting current; and a dummy ramp generator defining an input coupled to the current source and a signal output, the dummy ramp generator configured to generate a slope signal on the signal output, the slope signal being independent of the slope compensation signal and having a slope equal to a slope of the slope compensation signal.
The exemplary controller may further include: an error amplifier defining an error output terminal and configured to generate an error signal on the error output terminal using a feedback signal from the feedback terminal; and an adder defining a first input coupled to the error output terminal for receiving the error signal and a second input coupled to the slope compensation circuit for receiving the slope compensation signal, the adder being configured to generate the slope error signal as a sum or a difference of the error signal and the slope compensation signal.
The example controller may also include an adder defining a first input coupled to the current sense terminal for receiving the sensed current signal and a second input coupled to the slope compensation circuit for receiving the slope compensation signal, the adder configured to generate the ramped sensed current signal as a sum or a difference of the sensed current signal and the slope compensation signal.
Drawings
For a detailed description of exemplary embodiments, reference will now be made to the accompanying drawings in which:
FIG. 1 illustrates a combined electrical schematic and block diagram of a DC-to-DC converter in accordance with at least some embodiments;
FIG. 2 illustrates an electrical schematic diagram of a slope compensation circuit in accordance with at least some embodiments;
FIG. 3 illustrates a combined block diagram and timing diagram in accordance with at least some embodiments;
FIG. 4 illustrates a timing diagram in accordance with at least some embodiments;
FIG. 5 illustrates a timing diagram in accordance with at least some embodiments;
FIG. 6 illustrates a controller of a power converter in accordance with at least some embodiments;
FIG. 7 illustrates an offset generation circuit in accordance with at least some embodiments;
FIG. 8 illustrates an offset generation circuit in accordance with at least some embodiments;
FIG. 9 illustrates a timing diagram in accordance with at least some embodiments;
FIG. 10 illustrates a timing diagram in accordance with at least some embodiments;
FIG. 11 illustrates a combined electrical schematic and block diagram of a current controlled DC to DC converter in accordance with at least some embodiments; and is
FIG. 12 illustrates method steps according to at least some embodiments.
Definition of
Various terms are used to refer to particular system components. Different companies may refer to a component by different names-this document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus, these terms should be interpreted to mean "including, but not limited to … …". Additionally, the terms "coupled" or "coupled" are intended to mean either an indirect connection or a direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.
"controller" shall refer, individually or in combination, to a single circuit component, an Application Specific Integrated Circuit (ASIC), a microcontroller with control software, a Digital Signal Processor (DSP), a processor with control software, or a Field Programmable Gate Array (FPGA) configured to read an input and drive an output in response to the input.
In the case of electrical devices, the terms "input" and "output" refer to electrical connections to the electrical devices and should not be considered verbs requiring operation. For example, the controller may have a gate output and one or more sense inputs.
Detailed Description
The following discussion is directed to various embodiments of the invention. While one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
Exemplary embodiments relate to a Direct Current (DC) to DC power converter for converting a DC input voltage V from a power sourceINIs converted into an output voltage V to be supplied to a loadOUT. The power source may be a battery or another power source or converter circuit, such as a Power Factor Correction (PFC) converter. More particularly, various exemplary embodiments relate to slope compensated current mode dc-to-dc power converters, referred to simply as current mode dc-to-dc converters.
A dc-to-dc power converter constructed in accordance with the present disclosure may provide several advantages over conventional designs. For example, the present disclosure may enable a dc-to-dc power converter that may achieve accurate current limiting in clock applications without sub-harmonic oscillation. A dc-to-dc power converter constructed in accordance with the present disclosure may provide cycle-by-cycle limiting by clamping an error amplifier for good recovery from unregulated. The control methods and circuits of the present disclosure may also be applied to current loop control in a dc-to-dc converter to control peak current in a clocked application (e.g., for a fixed frequency LED driver). This specification now describes an exemplary current mode dc-to-dc converter for the reader.
Fig. 1 shows a dc-to-dc converter, which may also be referred to as a dc-to-dc power converter. More specifically, fig. 1 illustrates a current-mode dc-to-dc converter 100 in accordance with at least some embodiments. The current-mode dc-to-dc converter 100 of fig. 1 is configured to control the flow of current from the input terminal 102 through the inductor 104 and utilize the output voltage VOUTThe output node 106 is powered on to provide power to a load 107 connected to the output node 106. In particular, the current-mode dc-to-dc converter 100 of fig. 1 includes a switching Field Effect Transistor (FET)108 to control the flow of current from the input terminal 102 to the inductor 104. The switching FET 108 is an example used in many cases; however, the switching FET 108 represents any device that may be used as an electrically controlled switch (e.g., a transistor, a junction transistor, a gallium nitride (GaN) High Electron Mobility Transistor (HEMT), a silicon carbide (SiC) device, other types of FETs, and a silicon controlled rectifier). Switch FET 108 has a drain 110 coupled to input terminal 102 and a source 112 coupled to a switch node 114. The switching FET 108 also has a gate 116. Inductor 104 defines a first lead 118 coupled to switch node 114 and a second lead 119 coupled to output node 106. The switching FET 108 is configured to couple the input voltage V in response to assertion of the gate 116INSelectively coupled to inductor 104.
The current-mode dc-to-dc converter 100 also includes a rectifier 120 defining a first rectifier leg 121 and a second rectifier leg 122. A first rectifier lead 121 is connected to switch node 114 and a second rectifier lead 122 is connected to a common or ground 123. More specifically, the rectifier 120 shown in fig. 1 is configured to conduct current from ground 123 to the switching node 114 while blocking current flow in the opposite direction. In at least some embodiments, and as shown in fig. 1, the rectifier 120 includes a single diode, although other rectifier arrangements (e.g., a switching rectifier) may be used. The exemplary current-mode dc-to-dc converter 100 also includes an input coupled across the output node 106 and ground 123And out of the capacitor 128. The output capacitor 128 makes the output voltage VOUTAnd (6) smoothing.
The feedback circuit 124 includes a feedback output 125 and an input terminal 126 connected to the output node 106 of the dc-to-dc converter 100. The feedback circuit 124 is configured to generate a feedback signal FB on a feedback output 125. In some embodiments, the feedback signal FB represents the output voltage Vout. For example, the feedback signal FB may have a voltage proportional to the output voltage Vout. The feedback circuit 124 may include, for example, a voltage divider and/or an amplifier to generate the feedback signal FB from the output voltage Vout. In some embodiments, the feedback signal FB represents the current provided by the dc-to-dc converter 100 to the load 107. The feedback circuit 124 may generate a feedback signal FB from the current using a current sensor (not shown) or by measuring a differential voltage across a shunt resistor (not shown) to measure the amount of current flowing through the shunt resistor. For example, in case the dc-dc converter 100 is configured as a Light Emitting Diode (LED) driver, a feedback signal FB representing the current may be used.
The current sensor 130 includes a current signal output 132. Current sensor 130 senses an input current I from input terminal 102INAnd generates a sensed current signal CS on the current signal output 132, wherein the sensed current signal CS is related to the input current IINAnd (4) in proportion. In the exemplary dc-to-dc converter 100 of fig. 1, the current sensor 130 includes a current pickup 134 coupled to a current amplifier 136 to generate a sensed current signal CS at the current signal output 132. The current amplifier 136 is based on the input current IINAnd a current sense gain resistor RfTo generate the current signal CS. The current pickup 134 may include an inductive coupling to carry the input current IINTo measure the input current IINThe coil of (2). The current pickup 134 and/or the current amplifier 136 may have other configurations (not shown) that may include, for example, a shunt resistor and/or a voltage divider comprising two or more resistors.
The gate driver 140 defines an input 141 and a driver output 142 connected to the gate 116 of the switching FET 108. The gate driver 140 is configured to energize the driver output 142 in response to assertion of the input 141 and thereby cause the switching FET 108 to be in a conductive state.
The current-mode dc-to-dc converter 100 also includes a latch circuit 144 defining a latch output 146 coupled to the gate 116 of the switching FET 108. More specifically, the latch output 146 of the latch circuit 144 is coupled to the input 141 of the gate driver 140 to direct the gate driver 140 to energize the driver output 142 and thereby cause the switching FET 108 to be in a conductive state. The latch circuit 144 also defines a set input 148 and a reset input 149. The latch circuit 144 is configured to drive and hold the latch output 146 in a validate condition (i.e., latching) in response to the set input 148 being validated. The latch circuit 144 is further configured to disable (i.e., unlatch) the latch output 146 in response to the reset input 149 being asserted. In at least some embodiments, and as shown in fig. 1, latch circuit 144 includes a set-reset (SR) circuit, although other arrangements (e.g., JK flip-flops) may be used. The set input 148 is coupled to a clock output of an oscillator circuit (not shown) for receiving a periodic clock signal clk. Latch circuit 144 thus generates a PWM signal ON at latch output 146bckAnd the PWM signal is ONbckAs a function of the frequency of the clock signal and the timing of the reset input 149.
Still referring to fig. 1, the current-mode dc-to-dc converter 100 further includes a comparator 150 defining a comparison output 152 connected to the reset input 149 of the latch circuit 144. Comparator 150 also defines a non-inverting input 154 and an inverting input 156. The non-inverting input 154 is connected to the current signal output 132 of the current sensor 130 for monitoring the sensed current signal CS therefrom. The comparator 150 is configured to pass the ramp error signal EA on the inverting input 156 in response to the sensed current signal CS on the non-inverting input 154 exceeding the ramp error signal EA on the inverting input 156rampThe comparison output 152 is asserted, so that the comparison signal CS is generated at the comparison output 152comp. Comparison signal CScompCausing the latch output 146 of the latch circuit 144 to fail, thereby causingThe switching FET 108 prevents current from flowing from the input terminal 102 to the inductor 104. This function defines the current control loop of the current mode dc-to-dc converter.
The first summer 158 defines an output 160 and has a clamping error signal EAclampAnd has a slope compensation signal VSCAnd a second input 164. The first adder 158 is configured to generate a ramp error signal EA on an output 160rampAs a clamping error signal EA from the first input 162clampAnd slope compensation signal V from second input 164SCThe difference of (a). In the example shown in fig. 1, the first adder 158 is configured to derive the clamping error signal EA fromclampSubtracting the positive offset slope compensation signal VSC. In other embodiments, the first adder 158 may be configured to add the negative offset slope compensation signal VSCAdded to the clamp error signal EAclampTo generate a ramp error signal EAramp。
The error amplifier 168 defines a clamp error output 170 coupled to the first input 162 of the first summer 158 to provide a clamp error signal EAclamp. Error amplifier 168 also defines a feedback input 171, a reference input 172, and a signal having a slope offset VSOClamp input 173. The feedback input 171 is configured to receive the feedback signal FB from the feedback output 125 of the feedback circuit 124, as indicated by the FB symbol at the feedback input 171. The reference input terminal 172 has a first reference voltage Vref1. In some embodiments, a reference signal generator (not shown) may reference a first reference voltage Vref1To the reference input 172 of the error amplifier 168. The error amplifier 168 is configured to be based on a first reference voltage Vref1And the feedback signal FB on the feedback input 171 to generate the error signal EA. This function defines the voltage control loop of the current mode dc-to-dc converter. Error amplifier 168 limits or clamps error signal EA to no more than slope offset signal VSOTo generate a clamp error signal EA on a clamp error output 170clamp。
The current-mode dc-to-dc converter 100 also includes a slope compensation circuit 174 that defines a clock input 175, a slope compensation output 176, and a ramp current output 178. The clock input 175 is coupled to a clock output of an oscillator circuit (not shown) for receiving a periodic clock signal clk, which is also provided to the set input 148 of the latch circuit 144. The slope compensation circuit 174 is thus ON with the PWM signalbckAnd (6) synchronizing. The slope compensation circuit 174 generates a slope compensation signal V on a slope compensation output 176SC. The slope compensation circuit 174 also provides a signal current I on a ramp current output 178rampWherein the signal current IrampAnd for generating a slope compensation signal VSCGenerating a current ISCAnd (4) in proportion. FIG. 2 illustrates an exemplary slope compensation circuit 174 that includes circuitry for using the generated current ISCGenerating a slope compensation signal VSCDetails of (a).
Still referring to fig. 1, the current-mode dc-to-dc converter 100 further includes an offset generation circuit 180 defining an offset output 182 and a current input 184, and a signal input 186. The current input 184 is connected to the ramp current output 178 of the slope compensation circuit 174 for receiving the signal current Iramp. The signal input 186 is coupled to the latch output 146 of the latch circuit 144 for monitoring the PWM signal ONbck. The offset generation circuit 180 is configured to use the signal current I on the offset output 182rampAnd PWM signal ONbckGenerating a slope offset signal VSO. Fig. 7 and 8 show two different exemplary embodiments 700, 800 of the offset generation circuit 180.
Still referring to fig. 1, offset generation circuit 180 includes a ramp offset calculation circuit 188 defining a first input 189, a second input 190, and a ramp having an offset signal D × VRCAIs offset from output 191. A first input 189 of the ramp offset calculation circuit 188 is coupled to the current input 184 of the offset generation circuit 180 for receiving the signal current Iramp. A second input 190 of the ramp offset calculation circuit 188 is coupled to the offset generationSignal input 186 of circuit 180 for receiving PWM signal ONbck. The ramp offset calculation circuit 188 is configured to calculate the ramp offset based on the signal current IrampAnd PWM signal ONbckGenerating an offset signal D × V on a ramp offset output 191RCA. The offset generation circuit 180 further includes a threshold generator 192 defining a reference terminal 193 and a threshold output terminal 194 having a value representative of a predetermined threshold Rf×IpeakThe threshold signal of (2). In the exemplary embodiment of fig. 1, threshold generator 192 is a voltage source, wherein reference terminal 193 is coupled to ground 123, and wherein predetermined threshold R isf×IpeakHaving a peak current I equal to that of the current mode DC-DC converter 100peakAnd a current sense gain resistor RfA constant voltage of the product of (a). Peak current IpeakIs the input current I of the current mode DC-DC converter 100INIs set. In some embodiments, the peak current IpeakMay have a fixed value.
Offset generation circuit 180 also includes an adder 196 defining a first signal input 197, a second signal input 198, and an output terminal 199 coupled to offset output 182 of offset generation circuit 180. A first signal input 197 is coupled to a threshold output terminal 194 of the threshold generator 192 for receiving a signal representing a predetermined threshold value Rf×IpeakThe threshold signal of (2). The second signal input 198 is coupled to the ramp offset output 191 of the ramp offset calculation circuit 188 for receiving the offset signal D × RCA. The adder 196 is configured to generate a slope offset signal VSOAs a predetermined threshold value Rf×IpeakAnd offset signal D x VRCAThe sum of (1). By using offset signals D x VRCAGenerating a slope offset signal VSOThe slope compensation signal V may be taken into account when controlling the current mode DC-DC converter 100SCCan be used to reduce or eliminate the effect of the slope compensation signal V that might otherwise be caused by the slope compensation signal VSCThe resulting inaccuracy.
FIG. 2 illustrates the power of the slope compensation circuit 174 in accordance with at least some embodimentsPrinciple diagram of qi. In particular, the exemplary slope compensation circuit 174 shown in fig. 2 includes an integrating amplifier 200 that defines a signal output 202 coupled to the slope compensation output 176 of the slope compensation circuit 174. The integrating amplifier 200 also defines a current input 204 and a reset input 206. The integrating amplifier 200 is configured to pass through during a switching period TswInternal pair generating current ISCIntegrate to generate a slope compensation signal V at the signal output 202SC. In particular, the integrating amplifier 200 includes an operational amplifier 208 having an output terminal 210, a non-inverting input 212, and an inverting input 214. The output terminal 210 of the operational amplifier 208 is coupled to the signal output 202, the non-inverting input 212 is connected to the signal ground, and the inverting input 214 is connected to the current input 204 of the integrating amplifier 200. The integrating amplifier 200 further comprises a ramp generating capacitor 216 having a capacitance value CrampAnd is connected between the current input 204 and the signal output 202. The integrating amplifier 200 also includes a reset switch 218 configured to selectively couple the current input 204 and the signal output 202 in response to assertion of the reset input 206. The reset switch 218 may include one or more FETs or other switching devices.
In operation, the ramp generating capacitor 216 generates a current ISCCharging at a constant rate to generate a slope compensation signal VSCThe slope compensation signal passes through a switching period TSWIncreasing at a constant rate as shown by curve 310 of fig. 3. Assertion of the clock signal clk corresponding to the switching period TswAnd (4) ending. At this time, the clock signal clk causes the reset switch 218 to short the ramp generation capacitor 216, resulting in the slope compensation signal VSCReset to zero volts. The clock signal clk takes effect for the transient pulse. When completed (i.e., when the clock signal clk fails), the subsequent switching cycle TswIs started and the slope compensation signal V isSCAnd again increased.
Referring again to fig. 2, the slope compensation circuit 174 further includes a compensation current source 230 defining a current input coupled to the integrating amplifier 200204, and a compensated source terminal 232. The compensation current source 230 is configured to supply a resulting current I to the current input 204 of the integrating amplifier 200 via a compensation source terminal 232SCAs a Direct Current (DC) with a constant value. Slope compensation circuit 174 also includes a ramp current source 234 that defines a ramp source terminal 236 coupled to a ramp current output 178 of slope compensation circuit 174. Ramp current source 234 is configured to supply a signal current I to ramp source terminal 236rampWherein the signal current IrampAnd for generating a slope compensation signal VSCGenerating a current ISCAnd (4) in proportion. In some embodiments, the signal current IrampIs equal to the generated current ISC. For example, ramp current source 234 may be configured as a current mirror to generate signal current I at ramp source terminal 236rampThe signal current is equal to the generation current I at the compensated source terminal 232SC。
Fig. 3 illustrates a combined block diagram and timing diagram in accordance with at least some embodiments. In particular, fig. 3 shows an oscillator circuit 300 defining a clock output 302 having a clock signal clk. FIG. 3 also shows a graph 310 that includes a line 312 of the clock signal clk over time with pulses 314 at regular intervals and defining a switching period T between successive ones of the pulses 314sw. Fig. 3 also shows the slope compensation signal VSCLine 318 over time in which the slope compensation signal V isSCWith a period T of switchingSWHas a constant slope 320 over each switching period T, andSWdefines a peak amplitude V during each switching cycle ofRCA. In particular, the peak amplitude VRCAIs a slope compensation signal VSCIn the switching period TSWCorresponds to the difference between the minimum and maximum values over one switching period.
Fig. 4 illustrates a timing diagram in accordance with at least some embodiments. In particular, FIG. 4 shows a graph 400 in which a line 402 represents the PWM signal ON over timebck. PWM signal ONbckWith switching period TswIs periodic and comprisesPWM signal ONbckAt a value equal to DxTswHas an effective voltage V for a time span1Where D is the duty cycle. Also, the PWM signal is ONbckIn the switching period TSWHas a failure voltage V for the rest of each switching cycle0. Thus, the duty cycle D is a fraction or number between zero and one that specifies the PWM signal ONbckEffective switching period TswOf the corresponding switching period.
Fig. 5 illustrates a timing diagram 500 in accordance with at least some embodiments. In particular, timing diagram 500 shows graph 502, graph 504, graph 506, and graph 508 all plotted on corresponding time axes. Graph 502 includes a graph illustrating a PWM signal ONbck Line 510 of (a). Curve 504 includes showing the comparison signal CScompLine 512. Graph 506 includes a line 514 that illustrates a clock signal clk. Curve 508 includes line 516, line 518, and line 520, all of which have a shared voltage scale. Line 516 shows the value of the sensed current signal CS over time. Line 518 shows the ramp error signal EA over timerampThe value of (c). Line 518 is included during switching period TswIs derived from the slope compensation signal V on each switching cycleSC Downward slope 524. In some embodiments, the downward slope 524 is at the switching period TswIs constant during each switching cycle. The downward slope 524 is compensated by a slope compensation signal VSCIs created (e.g., as shown in fig. 2). In some embodiments, downward slope 524 is equal to current sense gain resistance RfMultiplied by the output voltage VOUTThe negative of (c) is divided by the inductance L of inductor 104.
In operating the current mode DC to DC converter 100, and as shown in FIG. 5, the clock signal clk is at time t0A transient pulse 530 is defined. At time t0Time ON of PWM signalbckEffective and current is derived from input voltage VINFlows (i.e., from input terminal 102) to inductor 104, which causes sensed current signal CS to rise. Although not specifically shown in FIG. 5, the clock signal clk is at time t0The transient pulse 530 at also results in slope compensationCircuit 174 increases slope compensation signal VSCAs described by way of example in figures 2 to 3. Due to slave clamp error signal EAclampSubtracting the slope compensation signal VSCSo that the slope error signal EArampDecreasing over time. At time t1At this point, the sensed current signal CS first exceeds the ramp error signal EA detected by the comparator 150rampThereby causing the PWM signal to be ONbckFails and inhibits current flow from the input voltage VINFlows (i.e., from input terminal 102) to inductor 104. At time t1At this point, the sensed current signal CS drops to zero. The process itself at time t2With subsequent transient pulses 530 of the clock signal clk being repeated. The time difference between a given transient pulse 530 of the clock signal clk and the next consecutive transient pulse 530 of the clock signal clk defines the switching period Tsw. A given transient pulse 530 of the clock signal clk (e.g., time t)0) The sensed current signal CS first exceeds the ramp error signal EArampTime (e.g., time t)1) The time difference between is equal to D multiplied by TswWhere D is a PWM signal ONbckDuty cycle of, and TswIs a switching cycle.
Still referring to fig. 5, graph 508 also shows equality to the clamp error signal EAclampOf the first signal level V11Is lower than the first signal level V11Of the second signal level V12And below the second signal level V12Of the third signal level V13. Ramp error signal EArampIn the switching period TswHas a peak amplitude VEAAThe peak amplitude is equal to the switching period Tsw(i.e., the first signal level V)11) Period of the ramp error signal EArampWith the highest value of at the immediate time t3At switching period TSWBefore the end of switching period TSW(i.e., the third signal level V)13) Period of the ramp error signal EArampThe lowest value of the first signal difference 528. Because of the ramp error signal EArampIs a slope compensation signal VSCAnd a clamp error signal EAclampSum or difference ofAs a result, so the slope error signal EArampPeak amplitude V ofEAAAt least in the clamp error signal EAclampEqual to the slope compensation signal V during the time period when held constantSCPeak amplitude V ofRCA. In some embodiments, this may be provided by using the ramp error signal EArampOr slope compensation signal VSCDetermines the ramp error signal EArampPeak amplitude V ofEAAOr slope compensation signal VSCPeak amplitude VR ofCAAThe method of (1).
Curve 508 also shows the error signal EA as a clamp error signalclampOf the first signal level V11And a second signal level V12A second signal difference 529 of the difference between, wherein the sensed current signal CS is during the switching period TSWFirst exceeds the ramp error signal EA in a given one of the switching cyclesramp. The second signal difference 529 is equal to the duty cycle D multiplied by the ramp error signal EArampPeak amplitude V ofEAA。
Fig. 6 illustrates an example controller 600 for a power converter in accordance with at least some embodiments. The example controller 600 of FIG. 6 is similar to most of FIG. 1 and includes many of the same components. However, the example controller 600 of fig. 6 includes some differences from the current-mode dc-to-dc converter 100 shown in fig. 1. For example, a slope compensation signal VSC is added to the sensed current signal CS in the example controller 600 of FIG. 6, where the slope compensation signal VSCClamp error signal EA in current-mode DC-DC converter 100 from FIG. 1clampIs subtracted. In some embodiments, the exemplary controller 600 may take the form of a packaged integrated circuit, such as a single integrated circuit encapsulated in a packaging material, with various terminals electrically exposed through the packaging material. As shown in fig. 6, the example controller 600 defines a current sense terminal 602 configured to receive a sensed current signal CS representative of a current provided to an inductor in the dc-to-dc converter using the example 600. The example controller 600 also defines a circuit for controlling a switch, such as a power FET in a power converterSwitch control terminal 604. The example controller 600 also defines a feedback terminal 606 for receiving the feedback signal FB.
In particular, the example controller 600 of fig. 6 includes an oscillator circuit 300 that defines a clock output 302 having a clock signal clk. The oscillator circuit 300 within the exemplary controller 600 may be similar to or the same as the oscillator circuit 300 shown in fig. 3. The exemplary controller 600 also includes a gate driver 140 defining an input 141 and a driver output 142 connected to a switch control terminal 604. Gate driver 140 is configured to energize driver output 142 in response to assertion of input 141.
The example controller 600 also includes a latch circuit 144 defining a latch output 146 coupled to the input 141 of the gate driver 140. The latch circuit 144 also defines a set input 148 and a reset input 149. The latch circuit 144 is configured to drive and hold the latch output 146 in a validate condition (i.e., latching) in response to the set input 148 being validated. The latch circuit 144 is further configured to disable (i.e., unlatch) the latch output 146 in response to assertion of the reset input 149. In at least some embodiments, the latch circuit 144 includes a set-reset (SR) circuit, although other arrangements (e.g., JK flip-flops) may be used. The set input 148 is coupled to the clock output 302 of the oscillator circuit 300 for receiving the clock signal clk. Latch circuit 144 thus generates a PWM signal ON at latch output 146bckAnd the PWM signal varies with the timing of the reset input 149.
The exemplary controller 600 also includes a comparator 150 defining a comparison output 152 connected to the reset input 149 of the latch circuit 144. Comparator 150 also defines a non-inverting input 154 and an inverting input 156. The comparator 150 is configured to respond to a clamping error signal EA on a non-inverting input 154clampSensed current signal IS exceeding the ramp on inverting input 156compValidating the comparison output 152, thereby generating a comparison signal CS on the comparison output 152comp. Comparison signal CScompResulting in latch circuit 14The latch output 146 of 4 is disabled, thereby de-energizing the switch control terminal 604.
The example controller 600 also includes a slope compensation circuit 174 that defines a clock input 175 and a slope compensation output 176 and a ramp current output 178. The clock input 175 is coupled to the clock output 302 of the oscillator circuit 300 for receiving the clock signal clk. The slope compensation circuit 174 is thus ON with the PWM signalbckAnd (6) synchronizing. The slope compensation circuit 174 generates a slope compensation signal V on a slope compensation output 176SC. The slope compensation circuit 174 also provides a signal current I on a ramp current output 178rampWherein the signal current IrampAnd for generating a slope compensation signal VSCGenerating a current ISCAnd (4) in proportion. FIG. 2 illustrates an exemplary slope compensation circuit 174 that includes circuitry for using the generated current ISCGenerating a slope compensation signal VSCDetails of (a).
Still referring to fig. 6, the example controller 600 also includes an error amplifier 630 that defines an error output terminal 632 having an error signal EA. Error amplifier 630 further defines a first reference voltage Vref1 A feedback input 634 and a reference input 636. A feedback input 634 of the error amplifier 630 is coupled to the feedback terminal 606 of the controller 600 for monitoring the feedback signal FB. The error amplifier 630 is configured to be based on the first reference voltage Vref1The difference with the feedback signal FB from the feedback terminal 606 generates an error signal EA on the error output terminal 632. This function defines the voltage control loop of the current mode dc-to-dc converter. The reference generator 640 defines a reference output 642 coupled to the reference input 636 for providing a first reference voltage V to the error amplifier 630ref1。
The example controller 600 also includes an offset generation circuit 180 that defines an offset output 182, a current input 184, and a signal input 186. The current input 184 is connected to the ramp current output 178 of the slope compensation circuit 174 for receiving the signal current Iramp. The signal input 186 is coupled to the latch output 146 of the latch circuit 144 for monitoringPWM signal ONbck. The offset generation circuit 180 is configured to use the signal current I on the offset output 182rampAnd PWM signal ONbckGenerating a slope offset signal VSO。
Error clamp circuit 646 defines an error input 648 and a clamp input 650 and a clamp error output 652. Error input 648 is coupled to an error output terminal of error amplifier 630 for receiving error signal EA therefrom. The clamp input 650 is coupled to the offset output 182 of the offset generation circuit 180 for receiving the slope offset signal V therefromSO. A clamping error output 652 is coupled to the non-inverting input 154 of the comparator 150 for providing a clamping error signal EA theretoclamp. Error clamp 646 limits or clamps error signal EA to no more than slope offset signal V by limiting or clamping error signal EA toSOTo generate a clamp error signal EA on a clamp error output 652clamp。
Still referring to fig. 6, the example controller 600 further includes an adder 656, the adder 656 defining a first input 658 and a second input 660 and an adder output 662, the adder being connected to the inverting input 156 of the comparator 150 to provide thereto the ramped sensed current signal IScomp. A first input 658 of the adder 656 is connected to the current sense terminal 602 of the controller 600 for receiving the sensed current signal CS therefrom. A second input 660 of the adder 656 is connected to the slope compensation output 176 of the slope compensation circuit 174 for receiving therefrom a slope compensation signal VSC. The adder 656 compensates the current signal CS from the first input 658 and the slope compensation signal V from the second input 660 by summing the sensed current signal CSSCSummed or added to generate a ramped sensed current signal IS at adder output 662comp。
Fig. 7 illustrates a first exemplary embodiment 700 of the offset generation circuit 180 according to at least some embodiments. In particular, the offset generation circuit 180 includes a filter 704 defining an input 706 and an output 708. The input 706 is coupled to the signal input 186 of the offset generation circuit 180 for monitoring the PWM signal ONbck. Filter elementThe wave filter 704 is configured to generate a duty cycle signal D V on the output 708ref2Wherein the duty cycle signal is DxVref2Indicating PWM signal ONbckDuty cycle D of. More specifically, the duty cycle signal D × Vref2Equal to PWM signal ONbckIs multiplied by a second reference voltage Vref2. For example, when the duty cycle D has a value of 0.5, the voltage at the output 708 of the filter 704 is 0.5Vref2. Reference generator 712 defines a reference voltage having a second reference voltage Vref2Reference output 714. In some embodiments, reference generator 712 takes the form of a voltage source configured to provide a second reference voltage Vref2To match the duty cycle signal D x Vref2The scaling factor of (c).
Still referring to fig. 7, the offset generation circuit 180 further includes a first voltage-to-current converter 720 defining a voltage input 722 and a current output 724. A voltage input 722 is coupled to the output 708 of the filter 704 for receiving a duty cycle signal D × V in the form of a voltageref2. The first voltage-to-current converter 720 is configured to generate a duty cycle signal on the current output 724 corresponding to the voltage input 722D Vref2First current signal Iduty. Offset generation circuit 180 also includes a second voltage-to-current converter 730 defining a voltage input 732 and a current output 734. A voltage input 732 is coupled to the reference output 714 of the reference generator 712 for receiving a second reference voltage V from the reference output 714ref2. The second voltage-to-current converter 730 is configured to generate a second reference voltage V on the current output 734 corresponding to the voltage input 732ref2Second current signal Iref2。
The first exemplary embodiment 700 of the offset generation circuit 180 also includes a multiplier/divider circuit 740 defining a first current input 742, a second current input 744, a third current input 746, and a current signal output 748. In some implementations, the multiplier/divider circuit 740 is an analog circuit. More specifically, multiplier/divider circuit 740 may include one or more transconductance linear cellsOne or more of the transconductance linear cells may include bipolar-based devices. The first current input 742 is coupled to the current output 724 of the first voltage-to-current converter 720 for receiving the first current signal I therefromduty. A second current input 744 is coupled to the current output 734 of the second voltage-to-current converter 730 for receiving the second current signal I therefromref2. The third current input 746 is coupled to the current input 184 of the offset generating circuit 180 for receiving the signal current I therefromramp. The multiplier/divider circuit 740 is configured to generate the intermediate signal D × I at the current signal output 748 as followsramp: the first current signal I on the first current input terminal 742dutyMultiplied by the signal current I at the third current input 746rampAnd divided by the second current signal I at the second current input 744ref2。
The first exemplary embodiment 700 of the offset generation circuit 180 also includes a transimpedance amplifier 750 that defines a first signal input 752, a second signal input 754, and an output terminal 756. The first signal input 752 is coupled to a threshold output terminal 194 of a threshold generator 192 for receiving a signal representing a predetermined threshold value Rf×IpeakThe threshold signal of (2). In some embodiments, represents a predetermined threshold Rf×IpeakIs in the form of a voltage signal. A second signal input 754 of the transimpedance amplifier 750 is coupled to the current signal output 748 of the multiplier/divider circuit 740 for receiving therefrom the intermediate signal D × I in the form of a currentramp. An output terminal 756 of the transimpedance amplifier 750 is coupled to the offset output 182 for providing a slope offset signal V thereonSO. Transimpedance amplifier 750 is configured to generate slope offset signal V on output terminal 756 as followsSO: scaling, shifting intermediate signal DxIrampAnd the intermediate signal is D × IrampConverted to a voltage. More specifically, and as shown in FIG. 7, the transimpedance amplifier 750 includes an operational amplifier 760 that defines a non-inverting input 762, an inverting input 764, and a signal inputAn outlet end 766. The non-inverting input 762 is coupled to the first signal input 752; inverting input 764 is coupled to second signal input 754; and the signal output 766 is coupled to the output terminal 756 of the transimpedance amplifier 750. The bias resistor 770 includes a first lead 772 coupled to the second signal input 754 and a second lead 774 coupled to the signal output 766. In some embodiments, the resistance value of bias resistor 770 is equal to the switching period TSWDivided by for generating a slope compensation signal VSCThe capacitance value C of the ramp generating capacitor 216ramp. In some embodiments, and in particular at the signal current IrampIs equal to the generated current ISCIn the case of (3), the slope compensation signal V may be setSCPeak amplitude V ofRCADetermined as signal current IrampMultiplied by the switching period TSWAnd divided by the capacitance value C of the ramp generating capacitor 216ramp. By providing bias resistor 770 with a period equal to the switching period TSWDivide by the capacitance value C of the ramp generating capacitor 216rampThe intermediate signal D × IrampResulting in a voltage drop across the bias resistor 770 equal to the duty cycle D multiplied by the slope compensation signal VSCPeak amplitude V ofRCA。
Operational amplifier 760 of transimpedance amplifier 750 will drop the voltage across bias resistor 770 to a predetermined threshold R on non-inverting input 762f×IpeakSummed to provide a summed signal on signal output 766. Thus, operational amplifier 760 generates slope offset signal VSOAs Rf×Ipeak+D×VRCA。
Thus, transimpedance amplifier 750 operates in conjunction with multiplier/divider circuit 740 to form signal generator 780 configured to use a duty cycle D and generate a current ISCGenerating a slope offset signal VSO. More specifically, the signal generator 780 uses the duty signal D × Vref2(which indicates the duty cycle D) and the signal current Iramp(based on generating a current ISC) Generating a slope offset signal VSO。
FIG. 8 shows a method according to at leastA second exemplary embodiment 800 of the offset generation circuit 180 of some embodiments. In addition to the offset output 182, the current input 184, and the signal input 186 shown in the exemplary circuit of fig. 1, the second exemplary embodiment 800 of the offset generation circuit 180 also includes a clock input 802 for receiving a clock signal clk from the oscillator circuit 300. The offset generation circuit 180 includes a dummy ramp generator 810 configured to generate a slope signal VslopeThe slope signal has a dummy ramp slope 917 (FIG. 9) as a change in voltage over time equal to the slope compensation signal VSCConstant slope 320 (fig. 3). In some embodiments, and as shown in fig. 8, the dummy ramp generator 810 is configured as an integrating amplifier similar in design and function to that used to create the slope compensation signal V in the slope compensation circuit 174 (fig. 2)SCThe integrating amplifier 200.
In particular, the dummy ramp generator 810 defines a signal output 812, a current input 814, and a reset input 816. The dummy ramp generator 810 is configured to generate a dummy ramp by applying a voltage across the switching period TswUpper pair slope generating current IslopeIntegrate to generate a slope signal V on the signal output 812slope. The dummy ramp generator 810 includes an operational amplifier 818 having an output terminal 820, a non-inverting input 822, and an inverting input 824. The output terminal 820 of the operational amplifier 818 is coupled to the signal output terminal 812; the non-inverting input 822 is coupled to a threshold output terminal 194 of a threshold generator 192 for receiving a signal representing a predetermined threshold value Rf×IpeakA threshold signal of (a); and inverting input 824 is connected to current input 814 of dummy ramp generator 810. The dummy ramp generator 810 also includes a slope generation capacitor 826 connected between the current input 814 and the signal output 812 and having a capacitance value Cslope. The dummy ramp generator 810 also includes a reset switch 828 configured to selectively couple the current input 814 and the signal output 812 in response to assertion of the reset input 816. The reset switch 218 may include one or more FETs or othersA switching device.
In operation, the slope generating capacitor 826 generates a current I through the slopeslopeCharging at a constant rate to generate a slope signal VslopeThe slope signal passing through a switching period TswIncreasing at a constant rate. Assertion of the clock signal clk corresponding to the switching period TswAnd (4) ending. At this time, the clock signal clk causes the reset switch 828 to short the slope generating capacitor 826, resulting in the slope signal VslopeReset to zero volts. The clock signal clk takes effect for the transient pulse. When completed (i.e., when the clock signal clk fails), the subsequent switching cycle TswIs started and the slope signal VslopeAgain increasing.
Still referring to fig. 8, the bias generation circuit 180 further includes a dummy current source 830 defining a compensation source terminal 832 and a current reference terminal 834 coupled to the current input 184 of the bias generation circuit 180 to receive the signal current Iramp. The compensated source terminal 832 is coupled to the current input 814 of the dummy ramp generator 810. Dummy current source 830 is configured to generate a slope generation current IslopeAs an AND signal current IrampProportional constant current. Thus, the slope generates a current IslopeAlso generates a current ISCIs predetermined multiple of. In some embodiments, the slope generating current IslopeEqual to the signal current IrampAnd/or generating a current ISC. The dummy current source 830 provides a slope generation current I to the current input 814 of the dummy ramp generator 810 via a compensated source terminal 832slope。
The second exemplary embodiment 800 of the offset generation circuit 180 includes a sampling switch 838 configured to selectively couple the signal output 812 of the dummy ramp generator 810 with a sampling node 840 in response to a sampling signal phi1 to selectively utilize a slope signal VslopeSampling node 840 is powered on. The sampling switch 838 may include one or more FETs or other switching devices. The offset generation circuit 180 further includes a first hold capacitor 842, which is connected between the sampling node 840 and signal ground,for maintaining the sampling node 840 at a constant voltage when the sampling switch 838 is in a non-conductive state. Thus, the sampling switch 838 and the first holding capacitor 842 operate in combination to generate the dummy ramp signal V on the sampling node 840sample。
The second exemplary embodiment 800 of the offset generation circuit 180 also includes a hold switch 844 configured to selectively couple the sampling node 840 with the offset output 182 of the offset generation circuit 180 in response to the hold signal phi2 to selectively utilize the dummy ramp signal VsampleThe offset output 182 is energized. The hold switch 844 may include one or more FETs or other switching devices. The offset generation circuit 180 also includes a second holding capacitor 846 connected between the offset output 182 and signal ground for maintaining the offset output 182 at a constant voltage when the hold switch 844 is in a non-conductive state. Thus, the hold switch 844 and the first hold capacitor 842 operate in combination to generate the slope offset signal V on the offset output 182SO。
The second exemplary embodiment 800 of the offset generation circuit 180 further includes a sample-and-hold control circuit 850 defining a PWM input 852 coupled to the signal input 186 of the offset generation circuit 180 for monitoring the PWM signal ONbck. The sample and hold control circuit 850 also defines a first control output 856 coupled to the sampling switch 838 via a first control line 858 and configured to provide the sampling signal phi1 to drive the sampling switch 838 to a conductive state by asserting the sampling signal phi 1. The sample and hold control circuit 850 also defines a second control output 860 coupled to the hold switch 844 via a second control line 862 and configured to provide the hold signal phi2 to drive the hold switch 844 to the on state by asserting the hold signal phi 2.
Fig. 9 illustrates a timing diagram 900 in accordance with at least some embodiments. The timing diagram 900 of fig. 9 includes a graph 902, a graph 904, and a graph 906 plotted on corresponding time axes. Curve 902 includes a line 912, which is shown to be equal to the switchPeriod TswDefines the clock signal clk of the transient pulse 913. Graph 904 includes showing a PWM signal ONbck Line 914. Curve 906 includes a plot showing the slope signal VslopeLine 916 shows dummy ramp signal VsampleLine 918 and shows the slope offset signal VSOLine 920. In particular, FIG. 9 shows a slope signal V having a sawtooth waveformslopeThe sawtooth waveform having a period equal to the switching period TSWSimilar to the slope compensation signal V shown at line 318 of fig. 3SC. Slope signal VslopeFrom a predetermined threshold Rf×IpeakIncrease, wherein the dummy slope 917 at the switching period TSWIs kept constant, so that during the switching period TSWDefining a peak amplitude V during each switching cycle ofRCA。
FIG. 9 also shows when the PWM signal is ONbckUpon validation (e.g., at time t)0And t1In between), the dummy ramp signal VsampleWith slope signal VslopeIs increased and is ON at the PWM signalbckAt time of failure (e.g. at time t)1And t2In between), the dummy ramp signal VsampleAt or equal to a predetermined threshold Rf×IpeakAdding an offset signal DxVRCAIs kept constant at the value of (c). Equal to a predetermined threshold Rf×IpeakAdding an offset signal DxVRCAIs sampled and held by the second exemplary embodiment 800 of the offset generation circuit 180 to define a slope offset signal V shown on line 920SO. Dummy ramp signal V shown on line 918sampleIs the sampling switch 838 is ON in the PWM signalbckIn an ON condition when active and ON with a PWM signalbckAs a result of a non-conducting condition at failure. Fig. 9 also shows a slope offset signal VSODuring the whole switching period TSWThe internal is kept constant. Slope offset signal V shown on line 920SOIs to keep the switch 844 ON only for the PWM signalbckIn a conductive state and in a non-conductive state after a failure, thereby preventing the slope offset signal VSOAt PWM signal ONbckChanges when it is in effect.
Fig. 10 illustrates a timing diagram in accordance with at least some embodiments. In particular, fig. 10 shows a graph 1000 including plots showing PWM signal ON plotted ON corresponding time axesbck Line 1002, line 1004 showing the sample signal phi1, and line 1006 showing the hold signal phi 2. At time t0At PWM signal ONbckAnd sampled signal phi1 transition from a failed condition to an active condition. At time t1At PWM signal ONbckAnd sampled signal phi1 transition from the active condition to the inactive condition. At t1Shortly thereafter, time t10At this point, hold signal phi2 transitions from the disabled condition to the enabled condition. The hold signal phi2 remains in the active condition until time t11. At time t11Shortly thereafter, time t2Where the process repeats, where the PWM signal is ONbckAnd sampled signal phi1 to transition from the failure condition to the vitals condition.
Fig. 11 illustrates a combined electrical schematic and block diagram of a current controlled dc-to-dc converter 1100 in accordance with at least some embodiments. The current controlled dc-dc converter 1100 of fig. 11 is similar in construction and operation to the dc-dc converter 100 of fig. 1, except that it does not include the error amplifier 168 or the associated feedback signal FB. In contrast, the current-controlled dc-dc converter 1100 shown in fig. 11 is controlled by only the current loop.
In particular, the current controlled dc-dc converter 1100 shown in fig. 11 includes a first adder 158 defining a first input 162, which is similar to the first adder 158 in the dc-dc converter 100 of fig. 1, except that the first input 162 is directly coupled to the offset output 182 of the offset generation circuit 180 for receiving the slope offset signal V therefromSO. Thus, the ramp error signal EA generated by the first adder 158 and supplied to the non-inverting input 154 of the comparator 150rampIs based on a slope offset signal VSOSubtracting the ramp error signal EArampThe difference between them.
Fig. 12 illustrates a method of operating a dc-to-dc converter in accordance with at least some embodiments. Specifically, the method starts (block 1200) and includes: a Pulse Width Modulation (PWM) signal is asserted during a switching cycle to couple an input voltage to an inductor (block 1202). The method also includes sensing an inductor current through the inductor to generate a sensed current signal (block 1204). The method also includes generating a slope compensation signal having a peak amplitude during the switching period (block 1206). The method also includes generating a slope offset signal based on a sum of a predetermined threshold and a product of a duty cycle and a peak amplitude of the PWM signal (block 1208). The method concludes by disabling the PWM signal based on the sensed current signal and the slope offset signal during the switching period (block 1210). The method then ends (block 1212).
In some embodiments, the step of generating a slope offset signal further comprises: averaging the PWM signal over time to determine a duty cycle from the PWM signal; and generating a slope offset signal using the duty cycle and the generation current. These functions may be performed, for example, by offset generation circuitry such as the exemplary circuitry shown in fig. 7.
In some embodiments, the step of generating a slope offset signal further comprises: generating a dummy ramp signal independent of the slope compensation signal by: generating a slope current proportional to the generation current; generating a slope signal using the slope current; sampling the slope signal using the PWM signal to generate a dummy ramp signal; and holding the dummy ramp signal as a slope offset signal. These functions may be performed, for example, by offset generation circuitry such as the exemplary circuitry shown in fig. 8.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims (13)

1. A method of operating a dc-to-dc converter, the method comprising:
asserting a pulse width modulated PWM signal during a switching period to couple an input voltage to an inductor;
sensing an inductor current through the inductor to generate a sensed current signal;
generating a slope compensation signal having a peak amplitude during the switching period;
generating a slope offset signal based on a sum of a predetermined threshold and a product of a duty cycle of the PWM signal and the peak amplitude; and
disabling the PWM signal during the switching period based on the sensed current signal and the slope offset signal.
2. The method of claim 1, further comprising:
generating a feedback signal using an output voltage of the DC-to-DC converter;
generating an error signal as a difference between the feedback signal and a voltage reference signal; and
clamping the error signal to not exceed the slope offset signal to define a clamped error signal.
3. The method of claim 1, wherein disabling the PWM signal further comprises disabling the PWM signal in response to the sensed current signal exceeding a difference of the slope offset signal and the slope compensation signal.
4. The method of claim 1, wherein generating the slope compensation signal further comprises integrating a resulting current over the switching period.
5. A power converter, comprising:
an inductor defining a first lead and a second lead, the first lead defining an output node;
a Field Effect Transistor (FET) defining a drain coupled to the second lead, a source coupled to a power source, and a gate; the FET is configured to selectively conduct current from the power supply to the inductor to energize the output node with an output voltage;
a latch circuit defining a reset input and an output coupled to the gate of the FET, the latch circuit configured to generate a PWM signal on the output;
a slope compensation circuit configured to generate a slope compensation signal having a peak amplitude during a switching period;
an offset generation circuit configured to generate a slope offset signal based on a product of a duty cycle of the PWM signal and the peak amplitude of the slope compensation signal; and
a comparator having a first input coupled to a sensed current signal, a second input coupled to the slope offset signal, and a comparison output coupled to the reset input of the latch circuit, the comparator configured to reset the latch circuit based on the sensed current signal and the slope offset signal during the switching period.
6. The power converter of claim 5, further comprising:
a compensation current source configured to generate a production current;
wherein the slope compensation circuit is further configured to generate the slope compensation signal using the resulting current.
7. The power converter of claim 5, further comprising:
a feedback circuit defining an input coupled to the output node and configured to generate a feedback signal based on the output voltage; and
an error amplifier defining a feedback input coupled to the feedback circuit for receiving the feedback signal, the error amplifier configured to generate an error signal using the feedback signal.
8. The power converter of claim 5, further comprising:
a compensation current source configured to generate a production current; and is
Wherein the slope compensation circuit further comprises an integrating amplifier configured to integrate the resulting current over the switching period to generate the slope compensation signal.
9. A controller for a power converter, the controller comprising:
a current sense terminal having a sensed current signal, a switch control terminal, and a feedback terminal;
a slope compensation circuit configured to generate a slope compensation signal having a peak amplitude during a switching period;
a latch circuit coupled to the switch control terminal, the latch circuit configured to energize the switch control terminal for a duty cycle that is a portion of the switching period; and
an offset generation circuit configured to generate a slope offset signal on an offset output, the slope offset signal being a sum of a predetermined threshold and a product of the duty cycle of the PWM signal and the peak amplitude of the slope compensation signal; and is
Wherein the latch circuit is configured to power down the switch control terminal based on the sensed current signal and the slope offset signal during the switching period.
10. The controller of claim 9, further comprising:
an error amplifier configured to generate an error signal based on a difference between a reference voltage and a feedback signal from the feedback terminal;
an error clamp configured to generate a clamped error signal using the lesser of the error signal and the slope offset signal; and is
Wherein the latch circuit is configured to power down the switch control terminal based on the sensed current signal and the clamping error signal during the switching period.
11. The controller of claim 9, further comprising:
a compensation current source configured to generate a production current; and is
Wherein the slope compensation circuit further comprises an integrating amplifier configured to integrate the resulting current over the switching period to generate the slope compensation signal.
12. The controller of claim 9, further comprising:
a compensation current source configured to generate a production current;
wherein the slope compensation circuit is configured to generate the slope compensation signal using the generation current.
13. The controller of claim 9, further comprising:
an error amplifier defining an error output terminal and configured to generate an error signal on the error output terminal using a feedback signal from the feedback terminal; and
an adder defining a first input coupled to the error output terminal for receiving the error signal and a second input coupled to the slope compensation circuit for receiving the slope compensation signal, the adder configured to generate a slope error signal as a sum or a difference of the error signal and the slope compensation signal.
CN202010964270.XA 2019-09-27 2020-09-15 Current mode DC-DC power converter and control method and controller thereof Pending CN112583257A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962907252P 2019-09-27 2019-09-27
US62/907,252 2019-09-27
US16/674,143 2019-11-05
US16/674,143 US10985655B1 (en) 2019-09-27 2019-11-05 Peak current limit in a slope-compensated current mode DC-DC converter

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CN112583257A true CN112583257A (en) 2021-03-30

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