CN112564891B - Sequence cipher algorithm computing system based on feedback shift register array - Google Patents
Sequence cipher algorithm computing system based on feedback shift register array Download PDFInfo
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- CN112564891B CN112564891B CN202011444216.9A CN202011444216A CN112564891B CN 112564891 B CN112564891 B CN 112564891B CN 202011444216 A CN202011444216 A CN 202011444216A CN 112564891 B CN112564891 B CN 112564891B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/582—Pseudo-random number generators
- G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
- H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
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Abstract
The invention relates to the technical field of sequential cipher algorithm, and particularly discloses a feedback shift register array-based sequential cipher algorithm computing system, which comprises: the feedback shift register array comprises N rows of registers and M columns of registers, each register comprises a plurality of input data, wherein N is more than or equal to 2, M is more than or equal to 2, and N and M are both natural numbers; and each computing module is connected with the corresponding feedback shift register array, can perform computing according to a sequence cipher algorithm, and feeds back an obtained computing result to the corresponding feedback shift register array. The sequence cipher algorithm computing system based on the feedback shift register array can simultaneously give consideration to performance and flexibility.
Description
Technical Field
The invention relates to the technical field of sequential cipher algorithm, in particular to a feedback shift register array-based sequential cipher algorithm computing system.
Background
The sequential Cipher, also known as Stream Cipher (Stream Cipher), is one of symmetric Cipher algorithms. The sequence cipher has the characteristics of simple realization, convenient hardware implementation, high encryption and decryption processing speed, no or limited error propagation and the like, so the sequence cipher has advantages in practical application, particularly in special or confidential institutions, and typical application fields comprise wireless communication and external communication. Shannon in 1949 demonstrated that the cryptosystem with only one-time pad is absolutely secure, which gives strong support to the study of the sequential cryptographic technique.
At present, the variety of the sequence cipher algorithms is various, and the calculation mode, especially the key component feedback shift register, has the differences of bit width, length, feedback point and the like. When various types of sequence cipher algorithms need to be supported simultaneously, the two technical indexes of performance and flexibility are difficult to be considered at the same time.
Disclosure of Invention
The invention provides a sequence cipher algorithm computing system based on a feedback shift register array, which solves the problem that the performance and the flexibility can not be considered simultaneously in the related technology.
As an aspect of the present invention, there is provided a feedback shift register array-based sequential cipher algorithm computing system, comprising:
the feedback shift register array comprises N rows of registers and M columns of registers, each register comprises a plurality of input data, wherein N is more than or equal to 2, M is more than or equal to 2, and N and M are both natural numbers;
and each computing module is connected with the corresponding feedback shift register array, can perform computing according to a sequence cipher algorithm, and feeds back an obtained computing result to the corresponding feedback shift register array.
Further, the computing module and the feedback shift register array can be connected and combined in different ways to achieve different sequence cipher algorithm computations.
Furthermore, each computing module comprises P feedback computing arrays and Q taps connected with each feedback computing array, wherein P is more than or equal to 2, Q is more than or equal to 16, and P and Q are natural numbers, each feedback computing array can perform computing according to a sequence cipher algorithm, and an obtained computing result is fed back to a corresponding feedback shift register array.
Further, each of the computation modules includes 3 feedback operation arrays, and each of the feedback operation arrays is connected to 32 taps.
Further, one of the plurality of taps is connected to the corresponding feedback shift register array.
Further, one of the plurality of taps is connected to an output of the connected feedback operation array.
Further, the feedback shift register array comprises four feedback shift register arrays, each feedback shift register array comprises 8 rows of 32 columns of registers, the four feedback shift register arrays can form register chains with different lengths, and can simultaneously support a register chain with 1 bit and a register chain with 32 bits.
Further, each register comprises a register and a multiplexer connected with the register, wherein the multiplexer is used for selecting one input from various input data to be input into the register.
Further, each of the registers includes 4 kinds of input data, which are initialization input data, feedback input data, row input data, and column input data, respectively.
Further, the input data of the last register in the first feedback shift register array includes the feedback calculated data of all other feedback shift register arrays.
The feedback shift register array-based sequence cipher algorithm computing system provided by the invention is composed of a plurality of feedback shift register arrays, and each feedback shift register array corresponds to one computing module, so that the computing of various different sequence cipher algorithms can be realized, the performance of a unit area can be improved, and meanwhile, the flexibility is higher.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic structural diagram of a feedback shift register array-based sequential cipher algorithm computing system provided by the present invention.
Fig. 2 is a schematic diagram of an implementation structure of the feedback shift register array-based sequential cipher algorithm computing system for implementing a trivium sequential cipher algorithm.
Fig. 3 is a schematic structural diagram of a shift register array according to the present invention.
Fig. 4 is a schematic diagram of input and output of a register according to the present invention.
Fig. 5 is a diagram of the special feedback inputs of LFSR0 provided by the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this embodiment, a feedback shift register array based sequential cipher algorithm computing system is provided, and fig. 1 is a schematic structural diagram of a feedback shift register array based sequential cipher algorithm computing system according to an embodiment of the present invention, as shown in fig. 1, including:
the feedback shift register array comprises N rows of registers and M columns of registers, each register comprises a plurality of input data, wherein N is more than or equal to 2, M is more than or equal to 2, and N and M are both natural numbers;
and each computing module is connected with the corresponding feedback shift register array, can perform computing according to a sequence cipher algorithm, and feeds back an obtained computing result to the corresponding feedback shift register array.
In the embodiment of the present invention, as shown in fig. 1, the four feedback shift register arrays are illustrated as LFSR0, LFSR1, LFSR2, and LFSR3, and each of the feedback shift register arrays includes 8 rows and 32 columns of registers, and the four feedback shift register arrays can form register chains with different lengths and can simultaneously support a 1-bit register chain and a 32-bit register chain.
It should be understood that other combinations of feedback shift register arrays may be included, and may be selected as desired.
In the embodiment of the present invention, the four feedback shift register arrays may be used as two 128-bit register chains, or may be used as 8 32-bit shift register chains.
The feedback shift register array-based sequence cipher algorithm computing system provided by the embodiment of the invention is composed of a plurality of feedback shift register arrays, and each feedback shift register array corresponds to one computing module, so that the computing of various different sequence cipher algorithms can be realized, the performance of a unit area can be improved, and meanwhile, the computing system has higher flexibility.
Specifically, the computing module and the feedback shift register array can be connected and combined differently to realize different sequence cipher algorithm computations.
It should be understood that the feedback shift register arrays may be used in combination to build longer register chains. Meanwhile, the feedback shift register array can be used as a shift register component of a sequence cipher algorithm.
Specifically, each calculation module comprises P feedback operation arrays and Q taps connected with each feedback operation array, wherein P is larger than or equal to 2, Q is larger than or equal to 16, and both P and Q are natural numbers, each feedback operation array can perform calculation according to a sequence cipher algorithm, and an obtained calculation result is fed back to a corresponding feedback shift register array.
In the embodiment of the present invention, as shown in fig. 1, each of the computation modules includes 3 feedback operation arrays, and each of the feedback operation arrays is connected to 32 taps.
In an embodiment of the present invention, the configuration and control module is responsible for control of the entire computing system and configuration of the configuration information for each register.
Specifically, as shown in fig. 1, one of the taps is connected to the corresponding feedback shift register array.
Specifically, as shown in fig. 2, one of the plurality of taps is connected to the output terminal of the feedback operation array to which it is connected.
In the embodiment of the present invention, 4 register arrays may be cascaded into a longer register chain to meet the requirements of different sequential cipher algorithms, fig. 2 gives reference to the implementation of a trivium sequential cipher algorithm, a 288-bit shift register chain in the algorithm is implemented by using 3 arrays, where S1-S93 is implemented on a first array, S94-S177 is implemented on a second array, S178-S288 is implemented on a third array, and the calculation results t1, t2, and t3 of the feedback operation array are respectively input to the S7.31 register of each array.
In the embodiment of the present invention, as shown in fig. 3 to 5, each of the registers includes a register and a multiplexer connected to the register, and the multiplexer is configured to select one of a plurality of kinds of input data to be input to the register.
In the embodiment of the present invention, as shown in fig. 4, each of the registers includes 4 kinds of input data, which are initialization input data, feedback input data, row input data, and column input data, respectively.
As shown in fig. 5, the input data of the last register in the first feedback shift register array includes the feedback calculated data of all other feedback shift register arrays.
Specifically, the S7.31 register of LFSR0 is special in that its feedback input may be from 4 arrays to perform the feedback calculations on the calculated values.
In order to improve the flexibility of implementing the sequential cipher algorithm, the register array provided by the embodiment of the invention can simultaneously support shift register chains with 1 bit and 32 bits, so that the flexibility of implementing the sequential cipher algorithm is improved; the working mode of cascade connection of a plurality of arrays can be carried out, register chains with different lengths can be formed through cascade connection, the number of the register chains can be expanded, and a sequence cipher algorithm adopting a plurality of register chains can be realized. In summary, in the hardware implementation of the sequence cipher, the reconfigurable feedback shift register array provided by the invention can simultaneously support various different types of sequence cipher algorithms, and the flexibility is improved.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and scope of the invention, and such modifications and improvements are also considered to be within the scope of the invention.
Claims (8)
1. A sequential cipher algorithm computing system based on a feedback shift register array, comprising:
the feedback shift register array comprises N rows of registers and M columns of registers, each register comprises a plurality of input data, wherein N is more than or equal to 2, M is more than or equal to 2, and N and M are both natural numbers;
each computing module is connected with the corresponding feedback shift register array, can perform computing according to a sequence cipher algorithm, and feeds back an obtained computing result to the corresponding feedback shift register array;
each calculation module comprises P feedback operation arrays and Q taps connected with each feedback operation array, wherein P is more than or equal to 2, Q is more than or equal to 16, and both P and Q are natural numbers, each feedback operation array can calculate according to a sequence cipher algorithm and feed back the obtained calculation result to the corresponding feedback shift register array;
each of the registers includes 4 kinds of input data, which are initialization input data, feedback input data, row input data, and column input data, respectively.
2. The feedback shift register array based sequence cipher algorithm computing system of claim 1, wherein the computing module and the feedback shift register array can be connected and combined differently to realize different sequence cipher algorithm computations.
3. The feedback shift register array based sequence cipher algorithm computing system of claim 1, wherein each computing module comprises 3 feedback operation arrays, each feedback operation array connected with 32 taps.
4. The feedback shift register array based sequence cipher algorithm computing system of claim 1, wherein one of the plurality of taps is connected to a corresponding feedback shift register array.
5. The feedback shift register array based sequence cipher algorithm computing system of claim 1, wherein one of the plurality of taps is connected to an output of the connected feedback arithmetic array.
6. The feedback shift register array based sequence cipher algorithm computing system of claim 1, comprising four feedback shift register arrays, each comprising 8 rows and 32 columns of registers, the four feedback shift register arrays being capable of forming register chains of different lengths and capable of simultaneously supporting a 1-bit register chain and a 32-bit register chain.
7. The feedback shift register array based Sequence cipher arithmetic computing system of claim 1, wherein each of said registers comprises a register and a multiplexer coupled to said register, said multiplexer for selecting one of a plurality of input data to be input to said register.
8. The feedback shift register array based sequence cipher algorithm computing system of claim 1, wherein the input data of the last register in the first feedback shift register array comprises feedback calculated data of all other feedback shift register arrays.
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| CN202011444216.9A CN112564891B (en) | 2020-12-11 | 2020-12-11 | Sequence cipher algorithm computing system based on feedback shift register array |
| PCT/CN2020/139798 WO2022120999A1 (en) | 2020-12-11 | 2020-12-27 | Feedback shift register array-based sequence cipher algorithm computing system |
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| CN202011444216.9A CN112564891B (en) | 2020-12-11 | 2020-12-11 | Sequence cipher algorithm computing system based on feedback shift register array |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106254062A (en) * | 2016-10-12 | 2016-12-21 | 中国人民解放军信息工程大学 | Stream cipher realizes device and sequential cipher realization method thereof |
| CN107402744A (en) * | 2017-07-12 | 2017-11-28 | 东南大学 | A kind of restructural feedback shift register |
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| US8176394B2 (en) * | 2008-04-11 | 2012-05-08 | Mediatek Inc. | Linear feedback shift register structure and method |
| US8879733B2 (en) * | 2012-07-10 | 2014-11-04 | Infineon Technologies Ag | Random bit stream generator with guaranteed minimum period |
| CN104052595B (en) * | 2014-05-23 | 2017-02-08 | 戴葵 | Cryptographic algorithm customizing method |
| CN109426738B (en) * | 2017-08-23 | 2021-11-12 | 中芯国际集成电路制造(上海)有限公司 | Hardware encryptor, encryption method and electronic device |
| CN107786211B (en) * | 2017-09-26 | 2021-01-05 | 华中科技大学 | Algebraic structure obtaining method, encoding method and encoder of IRA-QC-LDPC code |
| CN109033596A (en) * | 2018-07-16 | 2018-12-18 | 成都吉纬科技有限公司 | Parallel pseudo-random sequences Generator Design method based on FPGA |
| CN110058842B (en) * | 2019-03-14 | 2021-05-18 | 西安电子科技大学 | Structure-variable pseudo-random number generation method and device |
| CN111767584B (en) * | 2020-06-09 | 2022-01-25 | 北京智芯微电子科技有限公司 | Safety microprocessor with built-in random number generator and safety chip |
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| CN106254062A (en) * | 2016-10-12 | 2016-12-21 | 中国人民解放军信息工程大学 | Stream cipher realizes device and sequential cipher realization method thereof |
| CN107402744A (en) * | 2017-07-12 | 2017-11-28 | 东南大学 | A kind of restructural feedback shift register |
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