CN112416823B - Sensor data read-write control method, system and chip in burst mode - Google Patents

Sensor data read-write control method, system and chip in burst mode Download PDF

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CN112416823B
CN112416823B CN202011274233.2A CN202011274233A CN112416823B CN 112416823 B CN112416823 B CN 112416823B CN 202011274233 A CN202011274233 A CN 202011274233A CN 112416823 B CN112416823 B CN 112416823B
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burst
read
write
fifo module
sensor data
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CN112416823A (en
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肖刚军
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Zhuhai Amicro Semiconductor Co Ltd
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Zhuhai Amicro Semiconductor Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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Abstract

Compared with the prior art, the invention controls the transmission of the sensor data transmitted by the FIFO module in the same burst access mode with the outside of the FIFO module according to the storage address of the FIFO module pointed by the read pointer of the FIFO module in the process of right shifting the storage address of the stored sensor data in the FIFO module, is not limited by the empty and full of the FIFO module, completes the sensor data transmission of burst transmission length from the address pointed by the read pointer in real time according to the data transmission requirement of the outside of the FIFO module, and triggers the stop data transmission flag bit in advance without the full writing or the empty reading of the FIFO module, thereby improving the real-time property of the data transmission sampled by the sensor and the efficiency of the system processing data.

Description

Sensor data read-write control method, system and chip in burst mode
Technical Field
The invention relates to the technical field of AHB bus read-write FIFO, in particular to a sensor data read-write control method, system and chip in burst mode.
Background
In the related art, in the existing FIFO working mode, when the length of the remaining data in the FIFO is less than 8 and greater than 1 in the process of performing read-write operation on the FIFO by using a burst mechanism, the external functional module cannot complete a burst read operation, and the FIFO can only wait until the last data in the FIFO is read by the functional module to generate a data read empty signal; when the residual data space in the FIFO is less than 8, the functional module cannot complete a burst write operation, and the FIFO can only wait until one written data makes the FIFO become full, and then can generate a data full signal. Therefore, in the process of reading and writing the FIFO by the AHB bus, the read-write operation can not be performed on the data of the FIFO completely according to the burst transmission length, so that the read-empty and write-full signals generated by the FIFO module can not effectively meet the control requirements of the functional module in the data block transmission state.
Disclosure of Invention
Aiming at the problem of data instantaneity of an AHB bus read-write FIFO, the invention discloses a sensor data read-write control method, a system and a chip under a burst mode, and the overlapping condition of read-write address areas is controlled through displacement, so that the data of the AHB bus burst read-write FIFO is controlled, and the aim of triggering and stopping a data transmission zone bit in advance without the need of filling or emptying a FIFO module under the condition of meeting the current data block transmission state is achieved, so that the instantaneity of data transmission of sensor sampling and the efficiency of system processing data are improved. The specific technical scheme is as follows:
A method for controlling the read-write of sensor data in burst mode includes: under the burst access mode of the same kind, controlling the storage address of the stored sensor data in the FIFO module to shift by n bits to the right, and simultaneously controlling the FIFO module to transmit the sensor data to the FIFO module under the burst access mode of the same kind until one sensor data moves to the pointing address of the most significant bit of the read pointer of the FIFO module or the pointing address of the most significant bit of the write pointer of the FIFO module, and then triggering the FIFO module to send out an empty/full mark signal outwards so as to stop the data receiving, transmitting and receiving between the outside and the FIFO module; where n is a logarithmic value of 2 as a base of burst transmission length of sensor data configured in the same type of burst access mode, and n is an integer greater than or equal to 1.
Compared with the prior art, in the process of right shifting of the storage address of the stored sensor data in the FIFO module, according to the storage address of the FIFO module pointed by the read pointer of the FIFO module, the transmission of the sensor data transmitted by the FIFO module in the burst access mode, which is the same as the outside of the FIFO module, is controlled, the transmission is not limited by the empty and full of the FIFO module, the sensor data transmission with burst transmission length is completed from the address pointed by the read pointer in real time according to the data transmission requirement of the outside of the FIFO module, and the data transmission stop zone bit is triggered in advance without the full or empty reading of the FIFO module, so that the real-time performance of the data transmission of the sensor sampling and the efficiency of the system processing data are improved.
Further, before the control FIFO module transmits the sensor data to the FIFO module in the burst access mode of the same type, writing the burst write command of the preset transmission times in the burst access mode of the same type into the write buffer in sequence, or writing the burst read command of the preset transmission times in the burst access mode of the same type into the read buffer in sequence; the FIFO module comprises a write buffer area and a read buffer area, or comprises a storage unit supporting multiplexing into the write buffer area and the read buffer area; the preset transmission times are the burst transmission times needed between the configured AHB bus and the FIFO module for completing the sampling processing of the sensor data currently needed, and the instructions configured by the same type of burst access mode are burst read commands and burst write commands; the burst transmission length is equal for each time; wherein the sensor data is stored in a set of data registers within the FIFO module. According to the technical scheme, a certain buffer area is added in the FIFO module to buffer the burst read command received by the AHB bus interface, so that whether the pointing address of the burst read command received subsequently overlaps with the storage address of the sensor data or not is judged, and therefore multiple small data volume accesses are combined and sent to one bus burst read command, and the data reading efficiency of the FIFO module is remarkably improved.
Further, when it is detected that one of the burst read commands has been written into the FIFO module and the read operation flag bit of the burst read command is valid, the read pointer of the FIFO module is controlled to start shifting left by 1 bit, the storage address of the sensor data stored in the FIFO module is controlled to start shifting right by n bits synchronously, when it is detected that there is an overlapping address segment between the pointing address of the read pointer of the burst read command after shifting left and the storage address of the sensor data in the data register set after shifting right, the sensor data on the address segment of one burst transmission length stored in the data register set is directly transmitted to the outside according to the pointing address of the read pointer currently participating in detection, and then the read pointer of the FIFO module is controlled to continue shifting left and keep the storage address of the sensor data to shift right synchronously until there is one sensor data shifted to the address pointed by the most significant bit of the read pointer of the FIFO module. In the technical scheme, when the FIFO module transmits sensor data outwards in a burst transmission length or reads the sensor data of the FIFO module in a burst transmission length externally, the read pointer of the burst read command moves leftwards and the storage address of the sensor data in the data register group synchronously moves rightwards, so that the sensor data of the burst transmission length required to be acquired by intercepting the burst read command of a continuous address or the burst read command on a discontinuous address is quickened, the time for occupying an advanced microcontroller bus structure (AMBA) bus is reduced, and the work of other modules is prevented from being influenced. In addition, the problem of increased system power consumption caused by the fact that the AHB continuously sends out read-write interrupt requests is solved.
Further, when one burst write command is detected to be written into the FIFO module and the write operation flag bit of the burst write command is valid, controlling the write pointer of the FIFO module to shift left by 1 bit, controlling the storage address of the sensor data stored in the FIFO module to synchronously shift right by n bits, when the address field where the pointing address of the write pointer of the burst write command after the left shift overlaps with the free storage address in the data register set is detected, directly writing the sensor data transmitted by the AHB bus into the address field of one burst transmission length stored in the data register set according to the pointing address of the write pointer currently participating in the detection, and then controlling the write pointer of the FIFO module to continue to shift left and keep the storage address of the sensor data to synchronously shift right until one sensor data moves to the address pointed by the most significant bit of the write pointer of the FIFO module.
Compared with the prior art, each time a burst write operation is executed, the write pointer of the FIFO module is controlled to continue to move left and keep the storage address of the sensor data to move right synchronously, the writable space of the data register group is quickened, the sensor data with a plurality of burst transmission lengths required by writing is quickened, the control requirement of the functional module of the FIFO module in a data block transmission state is effectively met under a burst mechanism, the time of occupying an advanced microcontroller bus structure (AMBA) bus is reduced, and the transmission efficiency of the FIFO module is improved.
Further, when the invalid read operation flag bit of one burst read command is detected, writing the burst read command into a fault tolerant buffer zone, stopping externally reading sensor data on an address pointed by a read pointer included in the burst read command, waiting until the starting address pointed by the read pointer of a new burst read command with the valid read operation flag bit is detected to be overlapped with the starting address pointed by the read pointer of the burst read command with the invalid read operation flag bit, and directly transmitting the sensor data on the corresponding address stored in the data register group to the functional module according to the read pointer of the burst read command with the invalid read operation flag bit; wherein the FIFO module further comprises a fault tolerant buffer. When the burst read command is detected to be invalid, the technical scheme still uses the starting address pointed by the read pointer of the invalid burst read command to directly transmit the sensor data to the functional module without restarting new burst read operation, thereby realizing the effect of accessing and combining multiple small data volume and transmitting one bus read/burst write command.
Further, when the write operation flag bit of one burst write command is detected to be invalid, after the write operation flag bit of the burst write command is waited to become valid, the sensor data transmitted by the AHB bus is written into the data register group according to the write pointer included in the burst write command. The number of times of repeatedly initiating new burst write operation is avoided, and the waste of system resources can be effectively reduced for burst write commands of discontinuous addresses.
The sensor data read-write control system in burst mode includes FIFO module, AHB interface module, read-write control module and functional module; the FIFO module is a dual-port memory supporting read-write multiplexing, the AHB interface module and the functional module are electrically connected with the FIFO module, the FIFO module is used for carrying out data transmission operation according to a read pointer and a write pointer in the FIFO module, and the AHB interface module is used for receiving burst write commands or burst read commands of preset transmission times under the same burst access mode; the AHB interface module and the functional module are electrically connected with the read-write control module, the read-write control module is used for controlling the storage address of the stored sensor data in the FIFO module to shift right by n bits under the same burst access mode, and simultaneously controlling the FIFO module to transmit the sensor data to the FIFO module under the same burst access mode until one sensor data moves to the most significant bit of the read pointer of the FIFO module or the most significant bit of the write pointer of the FIFO module, and then triggering the FIFO module to send out an empty/full mark signal outwards so as to stop the data receiving and transmitting between the AHB interface module and the FIFO module and stop the data receiving and transmitting between the functional module and the FIFO module.
Compared with the prior art, in the process that the storage address of the stored sensor data in the FIFO module moves rightwards, according to the storage address of the FIFO module pointed by the read pointer of the FIFO module each time, the control FIFO module and the AHB interface module and the function module respectively carry out one-time burst read transmission or burst write transmission of the sensor data under the same burst access mode, the sensor data read-write control system is not limited by the empty and full states of the FIFO module, and completes the sensor data transmission with burst transmission length from the address pointed by the read pointer in real time according to the data transmission requirement outside the FIFO module in real time, and the data transmission stop flag bit is triggered in advance without the full writing or the empty reading of the FIFO module, so that the real-time performance of the data transmission sampled by the sensor and the efficiency of system processing data are improved.
Further, the FIFO module comprises a read buffer and a data register set for storing sensor data; the read-write control module is used for controlling the read pointer of the FIFO module to move left and controlling the storage address of the sensor data stored in the data register group to synchronously move right until one sensor data moves to the most significant bit of the read pointer of the FIFO module when one burst read command is written into the read buffer area and the read operation zone bit of the burst read command is valid, wherein the address pointed by the read pointer of the burst read command is in the access address range of the address line of the data register group; and the read-write control module is also used for directly transmitting the sensor data on the address field of one burst transmission length stored in the data register group to the functional module according to the pointing address of the read pointer when the fact that the pointing address of the read pointer of the read command after the left shift and the storage address of the sensor data in the data register group after the right shift are overlapped is detected on the premise that the read operation flag bit of the burst read command in the read buffer area is valid. According to the technical scheme, the read buffer area is added in the FIFO module to buffer the read burst command received by the AHB bus interface, so that the read-write control module can access and send multiple small data volume to the technical effect of sending one bus burst read command by judging whether the address pointed by the read burst command received subsequently overlaps with the storage address of the sensor data, and the read data efficiency of the FIFO module is obviously improved.
Further, the FIFO module comprises a write buffer and a data register set for storing sensor data; the read-write control module is used for controlling the write pointer of the FIFO module to move left and controlling the storage address of the sensor data stored in the data register group to synchronously move right until one sensor data moves to the most significant bit of the write pointer of the FIFO module when one burst write command is written into the FIFO module and the write operation zone bit of the burst write command is valid, wherein the address pointed by the write pointer of the burst write command is in the access address range of the address line of the data register group; and the read-write control module is also used for directly writing the sensor data transmitted by the AHB bus into an address segment of a burst transmission length stored in the data register group according to the pointing address of the writing pointer when the fact that the pointing address of the writing pointer of the burst writing command after the left shift is overlapped with the idle storage address in the data register group is detected on the premise that the writing operation flag bit of the burst reading command in the reading buffer area is valid.
Compared with the prior art, each time the AHB interface module executes a burst write operation, the read-write control module controls the write pointer of the FIFO module to continue to move leftwards and keep the storage address of sensor data to move rightwards synchronously, the writable space of the data register group is strived for once after each burst write operation, the sensor data with a plurality of burst transmission lengths required by writing is quickened until one sensor data moves to the most significant bit of the write pointer of the FIFO module, the control requirement of the functional module in the data block transmission state is effectively met by the FIFO module under a burst mechanism, the time of occupying an advanced microcontroller bus structure (AMBA) bus is reduced, and the transmission efficiency of the FIFO module is improved.
A chip is an SOC chip, and the sensor data read-write control system is embedded in the chip. The chip can trigger the stop data transmission flag bit in advance without the need of full writing or empty reading of the FIFO module, thereby improving the instantaneity of the transmission processing of the data in the chip and the efficiency of the chip for processing the data.
Drawings
Fig. 1 is a schematic diagram of a burst read embodiment of a method for controlling read/write of sensor data in burst mode according to the present invention.
Fig. 2 is a schematic diagram of a method for controlling reading and writing of sensor data in burst mode according to a burst writing embodiment of the present invention.
Fig. 3 is a schematic diagram of a sensor data read-write control system in burst mode according to the present disclosure.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings. Each module in the following embodiments is a logic circuit unit, and one logic circuit unit may be one physical unit, or may be a state machine formed by combining a plurality of logic devices according to a certain read-write timing and signal logic change, or may be a part of one physical unit, or may be implemented by combining a plurality of physical units. In addition, in order to highlight the innovative part of the present invention, elements that are not so close to solving the technical problem presented by the present invention are not introduced in the present embodiment, but it does not indicate that other elements are not present in the present embodiment.
The embodiment of the invention discloses a sensor data read-write control method in a burst mode, which comprises the following steps: in the same burst access mode, the storage address of the stored sensor data in the FIFO module is controlled to shift to the right by n bits, and the FIFO module is controlled to transmit the sensor data to the FIFO module in the same burst access mode until one pointing address of the most significant bit of the read pointer of the FIFO module or the pointing address of the most significant bit of the write pointer of the FIFO module exists, namely: there is a shift of the memory address of the sensor data to coincide with the pointing address of the most significant bit of the read pointer of the FIFO module, which overflows the memory space of the FIFO module if the right shift continues (the address range to which the read pointer or the write pointer can point); there is a shift of the memory address of the sensor data to coincide with the pointing address of the most significant bit of the write pointer of the FIFO module, which memory address of the FIFO module if continued to shift right is insufficient free memory space for accommodating the sensor data of the burst transfer length to be written. Triggering the FIFO module to send out an empty/full mark signal outwards to stop the data receiving and transmitting between the outside and the FIFO module, wherein the data receiving and transmitting signal is equivalent to that the FIFO does not wait until the last data in the FIFO is read by the functional module and then generates a data reading empty signal, or equivalent to that the FIFO does not wait until one written data causes the FIFO to become full; where n is a logarithmic value of burst transmission length of sensor data configured in the same type of burst access mode, where n is an integer greater than or equal to 1, and when the depth of the FIFO module is an m-th power of 2, the m-th power of 2 is greater than the n-th power of 2. It should be noted that, the burst transmission length in the same burst access mode may be any one of 4, 8, and 16, and this burst transmission length is set to be unchanged, and in the same burst access mode, the burst transmission length of each burst access is configurable. Compared with the prior art, in the process of right shifting of the storage address of the stored sensor data in the FIFO module, according to the storage address of the FIFO module pointed by the read pointer of the FIFO module, the transmission of the sensor data transmitted by the FIFO module in the burst access mode, which is the same as the outside of the FIFO module, is controlled, the transmission is not limited by the empty and full of the FIFO module, the sensor data transmission with burst transmission length is completed from the address pointed by the read pointer in real time according to the data transmission requirement of the outside of the FIFO module, and the data transmission stop zone bit is triggered in advance without the full or empty reading of the FIFO module, so that the real-time performance of the data transmission of the sensor sampling and the efficiency of the system processing data are improved.
Preferably, before the control FIFO module transmits the sensor data to the FIFO module in the burst access mode of the same type, the burst write commands of the preset transmission times in the burst access mode of the same type are sequentially written into the write buffer, or the burst read commands of the preset transmission times in the burst access mode of the same type are sequentially written into the read buffer; only the burst write command or the burst read command with the preset transmission times is written into the corresponding buffer area, and the data of the burst read command or the data of the FIFO module transmitted by the burst write command are not written into the same buffer area. The FIFO module comprises a write buffer area and a read buffer area, or comprises a storage unit supporting multiplexing into the write buffer area and the read buffer area; the preset transmission times are the burst transmission times needed between the configured AHB bus and the FIFO module for completing the sampling processing of the sensor data currently needed, the instructions configured by the same type of burst access mode are burst read commands and burst write commands, a read pointer for reading data stored in the FIFO module is arranged under the burst read commands, and a write pointer for writing into the FIFO module is arranged under the burst write commands; the burst transmission length of each time initiated in the burst access mode of the same type is equal, and the information can be preconfigured by a special register in the FIFO module; wherein the sensor data is stored in a set of data registers within the FIFO module. In the embodiment, a certain buffer area is added in the FIFO module to buffer the burst read command received by the AHB bus interface, so as to determine whether the address pointed by the burst read command received subsequently overlaps with the storage address of the sensor data, thereby realizing that multiple small data accesses are combined and sent to one bus burst read command, and remarkably improving the data reading efficiency of the FIFO module.
On the basis of the foregoing embodiment, the method for controlling reading and writing of sensor data further includes: when the current triggering FIFO module sends out an empty/full mark signal, the external current data receiving and transmitting with the FIFO module are stopped, and if the execution times of burst write commands and the execution times of burst read commands in the same burst access mode are detected to have no preset transmission times, the steps are repeatedly executed, so that the sensor data currently required by the sampling processing is completed.
It should be noted that FIFO is an abbreviation of english FIRST IN FIRST Out, which is a first-in first-Out dual-port buffer, i.e., the first data entered therein is first shifted Out, wherein one of the input ports of the memory is the output port of the memory, and the other port is the output port of the memory. The FIFO memory is different from the normal memory in that no external read-write address line is provided, so that the FIFO memory is very simple to use, can only sequentially write data, and sequentially read data, the data address of which is completed by the foregoing read pointer and the foregoing write pointer traversal, and cannot be decided by the address line to read or write a certain designated address like the normal memory. In this embodiment, FIFO memories are widely used in order to increase the sensor data transmission rate, process a large number of sensor data streams acquired in real time, and match sensor devices having different transmission rates, thereby improving system performance. For a monolithic FIFO, there are mainly two structures: trigger guide structure and zero guide transmission structure. The FIFO of the trigger-directed transport structure is constituted by a register set and the FIFO of the zero-directed transport structure is constituted by a dual-port RAM with read and write address pointers.
As an embodiment, as shown in fig. 1, an embodiment of the present invention discloses a method for controlling reading and writing of sensor data in burst mode, which specifically includes the steps of:
step S101, writing burst read commands of the preset transmission times in the same burst access mode into a read buffer area of the FIFO module in sequence, and then entering step S102. The bus addresses of the burst read commands may be discontinuous or continuous, but the starting addresses of the bus addresses of the burst read commands are not necessarily the same, for example, one of the burst read commands may initiate a burst read access to the OxO to Ox07 memory address segment of the FIFO module where the sensor data is stored, i.e. the starting memory address of the bus address of the burst read command is configured to OxO. It is advantageous to merge multiple configured bus burst read commands to initiate only 1 burst read command.
It should be noted that, the burst read command includes a start address, a data valid flag bit, a read operation flag bit of the burst read command, and a burst transmission length, and is stored in a special register; the sensor data stored in the data register group in the FIFO module are associated with the data valid flag bit, and the number of the read buffer areas opened up by the FIFO module is not limited; preferably, when the valid flag bit of the data written in the read buffer area is valid, the sensor data stored in the address corresponding to the data register set is effectively burst-read.
Step S102, after detecting that one burst read command is written into the read buffer area opened by the FIFO module, judging whether the read operation flag bit of the burst read command is valid, if yes, entering step S104, otherwise, entering step S103. The read operation flag bit of the burst read command is refreshed in real time by software according to the AHB bus environment, and determines when to start burst read operation on the sensor data stored in the FIFO module.
Step S104, the read pointer of the control FIFO module starts to shift left by 1 bit, the storage address of the sensor data stored in the control FIFO module starts to shift right by n bits synchronously, and then step S105 is performed. In step S104, the burst transfer length in the same burst access mode is 8, and before starting burst reading sensor data once, the read pointer of the FIFO module is added one, i.e. the address value pointed by the read pointer is shifted one bit to the left, for example, the read pointer is shifted from r_addr [00100] to r_addr [01000]; meanwhile, the storage address of the sensor data stored in the FIFO module is controlled to synchronously shift right by 3 bits instead of 8 bits (corresponding to burst transmission length) specified by the read-write of the existing AHB bus, and the high 3 bits on the storage address after the right shift are zero-padded, so that the value of the storage address after the right shift is kept unchanged, and the sensor data stored on the address pointed by the read pointer is quickened to be burst-transmitted without being limited by continuous addresses and discontinuous addresses.
Step S105, judging whether there is an address pointed by the most significant bit of the read pointer of the sensor data moving to the FIFO module, if yes, proceeding to step S108, otherwise proceeding to step S107. The step S105 determines the condition that the right shift of the storage address of the sensor data is finished, that is, the address pointed by the most significant bit of the read pointer of the FIFO module to which the sensor data is moved, which may be the address pointed by the most significant bit of the read pointer after the left shift, or the address pointed by the most significant bit of the read pointer to which the left shift has not occurred, where the most significant bit is: the rightmost bit "1" of the read pointer is located, i.e. the second bit of r_addr [00010] is the most significant bit, so as to avoid that the data of a burst transmission length, which is required to be read by the read pointer in a burst, has overflowed the memory space of the FIFO module.
Step S107, judging whether the address of the read pointer of the burst read command after the left shift in step S104 and the storage address of the sensor data in the data register set after the right shift in step S104 have overlapped address segments, if yes, proceeding to step S109, otherwise, returning to step S104. By judging whether the overlapped address fields exist, the sensor data read in multiple bursts is enabled to be effective, the combination of the multiple burst read commands into one burst read operation is realized, and meanwhile, the data with one burst transmission length of the burst read required by the read pointer is prevented from overflowing the memory space of the FIFO module.
Step S108, triggering the FIFO module to send out an empty mark signal to stop the external data transmission with the FIFO module, which is equivalent to: and as long as the step S104 repeatedly executes the left shift operation of not more than the preset transmission times, the storage address of the sensor data in the data register set is shifted to the right to the address pointed by the most significant bit of the read pointer of the burst read command, that is, the sensor data stored in the data register set is correspondingly shifted to the right to the address pointed by the most significant bit of the read pointer of the burst read command, the FIFO does not need to wait until the last data in the FIFO is read by the functional module to generate a data read empty signal, and the FIFO is not required to read empty to trigger the stop data transmission flag bit in advance, thereby improving the real-time performance of the sensor sampling data transmission and the efficiency of system processing data.
Step S109, according to the start address pointed by the read pointer currently participating in judgment, directly (without restarting a new burst read operation) transmitting the sensor data on the address segment of one burst transmission length stored in the data register set from this start address to the outside of the FIFO module, regarding as the sensor data of one burst transmission length stored in the FIFO module is read by the outside burst, returning to step S104, judging by maintaining the shift traversal of the read pointer, and completing the burst reading of the sensor data of the next burst transmission length from the FIFO module according to the steps S104 to S109. For example, a burst length is 8, the overlapping address fields in step S108 are address fields from Ox01 to Ox08, and from the start address Ox01, the read pointer initiates a data read access to the address fields from Ox01 to Ox08 to the FIFO module, and sequentially reads 3 bytes of sensor data.
Step S103, writing the burst read command with invalid read operation flag bit judged in step S102 into the fault-tolerant buffer area, stopping external reading of the sensor data on the address pointed by the read pointer included in the burst read command, and then entering step S106. The FIFO does not need to wait until the last data in the FIFO is read by the functional module to generate a data read empty signal, and the FIFO module does not need to read empty to trigger in advance to stop the data transmission flag bit, so that the real-time performance of the sensor for sampling data transmission and the data processing efficiency of the system are improved.
Step S106, judging whether the start address pointed by the read pointer of the new burst read command with the valid read operation flag bit is overlapped with the start address pointed by the read pointer of the burst read command with the invalid read operation flag bit in step S103, if yes, entering step S109, otherwise, returning to step S101. The new burst read command with valid read operation flag bit is detected in step S102 and written into the read buffer of the FIFO module, and the corresponding read pointer is set to point to the address matching the data register set in the FIFO module, where the sensor data is stored in the data register set in the FIFO module. The start address pointed by the read pointer of the burst read command with invalid read operation flag bit in step S103 is the start address pointed by the read pointer of the burst read command that is written in last or judged last (step S103 performs the judging operation of not more than the preset number of transmission times). Therefore, when the burst read command is detected to be invalid, the sensor data is still directly transmitted to the functional module from the starting address pointed by the read pointer of the invalid burst read command, and a new burst read operation is not required to be restarted, so that the effect of accessing and sending a plurality of small data volume to a bus read/burst write command is realized.
In the embodiment shown in fig. 1, when the FIFO module transmits sensor data outwards with a burst transmission length or reads sensor data of the FIFO module with a burst transmission length externally, the read pointer of the burst read command moves leftwards and the memory address of the sensor data in the data register set moves rightwards synchronously, so that the burst transmission length of the sensor data required to be acquired for intercepting the burst read command of a continuous address or the burst read command on a discontinuous address is quickened, the time for occupying an advanced microcontroller bus structure (AMBA) bus is reduced, and the work of other modules is prevented from being influenced. In addition, the problem of increased system power consumption caused by the fact that the AHB continuously sends out read-write interrupt requests is solved.
As another embodiment, as shown in fig. 2, an embodiment of the present invention discloses a method for controlling reading and writing of sensor data in burst mode, which specifically includes the steps of:
Step S201, writing burst write commands of the same type of burst access mode with preset transmission times into a write buffer of the FIFO module in sequence, and then entering step S202. The bus addresses of the burst write commands may be discontinuous or continuous, but the starting addresses of the bus addresses of the burst write commands are not necessarily identical, for example, one of the burst write commands may initiate burst write access to the OxO to Ox07 memory address segment storing the sensor data inside the FIFO module, i.e. the starting memory address of the bus address of the burst write command is configured to OxO. It is advantageous to merge multiple configured bus burst write commands to initiate only 1 burst write command.
It should be noted that, the burst write command includes a start address, a data valid flag bit, a write operation flag bit of the burst write command, and a burst transmission length, and is stored in a special register; the sensor data stored in the data register group in the FIFO module are associated with the data valid flag bit, and the number of the write buffer areas opened up by the FIFO module is not limited; preferably, when the valid flag bit of the data written in the write buffer area is valid, the sensor data transmitted by the AHB bus is effectively burst-written on the corresponding address of the data register set.
Step S202, after detecting that one burst write command is written into the write buffer area opened by the FIFO module, judging whether the write operation flag bit of the burst write command is valid, if yes, entering step S203, otherwise, entering step S208. The writing operation flag bit of the burst writing command is refreshed in real time by software according to the AHB bus environment, and determines when to start burst writing operation on the data register group in the FIFO module.
Step S203, the write pointer of the control FIFO module starts to shift left by 1 bit, the storage address of the sensor data stored in the control FIFO module starts to shift right by n bits synchronously, and then step S204 is entered. In step S203, the burst transfer length in the same burst access mode is 8, and before the burst write sensor data is turned on once, the write pointer of the FIFO module is added one, i.e. the address value pointed by the write pointer is shifted one bit to the left, e.g. the write pointer is shifted from r_addr [00100] to r_addr [01000]; meanwhile, the storage address of the stored sensor data in the FIFO module is controlled to synchronously shift right by 3 bits instead of writing the specified 8 bits (corresponding to burst transmission length) by the existing AHB bus, and the upper 3 bits on the storage address after the right shift are zero-padded, so that the value of the address after the right shift is kept unchanged, and the sensor data stored on the address pointed by the write pointer is quickened to be burst-transmitted without being limited by continuous addresses and discontinuous addresses.
Step S204, judging whether there is an address pointed by the most significant bit of the write pointer of the sensor data moving to the FIFO module, if yes, proceeding to step S206, otherwise proceeding to step S205. The step S204 determines the condition that the right shift of the storage address of the sensor data is finished, that is, the address pointed by the most significant bit of the write pointer of the FIFO module to which the sensor data is shifted, which may be the address pointed by the most significant bit of the write pointer after the left shift, or the address pointed by the most significant bit of the write pointer to which the left shift has not occurred, where the most significant bit is: the rightmost bit "1" of the write pointer is located, i.e. the second bit of w_addr [00010] is the most significant bit, so that it is avoided that data with a burst transmission length of burst writing required by the write pointer is not accommodated in enough memory space.
Step S205, judging whether the address field of the write pointer of the burst write command after the left shift in step S204 is overlapped with the free storage address in the data register group exists, if yes, proceeding to step S207, otherwise returning to step S203. In this embodiment, the memory address originally occupied by the sensor data in the right shifted data register set may become free. In this embodiment, by determining whether there is an overlapping address segment, the sensor data written in multiple bursts is enabled to be valid, so as to combine multiple burst write commands into one burst write operation, and meanwhile, in order to avoid that the data with a burst transmission length of burst write required by the write pointer is not enough to be accommodated in the memory space of the FIFO module.
Step S206, triggering the FIFO module to send out a full flag signal to stop the external and the FIFO module from receiving and transmitting data, which is equivalent to: if step S203 repeatedly performs the left shift operation with the number of times not more than the preset number of times, the storage address of the sensor data in the data register set is shifted to the right to the address pointed by the most significant bit of the write pointer of the burst write command, that is, when the sensor data stored in the data register set is correspondingly shifted to the right to the address pointed by the most significant bit of the write pointer of the burst write command, the FIFO does not need to wait until the inside of the FIFO is fully written by the functional module to generate the data full signal, and the FIFO is not required to be fully written by the functional module to trigger the stop data transmission flag bit in advance, thereby improving the real-time performance of the transmission of the sensor sampled data and the efficiency of the system processing data.
Step S207, according to the start address pointed by the write pointer currently participating in judgment, from this start address, the AHB bus transmits sensor data on an address segment with a burst transmission length to the data register group (without restarting a new burst write operation) inside the FIFO module, and regards the AHB bus as writing sensor data with a burst transmission length into the FIFO module in a burst manner, then returns to step S203, and completes writing sensor data with a next burst transmission length into the FIFO module according to the foregoing steps S203 to S207 by maintaining the write pointer shift traversal judgment. For example, a burst length is 8, the overlapping address field in step S205 is a free address field from Ox01 to Ox08, and the read pointer initiates a data write access to the FIFO module from the start address Ox01 to Ox08, and sequentially writes 3 bytes of sensor data.
Step S208, judging whether the write operation flag bit of the burst write command with the invalid write operation flag bit in step S202 is valid, if yes, proceeding to step S207, otherwise, delaying waiting until the write operation flag bit of the burst write command with the invalid write operation flag bit is valid. In this embodiment, the burst write command is detected in step S202 and written to the write buffer of the FIFO module, and the corresponding write pointer is set to point to the free address matching the data register set in the FIFO module. The start address pointed by the write pointer of the burst write command with the invalid write operation flag bit in step S202 is the start address pointed by the write pointer of the burst write command that is written or judged up to date (step S202 performs the judgment operation of not more than the preset number of transmission times). When the burst write command is detected to be effective again, the sensor data acquired by the AHB bus is directly written into the FIFO module from the starting address pointed by the write pointer of the burst write command without restarting new burst write operation, so that the number of times of repeatedly starting the new burst write operation is avoided, and the waste of system resources can be effectively reduced for the burst write command with discontinuous address.
In the embodiment shown in fig. 2, each time a burst write operation is executed, the write pointer of the FIFO module is controlled to continue to move left and keep the memory address of the sensor data to move right synchronously, the writable space of the data register set is strived for in the specified burst transmission time sequence, the sensor data with a plurality of burst transmission lengths required by writing is quickened, the control requirement of the FIFO module for a functional module in a data block transmission state is effectively met under a burst mechanism, the time of occupying an advanced microcontroller bus structure (AMBA) bus is reduced, and the transmission efficiency of the FIFO module is improved.
It is to be understood that when each read-write operation zone bit is set, the level of the read-write operation zone bit is low, and the level of the read-write operation zone bit is high, and the level of the read-write operation zone bit is invalid; the method may be such that the method is determined to be invalid when the level of the read/write operation flag bit is low, and the method is determined to be valid when the level of the read/write operation flag bit is high. The remaining valid identification bits are also similar and are not limited herein.
Aiming at the problem of data instantaneity of the AHB bus read-write FIFO, a further embodiment of the invention discloses a sensor data read-write control system in a burst mode, and the overlapping condition of read-write address areas is controlled through displacement, so that the data of the AHB bus burst read-write FIFO is controlled, and the aim of triggering and stopping data transmission flag bits in advance without the need of full or empty writing of a FIFO module under the condition of meeting the current data block transmission state is achieved, so that the instantaneity of data transmission of sensor sampling and the efficiency of system processing data are improved.
As shown in fig. 3, the sensor data read-write control system comprises a FIFO module, an AHB interface module, a read-write control module and a functional module; the FIFO module is a dual-port memory supporting read-write multiplexing, the AHB interface module and the functional module are electrically connected with the FIFO module, the FIFO module is used for carrying out data transmission operation according to a read pointer and a write pointer in the FIFO module, and the AHB interface module is used for receiving burst write commands or burst read commands of preset transmission times under the same burst access mode; the AHB interface module and the functional module are electrically connected with the read-write control module, the read-write control module is used for controlling the storage address of the stored sensor data in the FIFO module to shift right by n bits under the same burst access mode, and simultaneously controlling the FIFO module to transmit the sensor data to the FIFO module under the same burst access mode until one sensor data moves to the most significant bit of the read pointer of the FIFO module or the most significant bit of the write pointer of the FIFO module, and then triggering the FIFO module to send out an empty/full mark signal outwards so as to stop the data receiving and transmitting between the AHB interface module and the FIFO module and stop the data receiving and transmitting between the functional module and the FIFO module. Compared with the prior art, in the process that the storage address of the stored sensor data in the FIFO module moves rightwards, according to the storage address of the FIFO module pointed by the read pointer of the FIFO module each time, the control FIFO module and the AHB interface module and the function module respectively carry out one-time burst read transmission or burst write transmission of the sensor data under the same burst access mode, the sensor data read-write control system is not limited by the empty and full states of the FIFO module, and completes the sensor data transmission with burst transmission length from the address pointed by the read pointer in real time according to the data transmission requirement outside the FIFO module in real time, and the data transmission stop flag bit is triggered in advance without the full writing or the empty reading of the FIFO module, so that the real-time performance of the data transmission sampled by the sensor and the efficiency of system processing data are improved.
As shown in fig. 3, the FIFO module includes a read buffer and a data register set for storing sensor data; the read-write control module is used for controlling the read pointer of the FIFO module to move left and controlling the storage address of the sensor data stored in the data register group to synchronously move right until one sensor data moves to the most significant bit of the read pointer of the FIFO module when one burst read command is written into the read buffer area and the read operation zone bit of the burst read command is valid, wherein the address pointed by the read pointer of the burst read command is in the access address range of the address line of the data register group; and the read-write control module is also used for directly transmitting the sensor data on the address field of one burst transmission length stored in the data register group to the functional module according to the pointing address of the read pointer when the fact that the pointing address of the read pointer of the read command after the left shift and the storage address of the sensor data in the data register group after the right shift are overlapped is detected on the premise that the read operation flag bit of the burst read command in the read buffer area is valid. The specific burst read mode implemented by the read-write control module to control the FIFO module refers to the foregoing embodiment of fig. 1, and is not described herein again. According to the embodiment, the read buffer area is added in the FIFO module to buffer the read burst command received by the AHB bus interface, so that the read-write control module can access and send multiple small data volume to the technical effect of sending one bus burst read command by judging whether the address pointed by the read burst command received subsequently overlaps with the storage address of the sensor data, and the read data efficiency of the FIFO module is obviously improved.
As shown in fig. 3, the FIFO module includes a write buffer and a data register set for storing sensor data; the read-write control module is used for controlling the write pointer of the FIFO module to move left and controlling the storage address of the sensor data stored in the data register group to synchronously move right until one sensor data moves to the most significant bit of the write pointer of the FIFO module when one burst write command is written into the FIFO module and the write operation zone bit of the burst write command is valid, wherein the address pointed by the write pointer of the burst write command is in the access address range of the address line of the data register group; and the read-write control module is also used for directly writing the sensor data transmitted by the AHB bus into an address segment of a burst transmission length stored in the data register group according to the pointing address of the writing pointer when the fact that the pointing address of the writing pointer of the burst writing command after the left shift is overlapped with the idle storage address in the data register group is detected on the premise that the writing operation flag bit of the burst reading command in the reading buffer area is valid. The specific burst writing manner of the FIFO module for controlling the read-write control module refers to the embodiment of fig. 2, and is not described herein. Compared with the prior art, each time the AHB interface module executes a burst write operation, the read-write control module controls the write pointer of the FIFO module to continue to move leftwards and keep the storage address of sensor data to move rightwards synchronously, the writable space of the data register group is strived for once after each burst write operation, the sensor data with a plurality of burst transmission lengths required by writing is quickened until one sensor data moves to the most significant bit of the write pointer of the FIFO module, the control requirement of the functional module in the data block transmission state is effectively met by the FIFO module under a burst mechanism, the time of occupying an advanced microcontroller bus structure (AMBA) bus is reduced, and the transmission efficiency of the FIFO module is improved.
Based on the foregoing embodiment, a chip is also disclosed, which is an SOC chip, and the sensor data read-write control system is embedded. The chip can trigger the stop data transmission flag bit in advance without the need of full writing or empty reading of the FIFO module, thereby improving the instantaneity of the transmission processing of the data in the chip and the efficiency of the chip for processing the data. It is noted that, the foregoing read-write control module is used as a main state machine, and the logic control circuits set in other modules are used as sub-state machines, where the main state machine is composed of a state register and a combinational logic circuit, and is used for configuring a start address, a data valid flag bit, a read operation flag bit of a burst read command, a burst transmission length, and a read-write pointer in the FIFO according to a special register, and scheduling the automatic operation of the sub-state machines in batches, so as to realize burst transmission between the AHB interface module and the functional module after the storage address of the sensor data is shifted, where all the functional unit modules related in the embodiment of the invention are composed of digital operation circuits.
In the embodiments provided in the present application, it should be understood that the disclosed system and chip may be implemented in other manners. For example, the system embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Claims (8)

1. The method for controlling the reading and writing of the sensor data in the burst mode is characterized by comprising the following steps of:
Under the burst access mode of the same kind, controlling the storage address of the stored sensor data in the FIFO module to shift by n bits to the right, and simultaneously controlling the FIFO module to transmit the sensor data to the FIFO module under the burst access mode of the same kind until one sensor data moves to the pointing address of the most significant bit of the read pointer of the FIFO module or the pointing address of the most significant bit of the write pointer of the FIFO module, and then triggering the FIFO module to send out an empty/full mark signal outwards so as to stop the data receiving, transmitting and receiving between the outside and the FIFO module;
wherein n is a logarithmic value of burst transmission length of sensor data configured in the same type of burst access mode, wherein the logarithmic value is based on 2, and n is an integer greater than or equal to 1; the instructions configured by the burst access modes of the same type are burst read commands and burst write commands;
When detecting that one burst read command is written into the FIFO module and the read operation flag bit of the burst read command is valid, controlling the read pointer of the FIFO module to start shifting left by 1 bit, controlling the storage address of the sensor data stored in the FIFO module to synchronously start shifting right by n bits, when detecting that the address of the read pointer of the burst read command after shifting left and the storage address of the sensor data in the data register group after shifting right have overlapped address segments, directly transmitting the sensor data on the address segment of one burst transmission length stored in the data register group according to the pointing address of the read pointer currently participating in detection, and controlling the read pointer of the FIFO module to continue shifting left and keeping the storage address of the sensor data synchronously shifting right until one sensor data is moved to the address pointed by the most valid bit of the read pointer of the FIFO module.
2. The method according to claim 1, wherein the control FIFO module writes burst write commands of a preset number of transmissions in the same burst access mode into the write buffer in sequence, or writes burst read commands of a preset number of transmissions in the same burst access mode into the read buffer in sequence, before transmitting the sensor data to the FIFO module in the same burst access mode;
the FIFO module comprises a write buffer area and a read buffer area, or comprises a storage unit supporting multiplexing into the write buffer area and the read buffer area;
The preset transmission times are burst transmission times needed between the configured AHB bus and the FIFO module in order to complete the sampling processing of the currently needed sensor data; the burst transmission length is equal for each time;
wherein the sensor data is stored in a set of data registers within the FIFO module.
3. The method according to claim 2, wherein when it is detected that one of the burst write commands has been written into the FIFO module and a write operation flag bit of the burst write command is valid, the write pointer of the FIFO module is controlled to shift left by 1 bit, the storage addresses of the sensor data stored in the FIFO module are controlled to shift right synchronously by n bits, and when it is detected that there is an address segment overlapping the pointing address of the write pointer of the burst write command after the left shift with the free storage address in the data register set, the sensor data transferred by the AHB bus is directly written onto the address segment of one burst transfer length stored in the data register set according to the pointing address of the write pointer currently participating in the detection, and then the write pointer of the FIFO module is controlled to continue shifting left and the storage addresses of the sensor data are kept moving right synchronously until there is one sensor data shifted to the address pointed by the most significant bit of the write pointer of the FIFO module.
4. The method for controlling read and write of sensor data according to claim 3, wherein when a read operation flag bit of a burst read command is detected to be invalid, writing the burst read command into a fault tolerant buffer zone, stopping external reading of sensor data on an address pointed by a read pointer included in the burst read command, and waiting until a start address pointed by a read pointer of a new burst read command for which the read operation flag bit is detected to be valid overlaps with a start address pointed by a read pointer of a burst read command for which the read operation flag bit is detected to be invalid, directly transmitting the sensor data on a corresponding address stored in the data register set to a function module according to the read pointer of the burst read command for which the read operation flag bit is not valid;
wherein the FIFO module further comprises a fault tolerant buffer.
5. The method according to claim 3, wherein when the write operation flag bit of a burst write command is detected to be invalid, the write operation flag bit of the burst write command is waited to be valid, and the sensor data transferred to the AHB bus is written to the data register group according to the write pointer included in the burst write command.
6. The sensor data read-write control system in the burst mode is characterized by comprising a FIFO module, an AHB interface module, a read-write control module and a functional module;
The FIFO module is a dual-port memory supporting read-write multiplexing, the AHB interface module and the functional module are electrically connected with the FIFO module, the FIFO module is used for carrying out data transmission operation according to a read pointer and a write pointer in the FIFO module, and the AHB interface module is used for receiving burst write commands or burst read commands of preset transmission times under the same burst access mode;
The AHB interface module and the functional module are electrically connected with the read-write control module, the read-write control module is used for controlling the storage address of the stored sensor data in the FIFO module to shift right by n bits under the same burst access mode, and simultaneously controlling the FIFO module to transmit the sensor data to the FIFO module under the same burst access mode until one sensor data moves to the most significant bit of a read pointer of the FIFO module or the most significant bit of a write pointer of the FIFO module, and then triggering the FIFO module to send out an empty/full mark signal outwards so as to stop the AHB interface module and the FIFO module from transmitting and receiving data and stop the functional module and the FIFO module from transmitting and receiving data;
The FIFO module comprises a read buffer area and a data register group, wherein the data register group is used for storing sensor data;
The read-write control module is used for controlling the read pointer of the FIFO module to move left and controlling the storage address of the sensor data stored in the data register group to synchronously move right until one sensor data moves to the most significant bit of the read pointer of the FIFO module when one burst read command is written into the read buffer area and the read operation zone bit of the burst read command is valid, wherein the address pointed by the read pointer of the burst read command is in the access address range of the address line of the data register group;
and the read-write control module is also used for directly transmitting the sensor data on the address field of one burst transmission length stored in the data register group to the functional module according to the pointing address of the read pointer when the fact that the pointing address of the read pointer of the read command after the left shift and the storage address of the sensor data in the data register group after the right shift are overlapped is detected on the premise that the read operation flag bit of the burst read command in the read buffer area is valid.
7. The sensor data read-write control system according to claim 6, wherein the FIFO module includes a write buffer and a data register set for storing sensor data; the read-write control module is used for controlling the write pointer of the FIFO module to move left and controlling the storage address of the sensor data stored in the data register group to synchronously move right until one sensor data moves to the most significant bit of the write pointer of the FIFO module when one burst write command is written into the FIFO module and the write operation zone bit of the burst write command is valid, wherein the address pointed by the write pointer of the burst write command is in the access address range of the address line of the data register group;
And the read-write control module is also used for directly writing the sensor data transmitted by the AHB bus into an address segment of a burst transmission length stored in the data register group according to the pointing address of the writing pointer when the fact that the pointing address of the writing pointer of the burst writing command after the left shift is overlapped with the idle storage address in the data register group is detected on the premise that the writing operation flag bit of the burst reading command in the reading buffer area is valid.
8. A chip, characterized in that the chip is an SOC chip, in which the sensor data read-write control system according to any one of claims 6 to 7 is embedded.
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