CN112054671B - Charge pump voltage stabilizer - Google Patents
Charge pump voltage stabilizer Download PDFInfo
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- CN112054671B CN112054671B CN202010874870.7A CN202010874870A CN112054671B CN 112054671 B CN112054671 B CN 112054671B CN 202010874870 A CN202010874870 A CN 202010874870A CN 112054671 B CN112054671 B CN 112054671B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to the technical field of semiconductors, and provides a charge pump voltage stabilizer, which comprises: the sampling circuit is connected with the output end of the charge pump and obtains sampling voltage according to the voltage of the charge pump; the control circuit is connected between the sampling circuit and the ground to form a first path, and the on-off state of the first path is selected according to the sampling voltage under the control of a first enable signal; the compensation circuit is provided with a second path and generates a compensation signal according to the band-gap reference voltage and connects the compensation signal into the control circuit; and the output circuit is respectively connected with the output end of the sampling circuit and the output end of the compensation circuit, and generates the output voltage of the charge pump voltage stabilizer according to the sampling voltage and the compensation signal under the control of a second enabling signal. Therefore, the standby power consumption of the charge pump voltage stabilizer can be reduced while the voltage stabilizing function is realized.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a charge pump voltage stabilizer.
Background
With the development of electronic information technology, the low power consumption design and application of memory products play an important role in electronic systems. The charge pump is a switched capacitor voltage converter, has high conversion efficiency and simple peripheral circuit, is widely applied to modern power management circuits, and is very suitable for memories, Internet of things equipment and portable application products.
Fig. 1 is a schematic block diagram of a conventional charge pump regulator, and as shown in fig. 1, a conventional charge pump regulator 100 may include: the charge pump 110, the voltage divider circuit 120, the voltage comparator 130 and the clock oscillator 140, wherein an output end of the charge pump 110 is connected to an input end of the voltage divider circuit 120 to output a voltage VPXG, a resistance voltage dividing branch included in the voltage divider circuit 120 is adapted to divide the voltage VPXG and output a divided voltage Vo, a first input end of the voltage comparator 130 is connected to a reference voltage Vref, a second input end of the voltage comparator 130 is connected to an output end of the voltage divider circuit 120 and is connected to the divided voltage Vo, the clock oscillator 140 is connected between the voltage comparator 130 and the charge pump 110, and the clock oscillator 140 outputs a driving clock signal CLK according to a comparison result to drive the charge pump 110.
Taking the example of a memory integrated with the charge pump regulator 100, the memory may control the charge pump regulator 100 to operate in a standby mode and an active mode. With reference to fig. 1 and 2, VS is a target voltage of the output voltage of the charge pump 110, and when the voltage VPXG exceeds the target voltage VS, the signal voltage VPXG falls and the charge pump 110 is in the standby mode, and when the voltage VPXG is lower than the target voltage VS, the voltage VPXG rises and the charge pump 110 is in the active mode. The rising or falling of the voltage VPXG depends on the comparison result with the reference voltage Vref, and the voltage comparator 130 outputs a different comparison result showing a logic level recognized by a logic circuit (not shown) and controls the clock oscillator 140 to output the driving clock signal CLK. In the charge pump regulator 100, the charge pump 110 is turned on frequently, and the voltage VPXG is divided by the voltage dividing circuit 120, so that the quiescent current at the output terminal of the charge pump regulator 100 is large in the standby mode.
Therefore, the charge pump voltage regulator 100 in the prior art has a problem of large standby power consumption.
Disclosure of Invention
In order to solve the above technical problem, the present invention provides a charge pump voltage regulator, which can reduce standby power consumption while achieving a voltage stabilizing function.
According to the present invention, there is provided a charge pump voltage regulator, comprising:
the sampling circuit is provided with a first input end connected with the output end of the charge pump and a first output end, the sampling circuit comprises a voltage division network and a control switch tube which are connected between the first input end and the first output end, and the control switch tube responds to the control of the band-gap reference voltage and provides sampling voltage under the conducting state;
the control circuit is connected between the first output end and the ground to form a first path, and the on-off state of the first path is selected according to the sampling voltage under the control of a first enable signal;
the compensation circuit forms a second path for providing a compensation signal through a first current mirror structure, and is provided with a second input end connected with a band-gap reference voltage and a second output end for transmitting the generated compensation signal to the control circuit;
an output circuit having a third input terminal connected to the first output terminal and a fourth input terminal connected to the second output terminal, for generating an output voltage of the charge pump regulator according to the sampling voltage and the compensation signal under control of a second enable signal,
the compensation circuit generates a positive temperature coefficient current by using the first current mirror structure, and mirrors the positive temperature coefficient current to the control circuit to generate the compensation signal so as to compensate the reduction of the sampling voltage under the state switching of the charge pump voltage stabilizer.
Preferably, the control circuit comprises a first transistor and a second transistor, the first transistor and the second transistor being connected in series between the first output terminal of the sampling circuit and ground, forming the first path,
the control end of the first transistor is connected to the first enable signal, the first end of the first transistor is connected to the first output end, the second end of the first transistor is connected to the first end of the second transistor, the second end of the second transistor is grounded, and the control end of the first transistor is connected to the second output end.
Preferably, the first current mirror structure includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first resistor,
the third transistor, the fourth transistor and the first resistor are connected in series between a power supply terminal and the ground, the fifth transistor and the sixth transistor are connected in series between the power supply terminal and the ground to form the second path, the control terminal of the fourth transistor serves as the second input terminal connected to the bandgap reference voltage, and the control terminal of the sixth transistor serves as the second output terminal for transmitting the compensation signal.
Preferably, the output circuit includes:
a current comparator having a third input terminal connected to the first output terminal and a fourth input terminal connected to the second output terminal, the current comparator generating a comparison signal according to the sampling voltage and the compensation signal under the control of the second enable signal;
and an inverter connected to an output terminal of the current comparator, for generating the output voltage based on the comparison signal.
Preferably, the current comparator has a second current mirror structure including a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor,
the seventh transistor, the eighth transistor and the ninth transistor are connected in series between the power supply terminal and the ground, the tenth transistor, the eleventh transistor and the twelfth transistor are connected in series between the power supply terminal and the ground, a control terminal of the ninth transistor serves as a fourth input terminal connected to the second output terminal, a control terminal of the twelfth transistor serves as a third input terminal connected to the first output terminal, a control terminal of the eighth transistor is connected to the second enable signal,
the control end of the eleventh transistor is connected to the first enable signal, the control end of the twelfth transistor is connected to the first output end of the sampling circuit, and the connection node of the tenth transistor and the eleventh transistor provides the comparison signal.
Preferably, the current comparator further includes:
a thirteenth transistor, a first terminal of which is connected to a connection node between the eighth transistor and the ninth transistor, a second terminal of which is grounded, a control terminal of which is connected to the second enable signal, a control terminal of which is connected to a control terminal of the tenth transistor, and a connection node between the seventh transistor and the tenth transistor.
Preferably, the voltage divider network comprises a plurality of transistors connected in series between the output terminal of the charge pump and a first terminal of a fourteenth transistor, the fourteenth transistor is used as the control switch tube, a control terminal of the fourteenth transistor is connected to the bandgap reference voltage, a second terminal of the fourteenth transistor is used as the first output terminal for outputting the sampling voltage,
wherein a control terminal of at least one of the plurality of transistors is connected to its own first terminal.
Preferably, the first transistor, the second transistor, the sixth transistor, the ninth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the plurality of transistors in the voltage divider network are all N-type metal oxide semiconductor field effect transistors.
Preferably, the fourth transistor is an NPN-type bipolar junction transistor.
Preferably, the third transistor, the fifth transistor, the seventh transistor, the eighth transistor, the tenth transistor, and the fourteenth transistor are P-type metal oxide semiconductor field effect transistors.
The invention has the beneficial effects that: the invention provides a charge pump voltage stabilizer, which obtains sampling voltage according to charge pump voltage by a sampling circuit connected with a charge pump, simultaneously a control circuit connected with the sampling circuit forms a first path, the control circuit selects the on-off state of the first path according to the sampling voltage under the control of a first enable signal, a compensation circuit formed with a second path generates a compensation signal according to an accessed band gap reference voltage and outputs the compensation signal to the control circuit under the on state of the first path to compensate the level reduction of the sampling voltage, the final output circuit is respectively connected with the output end of the sampling circuit and the output end of the compensation circuit, the output voltage of the charge pump voltage stabilizer is generated according to the sampling voltage and the compensation signal under the control of a second enable signal, the on-state voltage reduction of a plurality of diode-connected transistors in a voltage division network of the sampling circuit is avoided along with the increase of working temperature, the level of the sampling voltage is reduced, and the standby power consumption of the charge pump voltage stabilizer is reduced while the voltage stabilizing function is realized.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic block diagram of a charge pump voltage regulator in the presence of a conventional charge pump voltage regulator;
FIG. 2 illustrates a waveform of a charge pump output voltage VPXG in the charge pump voltage regulator of FIG. 1;
fig. 3 is a schematic block diagram of a charge pump voltage regulator according to an embodiment of the present invention;
FIG. 4 shows a circuit configuration of the charge pump voltage regulator of FIG. 3;
FIG. 5 shows a schematic diagram of the output circuit of FIG. 4;
fig. 6 shows a schematic diagram of the sampling circuit of fig. 3.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
It is known that charge pumps, also referred to as switched capacitor voltage converters, may comprise a reference circuit, a comparison circuit, a conversion circuit and a control circuit. The voltage is boosted through the switch array, the oscillator, the logic circuit and the comparison circuit, and energy is stored by adopting the capacitor. The charge pump may employ a pulse frequency modulation scheme that generates charge only when charge must be transferred out to maintain output regulation. When the output voltage of the charge pump is higher than the target regulation voltage, the charge pump is in a standby mode, and the consumed current is minimum at the time, because the charge stored on the output capacitor provides the load current. As this capacitor is continuously discharged and the output voltage gradually drops below the target regulated voltage, the charge pump will enter the active mode and transfer charge to the output. This charge supplies the load current and increases the voltage on the output capacitor. In the charge pump voltage regulator shown in fig. 1 provided in the prior art, when the charge pump voltage regulator is in a standby mode, a quiescent current at an output terminal of the charge pump voltage regulator is large, and a problem of large standby power consumption exists. In order to solve the technical problem, embodiments of the present invention provide a charge pump voltage regulator, which can reduce standby power consumption while implementing a voltage stabilization function.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 3 is a schematic block diagram of a charge pump regulator according to an embodiment of the present invention, and fig. 4 is a circuit diagram of the charge pump regulator shown in fig. 3.
Referring to fig. 3, an embodiment of the invention provides a charge pump regulator 200, which includes but is not limited to: a sampling circuit 210, a control circuit 220, a compensation circuit 240 and an output circuit 230, wherein the sampling circuit 210 has a first input terminal connected with the output terminal of the charge pump 300, and a first output terminal, the sampling circuit 210 obtains a charge pump voltage VPXG through the first input terminal, obtains a sampling voltage Vt according to the charge pump voltage VPXG, the control circuit 220 is connected between the first output terminal and the ground to form a first path, the on-off state of the first path is selected according to the sampling voltage Vt under the control of a first enable signal EN1, the compensation circuit 240 is formed with a second path having a second input terminal connected with a band-gap reference voltage Vref and a second output terminal for transmitting a generated compensation signal Vb to the control circuit 220, the output circuit 230 has a third input terminal connected with the first output terminal, and a fourth input terminal connected with the second output terminal, the output circuit 230 generates the output voltage Vout of the charge pump regulator 200 according to the sampled voltage Vt and the compensation signal Vb under the control of the second enable signal.
In a preferred embodiment, the control circuit 220 includes a first transistor T1 and a second transistor T2, the first transistor T1 and the second transistor T2 are connected in series to form the aforementioned first path, and are connected between the first output terminal of the sampling circuit 210 and the ground, wherein a control terminal of the first transistor T1 is connected to the first enable signal EN1, a first terminal is connected to the aforementioned first output terminal, a second terminal is connected to a first terminal of the second transistor T2, a second terminal of the second transistor T2 is connected to the ground, and a control terminal thereof is connected to the aforementioned second output terminal to obtain the compensation signal Vb. Further, the first transistor T1 is a switch transistor.
In a preferred embodiment, the compensation circuit 240 has a first current mirror structure, as shown in fig. 4, the first current mirror structure includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a first resistor R1, wherein the third transistor T3, the fourth transistor T4 and the first resistor R1 are connected in series between the power supply terminal VCC and the ground, the fifth transistor T5 and the sixth transistor T6 are connected in series between the power supply terminal VCC and the ground to form the aforementioned second path, a control terminal of the fourth transistor T4 serves as the aforementioned second input terminal connected to the bandgap reference voltage Vref, and a control terminal of the sixth transistor T6 serves as the aforementioned second output terminal for transmitting the compensation signal Vb and is connected to the control terminal of the second transistor T2.
In a preferred embodiment, the output circuit 230 includes, but is not limited to: a current comparator 231 and an inverter 232, wherein the current comparator 231 has a third input terminal connected to the first output terminal and a fourth input terminal connected to the second output terminal, the current comparator 230 generates a comparison signal Vin according to the sampling voltage Vt and the compensation signal Vb under the control of the second enable signal, and the inverter 232 is connected to the output terminal of the current comparator 231 and generates an output voltage Vout according to the comparison signal Vin.
Fig. 5 shows a schematic diagram of the output circuit of fig. 4.
In a preferred embodiment, referring to fig. 5, the current comparator 231 has a second current mirror structure including a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12, wherein the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are connected in series between the power supply terminal VCC and the ground, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are connected in series between the power supply terminal VCC and the ground, a control terminal of the ninth transistor T9 serves as a fourth input terminal connected with the aforementioned second output terminal, a control terminal of the twelfth transistor T12 serves as a third input terminal connected with the aforementioned first output terminal, a control terminal of the eighth transistor T8 is connected to the second enable signal EN2, a control terminal of the eleventh transistor T11 is connected to the first enable signal EN1, a connection node of the tenth transistor T10 and the eleventh transistor T11 provides the comparison signal Vin as an output terminal of the current comparator 231.
In a preferred embodiment, the current comparator 231 further includes a thirteenth transistor T13, a first terminal of the thirteenth transistor T13 is connected to a connection node of the eighth transistor T8 and the ninth transistor T9, a second terminal is grounded, a control terminal of the thirteenth transistor T13 is connected to the second enable signal EN2, a control terminal of the seventh transistor T7 and a control terminal of the tenth transistor T10 are connected, and a connection node thereof is connected to a connection node of the eighth transistor T8 and the ninth transistor T9, control terminals of the eighth transistor T8 and the thirteenth transistor T13 are connected to the second enable signal EN2, a control terminal of the eleventh transistor T11 is connected to the first enable signal EN1, the eighth transistor T8 is turned on under the control of the second enable signal EN2, and the thirteenth transistor T13 is turned off, the aforementioned second current mirror structure is formed, and the eleventh transistor T11 is turned on under the control of the first enable signal EN1, the current comparator 231 is in an active state; when the eighth transistor T8 is turned off and the thirteenth transistor T13 is turned on under the control of the second enable signal EN2, the current comparator 231 is in an off state.
Fig. 6 shows a schematic diagram of the sampling circuit of fig. 3.
In a preferred embodiment, referring to fig. 6, the sampling circuit 210 includes: a fourteenth transistor T14 and a voltage divider network, wherein a control terminal of the fourteenth transistor T14 is connected to the bandgap reference voltage Vref, a second terminal is used as the first output terminal for outputting the sampling voltage Vt, the voltage divider network comprises a plurality of transistors (e.g., a fifteenth transistor T15 through a twentieth transistor T20 which are sequentially connected in series) connected in series between the output terminal of the charge pump 300 and the first terminal of the fourteenth transistor T14, and the control terminal of each of the plurality of transistors (e.g., a fifteenth transistor T15 through a twentieth transistor T20 which are sequentially connected in series) is connected to its own first terminal.
Furthermore, the transistors (for example, the fifteenth transistor T15 to the twentieth transistor T20 connected in series in sequence) in the voltage divider network are all nmos field effect transistors.
Here, the number of the plurality of diode-connected N-type MOS transistors (the fifteenth transistor T15 to the twentieth transistor T20) determines the voltage range of the sampling voltage Vt, and the size of the bandgap reference voltage Vref determines the accuracy of the sampling voltage Vt, thereby precisely controlling the value of the output voltage Vout of the charge pump voltage VPXG output through the charge pump regulator 200 and improving the accuracy and stability of the charge pump regulator 200.
It should be noted that, the voltage value of the bandgap reference voltage Vref and the number of the N-type MOS transistors in the diode connection may be modified according to actual working requirements, and is not limited herein.
In a preferred embodiment, the fourth Transistor is an NPN-type Bipolar Junction Transistor (BJT).
In a preferred embodiment, the first transistor T1, the second transistor T2, the sixth transistor T6, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are all N-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10 and the fourteenth transistor T14 are all P-type metal oxide semiconductor field effect transistors. The fifteenth transistor T15 to the twentieth transistor T20 are all N-type metal oxide semiconductor field effect transistors (hereinafter, referred to as N-type MOS transistors).
In this embodiment, the compensation circuit 240 is formed with a first current mirror structure, a positive temperature coefficient current is generated through the third transistor T3, the fourth transistor T4 and the first resistor R1 connected in series between the power supply terminal VCC and the ground, the same positive temperature coefficient current flows through the fifth transistor T5 and the sixth transistor T6 on the second path formed by the mirror structure of the current mirror, thereby forming a compensation (voltage) signal at the connection node of the fifth transistor T5 and the sixth transistor T6, and, the control terminal of the sixth transistor T6 is connected to the first terminal thereof, when the first path under the control of the first enable signal is in a conducting state, the first path and the second path form a third current mirror structure, so that the positive temperature coefficient current generated by the compensation circuit 240 is mirrored to the second path to compensate the level drop of the sampling voltage Vt. The charge pump voltage VPXG is divided by a plurality of diode-connected N-type MOS transistors (the fifteenth transistor T15 to the twentieth transistor T20), and when the fourteenth transistor T14 is in a conducting state under the control of the bandgap reference voltage Vref, the sampling voltage Vt is provided, and in this process, the charge pump regulator 200 consumes a certain static current.
When the first enable signal EN1 is in a high state and the second enable signal EN2 is in a low state, the first transistor T1 is turned on, and the eleventh transistor T11 and the eighth transistor T8 are turned on, and the thirteenth transistor T13 is turned off, at which time the charge pump regulator 200 enters an operation state, when the charge pump voltage VPXG is in the low level state, the sampling voltage Vt is also in the low level state, when the charge pump voltage VPXG rises to a certain voltage value, the fourteenth transistor T14 under the control of the bandgap reference voltage Vref is turned on, the level state of the sampling voltage Vt is rapidly pulled high, the ptc current generated by the compensation circuit 240 is then mirrored in the control circuit 220 via a current mirror arrangement, to compensate for the current flowing through the control circuit 220, the output circuit 230 obtains a comparison signal Vin according to the sampling voltage Vt and the compensation signal Vb, and then outputs the required output voltage Vout through level inversion of the inverter 232.
In the present embodiment, the charge pump regulator 200 connected to the charge pump 300 is switched between the standby state and the active state, and is turned on frequently, and as the temperature increases, the turn-on voltage VTh of the plurality of diode-connected N-type MOS transistors (the fifteenth transistor T15 to the twentieth transistor T20) decreases, which may cause the determination point voltage of the fourteenth transistor T14 under the control of the bandgap reference voltage Vref to decrease as the temperature increases after the charge pump voltage VPXG is divided. The charge pump regulator 200 according to the embodiment of the present invention generates a positive temperature coefficient current through the fourth transistor T4(NPN BJT) in the compensation circuit 240, and mirrors the positive temperature coefficient current to the control circuit 220 through the current mirror structure to compensate for the drop of the sampling voltage Vt, so as to prevent the charge pump voltage VPXG inaccuracy (unstable point level of the sampling voltage Vt) caused by the drop of the conduction voltage VTh of the plurality of diode-connected N-type MOS transistors (the fifteenth transistor T15 to the twentieth transistor T20) with the increase of temperature, and stabilize the output voltage Vout of the charge pump regulator 200.
Meanwhile, when the charge pump regulator 200 is in the standby mode, if the voltage formed at the first end (source) of the fourteenth transistor T14 after the voltage VPXG is divided is less than the threshold voltage value for turning on the fourteenth transistor T14 under the control of the bandgap reference voltage Vref, the charge pump regulator 200 remains in the sleep state, so that the charge pump regulator 200 is not frequently turned on, thereby achieving the purpose of reducing the standby power consumption of the charge pump regulator 200.
In summary, the charge pump voltage regulator provided in the embodiments of the present invention can reduce the standby power consumption while achieving the voltage stabilizing function.
It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "inner", and the like, indicate orientation or positional relationship, are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referenced components or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (10)
1. A charge pump voltage regulator, comprising:
the sampling circuit is provided with a first input end connected with the output end of the charge pump and a first output end, the sampling circuit comprises a voltage division network and a control switch tube which are connected between the first input end and the first output end, and the control switch tube provides sampling voltage under the conducting state in response to the control of the band-gap reference voltage;
the control circuit is connected between the first output end and the ground to form a first path, and the on-off state of the first path is selected according to the sampling voltage under the control of a first enable signal;
the compensation circuit forms a second path for providing a compensation signal through a first current mirror structure, has a second input end connected with a band-gap reference voltage, and transmits the generated compensation signal to a second output end of the control circuit;
an output circuit having a third input terminal connected to the first output terminal and a fourth input terminal connected to the second output terminal, generating an output voltage of the charge pump regulator according to the sampling voltage and the compensation signal under control of a second enable signal,
the compensation circuit generates positive temperature coefficient current by using the first current mirror structure and mirrors the positive temperature coefficient current to the control circuit to generate the compensation signal so as to compensate the reduction of the sampling voltage under the state switching of the charge pump voltage stabilizer.
2. The charge pump voltage regulator of claim 1, wherein the control circuit comprises a first transistor and a second transistor connected in series between the first output of the sampling circuit and ground forming the first path,
the control end of the first transistor is connected to the first enable signal, the first end of the first transistor is connected to the first output end, the second end of the first transistor is connected to the first end of the second transistor, the second end of the second transistor is grounded, and the control end of the first transistor is connected to the second output end.
3. The charge pump voltage regulator of claim 2, wherein the first current mirror structure comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first resistor,
the third transistor, the fourth transistor and the first resistor are connected in series between a power supply end and the ground, the fifth transistor and the sixth transistor are connected in series between the power supply end and the ground to form the second path, a control end of the fourth transistor serves as the second input end connected to the bandgap reference voltage, and a control end of the sixth transistor serves as the second output end for transmitting the compensation signal.
4. The charge pump voltage regulator of claim 3, wherein the output circuit comprises:
a current comparator having a third input connected to the first output terminal and a fourth input connected to the second output terminal, the current comparator generating a comparison signal according to the sampling voltage and the compensation signal under control of the second enable signal;
and the phase inverter is connected with the output end of the current comparator and generates the output voltage according to the comparison signal.
5. The charge pump voltage regulator according to claim 4, wherein the current comparator has a second current mirror structure including a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor,
the seventh transistor, the eighth transistor and the ninth transistor are connected in series between the power supply terminal and the ground, the tenth transistor, the eleventh transistor and the twelfth transistor are connected in series between the power supply terminal and the ground, a control terminal of the ninth transistor serves as a fourth input terminal connected with the second output terminal, a control terminal of the twelfth transistor serves as a third input terminal connected with the first output terminal, and a control terminal of the eighth transistor is connected to the second enable signal,
the control end of the eleventh transistor is connected to the first enable signal, the control end of the twelfth transistor is connected with the first output end of the sampling circuit, and the connection node of the tenth transistor and the eleventh transistor provides the comparison signal.
6. The charge pump voltage regulator of claim 5, wherein the current comparator further comprises:
and a thirteenth transistor, a first end of which is connected to a connection node of the eighth transistor and the ninth transistor, a second end of which is grounded, a control end of the thirteenth transistor is connected to the second enable signal, a control end of the seventh transistor is connected to a control end of the tenth transistor, and a connection node of the seventh transistor and the tenth transistor is connected to a connection node of the eighth transistor and the ninth transistor.
7. The charge pump voltage regulator according to claim 6, wherein the voltage divider network comprises a plurality of transistors connected in series between the output terminal of the charge pump and a first terminal of a fourteenth transistor, the fourteenth transistor is used as the control switch tube, a control terminal of the fourteenth transistor is connected to the bandgap reference voltage, a second terminal of the fourteenth transistor is used as the first output terminal for outputting the sampled voltage,
wherein a control terminal of at least one of the plurality of transistors is connected to its own first terminal.
8. The charge pump voltage regulator of claim 7, wherein the first transistor, the second transistor, the sixth transistor, the ninth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, and the plurality of transistors in the voltage divider network are all N-type metal oxide semiconductor field effect transistors.
9. The charge pump voltage regulator of claim 3, wherein the fourth transistor is an NPN bipolar junction transistor.
10. The charge pump voltage regulator of claim 7, wherein the third, fifth, seventh, eighth, tenth, and fourteenth transistors are P-type metal oxide semiconductor field effect transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010874870.7A CN112054671B (en) | 2020-08-27 | 2020-08-27 | Charge pump voltage stabilizer |
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| CN202010874870.7A CN112054671B (en) | 2020-08-27 | 2020-08-27 | Charge pump voltage stabilizer |
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| CN113053442B (en) * | 2021-03-18 | 2024-04-02 | 华南师范大学 | Low-power-consumption EEPROM memory |
| CN112967744A (en) * | 2021-05-18 | 2021-06-15 | 珠海博雅科技有限公司 | Circuit, circuit board, adjusting device and flash memory for adjusting voltage swing |
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| CN1362654A (en) * | 2001-01-02 | 2002-08-07 | 深圳赛意法微电子有限公司 | Current-limiting protection circuit for voltage stabilizer |
| US6724265B2 (en) * | 2002-06-14 | 2004-04-20 | Rf Micro Devices, Inc. | Compensation for oscillator tuning gain variations in frequency synthesizers |
| CN101505102A (en) * | 2002-11-14 | 2009-08-12 | 艾科嘉公司 | Switching power converter and system for controlling a plurality of switching power converters |
| CN101674009A (en) * | 2008-09-10 | 2010-03-17 | 中芯国际集成电路制造(上海)有限公司 | Charge pump output voltage regulation circuit |
| CN101814829A (en) * | 2010-04-22 | 2010-08-25 | 上海宏力半导体制造有限公司 | Charge pump circuit and reference voltage generating circuit thereof |
| CN202267484U (en) * | 2011-10-21 | 2012-06-06 | 上海腾怡半导体有限公司 | Single-chip latch type Hall sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102255502B (en) * | 2011-07-16 | 2014-04-16 | 西安电子科技大学 | Primary inductance correction circuit applied to flyback switching power supply |
| CN103177749B (en) * | 2013-02-01 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | Read voltage generation circuit |
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|---|---|---|---|---|
| CN1362654A (en) * | 2001-01-02 | 2002-08-07 | 深圳赛意法微电子有限公司 | Current-limiting protection circuit for voltage stabilizer |
| US6724265B2 (en) * | 2002-06-14 | 2004-04-20 | Rf Micro Devices, Inc. | Compensation for oscillator tuning gain variations in frequency synthesizers |
| CN101505102A (en) * | 2002-11-14 | 2009-08-12 | 艾科嘉公司 | Switching power converter and system for controlling a plurality of switching power converters |
| CN101674009A (en) * | 2008-09-10 | 2010-03-17 | 中芯国际集成电路制造(上海)有限公司 | Charge pump output voltage regulation circuit |
| CN101814829A (en) * | 2010-04-22 | 2010-08-25 | 上海宏力半导体制造有限公司 | Charge pump circuit and reference voltage generating circuit thereof |
| CN202267484U (en) * | 2011-10-21 | 2012-06-06 | 上海腾怡半导体有限公司 | Single-chip latch type Hall sensor |
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