CN111786546B - Power module driving system and control method - Google Patents
Power module driving system and control method Download PDFInfo
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- CN111786546B CN111786546B CN202010699035.4A CN202010699035A CN111786546B CN 111786546 B CN111786546 B CN 111786546B CN 202010699035 A CN202010699035 A CN 202010699035A CN 111786546 B CN111786546 B CN 111786546B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
- H02M1/092—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the control signals being transmitted optically
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Abstract
The invention provides a power module driving system and a control method. The drive system includes: a master node: the number of the processors is one, and the processors comprise a first processor and a second processor; the first processor is configured to generate a power driving signal, and the second processor is configured to receive, encode and transmit the power driving signal generated by the first processor; a slave node unit: a master node in data communication with the first processor, the master node comprising at least one slave node, each slave node comprising a third processor and a power module; the third processor is configured to acquire the power driving signal coded and transmitted by the second processor, and after the power driving signal is decoded and executed, the power driving signal is transmitted to the power module. The control method is based on single optical fiber ring network communication, improves an information transmission scheme to realize the drive control of the power module, effectively reduces the failure rate, improves the information transmission efficiency, and is beneficial to high-frequency development.
Description
Technical Field
The invention belongs to the field of power electronic control, and particularly relates to a power module driving system and a control method.
Background
The converter is a complex power electronic device, and the technology thereof relates to multiple disciplines such as power electronic technology, control technology, structural design, electrical design and the like, and is a multi-discipline cross product. The power module is a core component of the converter, mainly plays an important role of converting alternating current into direct current or converting direct current into alternating current, and has a switch conversion function of bearing high-voltage current in the converter.
The driving of a power module of the current converter is mostly realized by adopting a pure analog circuit mode, and the power module receives a master control system signal and provides a control signal for a driver; the driver passively receives the control signal instruction, detects the driving fault and transmits fault information, and therefore the driving control of the power module is achieved. In order to improve the stability of signal control, the existing power module mostly adopts optical fiber communication to transmit driving and feedback signals, and although the communication mode solves the anti-interference problem, the communication mode still has the problems of low data transmission quantity, high failure rate of a driving system, low reliability of synchronous control, failure detection processing and the like in information transmission, and low information transmission efficiency, and does not accord with the equipment health management trend of big data.
Disclosure of Invention
The invention aims to provide a power module driving system and a control method, wherein the driving system and the control method are based on single optical fiber ring network communication, a data communication scheme is improved to realize the driving control of a power module, the failure rate is effectively reduced, the information transmission efficiency is improved, and the high-frequency development is facilitated.
To achieve the above object, the present invention provides a power module driving system including
A master node: the number of the processors is one, and the processors comprise a first processor and a second processor; the first processor is configured to generate a power driving signal, and the second processor is configured to receive, encode and transmit the power driving signal generated by the first processor;
a slave node unit: a master node in data communication with the first processor, the master node comprising at least one slave node, each slave node comprising a third processor and a power module; the third processor is configured to acquire the power driving signal coded and transmitted by the second processor, and after the power driving signal is decoded and executed, the power driving signal is transmitted to the power module.
Preferably, the number of the first processors corresponds to the number of the slave nodes, and each first processor generates a power driving signal of the slave node power module, which can be transmitted to the power module of the corresponding slave node.
Preferably, the second processor comprises an interrupt module for generating an interrupt signal, and the first processor generates the power driving signal according to the interrupt signal and sends the power driving signal to the second processor.
Preferably, the master node further comprises a master node optical fiber receiving interface and a master node optical fiber transmitting interface;
the slave node further comprises a slave node optical fiber receiving interface and a slave node optical fiber transmitting interface;
if the number of slave nodes is one:
the master node optical fiber transmitting interface is connected with the slave node optical fiber receiving interface, and the slave node optical fiber transmitting interface is connected with the master node optical fiber receiving interface;
if the number of the slave nodes is multiple:
the slave node unit comprises a head slave node, a tail slave node and an intermediate slave node, the optical fiber transmitting interface of the master node is connected with the optical fiber receiving interface of the head slave node, and the optical fiber transmitting interface of the head slave node is connected with the optical fiber receiving interface of the intermediate slave node adjacent to the optical fiber transmitting interface of the head slave node; the main node optical fiber receiving interface is connected with the tail slave node optical fiber transmitting interface, and the tail slave node optical fiber receiving interface is connected with the middle slave node optical fiber transmitting interface adjacent to the tail slave node optical fiber receiving interface; the intermediate slave node optical fiber transmitting interface is connected with the adjacent intermediate slave node optical fiber receiving interface in turn.
Preferably, the third processor is further configured to: and acquiring a power driving signal transmitted by a previous node connected with the power driving signal, extracting and decoding the power driving signal of the slave node power module where the third processor is located, adding feedback information of the slave node power module, and transmitting the feedback information to a next node adjacent to the slave node.
Preferably, the second processor is further configured to acquire, decode and send the data information transmitted by the third processor to the first processor.
The invention also provides a power module driving control method, which comprises the following steps:
the main node first processor calculates a PWM (pulse-width modulation) algorithm of the power module, generates a power driving signal and sends the power driving signal to the second processor; the second processor receives the power driving signal, encodes the power driving signal and sends the power driving signal to the third processor of the slave node; and the third processor receives the power driving signal, decodes the power driving signal, and sends the power driving signal to the power module for driving and controlling the power module.
Preferably, the data communication between the master node and the slave node units is realized through optical fibers;
the slave nodes in the slave node unit realize data communication through optical fibers;
the data communication adopts Manchester coding, and the data frame comprises a master node transceiving flag bit, all slave nodes transceiving information and a data transceiving check bit.
Preferably, the number of the first processors of the master node corresponds to the number of the slave nodes, the first processors generate power driving signals, send the power driving signals to the second processors, store the power driving signals into corresponding slave node information receiving and transmitting data segments, form data receiving and transmitting zone bits, and perform coding transmission by the second processors.
Preferably, if the number of slave nodes is multiple:
after a third processor of the slave node receives a power driving signal transmitted by a second processor, extracting data from a corresponding slave node information receiving and transmitting data segment, decoding the data, verifying the data, loading self feedback information into the slave node information receiving and transmitting data segment, updating a verification bit, and transmitting an updated data frame to an adjacent intermediate slave node;
after receiving data, the third processor of the middle slave node extracts data from the corresponding slave node information receiving and transmitting data segment, decodes the data, performs data verification, loads self feedback information into the slave node information receiving and transmitting data segment, updates the verification bit, and transmits the updated data frame to the next adjacent slave node;
after receiving data, the third processor of the tail slave node extracts data from the corresponding slave node information receiving and transmitting data segment, decodes the data, performs data verification, loads self feedback information into the slave node information receiving and transmitting data segment, updates the verification bit, and transmits the updated data frame to the master node;
after receiving the data, the second processor of the main node extracts the data information from the data sections of the information sent and received by all the slave nodes respectively, decodes the data information, checks the data information to be correct, and sends the data information to the corresponding first processors respectively.
Preferably, after the second processor generates the interrupt signal, the first processor generates a power driving signal according to the interrupt signal and sends the power driving signal to the second processor, and the second processor receives the post-code and sends the post-code to the third processor;
the third processor generates a PWM (pulse-width modulation) interrupt signal according to the received power drive signal, updates a data frame, updates the power drive signal in real time before the PWM interrupt signal is not loaded, and transmits the power drive signal to the power module after the PWM interrupt signal is loaded so as to control the drive output of the power module;
and after the first processor receives the data, PWM modulation calculation is carried out according to the data, and the power driving signal is updated.
Compared with the prior art, the invention has the advantages and positive effects that:
1. data communication in the invention adopts Manchester coding, and data communication between slave nodes adopts an address self-increment mode, after receiving a power driving signal sent by a second processor of a master node, data are automatically extracted from corresponding data segments for decoding, so that convenience and intellectualization of slave node access are increased in both hardware and software aspects, wiring is reduced, and the reduction of failure rate is facilitated to a certain extent;
2. the invention adopts the intra-frame data segment multiplexing mode based on the slave nodes, improves the information transmission efficiency and is beneficial to high-frequency development.
Drawings
FIG. 1 is a diagram of a fiber optic communication topology according to the present invention;
FIG. 2 is a diagram of a configuration structure of a master node processor and a slave node processor in an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a power module according to the present invention;
FIG. 4 is a state machine layout of the drive system of the present invention;
FIG. 5 is a flow chart of a state machine of the drive system of the present invention;
FIG. 6 is a diagram illustrating a data frame structure according to the present invention;
FIG. 7 is a block diagram of information transmission using PWM parameters as information according to the present invention;
fig. 8 is a schematic diagram of information transmission using PWM parameters as information according to the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be further described with reference to the accompanying drawings.
In the description of the present invention, it should be noted that the terms "first", "second", "third", and "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The present invention first provides a power module driving system, which includes:
a master node: the number of the processors is one, and the processors comprise a first processor and a second processor; the first processor is configured to generate a power driving signal, and the second processor is configured to receive, encode and transmit the power driving signal generated by the first processor;
a slave node unit: a master node in data communication with the first processor, the master node comprising at least one slave node, each slave node comprising a third processor and a power module; the third processor is configured to acquire the power driving signal coded and transmitted by the second processor, and after the power driving signal is decoded and executed, the power driving signal is transmitted to the power module.
The number of the first processors corresponds to the number of the slave nodes, and each first processor correspondingly generates a power driving signal of the slave node power module to be transmitted to the power module of the corresponding slave node. Referring to fig. 1 and fig. 2, in this embodiment, for example, the master node uses 2 first processors, and the slave node unit uses 2 slave nodes, which is specifically described for the system implementation. The third processor of the slave node 1 adopts an FPGA1 processor, the third processor of the slave node 2 adopts an FPGA2 processor, the second processor of the master node adopts an FPGA processor, and the 2 first processors of the master node respectively adopt DSP1 and DSP2 processors. Referring to fig. 3, in the embodiment of the present invention, the power module includes a three-phase inverter unit and a chopper unit, which are composed of 4 bridge arms, a power supply unit, and 4 driving units, where the 4 driving units are respectively connected to IGBT switching tubes in the 4 bridge arms. The control power supply unit is a 110V or 24V direct-current power supply and supplies power to the driving unit; the chopper unit realizes the function of overvoltage chopping of the direct-current bus and is used for overvoltage protection of a main circuit, and the power module is the prior art, so that redundant description is not given.
The second processor comprises an interrupt module for generating an interrupt signal, and the first processor generates a power driving signal according to the interrupt signal and sends the power driving signal to the second processor. In this embodiment, the frequency of the interrupt signal generated by the second processor is 5 kHz.
Further, the main node further comprises a main node optical fiber receiving interface and a main node optical fiber transmitting interface;
the slave node further comprises a slave node optical fiber receiving interface and a slave node optical fiber transmitting interface;
if the number of slave nodes is one:
the master node optical fiber transmitting interface is connected with the slave node optical fiber receiving interface, and the slave node optical fiber transmitting interface is connected with the master node optical fiber receiving interface;
if the number of the slave nodes is multiple:
the slave node unit comprises a head slave node, a tail slave node and an intermediate slave node, the optical fiber transmitting interface of the master node is connected with the optical fiber receiving interface of the head slave node, and the optical fiber transmitting interface of the head slave node is connected with the optical fiber receiving interface of the intermediate slave node adjacent to the optical fiber transmitting interface of the head slave node; the main node optical fiber receiving interface is connected with the tail slave node optical fiber transmitting interface, and the tail slave node optical fiber receiving interface is connected with the middle slave node optical fiber transmitting interface adjacent to the tail slave node optical fiber receiving interface; the intermediate slave node optical fiber transmitting interface is connected with the adjacent intermediate slave node optical fiber receiving interface in turn. Referring to fig. 2, the number of the slave nodes is 2, the master node optical fiber transmitting interface is connected to the slave node 1 optical fiber receiving interface, the slave node 1 optical fiber transmitting interface is connected to the slave node 2 optical fiber receiving interface, and the slave node 2 optical fiber transmitting interface is connected to the master node optical fiber receiving interface, so as to form single ring network optical fiber communication.
The third processor is further configured to: and acquiring a power driving signal transmitted by a previous node connected with the power driving signal, extracting and decoding the power driving signal of a slave node power module where the third processor is located, adding feedback information of the slave node power module, and transmitting the feedback information to a next node adjacent to the slave node.
The second processor is further configured to acquire, decode and send the data information transmitted by the third processor to the first processor.
Referring to fig. 4 and 5, the driving system state machine planning specifically includes power-on, initialization, communication establishment, standby, normal operation, data upload, data issue, power-down, and other mode states, specifically:
initialization: and after initializing internal variables of the master node and the slave node respectively, performing parameter configuration, and performing fault self-detection on the master node.
Communication establishment: and performing communication handshake at a fixed time interval, performing basic information interaction on the master node and the slave node after the handshake is successful, and performing fault judgment on the feedback information of the slave node by the master node.
Standby: the standby state is a central link switched by each state, the master node sends a configuration frame to configure the slave node after entering the standby state, the system enters the standby communication state after the configuration is finished, further checks, detects a flag bit and the like, judges a fault, and receives a state conversion flag at any time.
And (4) normal operation: after receiving the status flag bit in the standby mode, the master node enters the status and configures the slave nodes, after the configuration is completed, the system enters normal communication to issue a data packet, and after the data packet is issued back, data verification and fault judgment are performed to further perform status judgment; if the state is still the state, the communication is circulated normally; and changing the state, recovering the master node and the slave node, entering a standby state when the standby condition is met, and jumping to other states when the standby state is entered.
And (3) data uploading: after receiving the flag bit of the data uploading state in the standby state, the master node enters the state to perform slave node configuration, the master node issues a data uploading request, and the slave node responds and uploads data; after the uploading is finished, the mobile terminal automatically enters a standby state, the data transmission is verified at the moment, and the uploading can be requested again when an error exists.
Data issuing: after receiving the flag bit of the data sending state in the standby state, the master node enters the state and performs slave node configuration, the master node sends a data request, the slave node responds and sends the data according to the requirement, and after the sending is finished, the data is verified and the sending condition is prompted; the power can be powered on again after power failure, and a recovery mode or a survival mode is provided.
The driving system adopts a master-slave control mode, a communication loop is formed by a single optical fiber ring network, and data exchange between the main node and each sub-node is realized through high-speed serial optical fiber communication, so that the driving of a power module is completed, the reliability of the system is improved, and the failure rate is reduced.
The invention further provides a power module driving control method, which comprises the following steps:
the main node first processor calculates a PWM (pulse-width modulation) algorithm of the power module, generates a power driving signal and sends the power driving signal to the second processor; the second processor receives the power driving signal, encodes the power driving signal and sends the power driving signal to the third processor of the slave node; and the third processor receives the power driving signal, decodes the power driving signal, and sends the power driving signal to the power module for driving and controlling the power module.
Further, referring to fig. 1 and fig. 2, the master node and the slave node unit implement data communication through an optical fiber;
the slave nodes in the slave node unit realize data communication through optical fibers;
the data communication adopts Manchester coding, and the data frame comprises a master node transceiving flag bit, all slave nodes transceiving information and a data transceiving check bit. Referring to fig. 6, the present embodiment employs 2 slave nodes, and thus each data frame includes a master node transceiving flag bit, a slave node 1 transceiving information, a slave node 2 transceiving information, and a data transceiving check bit 4 part.
Furthermore, the number of the first processors of the master node corresponds to the number of the slave nodes, the first processors generate power driving signals, send the power driving signals to the second processors, store the power driving signals into the corresponding slave node information receiving and sending data segments, form data receiving and sending zone bits, and carry out coding sending by the second processors. In this embodiment, 2 first processors DSP1, DSP2, and 2 slave nodes are used, and thus, 2 third processors FPGA1 and FPGA2 are provided. The master node first processor DSP1 calculates a PWM (pulse-width modulation) algorithm of a power module of the slave node 1, generates a power driving signal and sends the power driving signal to the second processor FPGA; the master node first processor DSP2 calculates a PWM (pulse-width modulation) algorithm of a power module of the slave node 2, generates a power driving signal and sends the power driving signal to the second processor FPGA; after receiving the power driving signals of the 2 power modules, the FPGA stores the power driving signals into 2 data sections for receiving and sending information from the node 1 and receiving and sending information from the node 2 respectively, and forms a data receiving and sending zone bit, and the second processor FPGA encodes and sends the data information in the two data sections for receiving and sending information from the node 1 and receiving and sending information from the node 2.
Further, if the number of the slave nodes is multiple:
after a third processor of the slave node receives a power driving signal transmitted by a second processor, extracting data from a corresponding slave node information receiving and transmitting data segment, decoding the data, verifying the data, loading self feedback information into the slave node information receiving and transmitting data segment, updating a verification bit, and transmitting an updated data frame to an adjacent intermediate slave node;
after receiving data, the third processor of the middle slave node extracts data from the corresponding slave node information receiving and transmitting data segment, decodes the data, performs data verification, loads self feedback information into the slave node information receiving and transmitting data segment, updates the verification bit, and transmits the updated data frame to the next adjacent slave node;
after receiving data, the third processor of the tail slave node extracts data from the corresponding slave node information receiving and transmitting data segment, decodes the data, performs data verification, loads self feedback information into the slave node information receiving and transmitting data segment, updates the verification bit, and transmits the updated data frame to the master node;
after receiving the data, the second processor of the main node extracts the data information from the data sections of the information sent and received by all the slave nodes respectively, decodes the data information, checks the data information to be correct, and sends the data information to the corresponding first processors respectively.
Specifically, in this embodiment, after receiving the power driving signal transmitted by the second processor FPGA from the third processor FPGA1 of the node 1, the slave node 1 extracts data from the information transmitting and receiving data segment and performs data check, loads the feedback information of the slave node 1 into the information transmitting and receiving data segment of the slave node 1, updates the check bit, and transmits the updated data frame to the slave node 2.
After receiving the power driving signal transmitted by the second processor FPGA, the third processor FPGA2 of the slave node 2 extracts data from the information receiving and transmitting data segment of the slave node 2, decodes the data, performs data check, loads the feedback information of the slave node 2 into the information receiving and transmitting data segment of the slave node 2, updates the check bit, and transmits the updated data frame to the master node.
After receiving the data, the second processor FPGA of the master node extracts and decodes the data information from the data segments of the information received and transmitted by the slave node 1 and the information received and transmitted by the slave node 2 respectively, and sends the data information to the DSP1 and the DSP2 respectively after checking the data without errors. In this embodiment, the third processor of the slave node further has functions of AD acquisition, receiving of failure feedback information of the driving unit, failure processing, rapid protection, and the like, and the AD acquisition mainly includes acquisition of a dc voltage, a dc current, a three-phase output current, a chopper unit output current, a temperature of the controlled motor, and a voltage of the power supply unit. And the third processor of the slave node has the functions of fault self-diagnosis and protection, and can execute a fault processing program to carry out quick protection after detecting a fault, and selectively encode and transmit data information such as collected and received feedback information back to the second processor of the master node. The slave node third processor collects data as much as possible, selectively uploads the data, has self-protection and cutting-off functions, is matched with intelligent drive, is beneficial to realizing intelligent diagnosis of equipment, and accords with the trend of equipment health management based on big data.
Table 1 details the data communication protocol for transmitting and receiving message data segments from a node, wherein in receiving a message (master node transmit message) from a node: PWMTPR is PWM period information, PWMCMP1, 2, 3 are PWM modulation information of three IGBT legs, enPWM is a three-phase inverter enable flag, enCHP is a chopper unit enable flag, CHPTPR is chopper period information, and CHPCMP is chopper modulation information. In the slave node transmission information (master node reception information): udc is direct-current bus voltage, Idc is direct-current bus current, Ia, Ib and Ic are three-phase output currents respectively, T1, T2 and T3 are temperatures of an arm 1, an arm 2 and an arm 3 of the slave node power module respectively, F _ IGBT 1-8 are 8 IGBT fault feedback signals respectively, INV _ numb is a slave node number, and Icto is chopping current. The slave node transmits and receives information with 224 bits, and performs zero padding processing on the reception and transmission invalid bits.
Table 1 main data communication protocol table
Furthermore, after the second processor generates an interrupt signal, the first processor generates a power driving signal according to the interrupt signal and sends the power driving signal to the second processor, and the second processor receives the post-coding and sends the post-coding to the third processor;
the third processor generates a PWM (pulse-width modulation) interrupt signal according to the received power drive signal, updates a data frame, updates the power drive signal in real time before the PWM interrupt signal is not loaded, and transmits the power drive signal to the power module after the PWM interrupt signal is loaded so as to control the drive output of the power module;
and after the first processor receives the data, PWM modulation calculation is carried out according to the data, and the power driving signal is updated.
Specifically, in this embodiment, the power driving signal generated by the first processor includes PWM period information, the third processor starts counting according to its own counting frequency after receiving the power driving signal encoded and transmitted by the second processor, the counting starts from 0, the counting is incremented, when the counting value reaches the PWM period value, the counting starts to be decremented, and after the counting value reaches 0, the third processor generates an interrupt signal and updates the data frame. Referring to fig. 7 and 8, taking the driving control of the power module of the slave node 1 as an example:
firstly, a second processor FPGA of the main node continuously generates an interrupt signal of 5kHz, and the DSP1 generates a power driving signal according to the interrupt signal; when the PWM interrupt signal generated by the third processor FPGA1 is detected, the DSP1 performs PWM modulation algorithm calculation according to the PWM interrupt signal generated by the FPGA1 to generate a power driving signal.
The DSP1 sends the generated power driving signal to the FPGA, and the FPGA receives the power driving signal and sends the power driving signal to the third processor FPGA 1.
And thirdly, the third processor FPGA1 updates the power driving signal in real time before the PWM interrupt signal generated by the third processor is not loaded, and transmits the power driving signal to the power module after the PWM interrupt signal generated by the third processor is loaded, so as to control the driving output of the power module.
And fourthly, the third processor FPGA1 encodes and transmits the PWM interrupt signal generated by the third processor.
After receiving the PWM interrupt signal, the second processor FPGA extracts data from the information receiving and transmitting data section from the node 1, decodes and transmits the data, and after the first processor DSP1 receives the data, the PWM modulation algorithm is calculated according to the data, and the power driving signal is updated.
Further, to improve reliability of data communication, the data communication further includes packet loss and fault data processing, specifically: data communication is realized between the slave node unit and the master node through optical fibers, with reference to fig. 7, the optical fiber network communication rate between the FPGA1 of the slave node 1 and the FPGA of the master node is adjustable to 5-20 kHz, when the optical fiber network communication rate is 20kHz, one packet of control data is sent every 50us, and the switching frequency of PWM modulation is 2kHz, so that even if frequency doubling is performed, that is, when the switching frequency is 4kHz, it can be guaranteed that the FPGA1 receives at least 5 packets of control data before each power driving signal is loaded, and multiple packets of data packet loss or error checking can be tolerated. When the switching frequency is lower or the frequency is not doubled, the fault tolerance rate is further improved.
Data received by the main node is mainly AD acquisition data, illustratively, when the execution cycle of a PWM (pulse-width modulation) algorithm is 200us, maximum or minimum data can be removed by a sliding window filtering method, the average value of the residual data is taken, when error data are removed, packet loss or error checking can be naturally allowed, and when the error data are not removed, the data are still in a normal range and can be accepted. In addition, the condition of executing the algorithm once through multiple communications can be formed by improving the communication rate or reducing the algorithm execution period, and the fault tolerance rate is further improved.
The power module driving control method provided by the invention has a better control effect, can effectively ensure the reliable and stable operation of a driving system, and realizes the driving of the power module.
The above description is only a preferred embodiment of the present invention, and not intended to limit the present invention in other forms, and any person skilled in the art may apply the above modifications or changes to the equivalent embodiments with equivalent changes, without departing from the technical spirit of the present invention, and any simple modification, equivalent change and change made to the above embodiments according to the technical spirit of the present invention still belong to the protection scope of the technical spirit of the present invention.
Claims (8)
1. Power module actuating system, its characterized in that: the method comprises the following steps:
a master node: the number of the processors is one, and the processors comprise a first processor and a second processor; the first processor is configured to generate a power driving signal, and the second processor is configured to receive, encode and transmit the power driving signal generated by the first processor;
a slave node unit: a master node in data communication with the first processor, the master node comprising at least one slave node, each slave node comprising a third processor and a power module; the third processor is configured to acquire the power driving signal coded and transmitted by the second processor, and after the power driving signal is decoded and executed, the power driving signal is transmitted to the power module;
the second processor is configured to include an interrupt module for generating an interrupt signal, the first processor generating a power driving signal according to the interrupt signal and transmitting it to the second processor;
data communication between the master node and the slave node units and data communication between the slave nodes and the slave nodes in the slave node units adopt Manchester coding, and data frames of the data frames comprise master node transceiving flag bits, all slave node transceiving information and data transceiving check bits; the data communication adopts a redundant mode for multiple data packets to realize packet loss and fault data processing of the data packets;
after the second processor generates an interrupt signal, the first processor generates a power driving signal according to the interrupt signal and sends the power driving signal to the second processor, and the second processor receives the post-coding and sends the post-coding to the third processor; the third processor generates a PWM (pulse-width modulation) interrupt signal according to the received power drive signal, updates a data frame, updates the power drive signal in real time before the PWM interrupt signal is not loaded, and transmits the power drive signal to the power module after the PWM interrupt signal is loaded so as to control the drive output of the power module; and after the first processor receives the data, PWM modulation calculation is carried out according to the data, and the power driving signal is updated.
2. The power module drive system of claim 1, wherein: the number of the first processors corresponds to the number of the slave nodes, and each first processor correspondingly generates a power driving signal of the slave node power module to be transmitted to the power module of the corresponding slave node.
3. The power module driving system according to claim 1 or 2, wherein:
the main node further comprises a main node optical fiber receiving interface and a main node optical fiber transmitting interface;
the slave node further comprises a slave node optical fiber receiving interface and a slave node optical fiber transmitting interface;
if the number of slave nodes is one:
the master node optical fiber transmitting interface is connected with the slave node optical fiber receiving interface, and the slave node optical fiber transmitting interface is connected with the master node optical fiber receiving interface;
if the number of the slave nodes is multiple:
the slave node unit comprises a head slave node, a tail slave node and an intermediate slave node, the optical fiber transmitting interface of the master node is connected with the optical fiber receiving interface of the head slave node, and the optical fiber transmitting interface of the head slave node is connected with the optical fiber receiving interface of the intermediate slave node adjacent to the optical fiber transmitting interface of the head slave node; the main node optical fiber receiving interface is connected with the tail slave node optical fiber transmitting interface, and the tail slave node optical fiber receiving interface is connected with the middle slave node optical fiber transmitting interface adjacent to the tail slave node optical fiber receiving interface; the intermediate slave node optical fiber transmitting interface is connected with the adjacent intermediate slave node optical fiber receiving interface in turn.
4. The power module drive system of claim 1, wherein: the third processor is further configured to: and acquiring a power driving signal transmitted by a previous node connected with the power driving signal, extracting and decoding the power driving signal of the slave node power module where the third processor is located, adding feedback information of the slave node power module, and transmitting the feedback information to a next node adjacent to the slave node.
5. The power module driving system according to claim 4, wherein: the second processor is further configured to acquire, decode and send the data information transmitted by the third processor to the first processor.
6. A power module drive control method using the power module drive system according to any one of claims 1 to 5, characterized by comprising:
the master node first processor calculates a power module PWM modulation algorithm according to the interrupt signal and the PWM interrupt signal, generates a power driving signal and sends the power driving signal to the second processor; the second processor receives the power driving signal, encodes the power driving signal and sends the power driving signal to the third processor of the slave node; and the third processor receives and updates the power driving signal in real time before loading the PWM interrupt signal, decodes the received power driving signal after loading the PWM interrupt signal, and sends the decoded power driving signal to the power module for driving control of the power module.
7. The power module drive control method according to claim 6, characterized in that: the number of the first processors of the main node corresponds to the number of the slave nodes, the first processors generate power driving signals, send the power driving signals to the second processors, store the power driving signals into the corresponding slave node information receiving and sending data sections, form data receiving and sending zone bits, and the second processors carry out coding sending.
8. The power module drive control method according to claim 7, characterized in that:
if the number of the slave nodes is multiple:
after a third processor of the slave node receives a power driving signal transmitted by a second processor, extracting data from a corresponding slave node information receiving and transmitting data segment, decoding the data, verifying the data, loading self feedback information into the slave node information receiving and transmitting data segment, updating a verification bit, and transmitting an updated data frame to an adjacent intermediate slave node;
after receiving data, the third processor of the middle slave node extracts data from the corresponding slave node information receiving and transmitting data segment, decodes the data, performs data verification, loads self feedback information into the slave node information receiving and transmitting data segment, updates the verification bit, and transmits the updated data frame to the next adjacent slave node;
after receiving data, the third processor of the tail slave node extracts data from the corresponding slave node information receiving and transmitting data segment, decodes the data, performs data verification, loads self feedback information into the slave node information receiving and transmitting data segment, updates the verification bit, and transmits the updated data frame to the master node;
after receiving the data, the second processor of the main node extracts the data information from the data sections of the information sent and received by all the slave nodes respectively, decodes the data information, checks the data information to be correct, and sends the data information to the corresponding first processors respectively.
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