CN111628641B - Bridgeless rectifier circuit, leakage current peak value control method and readable storage medium - Google Patents

Bridgeless rectifier circuit, leakage current peak value control method and readable storage medium Download PDF

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CN111628641B
CN111628641B CN202010449047.1A CN202010449047A CN111628641B CN 111628641 B CN111628641 B CN 111628641B CN 202010449047 A CN202010449047 A CN 202010449047A CN 111628641 B CN111628641 B CN 111628641B
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capacitor
circuit
power line
peak value
alternating current
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CN111628641A (en
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刘祖贵
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China Great Wall Technology Group Co ltd
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China Great Wall Technology Group Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Rectifiers (AREA)

Abstract

A bridgeless rectifying circuit, a leakage current peak value control method and a readable storage medium are provided, wherein the bridgeless rectifying circuit comprises a common mode filter circuit and a capacitor circuit. The common-mode filter circuit is used for suppressing a common-mode interference signal capacitance circuit in the alternating current signal and is used for controlling and reducing the voltage change rate of the common-mode filter circuit when the alternating current signal crosses zero. The common mode filter circuit includes: and the equivalent capacitance value of the capacitance circuit is greater than that of the first Y capacitor. According to the bridgeless rectifying circuit, the voltage change rate of the common mode filter circuit is reduced when an alternating current signal crosses zero by adding the capacitor circuit, so that the peak value of leakage current of the first Y capacitor is correspondingly reduced, the safety is high, and the situation that the peak value of the leakage current of an electronic product exceeds the standard and does not conform to the IEC62368 international product safety standard is avoided.

Description

Bridgeless rectifier circuit, leakage current peak value control method and readable storage medium
Technical Field
The application belongs to the technical field of switching power supplies, and particularly relates to a bridgeless rectifying circuit, a leakage current peak value control method and a readable storage medium.
Background
The conventional bridgeless rectifier circuit (see fig. 1(a) for details) has an inherent characteristic that when an AC (Alternating Current) input is at a zero-crossing point, the polarity of the input Current is reversed, so that N-PGND and PE-PGND both generate an abrupt voltage Vbulk, and the amplitude of the abrupt voltage Vbulk is large, so that a leakage Current I passing through a common-mode filter capacitor (hereinafter, referred to as a Y capacitor) CY1 is causedPEThe peak value of (c) is large (see fig. 1(b) in detail), thus threatening human safety and having low electronic product safety; the current solution is to reduce the peak value of the leakage current of the Y capacitor CY1 at the zero crossing point by reducing the capacitance value of the Y capacitor CY1, however, this operation can seriously affect the EMI characteristic of the bridgeless rectifier circuit.
Therefore, in the conventional bridgeless rectification technical scheme, the peak value of leakage current IPE of the Y capacitor CY1 is large at the zero-crossing point moment of the AC input, so that the safety of a human body is threatened, and the safety of electronic products is low.
Disclosure of Invention
The application aims to provide a bridgeless rectification circuit, a leakage current peak value control method and a readable storage medium, and aims to solve the problems that the leakage current peak value of a Y capacitor CY1 is large at the zero crossing point moment of AC input, so that the safety of a human body is threatened and the safety of electronic products is low in the traditional bridgeless rectification technical scheme.
A first aspect of an embodiment of the present application provides a bridgeless rectifier circuit, including a first energy storage circuit, a second energy storage circuit, a switch circuit, and a current flow direction control circuit, where the switch circuit is turned on or off according to a pulse width modulation signal; when the switch circuit is switched on, the first energy storage circuit and the second energy storage circuit are switched off, and an alternating current signal is output by a power line to charge the first energy storage circuit; when the switch circuit is switched off, the first energy storage circuit and the second energy storage circuit are switched on, and the first energy storage circuit discharges to the second energy storage circuit through the current flow direction control circuit so as to charge the second energy storage circuit; further comprising:
the common-mode filter circuit is connected with the power line and a protection ground and used for inhibiting common-mode interference signals in the alternating-current signals; and
the capacitor circuit is connected with the power line and the protective ground and/or the current flow direction control circuit and is used for controlling and reducing the voltage change rate of the common mode filter circuit when the alternating current signal crosses zero;
the common mode filter circuit includes: the first Y capacitor is connected between a safety ground wire of the power line and a protective ground; the equivalent capacitance value of the capacitance circuit is larger than that of the first Y capacitor.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: according to the bridgeless rectifier circuit, the capacitance circuit is additionally arranged, the equivalent capacitance value of the capacitance circuit is larger than that of the first Y capacitor, so that when an alternating current signal crosses zero, the voltage change rate of the common mode filter circuit is reduced, and the peak value of leakage current of the first Y capacitor is positively correlated with the voltage change rate at the zero crossing moment, so that the voltage change rate of the common mode filter circuit is reduced, the peak value of leakage current of the first Y capacitor is correspondingly reduced, the capacitance value of the first Y capacitor does not need to be reduced, the safety performance of an electronic product is improved, and the situation that the peak value of leakage current of the electronic product exceeds standard and does not accord with the safety standard of IEC62368 international products is avoided.
A second aspect of the embodiments of the present application provides a leakage current peak value control method, configured to perform leakage current peak value control on the bridgeless rectifier circuit, where the leakage current peak value control method includes:
detecting whether the alternating current signal crosses a zero point;
and controlling the switching circuit to perform soft start when the alternating current signal crosses zero so as to indicate that the amplitude of the alternating current signal is maintained within a preset threshold value.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the current peak value control method is applied to the bridgeless rectifier circuit provided by the first aspect of the embodiment of the application, and controls the amplitude of the alternating current signal input to the bridgeless rectifier circuit when the zero crossing point of the alternating current signal is detected, so that the amplitude is maintained within a preset threshold value; the characteristic that the peak value of leakage current of the first Y capacitor is in positive correlation with the amplitude of the alternating current signal at the zero crossing point moment is utilized, the peak value of the leakage current of the first Y capacitor is further reduced by the aid of the bridgeless rectification circuit by reducing the amplitude of the alternating current signal at the zero crossing point moment, safety performance of electronic products is improved, and the situation that the peak value of the leakage current of the electronic products exceeds the standard and does not accord with IEC62368 international product safety standards is avoided.
A third aspect of embodiments of the present application provides a readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the steps of the leakage current peak control method as described above.
Drawings
FIG. 1(a) is a schematic circuit diagram of a conventional bridgeless rectifier circuit;
FIG. 1(b) is a timing diagram of the bridgeless rectifier circuit shown in FIG. 1 (a);
fig. 2(a) is a schematic block diagram of a bridgeless rectifier circuit according to a first aspect of an embodiment of the present disclosure;
fig. 2(b) is a schematic block diagram of another bridgeless rectifier circuit according to the first aspect of an embodiment of the present application;
FIG. 3 is a schematic circuit diagram of the bridgeless rectifier circuit shown in FIG. 2 (b);
FIG. 4 is another schematic circuit diagram of the bridgeless rectifier circuit shown in FIG. 2 (b);
FIG. 5 is yet another schematic circuit diagram of the bridgeless rectifier circuit shown in FIG. 2 (b);
FIG. 6 is a further schematic circuit diagram of the bridgeless rectifier circuit shown in FIG. 2 (b);
FIG. 7 is a further schematic circuit diagram of the bridgeless rectifier circuit shown in FIG. 2 (b);
FIG. 8 is a first equivalent circuit diagram of the bridgeless rectifier circuit shown in FIG. 7;
FIG. 9 is a second equivalent circuit diagram of the first equivalent circuit diagram of FIG. 8;
fig. 10 is a detailed flowchart of a leakage current peak control method according to a second aspect of the present application;
FIG. 11 is a schematic diagram illustrating an application of the leakage current peak control method shown in FIG. 10;
FIG. 12 is a schematic diagram of a first operating state of the bridgeless rectifier circuit shown in FIG. 7;
FIG. 13 is a schematic diagram of a second operating state of the bridgeless rectifier circuit shown in FIG. 7;
FIG. 14 is a schematic diagram of a third operating state of the bridgeless rectifier circuit shown in FIG. 7;
fig. 15 is a fourth operating state diagram of the bridgeless rectifier circuit shown in fig. 7.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 2(a), a schematic block diagram of a bridgeless rectifier circuit according to a first aspect of an embodiment of the present application is shown, for convenience of description, only the parts related to the embodiment are shown, and the details are as follows:
a bridgeless rectifying circuit comprises a first energy storage circuit 10, a second energy storage circuit 20, a switch circuit 30, a current flow direction control circuit 40, a common mode filter circuit 50 and a capacitor circuit 60.
Wherein, the switch circuit 30 is turned on or off according to the pulse width modulation signal PWM; when the switch circuit 30 is turned on, the first tank circuit 10 and the second tank circuit 20 are turned off, and the power line outputs an ac signal Vin to charge the first tank circuit 10; when the switch circuit 30 is turned off, the first tank circuit 10 and the second tank circuit 20 are turned on, and the first tank circuit 10 discharges to the second tank circuit 20 through the current flow control circuit 40, so as to charge the second tank circuit 20.
Specifically, the ac signal Vin is mains supply throughout the text.
The common mode filter circuit 50 is connected with the power line and a protection ground PGND; the capacitor circuit 60 is connected to the power line and the protection ground PGND, and/or to the current flow direction control circuit 40.
The common mode filter circuit 50 is used for suppressing a common mode interference signal in the alternating current signal Vin; the capacitor circuit 60 is used for controlling and reducing the voltage change rate of the common mode filter circuit 50 when the alternating current signal Vin crosses zero, and specifically, reducing the voltage change rate of the first Y capacitor CY1 in the common mode filter circuit 50.
The common mode filter circuit 50 includes: and a first Y capacitor CY1 connected between the safety ground PE and the protection ground PGND of the power line.
In particular, the leakage current I of the first Y capacitor CY1 at the zero crossing pointPE＝CY1*(dVCY1/dt)，IPEIs the leakage current peak value, C, of the first Y capacitor CY1Y1Is the value, dV, of the first Y capacitor CY1CY1And/dt is the voltage rate of change of the first Y capacitor CY1 at the zero crossing. At the time of the zero crossing, the leakage current I of the first Y capacitor CY1PEIs positively correlated with the rate of change of voltage. In this embodiment, the capacitor circuit 60 is additionally provided on the basis of the conventional bridgeless rectifier circuit, the capacitor circuit 60 is set at a specific node, and the equivalent capacitance value of the capacitor circuit 60 is set to be greater than the capacitance value of the first Y capacitor CY1, so that the common mode filter circuit 5 is enabled to be a common mode filter circuitThe voltage change rate of the first Y capacitor CY1 at 0 is reduced at the zero-crossing point, so that the peak value of the leakage current of the first Y capacitor CY1 at the zero-crossing point can be reduced without reducing the capacitance value of the first Y capacitor CY 1.
Specifically, when the capacitor circuit 60 is connected to the power line and the protection ground PGND, it may be connected to the live line L and the protection ground PGND of the power line, or may be connected to the zero line N and the protection ground PGND of the power line; when the capacitor circuit 60 is connected to the current flow direction control circuit 40, two ends of the capacitor circuit 60 are connected to one input end and one output end of the current flow direction control circuit 40, respectively.
The equivalent capacitance value of the capacitance circuit 60 is greater than the capacitance value of the first Y capacitor CY 1. The capacitor circuit 60 has multiple connection modes, any connection mode can reduce the voltage change rate of the first Y capacitor CY1 at the zero crossing point, different designs can be performed according to actual needs when PCB layout is performed, and flexibility is high. It should be noted that fig. 2(a) only shows the case where the capacitor circuit 60 is connected between the live line L and the protection ground PGND of the power line for example, and other connection cases are not shown, and those skilled in the art should understand that the capacitor circuit 60 has various connection cases in combination with fig. 3 to 7 described below.
Optionally, as shown in fig. 2(b), the common mode filter circuit 50 further includes a second Y capacitor CY2 and a third Y capacitor CY 3.
The second Y capacitor CY2 is connected between the neutral line N of the power line and the protection ground PGND; the third Y capacitor CY3 is connected between the live line L of the power line and the protection ground PGND.
Specifically, the second Y capacitor CY2 and the third Y capacitor CY3 are used for filtering out common mode interference noise in the ac signal Vin.
Referring to fig. 3 to 7, schematic circuit schematic diagrams of the bridgeless rectifier circuit shown in fig. 2(b) are shown, and for convenience of description, only the parts related to the present embodiment are shown, and detailed descriptions are as follows:
as shown in fig. 3 to 7, the first energy storage circuit 10 is implemented by an inductor L1, and the inductor L1 is connected to the ac signal Vin and is connected to an input end of the control circuit 40.
The switching circuit 30 is implemented by a first NMOS transistor Q1 and a second NMOS transistor Q2 connected with the first NMOS transistor Q1, the first NMOS transistor Q1 is connected with the first energy storage circuit 10 and the current flow direction control circuit 40, and the second NMOS transistor current flows to the control circuit 40; and the controlled terminals of the first NMOS transistor Q1 and the second NMOS transistor Q2 are connected to the pulse width modulation signal PWM.
The current flow control circuit 40 is realized by four diodes D1, D2, D3 and D4, and a node where the cathode of the diode D1 and the cathode of the diode D3 are connected in common is used as a first output end of the current flow control circuit 40; the node at which the anode of the diode D2 and the anode of the diode D2 are connected together serves as a second output terminal of the current flow control circuit 40; the node where the anode of the diode D3 and the cathode of the diode D4 are connected together serves as a first input terminal of the current flow control circuit 40; the node at which the anode of the diode D1 and the cathode of the diode D2 are connected together serves as a second input terminal of the current flow control circuit 40.
The second tank circuit 20 is implemented by using a capacitor C5, and specifically, the capacitor C5 is an electrolytic capacitor. Of second C5
The first NMOS transistor Q1 and the second NMOS transistor Q2 are correspondingly switched on or off according to a pulse width modulation signal PWM; when the inductor L1 is connected, the capacitor C5 is disconnected, and the alternating current signal Vin charges the inductor L1; when the inductor L1 and the capacitor C5 are turned on, the inductor L1 discharges to the capacitor C5 through the current flowing to the control circuit 40, and the capacitor C5 charges. The rectifier circuit alternately stores energy through an inductor L1 and a capacitor C5 to achieve a rectifying function.
In an alternative embodiment, the capacitance circuit 60 includes at least one capacitor.
The two ends of the capacitor are connected to the power line and the protection ground PGND, respectively, or to the current flow direction control circuit 40. Specifically, when the two ends of the capacitor are connected to the power line and the protection ground PGND, respectively, the capacitor is connected to the live line L and the protection ground PGND of the power line, or connected to the neutral line N and the protection ground PGND of the power line.
As shown in fig. 3, in one embodiment, the capacitance circuit 60 includes a first capacitance C1.
The first end of the first capacitor C1 is connected to the live line L of the power line, and the second end of the first capacitor C1 is connected to the safety ground PE of the power line.
As shown in fig. 4, in one embodiment, the capacitor circuit 60 includes a second capacitor C2.
The first end of the second capacitor C2 is connected with a zero line N of the power line, and the second end of the second capacitor C2 is connected with a safety ground wire PE of the power line.
As shown in fig. 5, in one embodiment, the capacitor circuit 60 includes a third capacitor C3.
The first terminal of the third capacitor C3 is connected to the first output terminal of the current flow control circuit 40, and the second terminal of the third capacitor C3 is connected to the first input terminal of the current flow control circuit 40.
Specifically, the first output terminal of the current flow control circuit 40 is a node where the cathode of the diode D1 and the cathode of the diode D3 are connected together. The first input of the current flow control circuit 40 is the node where the anode of diode D3 is coupled to the cathode of diode D4.
As shown in fig. 6, in one embodiment, the capacitor circuit 60 includes a fourth capacitor C4.
The first terminal of the fourth capacitor C4 is connected to the second output terminal of the current flow control circuit 40, and the second terminal of the fourth capacitor C4 is connected to the second input terminal of the current flow control circuit 40.
Specifically, the second output terminal of the current flow control circuit 40 is a node at which the anode of the diode D2 and the anode of the diode D2 are connected together, and the second input terminal of the current flow control circuit is a node at which the anode of the diode D1 and the cathode of the diode D2 are connected together.
In an alternative embodiment, the capacitance circuit 60 includes at least two capacitors.
Two ends of one of the capacitors are respectively connected to the power line and the protection ground PGND, or respectively connected to an input terminal and an output terminal of the current flow direction control circuit 40.
Specifically, when the two ends of the capacitor are connected to the power line and the protection ground PGND, respectively, the capacitor is connected to the live line L and the protection ground PGND of the power line, or connected to the neutral line N and the protection ground PGND of the power line.
The other capacitor has two ends respectively connected to the power line and the protection ground PGND, or respectively connected to an input terminal and an output terminal of the current flow direction control circuit 40.
As shown in fig. 7, in an alternative embodiment, the capacitor circuit 60 includes the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4, and the specific connection manner of the capacitors is as shown in fig. 3 to fig. 6.
A first end of the first capacitor C1 is connected to the live line L of the power line, and a second end of the first capacitor C1 is connected to the safety ground PE of the power line.
The first end of the second capacitor C2 is connected with the zero line N of the power line, and the second end of the second capacitor C2 is connected with the safety ground PE of the power line.
A first terminal of the third capacitor C3 is coupled to the first output terminal of the current flow control circuit 40, and a second terminal of the third capacitor C3 is coupled to the first input terminal of the current flow control circuit 40.
The first terminal of the fourth capacitor C4 is connected to the second output terminal of the current-flow control circuit 40, and the second terminal of the third capacitor C3 is connected to the second input terminal of the current-flow control circuit 40.
It should be noted that the capacitor circuit 60 provided in the present application is implemented by using any one or more of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4, and the specific connection manner of each capacitor is respectively shown in fig. 3 to fig. 6. The specific implementation of which capacitor/capacitors are used for the capacitive circuit 60 does not affect the implementation of the functions of the capacitive circuit 60 itself.
In any connection type of the capacitor circuit 60, the equivalent capacitance value is larger than that of the first Y capacitor CY 1. For example: a capacitor circuit 60 is composed of the first capacitor C1 and the third capacitor C3, wherein the first end of the first capacitor C1 is connected with a live wire L of a power line, the second end of the first capacitor C1 is connected with a safety ground wire PE of the power line, the first end of the third capacitor C3 is connected with a first output end of a current flow control circuit 40, and the second end of the third capacitor C3 is connected with a first input end of the current flow control circuit 40; the equivalent capacitance value of the capacitor circuit 60 is determined by the capacitance value of the first capacitor C1 and the capacitance value of the third capacitor C3, and the equivalent capacitance value of the capacitor circuit 60 is greater than the capacitance value of the first Y capacitor CY 1.
As can be seen from fig. 3 to 7, the capacitor circuit 60 has a plurality of connection modes, and any connection mode can reduce the voltage change rate at the two ends of the first Y capacitor CY1 at the zero-crossing point, so that different designs can be performed according to actual requirements when PCB layout is performed, and flexibility is high.
The operation principle of the bridgeless rectifier circuit provided by the present application will be described with reference to fig. 7, 8 and 9.
Fig. 8 is a first equivalent circuit diagram of the bridgeless rectifier circuit shown in fig. 7, which only shows the parts related to the present embodiment for convenience of description, and the details are as follows:
for the alternating current signal Vin, that is, when the commercial power crosses the zero point, an abrupt voltage Vbulk is generated at the N-PGND, and a fundamental frequency of the abrupt voltage Vbulk is much higher than a frequency of the commercial power, that is, in an abrupt voltage interval of the N-PGND, an input voltage of the alternating current signal Vin is substantially unchanged. Therefore, when analyzing the effect of the abrupt voltage Vbulk on the peak value of the leakage current of the first wyrd capacitor, the input commercial power can be equivalent to direct current, so as to obtain the first equivalent circuit diagram shown in fig. 8.
As shown in fig. 8, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 in fig. 7 are actually connected in parallel in the equivalent model, and are connected in parallel between the zero line N of the power line and the protection ground PGND.
In the capacitor circuit 60 of another form, if any one of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 is used, the capacitor is connected between the neutral line N of the power line and the protection ground PGND in the equivalent model; if any capacitors of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are adopted, the capacitors are correspondingly connected in parallel between the zero line N of the power line and the protection ground PGND.
Please refer to fig. 9, which is a second equivalent circuit diagram of the first equivalent circuit diagram shown in fig. 8, for convenience of description, only the parts related to the present embodiment are shown, and the details are as follows:
according to FIG. 8, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitorThe capacitance values of the capacitor C4 jointly determine the equivalent capacitance value of the capacitor circuit 60 shown in FIG. 7, and the equivalent capacitance value of the capacitor circuit 60 shown in FIG. 7 is assumed to be CΣThen C isΣC1+ C2+ C3+ C4. In an actual circuit, the ground line PE and the neutral line N are independent of each other, but their potentials are the same, and therefore the second Y capacitor CY2 and the third Y capacitor CY3 are in a virtual short state with respect to their voltages and in a virtual off state with respect to their currents. Accordingly, the first equivalent circuit of fig. 8 can be further equivalent, resulting in the second equivalent circuit shown in fig. 9.
According to fig. 9, given the input current Iin of the mains, the rate of change of the voltage across the first Y capacitor CY1 can be determined:
dVCY1/dt＝dVCΣ/dt＝Iin/CΣ；
wherein, dVCY1The voltage change rate of the first Y capacitor CY1 at the zero crossing point is I/dtinThe amplitude value, C, of the input current Iin corresponding to the AC signal Vin at the zero crossing pointΣIs the equivalent capacitance value, C, of the capacitance circuit 60Σ＞CY1。
Therefore, at the time of the zero crossing point of the ac signal Vin, the peak value of the leakage current passing through the first Y capacitor CY1 is:
IPE＝CY1*(dVCY1/dt)＝Iin*(CY1/CΣ)；
wherein, IPEIs the leakage current peak value, C, of the first Y capacitor CY1Y1Is the capacitance value, I, of the first Y capacitor CY1inThe amplitude value, C, of the input current Iin of the mains supply at the zero crossing pointΣIs the equivalent capacitance value, dV, of the capacitance circuit 60CY1The voltage change rate of the first Y capacitor CY1 at the zero crossing point is/dt; cΣ＞CY1。
From the above analysis, at the zero crossing point of the ac signal Vin, the equivalent capacitor formed by the capacitor circuit 60 is connected in parallel with the first Y capacitor CY1, and I is knowninBy increasing the equivalent capacitance value CΣThe leakage current peak value passing through the first Y capacitor CY1 at the zero crossing point of the alternating current signal Vin can be reduced without reducing the capacitance value of the first Y capacitor CY1On the premise of not influencing the EMI characteristic of the bridgeless rectifying circuit, the leakage current peak value of the first Y capacitor CY1 at the zero crossing point moment is reduced.
Referring to fig. 10, a detailed flowchart of a leakage current peak control method according to a second aspect of the present application is shown, for convenience of description, only the relevant portions of the present embodiment are shown, and the following detailed description is given:
a leakage current peak value control method is used for the bridgeless rectification circuit to carry out leakage current peak value control, and comprises the following steps:
step S100: and detecting whether the alternating current signal Vin crosses the zero point.
Step S200: the control switch circuit 30 performs soft start at the zero crossing point of the ac signal Vin to indicate that the amplitude of the ac signal Vin is maintained within a preset threshold.
As can be seen from the foregoing analysis of the first equivalent circuit and the second equivalent circuit of the bridgeless rectifier circuit, at the time of the zero crossing point of the ac signal Vin, the peak value of the leakage current passing through the first Y capacitor CY1 is:
IPE＝CY1*(dVCY1/dt)＝Iin*(CY1/CΣ)；
wherein, IPEIs the leakage current peak value, C, of the first Y capacitor CY1Y1Is the capacitance value, I, of the first Y capacitor CY1inThe amplitude value, C, of the input current Iin corresponding to the AC signal Vin at the zero crossing pointΣIs the equivalent capacitance value, dV, of the capacitance circuit 60CY1The voltage change rate of the first Y capacitor CY1 at the zero crossing point is/dt; cΣ＞CY1。
According to the leakage current peak value control method provided by the embodiment, the amplitude of the alternating current signal Vin at the zero crossing point is controlled, so that the leakage current peak value of the first Y capacitor CY1 keeps a lower value at the zero crossing point, the auxiliary bridgeless rectification circuit further reduces the leakage current peak value of the first Y capacitor CY1, the safety performance of electronic products is improved, and the situation that the leakage current peak value of the electronic products exceeds the standard and does not accord with the IEC62368 international product safety standard is avoided.
In an optional embodiment, step S100 specifically includes:
step S101: detecting whether the voltage value at the two ends of the capacitor circuit 60 reaches a preset voltage value;
step S102: when the voltage value at the two ends of the capacitor circuit 60 reaches the preset voltage value, it is determined that the alternating current signal Vin is in the zero crossing point state.
In an optional embodiment, step S200 specifically includes:
step S201: and controlling the pulse width modulation signal PWM to be output to the switch circuit 30 according to the rule that the duty ratio is from small to large when the alternating current signal Vin crosses zero.
Please refer to fig. 11, which is a schematic diagram illustrating an application of the leakage current peak control method shown in fig. 10, for convenience of description, only the parts related to the present embodiment are shown, and the following details are described below:
with reference to the timing diagram of fig. 1(b), the leakage current peak control method provided by the present application actually controls the on and off laws of the first NMOS transistor Q1 and the second NMOS transistor Q2 near the zero crossing point of the ac signal Vin, specifically, by increasing the input current Iin at the time of the soft start control zero crossing point, the input current Iin maintains a smaller amplitude I near the zero crossing pointinUp to the equivalent capacitance CΣAfter full charge or discharge (i.e. C)ΣAfter the voltage at the two ends has been suddenly changed) and then switched back to the normal control mode; the "normal control mode" refers to a control module that directly outputs the pulse width modulation signal PWM to the first NMOS transistor Q1 and the second NMOS transistor Q2 according to a fixed duty ratio.
The sudden change of the voltage between the N-PGND, namely the two ends of the first Y capacitor CY1, near the zero crossing point of the mains supply can be slowed down, so that the peak value of the leakage current flowing through the first Y capacitor CY1 is reduced. A zero-crossing soft start module and a signal detection and algorithm control module thereof are added between a PWM control module (used for outputting a pulse width modulation signal PWM) and a driving module (used for driving a first NMOS transistor Q1 and a second NMOS transistor Q2). When the zero crossing point of the alternating current signal Vin is detected, the zero crossing soft start module is started, the pulse width modulation signal PWM is output to the driving module according to the rule that the duty ratio is from small to large, and the driving module soft starts the first NMOS tube Q1 and the second NMOS tube Q2. When the equivalent capacitance C is detectedΣAfter the voltage at both ends has finished the step change, the soft is finishedControl is started, and the driving modules of the first NMOS transistor Q1 and the second NMOS transistor Q2 return to be directly provided by the PWM control module.
Please refer to fig. 12 to 15, which are schematic diagrams of an operating state of the bridgeless rectifier circuit shown in fig. 7, for convenience of description, only the parts related to the present embodiment are shown, and the details are as follows:
the working principle of the bridgeless rectifier circuit provided by the present application in any timing cycle is analyzed below with reference to the waveform timing diagram shown in fig. 1(b) and fig. 12 to 15.
In the time period t0-t3, the alternating current signal Vin is in the positive half cycle:
(1) as shown in fig. 12, at time t0-t1, the first NMOS transistor Q1 and the second NMOS transistor Q2 are turned on, and the power line outputting the ac signal Vin, the inductor L1, the first NMOS transistor Q1, and the second NMOS transistor Q2 form a closed loop, at which time the inductor L1 stores energy.
(2) As shown in fig. 13, at time t1-t2, the first NMOS transistor Q1 and the second NMOS transistor Q2 are turned off, the power line outputting the ac signal Vin, the inductor L1, the diode D1, the capacitor C5, and the diode D4 form a closed loop, the inductor L1 discharges to the capacitor C5 through the diodes D1 and D4, and the capacitor C5 stores energy.
(3) Repeating the processes (1) and (2) in the time period of t2-t 3.
In the time period t3-t6, the alternating current signal Vin is at negative half cycle:
(4) as shown in fig. 14, at time t3-t4, the first NMOS transistor Q1 and the second NMOS transistor Q2 are turned on, and the power line outputting the ac signal Vin, the first NMOS transistor Q1, the second NMOS transistor Q2, and the inductor L1 form a closed loop, and at this time, the inductor L1 stores energy.
(5) As shown in fig. 15, at time t4-t5, the first NMOS transistor Q1 and the second NMOS transistor Q2 are turned off, a power line outputting the ac signal Vin, the diode D3, the capacitor C5, the diode D2, and the inductor L1 form a closed loop, the inductor L1 discharges to the capacitor C5 through the diodes D3 and D2, and the capacitor C5 stores energy.
(6) Repeating the processes (4) and (5) in the time period of t5-t 6.
In any timing cycle, the voltage jump state of the alternating current signal Vin at the zero-crossing time PE-PGND is as follows:
at time t0, the PE-PGND jumps from Vbulk to 0V;
at time t3, the PE-PGND jumps from 0V to Vbulk;
at time t6 (i.e., at time t0 of the next cycle), PE-PGND jumps from Vbulk to 0V, and the cycle is repeated.
The third aspect of the present application also provides a readable storage medium, which stores a computer program, which when executed by a processor implements the steps of the above-mentioned current peak control method.
Specifically, all or part of the steps in the current peak control method may be implemented by a computer program instructing related hardware, where the computer program may be stored in a readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as required by legislation and patent practice.
In summary, the present application provides a bridgeless rectifier circuit, a leakage current peak value control method, and a readable storage medium, wherein the bridgeless rectifier circuit reduces the voltage change rate of the common mode filter circuit through a newly added capacitor circuit when an ac signal crosses zero, thereby correspondingly reducing the leakage current peak value of the first Y capacitor, and avoiding the situation that the leakage current peak value of an electronic product exceeds the standard and does not meet the safety standard of IEC62368 international products. The provided current peak value control method is applied to the bridgeless rectification circuit provided by the application, and controls the amplitude of an alternating current signal input to the bridgeless rectification circuit when the zero crossing point of the alternating current signal is detected so as to keep the amplitude within a preset threshold value; the characteristic that the peak value of leakage current of the first Y capacitor at the zero crossing point moment is in positive correlation with the amplitude of the alternating current signal is utilized, the amplitude of the alternating current signal at the zero crossing point moment is reduced, the auxiliary bridgeless rectification circuit further reduces the peak value of the leakage current of the first Y capacitor, the safety performance of electronic products is improved, and the situation that the peak value of the leakage current of the electronic products exceeds the standard and does not accord with the IEC62368 international product safety standard is avoided.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

Claims (10)

1. A bridgeless rectification circuit comprises a first energy storage circuit, a second energy storage circuit, a switching circuit and a current flow direction control circuit, wherein the switching circuit is switched on or off according to a pulse width modulation signal; when the switch circuit is switched on, the first energy storage circuit and the second energy storage circuit are switched off, and an alternating current signal is output by a power line to charge the first energy storage circuit; when the switch circuit is switched off, the first energy storage circuit and the second energy storage circuit are switched on, and the first energy storage circuit discharges to the second energy storage circuit through the current flow direction control circuit so as to charge the second energy storage circuit; the switching circuit is based on whether the alternating current signal crosses the zero point and carries out soft start to control the amplitude of the alternating current signal input to the bridgeless rectification circuit, and is characterized by further comprising:
the common-mode filter circuit is connected with the power line and a protection ground and used for inhibiting common-mode interference signals in the alternating-current signals; and
the capacitor circuit is connected with the power line and the protective ground and/or the current flow direction control circuit and is used for controlling and reducing the voltage change rate of the common mode filter circuit when the alternating current signal crosses zero;
the common mode filter circuit includes: the first Y capacitor is connected between a safety ground wire of the power line and a protective ground; the equivalent capacitance value of the capacitance circuit is larger than that of the first Y capacitor.
2. The bridgeless rectifier circuit of claim 1 wherein the capacitive circuit comprises:
at least one capacitor;
and two ends of the capacitor are respectively connected with the power line and the protective ground or are connected with the current flow direction control circuit in parallel.
3. The bridgeless rectifier circuit of claim 1 wherein the capacitive circuit comprises:
at least two capacitors;
two ends of one capacitor are respectively connected with the power line and the protective ground, or respectively connected with one input end and one output end of the current flow direction control circuit;
and the two ends of the other capacitor are respectively connected with the power line and the protective ground, or respectively connected with one input end and one output end of the current flow direction control circuit.
4. The bridgeless rectifier circuit of claim 1 wherein the capacitive circuit comprises:
the first capacitor, the second capacitor, the third capacitor and the fourth capacitor;
the first end of the first capacitor is connected with a live wire of the power line, and the second end of the first capacitor is connected with a safety ground wire of the power line;
the first end of the second capacitor is connected with a zero line of the power line, and the second end of the second capacitor is connected with a safety ground wire of the power line;
the first end of the third capacitor is connected with the first output end of the current flow direction control circuit, and the second end of the third capacitor is connected with the first input end of the current flow direction control circuit;
and the first end of the fourth capacitor is connected with the second output end of the current flow direction control circuit, and the second end of the fourth capacitor is connected with the first input end of the current flow direction control circuit.
5. The bridgeless rectifier circuit of claim 1 wherein the common mode filter circuit further comprises:
a second Y capacitor and a third Y capacitor;
the second Y capacitor is connected between a zero line of the power line and a protective ground; the third Y capacitor is connected between the live wire of the power line and the protective ground.
6. A leakage current peak value control method for performing leakage current peak value control on the bridgeless rectifier circuit according to any one of claims 1 to 5, the leakage current peak value control method comprising:
detecting whether the alternating current signal crosses a zero point;
and controlling the switching circuit to perform soft start when the alternating current signal crosses zero so as to indicate that the amplitude of the alternating current signal is maintained within a preset threshold value.
7. The current peak control method of claim 6, wherein detecting whether the alternating current signal crosses a zero point specifically comprises:
detecting whether the voltage values at two ends of the capacitor circuit reach preset voltage values or not;
and when the voltage values at the two ends of the capacitor circuit reach a preset voltage value, judging that the alternating current signal is in a zero crossing point state.
8. The current peak control method of claim 6, wherein controlling the switching circuit to soft start at a zero crossing of the ac signal comprises:
and controlling the pulse width modulation signal to be output to the switching circuit according to the rule that the duty ratio is from small to large when the alternating current signal crosses zero.
9. The current peak control method according to claim 6, wherein the leakage current peak value of the first Y capacitor at the time of zero crossing is:
IPE＝CY1*(dVCY1/dt)＝Iin*(CY1/CΣ)；
wherein, IPEIs the leakage current peak value of the first Y capacitor, CY1Is the capacitance value of the first Y capacitor, IinAmplitude of the AC signal at zero crossing, CΣIs the equivalent capacitance value, dV, of a capacitive circuitCY1The voltage change rate of the first Y capacitor at the zero crossing point is/dt; cΣ＞CY1。
10. A readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the current peak control method according to any one of claims 6 to 9.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102946203A (en) * 2011-08-08 2013-02-27 西门子公司 Insulated power supply
CN106688170A (en) * 2014-09-11 2017-05-17 飞利浦照明控股有限公司 Charge pump effect compensation for high frequency isolation transformer in lighting device power supplies
CN107852087A (en) * 2015-07-09 2018-03-27 建筑电子与通信公司 High power density inverter (i)
CN108631580A (en) * 2017-03-21 2018-10-09 中国长城科技集团股份有限公司 A kind of current sampling circuit and without bridge commutation system
US10640007B2 (en) * 2013-06-11 2020-05-05 Panasonic Intellectual Property Management Co., Ltd. Charging device that reduces an amount of noise flowing through a charging system in a vehicle

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102843844B (en) * 2012-09-28 2015-06-03 深圳市明微电子股份有限公司 LED (Light Emitting Diode) control circuit and LED illumination device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102946203A (en) * 2011-08-08 2013-02-27 西门子公司 Insulated power supply
US10640007B2 (en) * 2013-06-11 2020-05-05 Panasonic Intellectual Property Management Co., Ltd. Charging device that reduces an amount of noise flowing through a charging system in a vehicle
CN106688170A (en) * 2014-09-11 2017-05-17 飞利浦照明控股有限公司 Charge pump effect compensation for high frequency isolation transformer in lighting device power supplies
CN107852087A (en) * 2015-07-09 2018-03-27 建筑电子与通信公司 High power density inverter (i)
CN108631580A (en) * 2017-03-21 2018-10-09 中国长城科技集团股份有限公司 A kind of current sampling circuit and without bridge commutation system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
6kW电动汽车充电桩三相整流模块研究与设计;齐如军;《中国优秀硕士论文》;20170215;全文 *
Signal compensation in CZT detectors grown by the Vertical Bridgman method using a twin-shaping filter technique;N. Auricchio;《2015 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)》;20161006;全文 *

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