CN111613260B - Digital signal processing circuit and method - Google Patents
Digital signal processing circuit and method Download PDFInfo
- Publication number
- CN111613260B CN111613260B CN202010289516.8A CN202010289516A CN111613260B CN 111613260 B CN111613260 B CN 111613260B CN 202010289516 A CN202010289516 A CN 202010289516A CN 111613260 B CN111613260 B CN 111613260B
- Authority
- CN
- China
- Prior art keywords
- digital signal
- signal processing
- unit
- processing unit
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Microcomputers (AREA)
Abstract
The invention discloses a digital signal processing circuit and a method, which relate to the technical field of data acquisition and comprise a digital signal processing unit, a programmable logic unit and a data memory unit; the programmable logic unit is connected with the digital signal processing unit, the data memory unit is connected with the digital signal processing unit, the digital signal processing unit is used for real-time digital signal data processing, the data memory unit is used for data caching in the real-time calculation process of the digital signal processing unit, and the programmable logic unit is a sequential logic control center to coordinate the work of the whole circuit; the invention provides a DSP signal processing circuit and a DSP signal processing method of data acquisition equipment, which adopt a series of chips of ADI company as a processor and form a hardware test platform by matching with necessary peripheral circuits, so that the whole scheme of the system can meet the real-time analysis requirement of multi-channel signals and obtain better effect in actual test.
Description
Technical Field
The invention relates to the technical field of data acquisition, in particular to data real-time signal analysis, a digital signal processing circuit and a digital signal processing method.
Background
The multichannel dynamic characteristic tester needs to be developed aiming at the application requirements of high precision and accurate flutter boundary prediction of thermal modal parameters of components such as an aircraft engine, a wing and the like in a ground resonance test and a flutter test flight test. And wherein the critical function is real-time signal analysis of the data. How to realize real-time processing of mass data and simultaneously ensure that data analysis is quick and effective is the problem to be solved by each number of acquisition devices. Along with the development of data acquisition equipment, the application of data acquisition equipment with multiple channels, high precision and high sampling rate is gradually wide, and new software and hardware design needs to be carried out on a digital signal processing circuit so as to meet the use requirement.
Disclosure of Invention
The embodiment of the invention provides a digital signal processing circuit and a digital signal processing method. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
The first aspect of the embodiments of the present invention provides a digital signal processing circuit, which includes a digital signal processing unit, a programmable logic unit, and a data memory unit;
the programmable logic unit is connected with the digital signal processing unit, and the data memory unit is connected with the digital signal processing unit;
the digital signal processing unit is used for real-time digital signal data processing;
the data memory unit is used for caching data in the real-time calculation process of the digital signal processing unit;
the programmable logic unit is a sequential logic control center to coordinate the work of the whole circuit.
Preferably, the programmable logic unit and the digital signal processing unit are connected in a manner of logic signal input and output, that is, logic input and logic output.
Preferably, the logic output is a control timing signal output by the programmable logic unit, so that timing coordination between the digital signal processing unit and various peripheral devices is realized.
Preferably, the peripheral device comprises an interrupt system of the digital signal processing unit, a storage space, an a/D sampling and sampling data transmission and data storage unit.
Preferably, the programmable logic unit controls the priority and triggering condition of the interrupt of the digital signal processing unit through the output control timing signal.
Preferably, the connection mode of the data memory unit and the digital signal processing unit is a communication mode, and the data in the data memory unit is transmitted to the digital signal processing unit in a transmission mode of a communication protocol.
Preferably, the digital signal processing unit selects a digital signal processor DSP for floating point calculation; the Programmable Logic unit is a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA) (field Programmable Gate array); the data memory unit is synchronous Dynamic random access memory SDRAM (synchronous Dynamic random access memory).
A second aspect of an embodiment of the present invention provides a digital signal processing method, where the digital signal processing circuit includes the following steps:
s1: initializing the digital signal processing unit;
s2: clearing the control command word value;
s3: opening an interrupt program;
s4: turning off the interrupt program;
s5: judging whether the value of the control command word is equal to 1 or not;
s6: if the number is equal to 1, entering a self-test program;
s7: if not, starting the interrupt program;
s8: return is made to S4.
Preferably, the Time for executing the interrupt routine is shorter than the Time for writing a batch of data into the FIFO or the dual-port RAM memory.
Preferably, the interrupt routine of S3 and S7 includes the steps of:
a1: reading in a first-in first-out queue FIFO or a buffer dest of a double-port RAM memory;
a2: adding 1 to the value of the batch counter;
a3: judging whether the batch counter value is equal to the execution Time of the interrupt program, if so, ending the interrupt program, and if not, entering the next step;
a4: putting the data in the memory buffer dest into a memory buffer source;
a5: sending a batch of data through an interface;
a6: clearing the value of the batch counter;
a7: paying an initial value of the address pointer;
a8: and (6) ending.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the invention provides a digital signal processing circuit and a method, which can realize real-time processing of mass data. The design adopts ADI serial chips as a processor and is matched with necessary peripheral circuits to form a hardware test platform, so that the whole scheme of the system can meet the requirement of real-time analysis of multi-channel signals and obtain better effect in actual test.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
FIG. 1 is a schematic diagram of a digital signal processing circuit according to an exemplary embodiment;
FIG. 2 is a schematic diagram illustrating a main program flow for digital signal processing according to an exemplary embodiment;
FIG. 3 is a digital signal processing interrupt subroutine flow diagram according to an exemplary embodiment;
FIG. 4 is a schematic circuit diagram of embodiment 1 shown in accordance with an exemplary embodiment;
in the figure: 1-digital signal processing unit, 2-programmable logic unit, 3-data memory unit.
Detailed Description
The technical solutions of the present invention will be clearly and completely described below in connection with specific embodiments, but it should be understood by those skilled in the art that the embodiments described below are only for illustrating the present invention and should not be construed as limiting the scope of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Preferred embodiments of the present invention will be described in detail with reference to the following examples. It is to be understood that the following examples are given for illustrative purposes only and are not intended to limit the scope of the present invention. Various modifications and substitutions may be made by those skilled in the art without departing from the spirit and scope of the invention, and all such modifications and substitutions are intended to be within the scope of the claims.
The experimental procedures used in the following examples are all conventional procedures unless otherwise specified. Materials, reagents and the like used in the following examples are commercially available unless otherwise specified.
Example 1
As shown in fig. 1, a digital signal processing circuit includes a digital signal processing unit 1, a programmable logic unit 2, and a data memory unit 3; the programmable logic unit is connected with the digital signal processing unit, and the data memory unit is connected with the digital signal processing unit; the digital signal processing unit is used for real-time digital signal data processing; the data memory unit is used for caching data in the real-time calculation process of the digital signal processing unit; the programmable logic unit is a sequential logic control center to coordinate the work of the whole circuit.
According to the above scheme, further, the programmable logic unit and the digital signal processing unit are connected in a manner of logic signal input and output, that is, logic input and logic output.
According to the above scheme, further, the logic output is a control timing signal output by the programmable logic unit, so that timing coordination between the digital signal processing unit and various peripheral devices is realized.
According to the above scheme, further, the peripheral device includes an interrupt system, a memory space, an a/D sampling and sampling data transmission and data storage unit of the digital signal processing unit.
According to the above scheme, further, the programmable logic unit controls the priority and the triggering condition of the interrupt of the digital signal processing unit through the output control timing signal.
According to the above scheme, further, the connection mode of the data memory unit and the digital signal processing unit is a communication mode, and the data in the data memory unit is transmitted to the digital signal processing unit in a transmission mode of a communication protocol.
In an embodiment, as shown in fig. 4, the DSP chip employs an SHARC DSP, which has excellent floating point processing capability and does not require additional logic. Specifically, an ADSP-21065L type DSP chip of ADI company is adopted, which is a general programmable 32-bit DSP, can be programmed with the same efficiency in two modes of fixed point or floating point algorithm, and is provided with a plurality of integrated peripherals. The characteristics are as follows: 400 MHz; 5Mb high-capacity on-chip memory; low power consumption floating point DSP (363 mW); single chip, floating point signal processing precision; the Programmable Logic unit is a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA) (field Programmable Gate array); the data memory unit is synchronous Dynamic random access memory SDRAM (synchronous Dynamic random access memory).
Example 2
As shown in fig. 2, a digital signal processing method includes the steps of:
s1: initializing the digital signal processing unit;
s2: clearing the control command word value;
s3: opening an interrupt program;
s4: turning off the interrupt program;
s5: judging whether the value of the control command word is equal to 1 or not;
s6: if the number is equal to 1, entering a self-test program;
s7: if not, starting the interrupt program;
s8: returning to S4.
In an embodiment, preferably, the Time for executing the interrupt routine is shorter than the Time for writing a batch of data into the FIFO or the dual-port RAM memory.
In an embodiment, preferably, as shown in fig. 3, the interrupt routine of S3 and S7 includes the following steps:
a1: reading in a first-in first-out queue FIFO or a buffer dest of a double-port RAM memory;
a2: adding 1 to the value of the batch counter;
a3: judging whether the batch counter value is equal to the execution Time of the interrupt program, if so, ending the interrupt program, and if not, entering the next step;
a4: putting the data in the memory buffer dest into a memory buffer source;
a5: sending a batch of data through an interface;
a6: clearing the value of the batch counter;
a7: and paying an initial value for the address pointer.
The invention provides a digital signal processing circuit and a digital signal processing method, which can realize real-time processing of mass data. The design adopts a series of chips of ADI company as a processor and is matched with necessary peripheral circuits to form a hardware test platform, so that the whole scheme of the system can meet the requirement of real-time analysis of multi-channel signals, and a better effect is achieved in actual test.
Although the invention has been described in detail with respect to the general description and the specific embodiments, it will be apparent to those skilled in the art that modifications and improvements may be made based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (3)
1. A digital signal processing method, wherein a digital signal processing circuit comprises:
the device comprises a digital signal processing unit, a programmable logic unit and a data memory unit;
the programmable logic unit is connected with the digital signal processing unit, and the data memory unit is connected with the digital signal processing unit;
the digital signal processing unit is used for real-time digital signal data processing; the data memory unit is used for caching data in the real-time calculation process of the digital signal processing unit;
the programmable logic unit is a sequential logic control center to coordinate the work of the whole circuit;
the data memory unit and the digital signal processing unit are connected in a communication mode, and data in the data memory unit are transmitted to the digital signal processing unit in a transmission mode of a communication protocol;
the programmable logic unit and the digital signal processing unit are connected in a logic signal input and output mode, namely, a logic input and a logic output mode;
the logic output is a control time sequence signal output by the programmable logic unit, and the digital signal processing unit is matched with various peripheral devices in time sequence;
the peripheral device comprises an interrupt system of the digital signal processing unit, a storage space, an A/D sampling and sampling data transmission and data storage unit;
the programmable logic unit controls the priority and the triggering condition of the interrupt of the digital signal processing unit through the output control time sequence signal;
the digital signal processing unit selects a digital signal processor DSP for floating point calculation; the Programmable Logic unit selects a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA) (field Programmable gate array); the data memory unit selects synchronous dynamic random access memory SDRAM (synchronous dynamic random access memory);
the method is characterized by comprising the following steps:
s1: initializing the digital signal processing unit;
s2: clearing the control command word value;
s3: opening an interrupt program;
s4: turning off the interrupt program;
s5: judging whether the value of the control command word is equal to 1 or not;
s6: if the number is equal to 1, entering a self-test program;
s7: if not equal to 1, starting the interrupt program;
s8: return is made to S4.
2. The method of claim 1, wherein the interrupt procedure execution Time is shorter than a Time for writing a batch of data into a FIFO or dual port RAM memory.
3. The digital signal processing method according to claim 2, wherein said interrupt routine of S3 and S7 comprises the steps of:
a1: reading in a first-in first-out queue FIFO or a buffer dest of a double-port RAM memory;
a2: adding 1 to the value of the batch counter;
a3: judging whether the batch counter value is equal to the execution Time of the interrupt program, if so, ending the interrupt program, and if not, entering the next step;
a4: putting the data in the memory buffer dest into a memory buffer source;
a5: sending a batch of data through an interface;
a6: clearing the value of the batch counter;
a7: paying an initial value of the address pointer;
a8: and (6) ending.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010289516.8A CN111613260B (en) | 2020-04-14 | 2020-04-14 | Digital signal processing circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010289516.8A CN111613260B (en) | 2020-04-14 | 2020-04-14 | Digital signal processing circuit and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111613260A CN111613260A (en) | 2020-09-01 |
| CN111613260B true CN111613260B (en) | 2022-08-19 |
Family
ID=72205619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010289516.8A Active CN111613260B (en) | 2020-04-14 | 2020-04-14 | Digital signal processing circuit and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111613260B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101105401A (en) * | 2007-08-06 | 2008-01-16 | 北京航空航天大学 | SDINS/GPS combined guidance system time synchronism and synchronous data extraction method |
| CN101493438A (en) * | 2009-02-18 | 2009-07-29 | 宁波工程学院 | Phased array ultrasonic detection, data acquisition and process device |
| CN202471100U (en) * | 2011-12-27 | 2012-10-03 | 成都众询科技有限公司 | USB and DSP based supersonic reflectoscope |
| CN107066200A (en) * | 2017-03-14 | 2017-08-18 | 北京航天自动控制研究所 | A kind of collecting method and data collecting system based on FPGA |
| US10027340B1 (en) * | 2012-12-31 | 2018-07-17 | Jefferson Science Associates, Llc | Method and apparatus to digitize pulse shapes from radiation detectors |
| CN110632879A (en) * | 2019-10-09 | 2019-12-31 | 西安航空制动科技有限公司 | Data acquisition system based on DSP and CPLD |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0736858A (en) * | 1993-07-21 | 1995-02-07 | Hitachi Ltd | Signal processor |
| US7340596B1 (en) * | 2000-06-12 | 2008-03-04 | Altera Corporation | Embedded processor with watchdog timer for programmable logic |
| US7693244B2 (en) * | 2006-03-31 | 2010-04-06 | Intel Corporation | Encoding, clock recovery, and data bit sampling system, apparatus, and method |
| CN109902061B (en) * | 2019-02-03 | 2023-06-02 | 旋智电子科技（上海）有限公司 | Digital logic circuit and microprocessor |
-
2020
- 2020-04-14 CN CN202010289516.8A patent/CN111613260B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101105401A (en) * | 2007-08-06 | 2008-01-16 | 北京航空航天大学 | SDINS/GPS combined guidance system time synchronism and synchronous data extraction method |
| CN101493438A (en) * | 2009-02-18 | 2009-07-29 | 宁波工程学院 | Phased array ultrasonic detection, data acquisition and process device |
| CN202471100U (en) * | 2011-12-27 | 2012-10-03 | 成都众询科技有限公司 | USB and DSP based supersonic reflectoscope |
| US10027340B1 (en) * | 2012-12-31 | 2018-07-17 | Jefferson Science Associates, Llc | Method and apparatus to digitize pulse shapes from radiation detectors |
| CN107066200A (en) * | 2017-03-14 | 2017-08-18 | 北京航天自动控制研究所 | A kind of collecting method and data collecting system based on FPGA |
| CN110632879A (en) * | 2019-10-09 | 2019-12-31 | 西安航空制动科技有限公司 | Data acquisition system based on DSP and CPLD |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111613260A (en) | 2020-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6539500B1 (en) | System and method for tracing | |
| US10318468B2 (en) | FPGA-based interface signal remapping method | |
| EP0080891B1 (en) | Direct memory access logic system for a data transfer network | |
| USRE36766E (en) | Microprocessor breakpoint apparatus | |
| KR101519771B1 (en) | Extending a processor system within an integrated circuit | |
| EP0080890B1 (en) | Interface circuit for subsystem controller | |
| CN112035389B (en) | PLB-AXI bus conversion bridge and working method thereof | |
| RU2417412C2 (en) | Standard analogue interface for multi-core processors | |
| CN112540952B (en) | System on chip with on-chip parallel interface | |
| US20230315298A1 (en) | Flash controller for asic and control method therefor | |
| CN113515482A (en) | Data transmission system, method, computer device and storage medium | |
| US5249278A (en) | Microprocessor breakpoint apparatus | |
| TW201303870A (en) | Effective utilization of flash interface | |
| CN111613260B (en) | Digital signal processing circuit and method | |
| EP3658928B1 (en) | Logic analyzer for integrated circuits | |
| JP2001184226A (en) | Digital system having memory block and emulating method of block of memory | |
| EP3921740A1 (en) | Circuit for and method of configuring and partially reconfiguring function blocks of an integrated circuit device | |
| US6453366B1 (en) | Method and apparatus for direct memory access (DMA) with dataflow blocking for users | |
| TWI727581B (en) | Data transmission system | |
| JP2001216152A (en) | Logical integrated circuit and computer readable recording medium in which source of its cpu core is recorded | |
| KR20230091861A (en) | High-throughput circuit architecture for hardware acceleration | |
| CN111290889B (en) | FPGA-based universal processor-oriented test method and system | |
| Bolat et al. | Investigation of communication overhead of SoC lookaside accelerators | |
| Zhang et al. | ARM and FPGA heterogeneous accelerated processing system based on HLS and PCIe | |
| Zhao et al. | A Novel Design of High-speed Multi-port Memory Interface for Digital Signal Processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230227 Address after: Room 1001, Xianfeng Technology Building, No. 298, Weiye Road, Binjiang District, Hangzhou City, Zhejiang Province, 310000 Patentee after: Xiyin Technology (Hangzhou) Co.,Ltd. Address before: 100000 No. c5012 and c5013, floor 5, block C, Kangjian Baosheng Plaza, building 1, No. 8, Heiquan Road, Haidian District, Beijing (Dongsheng area) Patentee before: T & S TECHNOLOGIES CO.,LTD. |
|
| TR01 | Transfer of patent right |